ATMEL AT97SC3201-01AC

Features
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Full TCG/TCPA V1.1b Compatibility
Single Chip Turnkey Solution
Hardware Asymmetric Crypto Engine
2048 RSA Sign in 500 ms Using CRT
AVR 8-bit RISC Microprocessor
Internal EEPROM Storage for 10+ RSA Keys
33 MHz LPC (Low Pin Count) Bus for Easy PC Interface
100 KHz System Management Bus (SMBus) Two-wire Interface
Secure Hardware and Firmware Design and Chip Layout
True Random Number Generator (RNG)
Secure Real-time Clock Option
3.3V ±10% Supply Voltage
28-lead TSSOP Package or 40-lead MLF Package
0–70°C Temperature Range
Trusted
Platform
Module
Description
The AT97SC3201 is a fully integrated security module designed to be integrated into
personal computers and other embedded systems. It implements version 1.1b of the
Trusted Computing Platform Alliance (TCPA) specification for Trusted Platform
Modules (TPM). This specification has been adopted by the Trusted Computing Group
(TCG).
The TPM includes a crypto accelerator capable of computing a 2048-bit RSA
signature in 500 ms and a 1024-bit RSA signature in 100 ms, both using CRT.
Communication to and from the TPM can occur through one of two interface
protocols: either a 33-MHz LPC interface or a 100-KHz SMBus two-wire interface.
AT97SC3201
Summary
Figure 1. AT97SC3201 Block Diagram
SMBCLK/IOA
SMBDAT/IOB
IOC
ROM
Program
EEPROM
Program
33 MHz
LPC
Interface
AVR
8/16 Bit
CPU
EEPROM
Data
SMBus Interface
or GPIO
RNG
VBB
32.768 kHz
SRAM
RTC
CRYPTO
Engine
Timer
Physical
Security
Circuitry
The chip includes a full hardware random number generator that is used for the TCG
protocol and is also available to the system for any random numbers it may need
during normal operation.
Rev. 2015DS-TPM–7/04
Note: This is a summary document. A complete document is
available under NDA. For more information, please contact your
local Atmel sales office.
1
A real-time clock function is available using an external battery and crystal. The chip provides
tamper detection if the battery or crystal are removed or tampered with, and the current time
value can be signed by the appropriate internal keys to verify its accuracy. (Contact Atmel for
current status of this option.)
The battery detector can be used without the crystal for lower cost. In this mode, the TPM can
indicate to the system if it has been removed from the PC in any way and can also take
actions internally.
The chip uses a dynamic internal memory management scheme to store from 10 to 20 keys.
Other than the standard TCG commands (TPM_Evictkey, TPM_Loadkey), no system intervention is required to manage this internal key cache.
The TPM is offered to OEM manufacturers as a turnkey solution, including the firmware integrated on the chip. In addition, Atmel provides the necessary driver software for integration
into certain operating systems, along with BIOS drivers. A TCG Software Stack (TSS), also
supplied by Atmel and available under license, provides communication support to any application using MSCAPI or PKCS #11 Cryptographic APIs. (Contact Atmel for a complete list of
operating systems supported.)
Ful l d ocumen tation for T CG primiti ves can be foun d o n the TCG W eb si te,
www.trustedcomputinggroup.org. This specification includes only mechanical and electrical
information.
2
AT97SC3201
2015DS-TPM–7/04
AT97SC3201
Absolute Maximum Ratings
Operating Temperature..............................0°C to +70°C
*NOTICE:
Storage Temperature (without Bias)...........0°C to + 70°C
Voltage on I/O Pins..............................−0.1 to VCC +0.3V
Voltage on VCC with Respect to Ground.................6.0V
Maximum ESD Voltage..........................................2000V
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or
any other conditions beyond those indicated in
the operational sections of this specification may
cause temporary or permanent failure. Exposure
to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 1. DC Parameters*
Symbol
Parameter
Min
Nom
Max
Units
VCC
Supply Voltage
3.0
3.3
3.6
V
ICC
Operating Current at fclk = 33 MHz
25
50
mA
IST
Static Current
5
10
mA
VCC = 3.6V; fxtal = 0 Hz,
active inputs
ISL
Sleep Current, Chip Idle
40
100
µA
VCC = 3.6V; fxtal = 0 Hz
IBB
Battery Current
2
4
µA
VCC = 0V; fxtal = 0 Hz.
ILIO
Input Leakage
0.1
3
µA
Vin = VCC or GND
VIH
Input High Threshold
0.5 * VCC
VCC + 0.5
V
VIL
Input Low Threshold
−0.5
0.3 * VCC
V
VOH
Output High Voltage
0.9 * VCC
VOL
Output Low Voltage
IOLCR
Output Low Current, CLKRUN#
CI
Input Pin Capacitance
0.98 * VCC
0.1 * VCC
7
6
Notes
V
At IOUT = −500 uA
V
At IOUT = 1.5mA
mA
At VOUT = .615 * VCC
pF
Note 1
* VCC = 3.0 to 3.6V; Temperature = 0 to 70°C
Note:
These parameters guaranteed but not tested.
3
2015DS-TPM–7/04
Table 2. AC Parameters*
Symbol
Parameter
Min
Nom
Max
Units
TVAL
CLK to Signal Valid Delay – LAD0-3
2
5
11
ns
TON
Float to Active Delay
2
4
TOFF
Active to Float Delay
TSU
Input Setup Time to CLK
7
2
ns
TH
Input Hold Time from CLK
0
−500
ns
TRST
Reset Active Time after Power Stable
1
ms
Note 2
TRST-CLK
Reset Active after CLK Stable
100
m
Note 2
TRST-OFF
Reset Active to Output Float Delay
40
ns
Note 2
TCLKIN
CLK Period
29.5
31
ns
Note 3
TCLKLO
CLK Low Duration
13.4
18
ns
Note 1, Note 3
TCLKHI
CLK High Duration
13.4
18
ns
Note 1, Note 3
Measured at Vtrise = 0.285 * V CC and Vtfal =
0.615 * VCC. Measured from clk at Vtest = 0.4
* VCC ; Load = 200Ω
ns
28
30
Notes
ns
* Cl = 10pf. VCC = 3.0 to 3.7V; Temperature = 0 to 70°C
Note:
1. All parameters measured with respect to signal crossing Vtest = 0.4 * VCC unless otherwise noted.
2. These parameters guaranteed but not tested.
3. The minimum parameter must never be violated under any circumstances unless Ireset# is asserted. If proper CLKRUN#
signaling is observed, the maximum specification can be violated.
Table 3. Ordering Information
4
Ordering Code
Package
Operation Range
AT97SC3201-01AC
28A3
Commercial (0° to 70° C)
AT97SC3201-X1AC
28A3
AT97SC3201-01MC
40ML1
AT97SC3201-X1MC
40ML1
lead-free
Commercial (0° to 70° C)
Commercial (0° to 70° C)
lead-free
Commercial (0° to 70° C)
AT97SC3201
2015DS-TPM–7/04
AT97SC3201
Package Drawing
28A3 – TSSOP
b
L
L1
E E1
e
End View
Top View
COMMON DIMENSIONS
(Unit of Measure = mm)
D
A
A2
SYMBOL
D
MIN
NOM
MAX
NOTE
9.60
9.70
9.80
2, 5
6.20
3, 5
E
E1
Side View
8.10 BSC
6.00
A
–
–
1.20
A2
0.80
1.00
1.05
b
0.19
–
0.30
e
L
L1
Notes:
6.10
4
0.65 BSC
0.45
0.60
0.75
1.00 REF
1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation DB for additional information.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in)
per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b
dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
1/8/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
28A3, 28-lead, 6.1 x 9.7 mm Body, 0.65 pitch,
Thin Shrink Small Outline Package (TSSOP)
DRAWING NO.
28A3
REV.
A
5
2015DS-TPM–7/04
40ML1
A
A1
D
N
A2
A3
1
Pin 1 Indicator
2
3
E
Top View
L
0
Side View
COMMON DIMENSIONS
(Unit of Measure = mm)
D2
SYMBOL
MIN
D
E2
E
MAX
1
3.95
4.10
4.25
2
E2
3.95
4.10
4.25
b
A
-
0.85
0.90
A1
0.0
0.01
0.05
A2
-
0.65
0.70
N
A3
e
L
0.20 REF
0.30
e
PIN1 ID
Bottom View
b
NOTE
6.00 BSC
D2
3
Notes:
NOM
6.00 BSC
0.40
0.50
0.50 BSC
0.18
0.23
0.30
2
1. This drawing is for general information only. Refer to JEDEC Drawing MO-220, Variation WJJD-2, for proper dimensions,
tolerances, datums, etc.
2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the
terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
3/9/04
R
6
2325 Orchard Parkway
San Jose, CA 95131
TITLE
40ML1, 40-lead 6.0 x 6.0 mm Body, 0.50 mm Pitch, Molded Quad
Flat No Lead Package (MLF2)
DRAWING NO.
40ML1
REV.
A
AT97SC3201
2015DS-TPM–7/04
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Printed on recycled paper.
2015DS-TPM–7/04