8-Bit Voltage Output DAC Datasheet DAC8 V 2.2
001-13430 Rev. *H
8-Bit Voltage Output DAC
Copyright © 2001-2015 Cypress Semiconductor Corporation. All Rights Reserved.
PSoC® Blocks
Resources
Digital
Analog CT
API Memory (Bytes)
Analog SC
Flash
RAM
Pins (per
External I/O)
CY8C29/27/24/22xxx, CY8C23x33, CY8CLED04/08/16, CY8CLED0xD, CY8CLED0xG, CY8CTST120,
CY8CTMG120, CY8CTMA120, CY8C28x45, CY8C28x45, CY8CPLC20, CY8CLED16P01, CY8C28x43,
CY8C28x52
0
0
2
175
0
1
Features and Overview
8-bit resolution
Voltage output
2’s complement, offset binary and sign/magnitude input data formats
Sample and hold for analog bus and external outputs
Update rates to 125 ksps
The DAC8 User Module translates digital codes to output voltages. The DAC8 translates digital codes to
output voltages at an update rate of up to 125k samples per second. The Application Programming
Interface (API) supports offset-binary, 2’s complement, and register-image data formats. Offset
compensation is employed to minimize error.
Figure 1.
DAC8 Block Diagram
Cypress Semiconductor Corporation
Document Number: 001-13430 Rev. *H
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198 Champion Court
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San Jose, CA 95134-1709
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408-943-2600
Revised March 8, 2015
8-Bit Voltage Output DAC
Functional Description
The DAC8 User Module converts digital codes into analog output voltages. The digital codes are
represented as numbers in 2’s complement form, ranging from -127 to +127. Alternatively, input codes
may be represented in offset-binary form, as a number ranging from 0 to 254. Several output voltage
ranges are possible, depending on the value selected for a system-level parameter, RefMux.
The DAC8 User Module maps onto any two adjacent switched capacitor analog PSoC blocks. These
blocks are designated LSB and MSB. The LSB block, or stage, is coupled to the MSB stage through that
block’s “BCap" capacitor, C4. Internally, the operation is based on sign-and-magnitude format. The five
most significant magnitude bits set the value of C3, an array of binary-weighted capacitors shown in the
simplified schematic of below. The two least significant magnitude bits set the value of C1. C3 assumes
values from zero to 31 units and C1 assumes values from the set {0, 8, 16, 24} in units of capacitance. The
reference voltage, which may be inverted by the ASign bit, is scaled in each stage by the ratio of the
magnitude capacitors, C1 and C3, to the feedback capacitors, C2 and C5, respectively. Each has a nominal
capacitance of 32 units. The output of the LSB stage is further scaled by the ratio of the coupling capacitor,
C4, to the C5 feedback capacitor.
Figure 2.
Simplified Schematic of the DAC8
The hardware performs offset compensation in each update cycle. Switches controlled by Φ1 and Φ2
configure the opamps as a unity-gain followers during Φ1. In this configuration, the offset voltages appear
at the summing nodes, charging the various ACaps, BCaps, and FCaps. As reconfigured in Φ2, the circuit
inverts the offset charges on these capacitors, effectively canceling the offset voltages.
On every update cycle, Vout slews between the opamp offset voltage (during Φ1) and the desired voltage
(settled during Φ2); a direct result of offset compensation. One way to mitigate this price for increased
accuracy is by employing the sample-and-hold circuit associated with the output bus. Vout charges both
the load and the hold capacitor (CHold in the DAC8 block diagram), during the last half of Φ2. CHold is
isolated from the opamp output at the end of that period. Each analog output bus is served by an analog
output buffer with suitably high input impedance.
Combining the scaled references results, the output is:
Equation 1
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8-Bit Voltage Output DAC
When the global parameter RefMux is configured to (2 BandGap) ± BandGap in the Device Editor, AGND
is 2.6V and the reference voltage is 1.3V. The corresponding output is:
Equation 2
Equation 2 appears to be a result with 10 bits of magnitude; however, recall that C1 is constrained to
values obtained scaling the 2 least significant magnitude bits by a factor of eight. Canceling the scale
factor in C1 and in its denominator, the result can be expressed as:
Equation 3
Example
Equations 2 and 3 above show that the 8 bit DAC input code is distributed across 2 values and the sign bit.
The MSB of the input code is used as the sign bit. Bits 2 through 7 are use to specify the 5 bit value of C3
and finally the two LSBs are used to specify C1. For a input code value of -74 the sign is negative, the
value of C3 is 18 and the value of C1 is 2. By applying these value to Equation 2 we get:
Equation 4
The value calculated is an ideal value and will most likely differ based on system noise and chip offsets.
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8-Bit Voltage Output DAC
DC and AC Electrical Characteristics
The following values are indicative of expected performance and based on initial characterization data.
Unless otherwise specified in the table below, TA = 25°C and Vdd = 5V. Unless otherwise noted, fclock =
125 kHz, external AGND 2.50V, external VRef 1.23V, REFPWR = HIGH, SCPOWER = ON, PSoC block
power HIGH.
Table 1.
5.0V DAC8 DC and AC Electrical Characteristics, CY8C29/27/24/22xxx, CY8C23x33,
CY8CLED04/08/16, CY8CLED0xD, CY8CLED0xG, CY8CTST120, CY8CTMG120, CY8CTMA120, CY8C28x45,
CY8C28x45, CY8CPLC20, CY8CLED16P01, CY8C28x43, CY8C28x52Family of PSoC Devices
Parameter
Resolution
Typical
—
Limit
8
Units
Conditions and Notes
Bits
Linearity
DNL
0.5
LSB
INL
0.3
LSB
Monotonic
YES
Gain Error
Including Reference Gain Error
3.5
%FSR
Excluding Reference Gain Error3
0.5
%FSR
VOS, Offset Voltage
±7.5
mV
Output Noise
4.5
mV rms
Low Power
8 to 500
kHz
Med Power
4 to 2000
kHz
High Power
4 to 3200
kHz
Low Power
305
µA
Med Power
1130
µA
High Power
4315
µA
0 to 300 kHz
fclock, Analog Column Clock1
Operating Current2
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8-Bit Voltage Output DAC
The following values are indicative of expected performance and based on initial characterization data.
Unless otherwise specified in the table below, TA = 25°C and Vdd = 3.3V. Unless otherwise noted, fclock =
125 kHz, external AGND 1.50V, external VRef 0.8V, REFPWR = HIGH, SCPOWER = ON, PSoC block
power HIGH.
Table 2.
3.3V DAC8 DC and AC Electrical Characteristics, CY8C29/27/24/22xxx, CY8C23x33,
CY8CLED04/08/16, CY8CLED0xD, CY8CLED0xG, CY8CTST120, CY8CTMG120, CY8CTMA120, CY8C28x45,
CY8C28x45, CY8CPLC20, CY8CLED16P01, CY8C28x43, CY8C28x52Family of PSoC Devices
Parameter
Resolution
Typical
—
Limit
8
Units
Conditions and Notes
Bits
Linearity
DNL
0.5
LSB
INL
0.4
LSB
Monotonic
YES
Gain Error
Including Reference Gain Error
2.6
%FSR
Excluding Reference Gain Error3
0.3
%FSR
VOS, Offset Voltage
±7.5
mV
Output Noise
2.5
mV rms
Low Power
8 to 500
kHz
Med Power
4 to 2000
kHz
High Power
4 to 3200
kHz
Low Power
290
µA
Med Power
1090
µA
High Power
4175
µA
0 to 300 kHz
fclock, Analog Column Clock1
Operating Current2
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8-Bit Voltage Output DAC
The following values are indicative of expected performance and based on initial characterization data.
Unless otherwise specified in the table below, TA = 25°C and Vdd = 2.7V. Unless otherwise noted, fclock =
125 kHz, external AGND 1.50V, external VRef 0.8V, REFPWR = HIGH, SCPOWER = ON, PSoC block
power HIGH.
Table 3.
2.7V DAC8 DC and AC Electrical Characteristics, CY8C29/27/24/22xxx, CY8C23x33,
CY8CLED04/08/16, CY8CLED0xD, CY8CLED0xG, CY8CTST120, CY8CTMG120, CY8CTMA120, CY8C28x45,
CY8C28x45, CY8CPLC20, CY8CLED16P01, CY8C28x43, CY8C28x52Family of PSoC Devices
Parameter
Resolution
Typical
—
Limit
8
Units
Conditions and Notes
Bits
Linearity
DNL
0.5
LSB
INL
0.4
LSB
Monotonic
YES
Gain Error
Including Reference Gain Error
2.6
%FSR
Excluding Reference Gain Error3
0.3
%FSR
VOS, Offset Voltage
±7.5
mV
Output Noise
2.5
mV rms
Low Power
8 to 500
kHz
Med Power
4 to 2000
kHz
High Power
4 to 3200
kHz
Low Power
290
µA
Med Power
1090
µA
High Power
4175
µA
0 to 300 kHz
fclock, Analog Column Clock1
Operating Current2
Electrical Characteristics Notes
1. Upper end of range specified for 3 dB increase in broadband noise. Lower end for droop < 1 LSB.
2. The analog column clock selected by the DAC is 4 times faster than the phase clock rate that governs
the update cycle. See the discussion of timing, below.
3. Does not include reference block power, common to all analog blocks (see the PSoC Family datasheet).
4. Reference Gain Error measured by comparing the external reference to VRefHigh and VRefLow routed
through the test mux and back out to a pin.
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8-Bit Voltage Output DAC
Placement
The DAC8 User Module maps onto two PSoC blocks designated LSB and MSB. The output of the LSB
block is fed into the input of the MSB block therefore they are always placed adjacent to each other. In the
CY8C26/25xxxdevice family the MSB block maps only to “Type A" switched capacitor PSoC blocks. In the
CY8C29/27/24/22xxx, CY8C23x33, CY8CLED04/08/16, CY8CLED0xD, CY8CLED0xG, CY8CTST120,
CY8CTMG120, CY8CTMA120, CY8C28x45, CY8C28x45, CY8CPLC20, CY8CLED16P01, CY8C28x43,
CY8C28x52device family the MSB block maps only to “Type C" switched capacitor PSoC Blocks. This
helps to minimize linearity errors because, these types of blocks permit the auto-zero process to cancel
offset errors across the “BCap" capacitor (C4 in the figure above) that couples the LSB and MSB blocks
together.
An additional consideration, in selecting a placement location, is that the MSB and LSB clocks must be
derived from the same source. This happens automatically, if they are placed in the same column in the
analog array. If they are placed in two different columns, both column multiplexers must be set to the same
source.
Parameters and Resources
To create a DAC8 instance, select the user module in the Device Editor, rename it if desired, and map it
onto the device. Placement considerations include availability of an analog column output bus if the signal
is to be driven off chip and interdependence with other user modules on the column clock resource(s).
Once placed, the user module displays its parameters.
DataFormat
The DAC8 User Module API handles three different data formats: offset binary, 2’s complement, and
sign-and-magnitude. The WriteBlind entry point of the API section (below), describes these conventions and the range of values associated with each.
AnalogBus
The DAC block broadcasts its output to adjacent analog PSoC blocks. Choosing one of the analog
bus options connects the DAC output to the outside world through one of the analog output buffers.
In certain columns, selecting the bus provides an additional local connection to the PSoC block at the
top of the array. Switched capacitor PSoC blocks incorporate a sample and hold circuit that samples
the DAC output in the last half of Φ2. This isolates external outputs from the voltage swings that occur
during auto-zero operation.
ClockPhase
This parameter determines the role of the phase clocks, Φ1 and Φ2, generated by the column clock
divider discussed in the clock and timing sections that follow. When Normal is selected, the auto-zero
cycle occurs during Φ1 and the output of the DAC is valid in Φ2. When ClockPhase is set to Swapped,
these roles are reversed. This can be useful when the DAC is connected to another peripheral that
samples its input on Φ1.
Note
Setting ClockPhase to Swapped disables the sample and hold function of the analog output bus. If
the AnalogBus parameter is set to Enabled, the bus output mirrors the local PSoC block output,
alternating between AGND (plus the offset voltage) during Φ1 and the desired output during Φ2.
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8-Bit Voltage Output DAC
Analog Column Clock
The DAC continuously updates its output whether or not it is commanded to “write" an new value by
calling the appropriate functions WriteBlind and WriteStall API functions. The analog column clock
multiplexors selects the source clock used to generate the phase clocks, Φ1 and Φ2 that control this
update operation. The phase clock generator divides the column clock by four to produce Φ1 and Φ2,
so the column clock frequency is four times faster than the actual analog output update rate. Two
levels of multiplexing provide choices for the column clock that include any of the digital blocks and
the system clock dividers. The Electrical Characteristics section, above, specifies lower and upper
limits for the column clock frequency.
For positive output voltages (Vout > AGND) and normal phase, the reference voltage is stored on the
A Cap during Φ1 as shown in the simplified schematic, above. In order to fully charge the A Cap, any
change to it’s value must meet set-up time tSU to the falling edge of Φ1. This set-up time, illustrated
in the figure below, is dependent on the reference power levels. Although the set-up time is not characterized, the hardware stall mechanism can be used to guarantee that it will be met. If the A Cap
does not fully charge due to set-up time violations the output will be incorrect until the next phase clock
cycle when the entire period of f1 when it will be corrected. A similar set-up time relative to the falling
edge of f2 governs behavior for negative output voltages (Vout < AGND).
Figure 3.
Update Timing for VOUT > AGND
For a large class of applications, momentary (one update-cycle) deviations are acceptable. Other
application may impose stricter requirements. Hardware synchronization may be employed to control
the timing of the register write that changes the value of the A Cap. This is directly supported in the
WriteStall API by entry point. When invoked, the underlying hardware recognizes the write to the
PSoC block register and freezes the CPU clock, holding off completion the write until the rising edge
of Φ1. The ASY_CR register controls.
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8-Bit Voltage Output DAC
Figure 4.
Hardware Synchronization and CPU Clock Stall
During the CPU stall, all analog and digital PSoC blocks function normally. The MOV instruction that
writes the DAC’s CR0 register is simply suspended and, during this period, any interrupts become or
remain pending. The number of CPU cycles lost during the stall equal, in time, the period of the can
be calculated using the following relation.
Equation 5
Clearly, to minimize the CPU cycles lost to the stall, the column clock should be run at the highest
practical frequency. This can be much higher than necessary for actual changes to the output voltage
as extra output cycles simply repeat the previous output cycle. A faster column clock also minimizes
the latency from calling the output function to the time the output changes.
There are practical limits to the column clock frequency, however. Since the DAC must slew from
AGND to the output voltage each phase-clock cycle, the column clock is limited to frequencies that
permit the output to settle. When the sample and hold feature of the analog output bus is used, the
opamp output drives the bus during the sampling window in the second half of Φ2. If the column clock
is so fast that the opamp is still slewing to and settling on the output voltage, this becomes observable
as noise on the output signal. In extreme cases, the output will slew only part way to the final output
voltage before the sampling window closes. This may be observed as severe non-linear gain
compression on the output most evident at the full-scale ends of the output range. Upper limits for the
analog column clock that prevent this from occurring are provided in the Electrical Characteristics
tables, above.
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8-Bit Voltage Output DAC
Application Programming Interface
The Application Programming Interface (API) routines are provided as part of the user module to allow the
designer to deal with the module at a higher level. This section specifies the interface to each function
together with related constants provided by the “include" files.
Note
In this, as in all user module APIs, the values of the A and X register may be altered by calling an API
function. It is the responsibility of the calling function to preserve the values of A and X prior to the call if
those values are required after the call. This “registers are volatile" policy was selected for efficiency
reasons and has been in force since version 1.0 of PSoC Designer. The C compiler automatically takes
care of this requirement. Assembly language programmers must ensure their code observes the policy,
too. Though some user module API function may leave A and X unchanged, there is no guarantee they
will do so in the future.
For Large Memory Model devices, it is also the caller's responsibility to preserve any value in the
CUR_PP, IDX_PP, MVR_PP, and MVW_PP registers. Even though some of these registers may not be
modified now, there is no guarantee that will remain the case in future releases.
Entry points are provided to initialize the DAC8 User Module, write updated values, and disable the user
module.
DAC8_Start
Description:
Performs all required initialization for this user module and sets the power level for the switched
capacitor PSoC block.
C Prototype:
void
DAC8_Start(BYTE bPowerSetting)
Assembler:
mov
A, bPowerSetting
lcall DAC8_Start
Parameters:
bPowerSetting: One byte that specifies the power level. Following reset and configuration, the PSoC
block assigned to the DAC block is powered down. Symbolic names provided in C and assembly, and
their associated values, are given in the following table.
Symbolic Name
Value
DAC8_OFF
0
DAC8_LOWPOWER
1
DAC8_MEDPOWER
2
DAC8_FULLPOWER
3
Return Value:
None
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8-Bit Voltage Output DAC
Side Effects:
The DAC outputs will be driven. By default, the initial value is AGND. Call one of the Write routines
prior to calling “Start," if some other output value is required at power on. The A and X registers may
be altered by this function.
DAC8_SetPower
Description:
Sets the power level for the DAC switched capacitor PSoC block. May be used to turn the block Off
and On.
C Prototype:
void
DAC8_SetPower(BYTE bPowerSetting)
Assembler:
mov
A, bPowerSetting
lcall DAC8_SetPower
Parameters:
bPowerSetting: Identical to the bPowerSetting parameter used for the Start entry point.
Return Values:
None
Side Effects:
The DAC outputs will be driven. By default, the initial value is AGND. Call one of the Write routines
prior to calling “Start," if some other output value is required at power on. The A and X registers may
be altered by this function.
DAC8_WriteBlind
Description:
Immediately updates the output voltage to the indicated value.
C Prototypes:
// For OffsetBinary:
void DAC8_WriteBlind(BYTE bOutputValue)
// For TwosComplement:
void DAC8_WriteBlind(CHAR cOutputValue)
// For TwoByteSignAndMagnitude:
void DAC8_WriteBlind2B(BYTE bMSB, BYTE bLSB)
Assembler:
; for
mov
lcall
; for
mov
mov
lcall
; for
mov
lcall
OffsetBinary and TwosComplement
A, bOutputValue
DAC8_WriteBlind
TwoByteSignAndMagnitude format:
A, bLSB
X, bMSB
DAC8_WriteBlind
OffsetBinary and TwosComplement
A, cOutputValue
DAC8_WriteBlind
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8-Bit Voltage Output DAC
; for TwoByteSignAndMagnitude format:
mov
A, bLSB
mov
X, bMSB
lcall DAC8_WriteBlind
Parameters:
cOutputValue: One byte that specifies the output voltage. Allowed values lie in the range corresponding to the selected value of DataFormat, as given in the following table.
Data Format
Minimum
Maximum
OffsetBinary
0
254
TwosComplement
-127
127
TwoByteSignAndMagnitude
3F18h
1F38h
Offset-binary values are positive numbers, with the lowest output voltage represented by zero and the
highest by 254. 2’s complement is the native signed format of the M8C processor. In TwoByteSignAndMagnitude format, high byte takes the form 00smmmmm2 and the low byte takes the form
00tmm0002, where ‘s‘ is the sign, ‘t‘ is the inverted sign, and ‘m‘ represents magnitude bits, for positive
numbers, s=0 and t=1.
Return Values:
None
Side Effects:
The output may glitch for reasons discussed in the Timing section in this user module. The A and X
registers may be altered by this function.
Note: When you select the OFFSET_BINARY, input values that are out of range are automatically
converted to two’s compliment data within the API. This means that an out of range value, above the
maximum allowed offset binary value, is converted to a small positive output (near Agnd).
DAC8_WriteStall
Description:
Possibly stalls the microprocessor until the beginning of Φ1, then updates the output voltage to the
indicated value. Note that the API assumes that either interrupts are disabled or the maximum interrupt latency is less than ACLKi (see the Forced Synchronization with Fast Update Clock figure).
C Prototypes:
// For OffsetBinary:
void DAC8_WriteStall(BYTE bOutputValue)
// For TwosComplement:
void DAC8_WriteStall(CHAR cOutputValue)
// For TwoByteSignAndMagnitude:
void DAC8_WriteStall2B(BYTE bMSB, BYTE bLSB)
Assembly:
; for OffsetBinary and TwosComplement
mov
A, cOutputValue
lcall DAC8_WriteStall
; for TwoByteSignAndMagnitude format:
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8-Bit Voltage Output DAC
mov
A, bLSB
mov
X, bMSB
lcall DAC8_WriteStall
Parameters:
cOutputValue: Identical in format and value range to the parameters described for the WriteBlind entry
point.
bMSB and bLSB: Identical in format and value range to the parameters described for the WriteBlind
entry point.
Return Values:
None
Side Effects:
If ACLKi is inactive (where ‘i’ is the column into which the analog PSoC block is mapped), the microprocessor’s CPU clock is disabled until Φ2 goes inactive, possibly for three-quarters of an update
cycle (plus two CPU clocks). Note that no interrupts are recognized during the stall interval. The A and
X registers may be altered by this function.
DAC8_Stop
Description:
Powers the user module Off.
C Prototype:
void
DAC8_Stop(void)
Assembly:
lcall
DAC8_Stop
Parameters:
None
Return Value:
None
Side Effects:
Outputs will not be driven. The A and X registers may be altered by this function.
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8-Bit Voltage Output DAC
Sample Firmware Source Code
This sample assembly code creates a periodic, descending sawtooth wave.
;------------------------------------------------------------------------; This sample code for the DAC8 User Module generates a periodic signal that
; ramps down
;------------------------------------------------------------------------include "m8c.inc"
include "memory.inc"
include "PSoCAPI.inc"
; part specific constants and macros
; Constants & macros for SMM/LMM and Compiler
; PSoC API definitions for all user modules
export _main
DAC_MAX: equ 254
; This is the maximum DAC value
area bss (RAM, REL, CON)
bDACValue: blk 1
; Variable to hold the DAC value
area text (ROM, REL, CON)
_main:
mov A, DAC8_HIGHPOWER
; Start DAC with HIGH power setting
call DAC8_Start
Init:
mov [bDACValue], DAC_MAX ; Initialize DAC value to hold the maximum
mov X, 0xFF
; Initialize X register to hold 0xFF
RampDown:
mov A, [bDACValue]
call DAC8_WriteStall
; Move DAC value into A register
; Write the value in A to the DAC
Delay:
dec X
jnz Delay
; Decrement X register
; Keep delaying if it hasn't reached zero yet
dec [bDACValue]
jnz RampDown
jmp Init
; Decrement DAC value variable
; If it is not zero, keep ramping down
; If it is zero, restart the ramp down
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8-Bit Voltage Output DAC
The following C sample code performs the same function as the previous assembly sample code:
//-----------------------------------------------------------------------// This C sample code for the DAC8 User Module creates a periodic signal
// that ramps down.
//-----------------------------------------------------------------------#include <m8c.h>
#include "PSoCAPI.h"
// part specific constants and macros
// PSoC API definitions for all user modules
#define DAC_MAX (254)
// Define max DAC value as 254
unsigned char bDACValue = 0;
unsigned char i;
// Variable for the DAC value
// Variable for an index
void main(void)
{
DAC8_Start(DAC8_HIGHPOWER); // Start DAC8 in HIGH power mode
while(1)
{
// Repeat forever
if(bDACValue == 0)
{
// Reset DAC value to the max if it reached zero
bDACValue = DAC_MAX;
}
// Write value to DAC and decrement
DAC8_WriteStall(bDACValue--);
// Delay loop
for(i = 0xFF; i != 0; i--);
}
}
Configuration Registers
The API provides a complete interface to the DAC. Writing directly to the configuration registers affords an
alternative means of updating the output. Either way, there are timing considerations which must be
understood to prevent output glitches. The following registers are used for the DAC8 switched capacitor
DAC block.
Table 4.
Block LSB: Register CR0
Bit
Value
7
1
6
0
5
Sign
4
Magnitude
3
2
0
1
0
0
0
Sign uses a ‘1’ for positive values (AGND up to RefHi) and a ‘0’ for negative values (RefLow up to AGND).
The default is ‘1’. Note that this is opposite the sense used in the MSB Block. Use one of the Write
functions in the API to change Sign. Magnitude is a 5-bit value (0..31) and its default is ‘0’. Use one of the
Write functions in the API to change Magnitude.
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8-Bit Voltage Output DAC
Table 5.
Block LSB: Register CR1
Switched Cap Type A
Bit
Value
7
0
6
5
4
3
2
1
0
1
0
0
0
0
0
0
Switched Cap Type B
Bit
7
6
5
4
3
2
1
0
Value
1
0
0
0
0
0
0
0
Table 6.
Block LSB: Register CR2
Bit
Value
7
6
Analog Bus 0
5
1
4
0
3
0
2
0
1
0
0
0
AnalogBus is enabled or disabled at configuration time in the Device Editor.
Table 7.
Block LSB: Register CR3
Switched Cap Type A
Bit
Value
7
0
6
5
4
3
2
1
0
1
1
0
0
Power
0
Switched Cap Type B
Bit
7
6
5
4
3
2
1
0
Value
0
0
1
1
1
0
Power
Power: The default is Off. Use the Start call in the API to set this value.
Table 8.
Block MSB: Register CR0
Bit
Value
7
1
6
0
5
Sign
4
3
2
1
0
Magnitude
Sign is set by the API Write routines. Magnitude is changed by using one of the Write functions in the API.
Table 9.
Block MSB: Register CR1
Bit
Value
7
0
6
1
Document Number: 001-13430 Rev. *H
5
0
4
0
3
0
2
0
1
0
0
1
Page 16 of 17
8-Bit Voltage Output DAC
Table 10.
Block MSB: Register CR2
Bit
7
Value
6
Analog Bus 0
5
1
4
0
3
0
2
0
1
0
0
0
AnalogBus is enabled or disabled at configuration time in the Device Editor.
Table 11.
Block MSB: Register CR3
Bit
Value
7
0
6
0
5
1
4
1
3
BMux
2
1
0
Power
BMux is configured to select the connection from the LSB PSoC block. Power: 0 = Off, 1 = Low, 2 =
Medium, 3 = Full. The default is Off. Use the Start call in the API to set this value.
Version History
Version Originator
2.2
Note
DHA
Description
Added Version History
PSoC Designer 5.1 introduces a Version History in all user module datasheets. This section documents high level descriptions of the differences between the current and previous user module versions.
Document Number: 001-13430 Rev. *H
Revised March 8, 2015
Page 17 of 17
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