CY14B256Q1 CY14B256Q2 CY14B256Q3 256-Kbit (32 K × 8) Serial (SPI) nvSRAM Features ■ ■ 256-Kbit nonvolatile static random access memory (nvSRAM) ❐ Internally organized as 32 K × 8 ❐ STORE to QuantumTrap nonvolatile elements initiated automatically on power-down (AutoStore) or by user using HSB pin (Hardware STORE) or SPI instruction (Software STORE) ❐ RECALL to SRAM initiated on power-up (Power-Up RECALL) or by SPI instruction (Software RECALL) ❐ Automatic STORE on power-down with a small capacitor (except for CY14B256Q1) ■ High reliability ❐ Infinite read, write, and RECALL cycles ❐ 1 million STORE cycles to QuantumTrap ❐ Data retention: 20 years ■ High-speed serial peripheral interface (SPI) ❐ 40-MHz clock rate ❐ Supports SPI mode 0 (0,0) and mode 3 (1,1) ■ Write protection ❐ Hardware protection using Write Protect (WP) pin ❐ Software protection using Write Disable instruction ❐ Software block protection for 1/4,1/2, or entire array ■ Low power consumption ❐ Single 3 V +20%, –10% operation ❐ Average active current of 10 mA at 40-MHz operation Industry standard configurations ❐ Industrial temperature ❐ CY14B256Q1 has identical pin configuration to industry standard 8-pin NV memory ❐ 8-pin dual flat no-lead (DFN) package and 16-pin small outline integrated circuit (SOIC) package ❐ Restriction of hazardous substances (RoHS) compliant Functional Overview The Cypress CY14B256Q1/CY14B256Q2/CY14B256Q3 combines a 256-Kbit nvSRAM[1] with a nonvolatile element in each memory cell with serial SPI interface. The memory is organized as 32 K words of 8 bits each. The embedded nonvolatile elements incorporate the QuantumTrap technology, creating the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while the QuantumTrap cell provides highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile elements (STORE operation) takes place automatically at power-down (except for CY14B256Q1). On power-up, data is restored to the SRAM from the nonvolatile memory (RECALL operation). The STORE and RECALL operations can also be initiated by the user through SPI instruction. For a complete list of related documentation, click here. Configuration Feature AutoStore Software STORE Hardware STORE CY14B256Q1 CY14B256Q2 No Yes Yes Yes No VCC Logic Block Diagram CS WP SCK QuantumTrap 32 K X 8 Instruction decode Write protect Control logic STORE SRAM Array HOLD RECALL 32 K X 8 Instruction register Address Decoder No CY14B256Q3 Yes Yes Yes VCAP Power Control STORE/RECALL Control HSB D0-D7 A0-A14 SI Data I/O register SO Status Register Note 1. This device will be referred to as nvSRAM throughout the document. Cypress Semiconductor Corporation Document Number: 001-53882 Rev. *K • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 5, 2014 Not Recommended for New Designs 256-Kbit (32 K × 8) Serial (SPI) nvSRAM CY14B256Q1 CY14B256Q2 CY14B256Q3 Pinouts .............................................................................. 3 Pin Definitions .................................................................. 4 Device Operation .............................................................. 5 SRAM Write ................................................................. 5 SRAM Read ................................................................ 5 STORE Operation ....................................................... 6 AutoStore Operation .................................................... 6 Software STORE Operation ........................................ 6 Hardware STORE and HSB Pin Operation ................. 6 Hardware RECALL (Power-Up) .................................. 7 Software RECALL ....................................................... 7 Disabling and Enabling AutoStore ............................... 7 Serial Peripheral Interface ............................................... 7 SPI Overview ............................................................... 7 SPI Modes ................................................................... 9 SPI Operating Features .................................................. 10 Power-Up .................................................................. 10 Power On Reset ........................................................ 10 Power-Down .............................................................. 10 Active Power and Standby Power Modes ................. 10 SPI Functional Description ............................................ 10 Status Register ............................................................... 11 Read Status Register (RDSR) Instruction ................. 11 Write Status Register (WRSR) Instruction ................ 11 Write Protection and Block Protection ......................... 12 Write Enable (WREN) Instruction .............................. 12 Write Disable (WRDI) Instruction .............................. 13 Block Protection ........................................................ 13 Write Protect (WP) Pin .............................................. 13 Memory Access .............................................................. 13 Read Sequence (READ) instruction .......................... 13 Write Sequence (WRITE) instruction ........................ 13 Document Number: 001-53882 Rev. *K nvSRAM Special Instructions ........................................ 15 Software STORE (STORE) instruction ...................... 15 Software RECALL (RECALL) instruction .................. 15 AutoStore Enable (ASENB) instruction ..................... 15 AutoStore Disable (ASDISB) instruction ................... 16 HOLD Pin Operation ................................................. 16 Maximum Ratings ........................................................... 17 Operating Range ............................................................. 17 DC Electrical Characteristics ........................................ 17 Data Retention and Endurance ..................................... 18 Capacitance .................................................................... 18 Thermal Resistance ........................................................ 18 AC Test Loads and Waveforms ..................................... 18 AC Test Conditions ........................................................ 18 AC Switching Characteristics ....................................... 19 Switching Waveforms .................................................... 19 AutoStore or Power-Up RECALL .................................. 20 Software Controlled STORE and RECALL Cycles ...... 21 Switching Waveforms .................................................... 21 Hardware STORE Cycle ................................................. 22 Switching Waveforms .................................................... 22 Ordering Information ...................................................... 23 Ordering Code Definitions ......................................... 23 Package Diagrams .......................................................... 24 Acronyms ........................................................................ 26 Document Conventions ................................................. 26 Units of Measure ....................................................... 26 Document History Page ................................................. 27 Sales, Solutions, and Legal Information ...................... 29 Worldwide Sales and Design Support ....................... 29 Products .................................................................... 29 PSoC Solutions ......................................................... 29 Page 2 of 29 Not Recommended for New Designs Contents CY14B256Q1 CY14B256Q2 CY14B256Q3 Pinouts Figure 1. 8-pin DFN pinout [2, 3, 4] CY14B256Q1 SO 1 2 WP 3 VSS 4 EXPOSED PAD CY14B256Q2 O 8 VCC CS 7 HOLD SO 6 SCK 5 SI 1 2 VCAP 3 VSS 4 Top View (not to scale) EXPOSED PAD 8 VCC 7 HOLD 6 SCK 5 SI Not Recommended for New Designs CS O Top View (not to scale) Figure 2. 16-pin SOIC pinout NC 1 16 VCC NC 2 15 NC NC 3 14 VCAP 13 SO 12 SI SCK CY14B256Q3 NC 4 WP 5 HOLD 6 11 NC 7 10 8 9 VSS Top View not to scale CS HSB Notes 2. HSB pin is not available in 8-pin DFN packages. 3. CY14B256Q1 part does not have VCAP pin and does not support AutoStore. 4. CY14B256Q2 part does not have WP pin. Document Number: 001-53882 Rev. *K Page 3 of 29 CY14B256Q1 CY14B256Q2 CY14B256Q3 Pin Name CS I/O Type Input SCK Input SI SO WP HOLD HSB Input Output Input Input Input/output VCAP Power supply NC No connect Power supply VSS Power supply VCC EXPOSED No connect PAD Description Chip select. Activates the device when pulled LOW. Driving this pin HIGH puts the device in low-power standby mode. Serial clock. Runs at speeds up to maximum of fSCK. Serial input is latched at the rising edge of this clock. Serial output is driven at the falling edge of the clock. Serial input. Pin for input of all SPI instructions and data. Serial output. Pin for output of data through SPI. Write protect. Implements hardware write protection in SPI. HOLD pin. Suspends serial operation. Hardware STORE busy: Output: Indicates busy status of nvSRAM when LOW. After each hardware and software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection optional). Input: Hardware STORE implemented by pulling this pin LOW externally. AutoStore capacitor. Supplies power to the nvSRAM during power loss to STORE data from the SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It must never be connected to ground. No connect: This pin is not connected to the die. Ground. Power supply (2.7 V to 3.6 V). The exposed pad on the bottom of 8-pin DFN package is not connected to the die. It is recommended to connect the exposed pad to VSS. Thermal vias can be used to increase thermal conductivity. Document Number: 001-53882 Rev. *K Page 4 of 29 Not Recommended for New Designs Pin Definitions CY14B256Q1 CY14B256Q2 CY14B256Q3 CY14B256Q1/CY14B256Q2/CY14B256Q3 is a 256-Kbit nvSRAM memory with a nonvolatile element in each memory cell. All the reads and writes to nvSRAM happen to the SRAM which gives nvSRAM the unique capability to handle infinite writes to the memory. The data in SRAM is secured by a STORE sequence that transfers the data in parallel to the nonvolatile QuantumTrap cells. A small capacitor (VCAP) is used to AutoStore the SRAM data in nonvolatile cells when power goes down providing power-down data security. The QuantumTrap nonvolatile elements built in the reliable SONOS technology make nvSRAM the ideal choice for secure data storage. The 256-Kbit memory array is organized as 32 K words × 8 bits. The memory is accessed through a standard SPI interface that enables very high clock speeds up to 40 MHz with zero cycle delay read and write cycles. This device supports SPI modes 0 and 3 (CPOL, CPHA = 0, 0 and 1, 1) and operates as SPI slave. The device is enabled using the chip select (CS) pin and accessed through serial input (SI), serial output (SO), and serial clock (SCK) pins. This device provides the feature for hardware and software write protection through the WP pin and WRDI instruction respectively along with mechanisms for block write protection (one quarter, one half, or full array) using BP0 and BP1 pins in the Status Register. Further, the HOLD pin is used to suspend any serial communication without resetting the serial sequence. CY14B256Q1/CY14B256Q2/CY14B256Q3 uses the standard SPI opcodes for memory access. In addition to the general SPI instructions for read and write, it provides four special instructions which enable access to four nvSRAM specific functions: STORE, RECALL, AutoStore Disable (ASDISB), and AutoStore Enable (ASENB). The major benefit of nvSRAM over serial EEPROMs is that all reads and writes to nvSRAM are performed at the speed of SPI bus with zero cycle delay. Therefore, no wait time is required after any of the memory accesses. The STORE and RECALL operations need finite time to complete and all memory accesses are inhibited during this time. While a STORE or RECALL operation is in progress, the busy status of the device is indicated by the Hardware STORE Busy (HSB) pin and also reflected on the RDY bit of the Status Register. The device is available in three different pin configurations that enable the user to choose a part which fits in best in their application. The feature summary is given in Table 1. Table 1. Feature Summary Feature CY14B256Q1 CY14B256Q2 CY14B256Q3 WP Yes No Yes VCAP No Yes Yes HSB No No Yes AutoStore No Yes Yes Power-Up RECALL Yes Yes Yes Hardware STORE No No Yes Software STORE Yes Yes Yes Software RECALL Yes Yes Yes SRAM Write Not Recommended for New Designs Device Operation All writes to nvSRAM are carried out on the SRAM and do not use up any endurance cycles of the nonvolatile memory. This enables user to perform infinite write operations. A write cycle is performed through the WRITE instruction. The WRITE instruction is issued through the SI pin of the nvSRAM and consists of the WRITE opcode, two bytes of address, and one byte of data. Write to nvSRAM is done at SPI bus speed with zero cycle delay. The device allows burst mode writes to be performed through SPI. This enables write operations on consecutive addresses without issuing a new WRITE instruction. When the last address in memory is reached in burst mode, the address rolls over to 0x0000 and the device continues to write. The SPI write cycle sequence is defined in the section Memory Access on page 13 of SPI Protocol Description. SRAM Read A read cycle is performed at the SPI bus speed and the data is read out with zero cycle delay after the READ instruction is executed. The READ instruction is issued through the SI pin of the nvSRAM and consists of the READ opcode and two bytes of address. The data is read out on the SO pin. This device allows burst mode reads to be performed through SPI. This enables reads on consecutive addresses without issuing a new READ instruction. When the last address in memory is reached in burst mode read, the address rolls over to 0x0000 and the device continues to read. The SPI read cycle sequence is defined explicitly in the section Memory Access on page 13 of SPI Protocol Description. Document Number: 001-53882 Rev. *K Page 5 of 29 CY14B256Q1 CY14B256Q2 CY14B256Q3 STORE Operation The AutoStore operation is a unique feature of nvSRAM which automatically stores the SRAM data to QuantumTrap cells during power-down. This STORE makes use of an external capacitor (VCAP) and enables the device to safely STORE the data in the nonvolatile memory when power goes down. During normal operation, the device draws current from VCC to charge the capacitor connected to the VCAP pin. When the voltage on the VCC pin drops below VSWITCH during power-down, the device inhibits all memory accesses to nvSRAM and automatically performs a conditional STORE operation using the charge from the VCAP capacitor. The AutoStore operation is not initiated if no write cycle has been performed since the last RECALL. Note If a capacitor is not connected to VCAP pin, AutoStore must be disabled by issuing the AutoStore Disable instruction specified in AutoStore Enable (ASENB) instruction on page 15. If AutoStore is enabled without a capacitor on the VCAP pin, the device attempts an AutoStore operation without sufficient charge to complete the STORE. This corrupts the data stored in the nvSRAM and Status Register. To resume normal functionality, the WRSR instruction must be issued to update the nonvolatile bits BP0, BP1 and WPEN in the Status Register. Figure 3 shows the proper connection of the storage capacitor (VCAP) for AutoStore operation. Refer to DC Electrical Characteristics on page 17 for the size of the VCAP. Note CY14B256Q1 does not support AutoStore operation. The user must perform Software STORE operation by using the SPI STORE instruction to secure the data. 0.1 uF VCC CS VCAP VSS VCAP Software STORE Operation Software STORE enables the user to trigger a STORE operation through a special SPI instruction. STORE operation is initiated by executing STORE instruction irrespective of whether a write has been performed since the last NV operation. A STORE cycle takes tSTORE time to complete, during which all the memory accesses to nvSRAM are inhibited. The RDY bit of the Status Register or the HSB pin may be polled to find the ready or busy status of the nvSRAM. After the tSTORE cycle time is completed, the SRAM is activated again for read and write operations. Hardware STORE and HSB Pin Operation The HSB pin in CY14B256Q3 is used to control and acknowledge STORE operations. If no STORE or RECALL is in progress, this pin can be used to request a Hardware STORE cycle. When the HSB pin is driven LOW, nvSRAM conditionally initiates a STORE operation after tDELAY duration. An actual STORE cycle starts only if a write to the SRAM is performed since the last STORE or RECALL cycle. Reads and writes to the memory are inhibited for tSTORE duration or as long as HSB pin is LOW. The HSB pin also acts as an open drain driver (internal 100 k weak pull-up resistor) that is internally driven LOW to indicate a busy condition when the STORE (initiated by any means) is in progress. Note After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then remains HIGH by an internal 100 k pull-up resistor. Note For successful last data byte STORE, a hardware store should be initiated at least one clock cycle after the last data bit D0 is received. Upon completion of the STORE operation, the nvSRAM memory access is inhibited for tLZHSB time after HSB pin returns HIGH. The HSB pin must be left unconnected if not used. Document Number: 001-53882 Rev. *K Page 6 of 29 Not Recommended for New Designs AutoStore Operation VCC 10 kOhm STORE operation transfers the data from the SRAM to the nonvolatile QuantumTrap cells. The device STOREs data to the nonvolatile cells using one of the three STORE operations: AutoStore, activated on device power-down; Software STORE, activated by a STORE instruction; and Hardware STORE, activated by the HSB. During the STORE cycle, an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, read/write to CY14B256Q1/CY14B256Q2/CY14B256Q3 is inhibited until the cycle is completed. The HSB signal or the RDY bit in the Status Register can be monitored by the system to detect if a STORE or Software RECALL cycle is in progress. The busy status of nvSRAM is indicated by HSB being pulled LOW or RDY bit being set to ‘1’. To avoid unnecessary nonvolatile STOREs, AutoStore and Hardware STORE operations are ignored unless at least one write operation has taken place since the most recent STORE or RECALL cycle. However, software initiated STORE cycles are performed regardless of whether a write operation has taken place. Figure 3. AutoStore Mode CY14B256Q1 CY14B256Q2 CY14B256Q3 Note CY14B256Q1/CY14B256Q2 do not have HSB pin. RDY bit of the SPI Status Register may be probed to determine the ready or busy status of nvSRAM. Serial Peripheral Interface RECALL Operation The SPI is a four-pin interface with chip select (CS), serial input (SI), serial output (SO), and serial clock (SCK) pins. CY14B256Q1/CY14B256Q2/CY14B256Q3 provides serial access to nvSRAM through SPI interface. The SPI bus on this device can run at speeds up to 40 MHz. Internally, RECALL is a two step procedure. First, the SRAM data is cleared. Next, the nonvolatile information is transferred into the SRAM cells. All memory accesses are inhibited while a RECALL cycle is in progress. The RECALL operation does not alter the data in the nonvolatile elements. Hardware RECALL (Power-Up) During power-up, when VCC crosses VSWITCH, an automatic RECALL sequence is initiated, which transfers the content of nonvolatile memory on to the SRAM. The data would previously have been stored on the nonvolatile memory through a STORE sequence. The SPI is a synchronous serial interface which uses clock and data pins for memory access and supports multiple devices on the data bus. A device on SPI bus is activated using the CS pin. The relationship between chip select, clock, and data is dictated by the SPI mode. This device supports SPI modes 0 and 3. In both these modes, data is clocked into the nvSRAM on the rising edge of SCK starting from the first rising edge after CS goes active. A Power-Up RECALL cycle takes tFA time to complete and the memory access is disabled during this time. HSB pin is used to detect the ready status of the device. The SPI protocol is controlled by opcodes. These opcodes specify the commands from the bus master to the slave device. After CS is activated the first byte transferred from the bus master is the opcode. Following the opcode, any addresses and data are then transferred. The CS must go inactive after an operation is complete and before a new opcode can be issued. The commonly used terms used in SPI protocol are as follows: Software RECALL SPI Master Software RECALL enables the user to initiate a RECALL operation to restore the content of nonvolatile memory on to the SRAM. A Software RECALL is issued by using the SPI instruction for RECALL. The SPI master device controls the operations on a SPI bus. A SPI bus may have only one master with one or more slave devices. All the slaves share the same SPI bus lines and the master may select any of the slave devices using the CS pin. All the operations must be initiated by the master activating a slave device by pulling the CS pin of the slave LOW. The master also generates the SCK and all the data transmission on SI and SO lines are synchronized with this clock. A Software RECALL takes tRECALL time to complete during which all memory accesses to nvSRAM are inhibited. The controller must provide sufficient delay for the RECALL operation to complete before issuing any memory access instructions. Disabling and Enabling AutoStore If the application does not require the AutoStore feature, it can be disabled by using the ASDISB instruction. If this is done, the nvSRAM does not perform a STORE operation at power-down. AutoStore can be re-enabled by using the ASENB instruction. However, these operations are not nonvolatile and if the user needs this setting to survive the power cycle, a STORE operation must be performed following AutoStore Disable or Enable operation. Note CY14B256Q2/CY14B256Q3 comes from the factory with AutoStore enabled and CY14B256Q1/CY14B256Q2/CY14B256Q3 comes from the factory with 0x00 written in all cells. In CY14B256Q1, VCAP pin is not present and AutoStore option is not available. The AutoStore Enable and Disable instructions to CY14B256Q1 are ignored. Note If AutoStore is disabled and VCAP is not required, then the VCAP pin must be left open. The VCAP pin must never be connected to ground. The Power-Up RECALL operation cannot be disabled in any case. SPI Slave The SPI slave device is activated by the master through the chip select line. A slave device gets the SCK as an input from the SPI master and all the communication is synchronized with this clock. SPI slave never initiates a communication on the SPI bus and acts on the instruction from the master. CY14B256Q1/CY14B256Q2/CY14B256Q3 operates as a SPI slave and may share the SPI bus with other SPI slave devices. Chip Select (CS) For selecting any slave device, the master needs to pull-down the corresponding CS pin. Any instruction can be issued to a slave device only while the CS pin is LOW. When the device is not selected, data through the SI pin is ignored and the serial output pin (SO) remains in a high-impedance state. Note A new instruction must begin with the falling edge of CS. Therefore, only one opcode can be issued for each active chip select cycle. Serial Clock (SCK) Serial clock is generated by the SPI master and the communication is synchronized with this clock after CS goes LOW. CY14B256Q1/CY14B256Q2/CY14B256Q3 enables SPI modes 0 and 3 for data communication. In both these modes, the inputs Document Number: 001-53882 Rev. *K Page 7 of 29 Not Recommended for New Designs A RECALL operation transfers the data stored in the nonvolatile QuantumTrap elements to the SRAM. A RECALL may be initiated in two ways: Hardware RECALL, initiated on power-up; and Software RECALL, initiated by a SPI RECALL instruction. SPI Overview CY14B256Q1 CY14B256Q2 CY14B256Q3 are latched by the slave device on the rising edge of SCK and outputs are issued on the falling edge. Therefore, the first rising edge of SCK signifies the arrival of the first bit (MSB) of SPI instruction on the SI pin. Further, all data inputs and outputs are synchronized with SCK. 15-bits, it implies that the first MSB that is fed in is ignored by the device. Although this bit is ‘don’t care’, Cypress recommends that this bit is treated as 0 to enable seamless transition to higher memory densities. Data Transmission - SI and SO After the slave device is selected with CS going LOW, the first byte received is treated as the opcode for the intended operation. CY14B256Q1/CY14B256Q2/CY14B256Q3 uses the standard opcodes for memory accesses. In addition to the memory accesses, it provides additional opcodes for the nvSRAM specific functions: STORE, RECALL, AutoStore Enable, and AutoStore Disable. Refer to Table 2 on page 10 for details. SPI data bus consists of two lines, SI and SO, for serial data communication. The SI is also referred to as Master Out Slave In (MOSI) and SO is referred to as Master In Slave Out (MISO). The master issues instructions to the slave through the SI pin, while the slave responds through the SO pin. Multiple slave devices may share the SI and SO lines as described earlier. CY14B256Q1/CY14B256Q2/CY14B256Q3 has two separate pins for SI and SO, which can be connected with the master as shown in Figure 4 on page 8. Invalid Opcode If an invalid opcode is received, the opcode is ignored and the device ignores any additional serial data on the SI pin till the next falling edge of CS and the SO pin remains tristated. Most Significant Bit (MSB) The SPI protocol requires that the first bit to be transmitted is the most significant bit (MSB). This is valid for both address and data transmission. Status Register CY14B256Q1/CY14B256Q2/CY14B256Q3 has an 8-bit Status Register. The bits in the Status Register are used to configure the SPI bus. These bits are described in the Table 4 on page 11. The 256-Kbit serial nvSRAM requires a 2-byte address for any read or write operation. However, since the address is only Figure 4. System Configuration Using SPI nvSRAM SCK M OSI M IS O SCK SI SO SCK SI SO u C o n tro lle r C Y14B 256Q x CS HO LD C Y14B 256Q x CS HO LD CS1 HO LD 1 CS2 HO LD 2 Document Number: 001-53882 Rev. *K Page 8 of 29 Not Recommended for New Designs Serial Opcode CY14B256Q1 CY14B256Q2 CY14B256Q3 SPI Modes ■ SPI Mode 0 (CPOL=0, CPHA=0) ■ SPI Mode 3 (CPOL=1, CPHA=1) For both these modes, the input data is latched in on the rising edge of SCK starting from the first rising edge after CS goes active. If the clock starts from a HIGH state (in mode 3), the first rising edge after the clock toggles, is considered. The output data is available on the falling edge of SCK. Figure 5. SPI Mode 0 CS 0 1 2 3 4 5 6 7 SCK SI 7 6 5 4 3 2 1 Not Recommended for New Designs CY14B256Q1/CY14B256Q2/CY14B256Q3 may be driven by a microcontroller with its SPI peripheral running in either of the following two modes: 0 MSB LSB The two SPI modes are shown in Figure 5 and Figure 6. The status of clock when the bus master is in standby mode and not transferring data is: ■ SCK remains at 0 for Mode 0 ■ SCK remains at 1 for Mode 3 CPOL and CPHA bits must be set in the SPI controller for the either Mode 0 or Mode 3. The device detects the SPI mode from the status of SCK pin when the device is selected by bringing the CS pin LOW. If SCK pin is LOW when the device is selected, SPI Mode 0 is assumed and if SCK pin is HIGH, it works in SPI Mode 3. Figure 6. SPI Mode 3 CS 0 SI 7 MSB Document Number: 001-53882 Rev. *K 1 2 3 4 5 6 7 SCK 6 5 4 3 2 1 0 LSB Page 9 of 29 SPI Operating Features Active Power and Standby Power Modes Power-Up When CS is LOW, the device is selected and is in the active power mode. The device consumes ICC current, as specified in DC Electrical Characteristics on page 17. When CS is HIGH, the device is deselected and the device goes into the standby power mode if a STORE or RECALL cycle is not in progress. If a STORE or RECALL cycle is in progress, the device goes into the standby power mode after the STORE or RECALL cycle is completed. In the standby power mode, the current drawn by the device drops to ISB. Power-up is defined as the condition when the power supply is turned on and VCC crosses Vswitch voltage. During this time, the CS must be allowed to follow the VCC voltage. Therefore, CS must be connected to VCC through a suitable pull-up resistor. As a built in safety feature, CS is both edge sensitive and level sensitive. After power-up, the device is not selected until a falling edge is detected on CS. This ensures that CS must have been HIGH, before going LOW to start the first operation. As described earlier, nvSRAM performs a Power-Up RECALL operation after power-up and therefore, all memory accesses are disabled for tFA duration after power-up. The HSB pin can be probed to check the Ready or Busy status of nvSRAM after power-up. Power On Reset A power on reset (POR) circuit is included to prevent inadvertent writes. At power-up, the device does not respond to any instruction until the VCC reaches the POR threshold voltage (VSWITCH). After VCC transitions the POR threshold, the device is internally reset and performs an Power-Up RECALL operation. During Power-Up RECALL all device accesses are inhibited. The device is in the following state after POR: ■ Deselected (after power-up, a falling edge is required on CS before any instructions are started). ■ Standby power mode ■ Not in the HOLD condition Status Register state: ❐ Write Enable (WEN) bit is reset to ‘0’. ❐ WPEN, BP1, BP0 unchanged from previous STORE operation ❐ Don’t care bits 4–6 are reset to ‘0’. The WPEN, BP1, and BP0 bits of the Status Register are nonvolatile bits and remain unchanged from the previous STORE operation. SPI Functional Description The CY14B256Q1/CY14B256Q2/CY14B256Q3 uses an 8-bit instruction register. Instructions and their operation codes are listed in Table 2. All instructions, addresses, and data are transferred with the MSB first and start with a HIGH to LOW CS transition. There are, in all, 10 SPI instructions that provide access to most of the functions in nvSRAM. Further, the WP, HOLD and HSB pins provide additional functionality driven through hardware. Table 2. Instruction Set Instruction Category Status Register control instructions Instruction Name 0000 0110 Set write enable latch WRDI 0000 0100 Reset write enable latch RDSR 0000 0101 Read Status Register WRSR 0000 0001 Write Status Register SRAM Read/Write instructions READ 0000 0011 Read data from memory array WRITE 0000 0010 Write data to memory array Special NV instructions STORE 0011 1100 Software STORE RECALL 0110 0000 Software RECALL ASENB 0101 1001 AutoStore Enable ASDISB 0001 1001 AutoStore Disable Power-Down At power-down (continuous decay of VCC), when VCC drops from the normal operating voltage and below the VSWITCH threshold voltage, the device stops responding to any instruction sent to it. If a write cycle is in progress and the last data bit D0 has been received when the power goes down, it is allowed tDELAY time to complete the write. After this, all memory accesses are inhibited and a conditional AutoStore operation is performed (AutoStore is not performed if no writes have happened since the last RECALL cycle). This feature prevents inadvertent writes to nvSRAM from happening during power-down. However, to completely avoid the possibility of inadvertent writes during power-down, ensure that the device is deselected and is in standby power mode, and the CS follows the voltage applied on VCC. Document Number: 001-53882 Rev. *K Operation WREN ■ Before selecting and issuing instructions to the memory, a valid and stable VCC voltage must be applied. This voltage must remain valid until the end of the instruction transmission. Opcode Reserved - Reserved - 0001 1110 The SPI instructions are divided based on their functionality in the following types: ❐ Status Register access: RDSR and WRSR instructions ❐ Write protection functions: WREN and WRDI instructions along with WP pin and WEN, BP0, and BP1 bits ❐ SRAM memory access: READ and WRITE instructions ❐ nvSRAM special instructions: STORE, RECALL, ASENB, and ASDISB Page 10 of 29 Not Recommended for New Designs CY14B256Q1 CY14B256Q2 CY14B256Q3 CY14B256Q1 CY14B256Q2 CY14B256Q3 The Status Register bits are listed in Table 3. The Status Register consists of a Ready bit (RDY) and data protection bits BP1, BP0, WEN, and WPEN. The RDY bit can be polled to check the Ready or Busy status while a nvSRAM STORE or Software RECALL cycle is in progress. The Status Register can be modified by WRSR instruction and read by RDSR instruction. However, only the WPEN, BP1, and BP0 bits of the Status Register can be modified by using the WRSR instruction. The WRSR instruction has no effect on WEN and RDY bits. The default value shipped from the factory for WEN, BP0, BP1, bits 4–6 and WPEN bits is ‘0’. Table 3. Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WPEN (0) X (0) X (0) X (0) BP1 (0) BP0 (0) WEN (0) RDY Table 4. Status Register Bit Definition Bit Definition Description Bit 0 (RDY) Ready Read only bit indicates the ready status of device to perform a memory access. This bit is set to ‘1’ by the device while a STORE or Software RECALL cycle is in progress. Bit 1 (WEN) Write Enable WEN indicates if the device is write enabled. This bit defaults to ‘0’ (disabled) on power-up. WEN = '1' --> Write enabled WEN = '0' --> Write disabled Bit 2 (BP0) Block Protect bit ‘0’ Used for block protection. For details see Table 5 on page 13. Bit 3 (BP1) Block Protect bit ‘1’ Used for block protection. For details see Table 5 on page 13. Bit 4-6 Don’t care Bits are writable and volatile. On power-up, bits are written with ‘0’. Bit 7 (WPEN) Write Protect Enable bit Used for enabling the function of Write Protect Pin (WP). For details see Table 6 on page 13. Read Status Register (RDSR) Instruction The Read Status Register (RDSR) instruction provides access to the status register. This instruction is used to probe the write enable status of the device or the Ready status of the device. RDY bit is set by the device to ‘1’ whenever a STORE or Software RECALL cycle is in progress. The block protection and WPEN bits indicate the extent of protection employed. This instruction is issued after the falling edge of CS using the opcode for RDSR. Write Status Register (WRSR) Instruction The WRSR instruction enables the user to write to the Status Register. However, this instruction cannot be used to modify bit 0 and bit 1 (RDY and WEN). The BP0 and BP1 bits can be used to select one of four levels of block protection. Further, WPEN bit must be set to ‘1’ to enable the use of Write Protect (WP) pin. Document Number: 001-53882 Rev. *K WRSR instruction is a write instruction and needs writes to be enabled (WEN bit set to ‘1’) using the WREN instruction before it is issued. The instruction is issued after the falling edge of CS using the opcode for WRSR followed by 8 bits of data to be stored in the Status Register. Since only bits 2, 3, and 7 can be modified by WRSR instruction, it is recommended to leave the bits 4-6 as ‘0’ while writing to the Status Register. Note In CY14B256Q1/CY14B256Q2/CY14B256Q3, the values written to Status Register are saved to nonvolatile memory only after a STORE operation. If AutoStore is disabled (or while using CY14B256Q1), any modifications to the Status Register must be secured by performing a Software STORE operation. Note CY14B256Q2 does not have WP pin. Any modification to bit 7 of the Status Register has no effect on the functionality of CY14B256Q2. Page 11 of 29 Not Recommended for New Designs Status Register CY14B256Q1 CY14B256Q2 CY14B256Q3 Figure 7. Read Status Register (RDSR) Instruction Timing CS 0 1 2 3 4 5 6 7 0 1 1 0 MSB 2 3 4 5 6 7 SI 0 0 0 0 0 1 0 HI-Z SO LSB D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB Data Figure 8. Write Status Register (WRSR) Instruction Timing CS 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 SCK Data in Opcode SI SO 0 0 0 0 0 0 0 X X D3 D2 X X LSB HI-Z Write Protection and Block Protection CY14B256Q1/CY14B256Q2/CY14B256Q3 provides features for both software and hardware write protection using WRDI instruction and WP. Additionally, this device also provides block protection mechanism through BP0 and BP1 pins of the Status Register. The write enable and disable status of the device is indicated by WEN bit of the Status Register. The write instructions (WRSR and WRITE) and nvSRAM special instruction (STORE, RECALL, ASENB, and ASDISB) need the write to be enabled (WEN bit = 1) before they can be issued. Write Enable (WREN) Instruction On power-up, the device is always in the write disable state. The following WRITE, WRSR, or nvSRAM special instruction must therefore be preceded by a Write Enable instruction. If the device is not write enabled (WEN = ‘0’), it ignores the write instructions and returns to the standby state when CS is brought HIGH. A new CS falling edge is required to re-initiate serial communication. The instruction is issued following the falling Document Number: 001-53882 Rev. *K 1 D7 X MSB edge of CS. When this instruction is used, the WEN bit of Status Register is set to ‘1’. WEN bit defaults to ‘0’ on power-up. Note After completion of a write instruction (WRSR or WRITE) or nvSRAM special instruction (STORE, RECALL, ASENB, and ASDISB) instruction, WEN bit is cleared to ‘0’. This is done to provide protection from any inadvertent writes. Therefore, WREN instruction must be used before a new write instruction is issued. Figure 9. WREN Instruction CS 0 1 2 3 4 5 6 7 SCK SI SO 0 0 0 0 0 1 1 0 HI-Z Page 12 of 29 Not Recommended for New Designs SCK CY14B256Q1 CY14B256Q2 CY14B256Q3 Write Disable (WRDI) Instruction Table 6 summarizes all the protection features of this device. Write Disable instruction disables the write by clearing the WEN bit to ‘0’ in order to protect the device against inadvertent writes. This instruction is issued following the falling edge of CS followed by opcode for WRDI instruction. The WEN bit is cleared on the rising edge of CS following a WRDI instruction. Table 6. Write Protection Operation CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 0 0 HI-Z SO X X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 LOW 1 Protected Writable Protected 1 HIGH 1 Protected Writable Writable Memory Access All memory accesses are done using the READ and WRITE instructions. These instructions cannot be used while a STORE or RECALL cycle is in progress. A STORE cycle in progress is indicated by the RDY bit of the Status Register and the HSB pin. Read Sequence (READ) instruction Block Protection Block protection is provided using the BP0 and BP1 pins of the Status Register. These bits can be set using WRSR instruction and probed using the RDSR instruction. The nvSRAM is divided into four array segments. One-quarter, one-half, or all of the memory segments can be protected. Any data within the protected segment is read only. Table 5 shows the function of Block Protect bits. Table 5. Block Write Protect Bits Level WP Status Register Bits Array Addresses Protected BP1 BP0 0 0 0 None 1 (1/4) 0 1 0x6000–0x7FFF 2 (1/2) 1 0 0x4000–0x7FFF 3 (All) 1 1 0x0000–0x7FFF Write Protect (WP) Pin The write protect pin (WP) is used to provide hardware write protection. WP pin enables all normal read and write operations when held HIGH. When the WP pin is brought LOW and WPEN bit is ‘1’, all write operations to the Status Register are inhibited. The hardware write protection function is blocked when the WPEN bit is ‘0’. This enables the user to install the device in a system with the WP pin tied to ground, and still write to the Status Register. WP pin can be used along with WPEN and Block Protect bits (BP1 and BP0) of the Status Register to inhibit writes to memory. When WP pin is LOW and WPEN is set to ‘1’, any modifications to the Status Register are disabled. Therefore, the memory is protected by setting the BP0 and BP1 bits and the WP pin inhibits any modification of the Status Register bits, providing hardware write protection. Note WP going LOW when CS is still LOW has no effect on any of the ongoing write operations to the Status Register. CY14B256Q2 does not have WP pin and therefore does not provide hardware write protection. Document Number: 001-53882 Rev. *K The read operations on this device are performed by giving the instruction on the SI pin and reading the output on SO pin. The following sequence needs to be followed for a read operation: After the CS line is pulled LOW to select a device, the read opcode is transmitted through the SI line followed by two bytes of address. The MSB bit (A15) of the address is a “don’t care”. After the last address bit is transmitted on the SI pin, the data (D7–D0) at the specific address is shifted out on the SO line on the falling edge of SCK starting with D7. Any other data on SI line after the last address bit is ignored. CY14B256Q1/CY14B256Q2/CY14B256Q3 allows reads to be performed in bursts through SPI which can be used to read consecutive addresses without issuing a new READ instruction. If only one byte is to be read, the CS line must be driven HIGH after one byte of data comes out. However, the read sequence may be continued by holding the CS line LOW and the address is automatically incremented and data continues to shift out on SO pin. When the last data memory address (0x7FFF) is reached, the address rolls over to 0x0000 and the device continues to read. Write Sequence (WRITE) instruction The write operations on this device are performed through the SI pin. To perform a write operation, if the device is write disabled, then the device must first be write enabled through the WREN instruction. When the writes are enabled (WEN = ‘1’), WRITE instruction is issued after the falling edge of CS. A WRITE instruction constitutes transmitting the WRITE opcode on SI line followed by 2 bytes of address and the data (D7-D0) which is to be written. The MSB bit (A15) of the address is a “don’t care”. CY14B256Q1/CY14B256Q2/CY14B256Q3 enables writes to be performed in bursts through SPI which can be used to write consecutive addresses without issuing a new WRITE instruction. If only one byte is to be written, the CS line must be driven HIGH after the D0 (LSB of data) is transmitted. However, if more bytes are to be written, CS line must be held LOW and address is incremented automatically. The following bytes on the SI line are treated as data bytes and written in the successive addresses. When the last data memory address (0x7FFF) is reached, the address rolls over to 0x0000 and the device continues to write. The WEN bit is reset to ‘0’ on completion of a WRITE sequence. Page 13 of 29 Not Recommended for New Designs Figure 10. WRDI Instruction Unprotected Status WEN Protected Blocks Blocks Register WPEN CY14B256Q1 CY14B256Q2 CY14B256Q3 roll over takes the burst write to unprotected space, it resumes writes. The same operation is true if a burst write is initiated within a write protected block. Note When a burst write reaches a protected block address, it continues the address increment into the protected space but does not write any data to the protected memory. If the address Figure 11. Read Instruction Timing 1 2 3 4 5 6 0 7 1 2 3 4 5 6 7 SCK 0 0 0 0 0 12 13 14 15 0 1 2 3 4 5 6 7 15-bit Address Op-Code SI ~ ~ ~ ~ 0 0 1 X 14 13 12 11 10 9 MSB 1 8 3 2 1 0 LSB HI-Z SO D7 D6 D5 D4 D3 D2 D1 D0 LSB Data MSB Figure 12. Burst Mode Read Instruction Timing 2 3 4 5 6 0 7 1 2 3 4 5 6 7 Op-Code SI 0 0 0 0 0 12 13 14 15 0 1 2 3 4 5 6 7 0 0 7 ~ ~ 1 1 2 3 4 5 6 7 15-bit Address 1 0 1 X 14 13 12 11 10 9 8 MSB ~ ~ 0 SCK ~ ~ CS 3 2 1 0 LSB Data Byte N ~ ~ Data Byte 1 HI-Z SO D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 MSB MSB LSB LSB Figure 13. Write Instruction Timing CS 1 2 3 4 5 7 6 0 1 2 3 4 5 6 7 SCK Op-Code SI 0 0 0 0 0 0 ~ ~ ~ ~ 0 12 13 14 15 0 1 2 3 4 5 6 7 15-bit Address 1 0 X 14 13 12 11 10 9 MSB SO Document Number: 001-53882 Rev. *K 8 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 LSB MSB Data LSB HI-Z Page 14 of 29 Not Recommended for New Designs CS CY14B256Q1 CY14B256Q2 CY14B256Q3 Figure 14. Burst Mode Write Instruction Timing CS 3 4 5 6 0 7 1 2 3 4 5 6 7 12 13 14 15 0 1 2 3 4 5 6 7 0 7 0 1 2 0 0 0 0 1 0 X 14 13 12 11 10 9 8 3 2 1 0 6 7 D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0 LSB MSB MSB 5 ~ ~ 0 15-bit Address ~ ~ 0 SI 4 Data Byte N Data Byte 1 Op-Code 3 LSB HI-Z SO nvSRAM Special Instructions Software RECALL (RECALL) instruction CY14B256Q1/CY14B256Q2/CY14B256Q3 provides four special instructions which enables access to the nvSRAM specific functions: STORE, RECALL, ASDISB, and ASENB. Table 7 lists these instructions. Table 7. nvSRAM Special Instructions Function Name Opcode STORE 0011 1100 Software STORE Operation RECALL 0110 0000 Software RECALL ASENB 0101 1001 AutoStore Enable ASDISB 0001 1001 AutoStore Disable When a RECALL instruction is executed, nvSRAM performs a Software RECALL operation. To issue this instruction, the device must be write enabled (WEN = ‘1’). The instruction is performed by transmitting the RECALL opcode on the SI pin following the falling edge of CS. The WEN bit is cleared on the positive edge of CS following the RECALL instruction. Figure 16. Software RECALL Operation CS 0 1 2 3 4 5 6 7 SCK Software STORE (STORE) instruction When a STORE instruction is executed, nvSRAM performs a Software STORE operation. The STORE operation is performed irrespective of whether a write has taken place since the last STORE or RECALL operation. To issue this instruction, the device must be write enabled (WEN bit = ‘1’). The instruction is performed by transmitting the STORE opcode on the SI pin following the falling edge of CS. The WEN bit is cleared on the positive edge of CS following the STORE instruction. Figure 15. Software STORE Operation CS 0 1 2 3 4 5 6 7 SCK SI SO 0 0 1 1 1 1 HI-Z Document Number: 001-53882 Rev. *K 0 0 SI SO 0 1 1 0 0 0 0 0 HI-Z AutoStore Enable (ASENB) instruction The AutoStore Enable instruction enables the AutoStore on CY14B256Q1. This setting is not nonvolatile and needs to be followed by a STORE sequence if this is desired to survive the power cycle. To issue this instruction, the device must be write enabled (WEN = ‘1’). The instruction is performed by transmitting the ASENB opcode on the SI pin following the falling edge of CS. The WEN bit is cleared on the positive edge of CS following the ASENB instruction. Note If ASDISB and ASENB instructions are executed in CY14B256Q1, the device is busy for the duration of software sequence processing time (tSS). However, ASDISB and ASENB instructions have no effect on CY14B256Q1 as AutoStore is internally disabled. Page 15 of 29 Not Recommended for New Designs 2 ~ ~ 1 ~ ~ 0 SCK CY14B256Q1 CY14B256Q2 CY14B256Q3 0 1 2 3 4 5 6 7 SCK SI 0 1 0 1 1 0 0 1 HI-Z SO AutoStore Disable (ASDISB) instruction AutoStore is enabled by default in CY14B256Q2/CY14B256Q3. The ASDISB instruction disables the AutoStore. This setting is not nonvolatile and needs to be followed by a STORE sequence if this is desired to survive the power cycle. To issue this instruction, the device must be write enabled (WEN = ‘1’). The instruction is performed by transmitting the ASDISB opcode on the SI pin following the falling edge of CS. The WEN bit is cleared on the positive edge of CS following the ASDISB instruction. Figure 19. HOLD Operation CS SCK ~ ~ CS The HOLD pin is used to pause the serial communication. When the device is selected and a serial sequence is underway, HOLD is used to pause the serial communication with the master device without resetting the ongoing serial sequence. To pause, the HOLD pin must be brought LOW when the SCK pin is LOW. CS pin must remain LOW along with HOLD pin to pause serial communication. While the device serial communication is paused, inputs to the SI pin are ignored and the SO pin is in the high impedance state. To resume serial communication, the HOLD pin must be brought HIGH when the SCK pin is LOW (SCK may toggle during HOLD). HOLD SO Figure 18. AutoStore Disable Operation CS 0 1 2 3 4 5 6 7 SCK SI SO 0 0 0 1 1 0 0 1 HI-Z Document Number: 001-53882 Rev. *K Page 16 of 29 Not Recommended for New Designs HOLD Pin Operation Figure 17. AutoStore Enable Operation CY14B256Q1 CY14B256Q2 CY14B256Q3 Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Maximum accumulated storage time Transient voltage (< 20 ns) on any pin to ground potential ................. –2.0 V to VCC + 2.0 V Package power dissipation capability (TA = 25 °C) ................................................. 1.0 W Surface mount lead soldering temperature (3 seconds) ......................................... +260 C At 150 C ambient temperature ...................... 1000 h DC output current (1 output at a time, 1 s duration) ... 15 mA At 85 C ambient temperature .................... 20 Years Static discharge voltage (per MIL-STD-883, method 3015) ......................... > 2001 V Maximum junction temperature ................................. 150 C Supply voltage on VCC relative to VSS .........–0.5 V to +4.1 V DC voltage applied to outputs in high Z state ..................................... –0.5 V to VCC + 0.5 V Input voltage ....................................... –0.5 V to VCC + 0.5 V Latch up current .................................................... > 200 mA Operating Range Range Industrial Ambient Temperature VCC –40 C to +85 C 2.7 V to 3.6 V DC Electrical Characteristics Over the Operating Range Parameter VCC ICC1 ICC2 ICC4 ISB IIX[6] IOZ VIH VIL VOH VOL VCAP[7] VVCAP[8, 9] Description Power supply voltage Average Vcc current Average VCC current during STORE Average VCAP current during AutoStore cycle VCC standby current Input leakage current (except HSB) Input leakage current (for HSB) Off state output leakage current Input HIGH voltage Input LOW voltage Output HIGH voltage Output LOW voltage Storage capacitor Test Conditions At fSCK = 40 MHz. Values obtained without output loads (IOUT = 0 mA) All inputs don’t care, VCC = Max. Average current for duration tSTORE All inputs don’t care. Average current for duration tSTORE CS > (VCC – 0.2 V). VIN < 0.2 V or > (VCC – 0.2 V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz VCC = Max, VSS < VIN < VCC VCC = Max, VSS < VIN < VCC VCC = Max, VSS < VOUT < VCC IOUT = –2 mA IOUT = 4 mA Between VCAP pin and VSS Maximum voltage driven on VCAP VCC = Max pin by the device Min 2.7 – Typ [5] 3.0 – Max 3.6 10 Unit V mA – – 10 mA – – 5 mA – – 5 mA –1 – +1 µA –100 –1 2.0 VSS – 0.5 2.4 – 61 – – – – – – 68 +1 +1 VCC + 0.5 0.8 – 0.4 180 µA µA V V V V µF – – VCC V Notes 5. Typical values are at 25 °C, VCC= VCC(Typ). Not 100% tested. 6. The HSB pin has IOUT = –2 µA for VOH of 2.4 V when both active high and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This parameter is characterized but not tested. 7. Min VCAP value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max VCAP value guarantees that the capacitor on VCAP is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore it is always recommended to use a capacitor within the specified min and max limits. Refer application note AN43593 for more details on VCAP options. 8. Maximum voltage on VCAP pin (VVCAP) is provided for guidance when choosing the VCAP capacitor. The voltage rating of the VCAP capacitor across the operating temperature range should be higher than the VVCAP voltage. 9. These parameters are guaranteed by design and are not tested. Document Number: 001-53882 Rev. *K Page 17 of 29 Not Recommended for New Designs Maximum Ratings CY14B256Q1 CY14B256Q2 CY14B256Q3 Data Retention and Endurance Parameter Description DATAR Data retention NVC Nonvolatile STORE operations Min Unit 20 Years 1,000 K Max Unit 6 pF 8 pF Capacitance Parameter [10] Description Test Conditions TA = 25 C, f = 1 MHz, VCC = VCC(Typ) CIN Input capacitance COUT Output pin capacitance Thermal Resistance Parameter [10] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 16-pin SOIC 8-pin DFN Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 55.17 17.7 C/W 2.64 18.8 C/W AC Test Loads and Waveforms Figure 20. AC Test Loads and Waveforms 577 577 3.0 V 3.0 V R1 R1 OUTPUT OUTPUT 30 pF R2 789 5 pF R2 789 AC Test Conditions Input pulse levels ................................................... 0 V to 3 V Input rise and fall times (10% to 90%) ........................ < 3 ns Input and output timing reference levels ....................... 1.5 V Note 10. These parameters are guaranteed by design and are not tested. Document Number: 001-53882 Rev. *K Page 18 of 29 Not Recommended for New Designs Over the Operating Range CY14B256Q1 CY14B256Q2 CY14B256Q3 AC Switching Characteristics Over the Operating Range Parameters [11] fSCK tCL tCH tCS tCSS tCSH tSD tHD tHH tSH tCO tHHZ[12] tHLZ[12] tOH tHZCS 40 MHz Description Alt. Parameter Min Max Unit fSCK tWL tWH tCE tCES tCEH tSU tH Clock frequency, SCK Clock pulse width LOW Clock pulse width HIGH CS high time CS setup time CS hold time Data in setup time Data in hold time – 11 11 20 10 10 5 5 40 – – – – – – – MHz ns ns ns ns ns ns ns tHD tCD tV tHZ tLZ tHO tDIS HOLD hold time HOLD setup time Output valid HOLD to output High-Z HOLD to output Low-Z Output hold time Output disable time 5 5 – – – 0 – – – 9 15 15 – 25 ns ns ns ns ns ns ns Switching Waveforms Figure 21. Synchronous Data Timing (Mode 0) tCS CS tCSS tCH tCL tCSH SCK tSD SI tHD VALID IN VALID IN VALID IN tOH tCO SO HI-Z tHZCS HI-Z Figure 22. HOLD Timing ~ ~ CS SCK tHH tHH tSH tSH HOLD tHHZ tHLZ SO Notes 11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH and load capacitance shown in Figure 20 on page 18. 12. These parameters are guaranteed by design and are not tested. Document Number: 001-53882 Rev. *K Page 19 of 29 Not Recommended for New Designs Cypress Parameter CY14B256Q1 CY14B256Q2 CY14B256Q3 AutoStore or Power-Up RECALL Over the Operating Range Description Power-Up RECALL duration tFA [13] tSTORE [14] [15] tDELAY VSWITCH Unit ms STORE cycle duration – 8 ms Time allowed to complete SRAM write cycle – 25 ns – 150 2.65 – V s tVCCRISE[16] Low voltage trigger level VCC rise time VHDIS[16] HSB output disable voltage – 1.9 V tLZHSB[16] tHHHD[16] HSB high to nvSRAM active time – 5 s HSB high active time – 500 ns Switching Waveforms Figure 23. AutoStore or Power-Up RECALL [17] VCC VSWITCH VHDIS t VCCRISE 14 tHHHD Note tSTORE Note tHHHD 18 Note 14 tSTORE Note18 HSB OUT tDELAY tLZHSB AutoStore tLZHSB tDELAY POWERUP RECALL tFA tFA Read & Write Inhibited (RWI) POWER-UP RECALL Read & Write BROWN OUT AutoStore POWER-UP RECALL Read & Write POWER DOWN AutoStore Notes 13. tFA starts from the time VCC rises above VSWITCH. 14. If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware STORE is not initiated 15. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY. 16. These parameters are guaranteed by design and are not tested. 17. Read and write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH. 18. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor. Document Number: 001-53882 Rev. *K Page 20 of 29 Not Recommended for New Designs Parameter CY14B256Q1 / CY14B256Q2 / CY14B256Q3 Min Max – 20 CY14B256Q1 CY14B256Q2 CY14B256Q3 Software Controlled STORE and RECALL Cycles Over the Operating Range Description Min Max Unit tRECALL RECALL duration – 200 s tSS [19, 20] Soft sequence processing time – 100 s Switching Waveforms Figure 24. Software STORE Cycle [20] CS CS 0 1 2 3 4 5 6 7 0 SCK SI Figure 25. Software RECALL Cycle [20] 1 2 3 4 5 6 7 SCK 0 0 1 1 1 1 0 0 SI 0 1 1 0 0 0 0 0 tRECALL tSTORE HI-Z RWI RDY RDY Figure 26. AutoStore Enable Cycle Figure 27. AutoStore Disable Cycle CS CS 0 1 2 3 4 5 6 0 7 1 2 3 4 5 6 7 SCK SCK SI HI-Z RWI 0 1 0 1 1 0 0 SI 1 0 0 0 1 1 0 0 1 tSS tSS RWI HI-Z RDY RWI HI-Z RDY Notes 19. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command. 20. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command. Document Number: 001-53882 Rev. *K Page 21 of 29 Not Recommended for New Designs Parameter CY14B256Q1 / CY14B256Q2 / CY14B256Q3 CY14B256Q1 CY14B256Q2 CY14B256Q3 Hardware STORE Cycle Over the Operating Range tPHSB CY14B256Q3 Description Hardware STORE pulse width Min Max 15 – Unit ns Switching Waveforms Figure 28. Hardware STORE Cycle [21] Write Latch set ~ ~ tPHSB HSB (IN) tSTORE tHHHD ~ ~ tDELAY HSB (OUT) tLZHSB RWI tPHSB HSB (IN) HSB pin is driven HIGH to VCC only by Internal 100 K: resistor, HSB driver is disabled SRAM is disabled as long as HSB (IN) is driven LOW. tDELAY RWI ~ ~ HSB (OUT) ~ ~ Write Latch not set Note 21. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place. Document Number: 001-53882 Rev. *K Page 22 of 29 Not Recommended for New Designs Parameter CY14B256Q1 CY14B256Q2 CY14B256Q3 Ordering Information Ordering Code CY14B256Q2-LHXI Package Diagram Operating Range Package Type 001-50671 8-pin DFN (with VCAP) Industrial Ordering Code Definitions CY 14 B 256 Q 2 - LH X I T Option: T - Tape and Reel Blank - Std. Pb-free Temperature: I - Industrial (-40 °C to 85 °C) Package: SF - 16-pin SOIC LH - 8-pin DFN 1 - With WP 2 - With VCAP 3 - With VCAP, WP and HSB Voltage: B - 3.0 V Q - Serial (SPI) nvSRAM Density: 256 - 256 Kb 14- nvSRAM Cypress Document Number: 001-53882 Rev. *K Page 23 of 29 Not Recommended for New Designs All the above parts are Pb-free. CY14B256Q1 CY14B256Q2 CY14B256Q3 Package Diagrams 001-50671 *C Document Number: 001-53882 Rev. *K Page 24 of 29 Not Recommended for New Designs Figure 29. 8-pin DFN (5 × 6 × 0.85 mm) Package Outline, 001-50671 CY14B256Q1 CY14B256Q2 CY14B256Q3 Package Diagrams (continued) Not Recommended for New Designs Figure 30. 16-pin SOIC (0.413 × 0.299 × 0.932 inches) Package Outline, 51-85022 51-85022 *E Document Number: 001-53882 Rev. *K Page 25 of 29 CY14B256Q1 CY14B256Q2 CY14B256Q3 Acronym Document Conventions Description Units of Measure CPHA Clock Phase CPOL Clock Polarity °C degree Celsius DFN Dual Flat No-lead Hz hertz EEPROM Electrically Erasable Programmable Read-Only Memory kHz kilohertz K kilohm Mbit megabit MHz megahertz A microampere F microfarad s microsecond mA milliampere ms millisecond ns nanosecond ohm % percent pF picofarad V volt W watt EIA Electronic Industries Alliance I/O Input/Output JEDEC Joint Electron Devices Engineering Council LSB Least Significant Bit MSB Most Significant Bit nvSRAM non-volatile Static Random Access Memory RWI Read and Write Inhibit RoHS Restriction of Hazardous Substances SPI Serial Peripheral Interface SONOS Silicon-Oxide-Nitride-Oxide Semiconductor SOIC Small Outline Integrated Circuit SRAM Static Random Access Memory Document Number: 001-53882 Rev. *K Symbol Unit of Measure Not Recommended for New Designs Acronyms Page 26 of 29 CY14B256Q1 CY14B256Q2 CY14B256Q3 Document History Page Document Title: CY14B256Q1, CY14B256Q2, CY14B256Q3, 256-Kbit (32 K × 8) Serial (SPI) nvSRAM Document Number: 001-53882 Rev. ECN Orig. of Change Submission Date ** 2733272 GVCH / AESA 07/08/09 New data sheet *A 2758444 GVCH 09/01/09 Moved data sheet status from Preliminary to Final Removed commercial temperature related specs Added thermal resistance values for 16-pin SOIC and DFN package Added note to Write Sequence (WRITE) description *B 2839453 GVCH / PYRS 01/06/10 Changed STORE cycles to QuantumTrap from 200 K to 1 Million Added Contents Updated Figure 3 *C 3009761 GVCH 08/17/2010 Changed ground naming convention from GND to VSS Table 1: Added more clarity on HSB pin operation Hardware STORE and HSB Pin Operation: Added more clarity on HSB pin operation Updated Power-Down description Power On Reset: Added status of bits 4–6 Table 4: Added definition of bits 4–6 Updated Figure 8 Updated Figure 21, Figure 22, and Figure 23 Updated footnote 14 Added Figure 26 and Figure 27 Removed tDHSB parameter Updated Figure 28 Updated Package Diagrams. Added Acronyms and Document Conventions. *D 3054787 GVCH 10/11/2010 Added watermark as “For Evaluation Samples only. Production will be supported with the next revision silicon in SOIC package.” Updated HOLD Pin Operation, Figure 19 and Figure 22 to indicate that CS pin must remain LOW along with HOLD pin to pause serial communication *E 3143330 GVCH 01/17/2011 Hardware STORE and HSB Pin Operation: Added more clarity on HSB pin operation Updated tLZHSB parameter description Fixed typo in Figure 23. *F 3320699 GVCH 07/19/2011 Updated DC Electrical Characteristics (Added Note 7 and referred the same note in VCAP parameter). Updated AC Switching Characteristics (Added Note 11 and referred the same note in parameters column). *G 3510173 GVCH 01/27/2012 Updated Ordering Information (Removed CY14B256Q1-LHXIT, CY14B256Q1-LHXI, CY14B256Q3-SFXIT, CY14B256Q3-SFXI and CY14B256Q2-LHXIT). Updated Package Diagrams. *H 3666763 GVCH 07/05/2012 Updated DC Electrical Characteristics (Added VVCAP parameter and its details, added Note 8 and referred the same note in VVCAP parameter, also referred Note 9 in VVCAP parameter). *I 3710859 GVCH 08/13/2012 Updated Maximum Ratings (Changed “Ambient temperature with power applied” to “Maximum junction temperature”). *J 4011614 GVCH 05/27/2013 Updated Package Diagrams: spec 51-85022 – Changed revision from *D to *E. Removed watermark as “For Evaluation Samples only. Production will be supported with the next revision silicon in SOIC package.” Added watermark as “Not Recommended for New Designs.” *K 4557366 GVCH 11/05/2014 Added related documentation hyperlink in page 1 Document Number: 001-53882 Rev. *K Page 27 of 29 Not Recommended for New Designs Description of Change CY14B256Q1 CY14B256Q2 CY14B256Q3 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive psoc.cypress.com/solutions cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 Not Recommended for New Designs Products cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC Touch Sensing cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless Document Number: 001-53882 Rev. *K Page 28 of 29 © Cypress Semiconductor Corporation, 2009-2014 The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-53882 Rev. *K Revised November 5, 2014 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 29 of 29 Not Recommended for New Designs CY14B256Q1 CY14B256Q2 CY14B256Q3