UltraMAX™
LX5241/5242/5243
MULTIMODE SCSI TERMINATOR
T
H E
I
N F I N I T E
P
O W E R
I
O F
N N O V A T I O N
P
R O D U C T I O N
D
A T A
H E E T
KEY FEATURES
DESCRIPTION
Auto-Selectable LVD or Single-
voltage between 1.2V and 1.4V. In application
this pin is tied to the DIFFSENSE input of the
corresponding LVD transceivers. This action
enables
the
LVD
transceiver
function.
DIFFSENSE is capable of supplying a maximum
of 15mA. Tying the DIFFSENSE pin high places
the LX5241/42/43 in a HI Z state indicating the
presence of an HVD device. Tying the pin low
places the part in a single-ended mode while also
signaling the multimode transceiver to operate in a
single-ended mode.
Recognizing the needs of portable and
configurable peripherals, the LX5241/42/43 have
a TTL compatible sleep/disable mode. During
this sleep/disable mode, power dissipation is
reduced to a meager 15uA while also placing all
outputs in a HI Z state. Also during sleep/disable
mode, the DIFFSENSE function is disabled and is
placed in a HI Z state.
Another key feature of the LX5241/42/43 is the
master / slave function. Driving this pin high or
floating the pin enables the 1.3V DIFFSENSE
reference. Driving the pin low disables the on
board DIFFSENSE reference and enables use of
an external master reference device.
Ended Termination
3.0pF Maximum Disabled Output
Capacitance
Fast Response, No External
Capacitors Required
Compatible with Active Negation
Drivers
15µA Supply Current in
Disconnect Mode
Logic Command Disconnects All
Termination Lines
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The LX5241/42/43 is a multimode SCSI
terminator that is compatible with to the SCSI
SPI02 (Ultra2 SCSI), SCSI SPI-3 (Ultra3 SCSI or
Ultra160 SCSI), and pending SCSI SPI-4
(Ultra320) specifications developed by the T10
standards committee for low voltage differential
(LVD) termination, while providing backwards
compatibility to the SCSI, SCSI-2, and SPI singleended specifications. Multimode compatibility
permits the use of legacy devices on the bus
without hardware alterations. Automatic mode
selection is achieved through voltage detection on
the Diffsense line.
The
LX5241/42/43
utilizes
Linfinity’s
UltraMAX technology which delivers the ultimate
in SCSI bus performance while saving component
cost and board area. Elimination of the external
capacitors also mitigates the need for a lengthy
capacitor selection process. The individual high
bandwidth drivers also maximize channel
separation and reduce channel to channel noise and
cross talk. The high bandwidth architecture insures
ULTRA2 performance while providing a clear
migration path to ULTRA3 and beyond.
When the LX5241/42/43 is enabled, the
differential sense (DIFFSENSE) pin supplies a
S
Diffsense Line Driver
Ground Driver Integrated for
Single-Ended Operation
Current Limit and Thermal
Protection
Hot-Swap Compatible (SingleEnded)
Ultra160 compliant
See LX5245/5246 for LVD
Termination Only
Pin Compatible With DS2119
and UCC5630
IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com
PRODUCT HIGHLIGHT
BUS VOLTAGE 6
VOD
V(+)
VOD = V(-) - V(+), Logic =0
NEGATED
VCM
100mV
0V
-100mV
O
V(-)
-
LX5241
TA (°C)
0 to 70
DB
+
-
+
LX5241
PACKAGE ORDER INFO
Plastic TSSOP
Plastic TSSOP
PW 24-Pin
36-Pin
LX5241CDBK
LX5242CDBK
PW
Plastic TSSOP
28-Pin
RoHS Compliant / Pb-free
Transition DC: 0442
RoHS Compliant / Pb-free
Transition DC: 0518
LX5241CPWK
LX5242CPWK
LX5243CPW
-
Note: Available in Tape & Reel. Append the letters “TR” to the part number. (i.e. LX5241CDB-TR)
Copyright © 2000
Rev. 1.5a,2005-02-28
LINFINITY MICROELECTRONICS INC.
11861 WESTERN AVENUE, GARDEN GROVE, CA. 92841, 714-898-8121, FAX: 714-893-2570
1
PRODUCT DATABOOK 1996/1997
UltraMAX
LX5241/5242/5243
M U LT I M O D E S C S I T E R M I N AT O R
P
R O D U C T I O N
A B S O L U T E M A X I M U M R AT I N G S
D
A T A
S
H E E T
PACKAGE PIN OUTS
(Note 1)
TermPwr Voltage ................................................................................................. +7V
Operating Junction Temperature
Plastic (DB, PW Packages) .......................................................................... 150°C
Storage Temperature Range .............................................................. -65°C to 150°C
Lead Temperature (Soldering, 10 seconds) .................................................... 300°C
RoHS / Pb-free Peak Package Solder Reflow Temp (40 sec. max. exp.)...260°C(+0, -5)
T H E R M A L D ATA
DB PACKAGE:
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
50°C/W
PW PACKAGE:
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θJA
100°C/W
Junction Temperature Calculation: TJ = TA + (PD x θJA).
The θJA numbers are guidelines for the thermal performance of the device/pc-board
system. All of the above assume no ambient airflow.
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13
24
14
23
MASTER /
SLAVE
DIFFSENSE
Status
L*
H
Open (Pull-up)
HI Z
1.3V
1.3V
0mA
15mA Source
15mA Source
* When in Low state, terminator will detect state of DIFFSENSE line.
L < 0.5V
O
H
DIFF
SENSE
L
L
H
Open
H
H
L
Open
0.7 - 1.9V
H > 2.4V
X
Outputs
Status
Enable
Enable
Disable
Disable
Type
S.E.
LVD
HI Z
HI Z
22
16
21
17
20
18
19
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VTERM
N.C.
99+
88+
77+
66+
DIFFSENSE
MASTER/SLAVE
PW PACKAGE (Top View)
LX5241/5242 ("N.C." = No Internal Connection)
DIFFSENSE / POWER UP / POWER DOWN FUNCTION TABLE
LX5241/5243
LX5242
DISCONNECT DISCONNECT
15
VTERM
HVD
LVD
SE
99+
88+
HEATSINK
HEATSINK
HEATSINK
77+
66+
DIFF B
DIFFSENSE
MASTER/SLAVE
DB PACKAGE (Top View)
LX5241/5242 ("N.C." = No Internal Connection)
1+
12+
23+
34+
45+
5DISCONNECT
GND
MASTER / SLAVE FUNCTION TABLE
L
1
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Note 1. Exceeding these ratings could cause damage to the device. All voltages are with
respect to Ground. Currents are positive into, negative out of the specified
terminal.
N.C.
N.C.
N.C.
1+
12+
2HEATSINK
HEATSINK
HEATSINK
3+
34+
45+
5DISCONNECT
GND
Quiescent
Current
7mA
21mA
1mA
10µA
N.C.
1+
12+
2N.C.
3+
34+
45+
5DISCONNECT
GND
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VTERM
N.C.
99+
88+
N.C.
77+
66+
DIFFB
DIFFSENSE
MASTER/SLAVE
PW PACKAGE (Top View)
LX5243 ("N.C." = No Internal Connection)
RoHS / Pb-free 100% Matte Tin Lead Finish
2
Copyright © 2001
Rev. 1.5a 02/13
PRODUCT DATABOOK 1996/1997
UltraMAX
LX5241/5242/5243
M U LT I M O D E S C S I T E R M I N AT O R
P
R O D U C T I O N
D
A T A
S
H E E T
R E C O M M E N D E D O P E R AT I N G C O N D I T I O N S
Parameter
Termpwr Voltage
Symbol
LVD
SE
VTERM
Recommended Operating Conditions
Min.
Typ.
Max.
Units
3.0
3.5
0
0
5.25
5.25
5.0
VTERM
V
V
V
V
0
70
°C
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Signal Line Voltage
Disconnect Input Voltage
Operating Virtual Junction Temperature Range
LX5241C / 5242C / 5243C
Note 2. Range over which the device is functional.
(Note 2)
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, these specifications apply over the operating ambient temperature range of 0°C ≤ TA ≤ 70°C, TermPwr = 4.75V.
For the LX5241/5243 DISCONNECT = L, for the LX5242 DISCONNECT = H. Low duty cycle pulse testing techniques are used which maintains junction and
case temperatures equal to the ambient temperature.)
Parameter
Symbol
Test Conditions
LVD ICC
All term lines = Open
LX5241/5243: DISCONNECT > 2.0V, LX5242: DISCONNECT < 0.8V
LX5241 / 5242 / 5243
Min. Typ.
Max.
Units
LVD Terminator Section
TermPwr Supply Current
Common Mode Voltage
Offset Voltage
Differential Terminator Impedance
Common Mode Impedance
Output Capacitance
Output Leakage
Mode Change Delay
VCM
VFSB
ZD
ZCM
CO
ILEAK
tDF
Open circuit between - and + (see Note 3)
VOUT Differential = -1V to 1V
0V to 2.5V
LX5241/5243: DISCONNECT > 2.0V, LX5242: DISCONNECT < 0.8V
LX5241/5243: DISCONNECT > 2.0V, LX5242: DISCONNECT < 0.8V,
VLINE = 0 to 4V, TA = 25°C
LX5241/5243: DISCONNECT > 2.0V, LX5242: DISCONNECT < 0.8V,
VTERM = 0V, VLINE = 2.7V
DIFFSENSE = 1.4V to 0V
1.125
100
100
100
25
15
1.25
112
105
200
2.5
30
35
1.375
125
110
300
2
mA
µA
V
mV
Ω
Ω
pF
µA
1
µA
115
ms
DIFFSENSE Section
VDIFF
IDIFF
ISINK(DIFF)
ILEAK(DIFF)
O
DIFFSENSE Output Voltage
DIFFSENSE Output Source Current
DIFFSENSE Sink Current
DIFFSENSE Output Leakage
VDIFF = 0V
VDIFF = 2.75V
LX5241/5243: DISCONNECT > 2.0V, LX5242: DISCONNECT < 0.8V,
TA = 25°C
1.2
5.0
1.3
1.4
15.0
200
10
V
mA
µA
µA
7
214
15
2.85
23
65
2.5
10
226
35
mA
mA
µA
V
mA
mA
pF
µA
Single-Ended Termination Section
Termpwr Supply Current
Terminator Output High Volt
Output Current
Sink Current
Output Capacitance
Leakage Current
SE ICC
VO
IO
ISINK
CO
ILEAK
All term lines = Open, Master/Slave = 0V
All term lines = 0.2V, Master/Slave = 0V
LX5241/5243: DISCONNECT > 2.0V, LX5242: DISCONNECT < 0.8V
VOUT = 0.2V
VOUT = 4V, All lines
LX5241/5243: DISCONNECT > 2.0V, LX5242: DISCONNECT < 0.8V
LX5241/5243: DISCONNECT > 2.0V, LX5242: DISCONNECT < 0.8V,
VOUT = 0 to 4V, TA = 25°C
LX5241/5243: DISCONNECT > 2.0V, LX5242: DISCONNECT < 0.8V,
VTERM = Open, VLINE = 2.7V, TA = 25°C
2.6
21
45
24
2
1
µA
Note 3. Open circuit failsafe voltage.
Copyright © 2001
Rev. 1.5a 02/13
3
PRODUCT DATABOOK 1996/1997
UltraMAX
LX5241/5242/5243
M U LT I M O D E S C S I T E R M I N AT O R
P
D
R O D U C T I O N
S
A T A
H E E T
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
LX5241 / 5242
Min. Typ.
Max.
Test Conditions
Units
Single-Ended Termination Section (continued)
Ground Driver Impedance
Thermal Shutdown
ZG
I = 1mA
100
Ω
°C
2.0
10
V
µA
nA
nA
µA
150
DISCONNECT Section
DISCONNECT Thresholds
Input Current
VTH
IIL
IIL
IIH
IIH
0.8
DISCONNECT = 0V
DISCONNECT = 0V
DISCONNECT = 2.4V
DISCONNECT = 2.4V
100
100
bs
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LX5241/43
LX5242
LX5241/43
LX5242
10
MASTER / SLAVE Section
MASTER / SLAVE Thresholds
Input Current
VTH (MS)
IIL (MS)
IIH (MS)
0.8
MASTER / SLAVE = 0V
MASTER / SLAVE = 2.4V
2.0
10
100
V
µA
nA
BLOCK DIAGRAM
1 of 9
SE
2.85V, 22.5mA
Power ON
VTERM
DISCONNECT
S.E.
2.2V
Internal VREF
1.30V
1.07mA
SE
LVD (-)
/ SE
DISC/HVD
LVD
52.5
200
LVD
1.25V
SE
52.5
LVD (+)
/ SE (Pseudo-GND)
HVD
O
LVD
M/S
DIFFSENSE
DIFFB
10mA
20
1.07mA
MODE Control & Delay
LATCH
SE
Window
Comp.
SE
HVD
LVD
HVD
LVD
Power ON
POWER
ON
&
MODE
DELAY
FIGURE 1 — LX5241/5242 Block Diagram
4
Copyright © 2001
Rev. 1.5a 02/13
PRODUCT DATABOOK 1996/1997
UltraMAX
LX5241/5242/5243
M U LT I M O D E S C S I T E R M I N AT O R
P
R O D U C T I O N
D
A T A
S
H E E T
FUNCTIONAL PIN DESCRIPTION
Pin
Designator
1-, 2-, 3-, 4-, 5-, 6-, 7-, 8-, 9-6
Description
Negative signal termination lines for LVD mode. Signal termination lines for SE mode.
1+, 2+, 3+, 4+, 5+, 6+, 7+, 8+, 9+ Positive signal termination lines for LVD mode. Pseudo-ground lines for SE mode.
Power supply pin for terminator. Connect to SCSI bus TERMPWR. Must be decoupled by one 4.7µF
low-ESR capacitor for every three terminator devices. It is absolutely necessary to connect this pin to
the decoupling capacitor through a very low impedance (big traces on PCB). Keeping distances very
short from the decoupling capacitors to the VTERM pin is also critical. The value of the decoupling
capacitor is somewhat layout dependant and some applications may benefit from high-frequency
decoupling with 0.1µF capacitors right at VTERM pin.
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VTERM
DISCONNECT6
GND6
Enables / disables terminator. See Power Down Function Table for logic levels per device.
Terminator ground pin. Connect to ground.
MASTER / SLAVE6
Sometimes referred to as M/S pin in this data sheet. Used to select which terminator is the controlling device. MASTER/SLAVE pin High or Open enables the DIFFSENSE output drive. Please see
MASTER/SLAVE Function Table.
DIFFSENSE6
This is a dual function pin. It drives the SCSI bus DIFFSENS line. It is also the sense pin to detect the
SCSI bus mode (LVD, SE or HVD). DIFFSENSE output drive can be disabled with Low level on the
MASTER/SLAVE pin. Please see DIFFSENSE and MASTER/SLAVE Function Tables. Internally
connected to DIFFB pin through 20kOhm resistor.
DIFFB6
SE6
Internally connected to DIFFSENSE pin through 20kOhm resistor. It can be used as a mode sense
pin when the device is a non-controlling terminator (MASTER/SLAVE pin is Low). An RC filter
(20kOhm / 0.1µF) is not required on the LX5241/42/43, as it has an internal timer.
Single-ended output; when High, terminator is operating in SE mode.
LVD6
Low Voltage Differential output. When High, terminator is operating in LVD mode.
HVD6
High Voltage Differential output. When High, terminator is operating in HVD mode.
Attached to die mounting pad, but not bonded to GND pin. Pins should be considered a heat sink
only, and not a true ground connection. It is recommeneded that these pins be connected to ground,
but can be left floating.
O
HEATSINK6
Copyright © 2001
Rev. 1.5a 02/13
5
PRODUCT DATABOOK 1996/1997
UltraMAX
LX5241/5242/5243
M U LT I M O D E S C S I T E R M I N AT O R
P
R O D U C T I O N
D
A T A
S
H E E T
A P P L I C AT I O N S C H E M AT I C
H O S T
T E R M P O W E R
V
1 1 +
T E R M
L X 5 2 4 1 / 4 2
L X 5 2 4 3
D IS C O N N E C T
P E R IP H E R A L
1 -
T E R M
1 +
D a ta L in e s ( 9 )
9 -
9 -
9 +
9 +
D IS C O N N E C T
L X 5 2 4 1 / 4 2
L X 5 2 4 3
D IS C O N N E C T
D IS C O N N E C T
D IF F S E N S E
M /S
D IF F S E N S E
bs
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M /S
V
T E R M P O W E R
G N D
V
4 .7 µ F
D IF F B *
D IF F B *
1 1 +
T E R M
L X 5 2 4 1 / 4 2
L X 5 2 4 3
1 -
G N D
V
D a ta L in e s ( 9 )
9 -
9 -
9 +
9 +
O
G N D
* D IF F B P in n o t p r e s e n t o n L X 5 2 4 1 /5 2 4 2 C P W
6
4 .7 µ F
1 1 +
1 -
C o n tr o l L in e s ( 9 )
9 -
9 +
9 +
D IF F B *
V
1 +
9 -
D IF F S E N S E
M /S
G N D
D IF F B *
D IS C O N N E C T
M /S
L X 5 2 4 1 / 4 2
L X 5 2 4 3
D IS C O N N E C T
D IF F B *
L X 5 2 4 1 / 4 2
L X 5 2 4 3
T E R M
D IF F S E N S E
D IF F S E N S E
T E R M
V
1 +
D IS C O N N E C T
M /S
G N D
T E R M
L X 5 2 4 1 / 4 2
L X 5 2 4 3
D IS C O N N E C T
D IF F S E N S E
D IF F B *
P a c k a g e . M u s t c o n n e c t D IF F S E N S s ig n a l to D IF F S E N S E p in o n P W
M /S
G N D
p a c k a g e .
FIGURE 2 — Linfinity ONLY Application Schematic
Copyright © 2001
Rev. 1.5a 02/13
PRODUCT DATABOOK 1996/1997
UltraMAX
LX5241/5242/5243
M U LT I M O D E S C S I T E R M I N AT O R
P
R O D U C T I O N
D
S
A T A
H E E T
A P P L I C AT I O N S C H E M AT I C
H O S T
T E R M P O W E R
V
1 1 +
T E R M
L X 5 2 4 1 / 4 2
L X 5 2 4 3
D IS C O N N E C T
P E R IP H E R A L
1 -
T E R M
1 +
D a ta L in e s ( 9 )
9 -
9 -
9 +
9 +
D IS C O N N E C T
L X 5 2 4 1 / 4 2
L X 5 2 4 3
D IS C O N N E C T
D IS C O N N E C T
D IF F S E N S E
2 0 k
M /S
D IF F S E N S E
2 0 k
bs
ol
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e
M /S
V
T E R M P O W E R
G N D
N .C .*
P in 1
D IF F B
0 .1 µ F
0 .1 µ F
4 .7 µ F *
G N D
D IF F B
N .C .*
P in 1
4 .7 µ F *
V
1 1 +
T E R M
L X 5 2 4 1 / 4 2
L X 5 2 4 3
4 .7 µ F
1 -
D a ta L in e s ( 9 )
9 -
9 -
9 +
9 +
D IS C O N N E C T
M /S
G N D
T E R M
L X 5 2 4 1 / 4 2
L X 5 2 4 3
4 .7 µ F
D IS C O N N E C T
M /S
D IF F S E N S E
D IF F S E N S E
N .C .*
P in 1
V
1 +
G N D
D IF F B
D IF F B
4 .7 µ F *
N .C .*
P in 1
4 .7 µ F *
V
1 1 +
T E R M
L X 5 2 4 1 / 4 2
L X 5 2 4 3
1 -
C o n tr o l L in e s ( 9 )
9 -
9 -
9 +
9 +
D IS C O N N E C T
M /S
G N D
T E R M
L X 5 2 4 1 / 4 2
L X 5 2 4 3
D IS C O N N E C T
D IF F S E N S E
D IF F S E N S E
N .C .*
P in 1
V
1 +
D IF F B
D IF F B
N .C .*
P in 1
4 .7 µ F *
O
4 .7 µ F *
M /S
G N D
* T h e c a p a c ito r o n P in 1 c a n b e p la c e d o n th e L X 5 2 4 1 C D B , L X 5 2 4 2 C D B o r th e L X 5 2 4 3 C P W
to b e p in - c o m p a tib le w ith o th e r d e v ic e s . T h is V
R E G
/R E F c a p a c ito r is n o t r e q u ir e d .
FIGURE 3 — Suggested Linfinity LX5241/5242/5243 Universal Application Schematic
(Please Reference Manufacturer's Current Data Sheet To Ensure Compatibility)
UltraMAX is a trademark of LinFinity Microelectronics Inc.
Prodution Data - Information Contained in this document is proprietary to Microsemi and is current as of publication date. This document may not be modified in any way without the express written consent of Microsemi. Product processing does not necessarily include testing of all parameters. Microsemi
reserves the right to change the configuration and performance of the product and to discontinue product at any time.
Copyright © 2001
Rev. 1.5a 02/13
7