CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
®
PowerPSoC Intelligent LED Driver
PowerPSoC Intelligent LED Driver
1. Features
■ Applications
❐ Stage LED lighting
❐ Architectural LED lighting
❐ General purpose LED lighting
❐ Automotive and emergency vehicle LED lighting
❐ Landscape LED lighting
❐ Display LED lighting
❐ Effects LED lighting
❐ Signage LED lighting
■ Device options
❐ CY8CLED04D0x
• Four internal FETs with 0.5 A and 1.0 A
options
• Four external gate drivers
❐ CY8CLED04G01
• Four external gate drivers
❐ CY8CLED03D0x
• Three internal FETs with 0.5 A and 1.0 A
options
• Three external gate drivers
❐ CY8CLED03G01
• Three external gate drivers
❐ CY8CLED02D01
• Two 1.0 A internal FETs
• Two external gate drivers
❐ CY8CLED01D01
• One 1.0 A internal FET
• One external gate driver
❐ Up to 9-bit DACs
❐ Programmable gain amplifiers
❐ Programmable filters and comparators
❐ 8 to 32-bit timers and counters
❐ Complex peripherals by combining blocks
❐ Configurable to all GPIO pins
■ Programmable pin configurations
❐ 25 mA sink, 10 mA source on all GPIO and function pins
❐ Pull-up, pull-down, high Z, strong, or open drain
drive modes on all GPIO and function pins
❐ Up to 10 analog inputs on GPIO
❐ Two 30 mA analog outputs on GPIO
❐ Configurable interrupt on all GPIO
■ Flexible on-chip memory
❐ 16 K flash program storage 50,000 erase / write
cycles
❐ 1 K SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
■ Complete development tools
❐ Free development software (PSoC Designer™)
❐ Full-featured, in-circuit emulator (ICE) and
programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
■ Integrated power peripherals
❐ Four internal 32 V low side N-Channel power
FETs
• RDS(ON)– 0.5 for 1.0 A devices
• Up to 2 MHz configurable switching frequency
❐ Four hysteretic controllers
• Independently programmable upper and
lower thresholds
• Programmable minimum ON/OFF timers
❐ Four low side gate drivers with programmable
drive strength
❐ Four precision high side current sense amplifiers
❐ Three 16-bit LED dimming modulators: PrISM,
DMM, and PWM
❐ Six fast response (100 ns) voltage comparators
❐ Six 8-bit reference DACs
❐ Built-in switching regulator eliminates external
5 V supply
❐ Multiple topologies including floating load buck,
floating load buck-boost, and boost
■ M8C CPU core
❐ Processor speeds up to 24 MHz
■ Advanced peripherals (PSoC® Blocks)
❐ Capacitive sensing application capability
❐ DMX512 interface
❐ I2C master or slave
❐ Full-duplex UARTs
❐ Multiple SPI masters or slaves
❐ Integrated temperature sensor
❐ Up to 12-bit ADCs
❐ 6 to 12-bit incremental ADCs
■ 56-pin QFN package
Figure 1-1. PowerPSoC Architectural Block Diagram
Port 1
Port 0
Analog
Drivers
FN0
CSA
Interupt Bus
SYSTEM BUS
Analog Mux Bus
Global Digital Interconnect
CORE
Clock Signals
CPU
(M8C)
Core
Sleep and
Watchdog
System Bus
24 MHz Internal Main
Oscillator( IMO)
Internal Low Speed
Oscillator ( ILO)
Decoder
C3
GDRV
DAC
Hysteretic
PWM
GDRV
DAC
Hysteretic
PWM
GDRV
DAC
Hysteretic
PWM
GDRV
C4
C5
Analog PSoC
Block Array
DBB 00 DBB 01 DCB 02 DCB 03
Hysteretic
PWM
C2
C6
ANALOG SYSTEM
Digital PSoC Block Array
DAC
Power
FETs (HV)
C1
Multiple Clock Sources
DIGITAL SYSTEM
Gate
Driver(LV)
Analog Block
CT
CT
DBB 01 DBB 11 DCB 12 DCB13
SC
SC
2 Digital Rows
SC
SC
Comparator
Bank
Analog
Ref
DAC
AINX
Power System Digital Bus
Interrupt
Controller
PrISM/ DMM /
PWM
Power System Analog Bus
PSoC
Supervisory ROM Flash Nonvolatile
Memory(16 K)
( SROM)
PWM Controller
Channels( LV)
Logic Core
Global Analog Interconnect
SRAM
(1 K bytes)
CSA
Chbond_bus
Port 2
DAC
DAC
2Analog Columns
DAC Bank
Vref
Digital
Clocks
MACs
(2)
Decimator
( Type2)
POR and LVD
I2C
System Resets
Internal
IO Analog
Voltage
Multiplexer
Reference
PSoC SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 001-46319 Rev. *R
POWER PERIPHERALS
SW Regulator
CSA
•
198 Champion Court
•
CSA
San Jose, CA 95134-1709
•
408-943-2600
Revised April 16, 2015
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
2. Contents
Logic Block Diagrams.................................................... 3
PowerPSoC Functional Overview ................................. 9
Power Peripherals .......................................................... 9
Hysteretic Controllers ................................................ 9
Low Side N-Channel FETs...................................... 10
External Gate Drivers .............................................. 10
Dimming Modulation Schemes................................ 10
Current Sense Amplifier .......................................... 10
Voltage Comparators .............................................. 11
Reference DACs ..................................................... 11
Built-in Switching Regulator .................................... 11
Analog Multiplexer................................................... 11
Digital Multiplexer .................................................... 12
Function Pins (FN0[0:3]) ......................................... 12
PSoC Core.....................................................................
Digital System .........................................................
Analog System ........................................................
Analog Multiplexer System......................................
Additional System Resources .................................
13
13
13
14
14
Applications .................................................................. 15
PowerPSoC Device Characteristics............................ 17
Getting Started..............................................................
Application Notes ....................................................
Development Kits ....................................................
Training ...................................................................
CYPros Consultants ................................................
Technical Support ...................................................
18
18
18
18
18
18
Development Tools ...................................................... 18
PSoC Designer Software Subsystems.................... 18
In-Circuit Emulator................................................... 19
Designing with User Modules ..................................... 19
Pin Information ............................................................. 20
CY8CLED04D0x 56-Pin Part Pinout (without OCD) 20
CY8CLED04G01 56-Pin Part Pinout (without OCD) 21
CY8CLED04DOCD1 56-Pin Part Pinout (with OCD) 22
CY8CLED03D0x 56-Pin Part Pinout (without OCD) 23
CY8CLED03G01 56-Pin Part Pinout (without OCD) 24
CY8CLED02D01 56-Pin Part Pinout (without OCD) 25
CY8CLED01D01 56-Pin Part Pinout (without OCD) 26
Register General Conventions ....................................
Abbreviations Used .................................................
Register Naming Conventions.................................
Register Mapping Tables ........................................
Document Number: 001-46319 Rev. *R
27
27
27
27
Register Map Bank 0 Table .................................... 28
Register Map Bank 1 Table: User Space ................ 29
Electrical Specifications .............................................. 30
Absolute Maximum Ratings..................................... 30
Operating Temperature ........................................... 31
Electrical Characteristics.............................................
System Level...........................................................
Chip Level ...............................................................
Power Peripheral Low Side N-Channel FET ...........
Power Peripheral External Power FET Driver .........
Power Peripheral Hysteretic Controller ...................
Power Peripheral Comparator.................................
Power Peripheral Current Sense Amplifier..............
Power Peripheral PWM/PrISM/DMM Specification
Table .......................................................................
Power Peripheral Reference DAC Specification .....
Power Peripheral Built-in Switching Regulator........
General Purpose I/O / Function Pin I/O...................
PSoC Core Operational Amplifier Specifications ....
PSoC Core Low Power Comparator .......................
PSoC Core Analog Output Buffer............................
PSoC Core Analog Reference ................................
PSoC Core Analog Block ........................................
PSoC Core POR and LVD ......................................
PSoC Core Programming Specifications ................
PSoC Core Digital Block Specifications ..................
PSoC Core I2C Specifications ................................
31
31
31
33
34
34
35
37
38
39
39
42
43
44
45
47
47
48
48
49
50
Ordering Information.................................................... 51
Ordering Code Definitions ....................................... 51
Packaging Information.................................................
Packaging Dimensions............................................
Thermal Impedance ................................................
Solder Reflow Peak Temperature ...........................
52
52
52
52
Acronyms ...................................................................... 53
Document Conventions ............................................... 53
Units of Measure ..................................................... 53
Document History Page ............................................... 55
Sales, Solutions, and Legal Information ....................
Worldwide Sales and Design Support.....................
Products ..................................................................
PSoC® Solutions ....................................................
Cypress Developer Community...............................
Technical Support ...................................................
56
56
56
56
56
56
Page 2 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
3. Logic Block Diagrams
Figure 3-1. CY8CLED04D0x Logic Block Diagram
SW0
CSA0
DAC0
CSP0
CSN0
Gate Drive 0
Hysteretic Mode
Controller 0
DAC1
PGND0
External
Gate Drive 0
GD 0
SW1
CSA1
Gate Drive 1
DAC2
CSP1
CSN1
Hysteretic Mode
Controller 1
Analog Mux
DAC3
CSA2
CSP2
CSN2
PGND1
External
Gate Drive 1
Gate Drive 2
DAC4
Hysteretic Mode
Controller 2
DAC5
CSA3
External
Gate Drive 2
Gate Drive 3
DAC6
CSP3
CSN3
Hysteretic Mode
Controller 3
External
Gate Drive 3
SW2
PGND2
GD 2
SW3
PGND3
GD 3
FN0
DAC7
GD 1
FN0[0:3]
Comp 13
Comp 12
Comp 11
Comp 9
Comp 8
4
Comp 10
Power Peripherals Digital Mux
4
4 Channel PWM/
PrISM/DMM
Power Peripherals Analog Mux
DAC13
DAC12
DAC11
DAC10
6
DAC9
DAC8
SREGHVIN
From Analog Mux
SREGSW
Auxiliary
Power
Regulator
SREGCSP
SREGCSN
SREGFB
AINX
System Bus
SREGCOMP
Global Digital Interconnect
Global Analog Interconnect
Flash 16K
P1[0,1,4,5,7]
P0[3,4,5,7]
Sleep and
Watchdog
CPU Core (M8C)
Interrupt
Controller
P2[2]
Port 0
SROM
Port 1
SRAM
1K
Port 2
PSoC CORE
Clock Sources
(Includes IMO and ILO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog Ref.
Digital
Block
Array
Digital
Clocks
2 MACs
Analog
Block Array
Decimator Type
2
I2C
POR and LVD
System Resets
Internal
Voltage Ref.
Analog
Input Muxing
SYSTEM RESOURCES
Document Number: 001-46319 Rev. *R
Page 3 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
Figure 3-2. CY8CLED04G01 Logic Block Diagram
CSA0
DAC0
CSP0
CSN0
DAC1
CSA1
Hysteretic Mode
Controller 0
External
Gate Drive 0
GD 0
Hysteretic Mode
Controller 1
External
Gate Drive 1
GD 1
Hysteretic Mode
Controller 2
External
Gate Drive 2
GD 2
Hysteretic Mode
Controller 3
External
Gate Drive 3
GD 3
DAC2
CSP1
CSN1
Analog Mux
DAC3
CSA2
CSP2
CSN2
DAC4
DAC5
CSA3
DAC6
CSP3
CSN3
FN0
DAC7
FN0[0:3]
Comp 13
Comp 12
Comp 11
Comp 9
4
Comp 8
4
Comp 10
Power Peripherals Digital Mux
4 Channel PWM/
PrISM/DMM
Power Peripherals Analog Mux
DAC13
DAC12
DAC11
DAC10
6
DAC9
DAC8
SREGHVIN
From Analog Mux
SREGSW
Auxiliary
Power
Regulator
SREGCSP
SREGCSN
SREGFB
AINX
System Bus
SREGCOMP
Global Digital Interconnect
Global Analog Interconnect
Flash 16K
P1[0,1,4,5,7]
P0[3,4,5,7]
Sleep and
Watchdog
CPU Core (M8C)
Interrupt
Controller
P2[2]
Port 0
SROM
Port 1
SRAM
1K
Port 2
PSoC CORE
Clock Sources
(Includes IMO and ILO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog Ref.
Digital
Block
Array
Digital
Clocks
2 MACs
Analog
Block Array
Decimator Type
2
I2C
POR and LVD
System Resets
Internal
Voltage Ref.
Analog
Input Muxing
SYSTEM RESOURCES
Document Number: 001-46319 Rev. *R
Page 4 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
Figure 3-3. CY8CLED03D0x Logic Block Diagram
SW0
CSA0
DAC0
CSP0
CSN0
Gate Drive 0
Hysteretic Mode
Controller 0
DAC1
PGND0
External
Gate Drive 0
GD 0
SW1
CSA1
Gate Drive 1
DAC2
CSP1
CSN1
Hysteretic Mode
Controller 1
Analog Mux
DAC3
CSA2
CSP2
PGND1
External
Gate Drive 1
Gate Drive 2
DAC4
CSN2
Hysteretic Mode
Controller 2
External
Gate Drive 2
SW2
PGND2
GD 2
FN0
DAC5
GD 1
FN0[0:3]
Comp 13
Comp 12
Comp 11
Comp 9
4
Comp 8
4
Comp 10
Power Peripherals Digital Mux
3 Channel PWM/
PrISM/DMM
Power Peripherals Analog Mux
DAC13
DAC12
DAC11
DAC10
6
DAC9
DAC8
SREGHVIN
From Analog Mux
SREGSW
Auxiliary
Power
Regulator
SREGCSP
SREGCSN
SREGFB
AINX
System Bus
SREGCOMP
Global Digital Interconnect
Global Analog Interconnect
Flash 16K
P1[0,1,4,5,7]
P0[3,4,5,7]
Sleep and
Watchdog
CPU Core (M8C)
Interrupt
Controller
P2[2]
Port 0
SROM
Port 1
SRAM
1K
Port 2
PSoC CORE
Clock Sources
(Includes IMO and ILO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog Ref.
Digital
Block
Array
Digital
Clocks
2 MACs
Analog
Block Array
Decimator Type
2
I2C
POR and LVD
System Resets
Internal
Voltage Ref.
Analog
Input Muxing
SYSTEM RESOURCES
Document Number: 001-46319 Rev. *R
Page 5 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
Figure 3-4. CY8CLED03G01 Logic Block Diagram
CSA0
DAC0
CSP0
CSN0
DAC1
CSA1
Hysteretic Mode
Controller 0
External
Gate Drive 0
GD 0
Hysteretic Mode
Controller 1
External
Gate Drive 1
GD 1
Hysteretic Mode
Controller 2
External
Gate Drive 2
DAC2
CSP1
CSN1
Analog Mux
DAC3
CSA2
CSP2
DAC4
CSN2
GD 2
FN0
DAC5
FN0[0:3]
Comp 13
Comp 12
Comp 11
Comp 9
Comp 8
4
Comp 10
Power Peripherals Digital Mux
4
3 Channel PWM/
PrISM/DMM
Power Peripherals Analog Mux
DAC13
DAC12
DAC11
DAC10
6
DAC9
DAC8
SREGHVIN
From Analog Mux
SREGSW
Auxiliary
Power
Regulator
SREGCSP
SREGCSN
SREGFB
System Bus
AINX
Global Digital Interconnect
SREGCOMP
Global Analog Interconnect
Flash 16K
P1[0,1,4,5,7]
P0[3,4,5,7]
Sleep and
Watchdog
CPU Core (M8C)
Interrupt
Controller
P2[2]
Port 0
SROM
Port 1
SRAM
1K
Port 2
PSoC CORE
Clock Sources
(Includes IMO and ILO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog Ref.
Digital
Block
Array
Digital
Clocks
2 MACs
Analog
Block Array
Decimator Type
2
I2C
POR and LVD
System Resets
Internal
Voltage Ref.
Analog
Input Muxing
SYSTEM RESOURCES
Document Number: 001-46319 Rev. *R
Page 6 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
Figure 3-5. CY8CLED02D01 Logic Block Diagram
SW0
CSA0
DAC0
CSP0
CSN0
Gate Drive 0
Hysteretic Mode
Controller 0
DAC1
PGND0
External
Gate Drive 0
GD 0
SW1
CSA1
Gate Drive 1
DAC2
Analog Mux
CSP1
Hysteretic Mode
Controller 1
DAC3
PGND1
External
Gate Drive 1
GD 1
FN0
CSN1
FN0[0:3]
Comp 13
Comp 12
Comp 11
Comp 9
4
Comp 8
4
Comp 10
Power Peripherals Digital Mux
2 Channel PWM/
PrISM/DMM
Power Peripherals Analog Mux
DAC13
DAC12
DAC11
DAC10
6
DAC9
DAC8
SREGHVIN
From Analog Mux
SREGSW
Auxiliary
Power
Regulator
SREGCSP
SREGCSN
SREGFB
AINX
System Bus
SREGCOMP
Global Digital Interconnect
Global Analog Interconnect
Flash 16K
P1[0,1,4,5,7]
P0[3,4,5,7]
Sleep and
Watchdog
CPU Core (M8C)
Interrupt
Controller
P2[2]
Port 0
SROM
Port 1
SRAM
1K
Port 2
PSoC CORE
Clock Sources
(Includes IMO and ILO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog Ref.
Digital
Block
Array
Digital
Clocks
2 MACs
Analog
Block Array
Decimator Type
2
I2C
POR and LVD
System Resets
Internal
Voltage Ref.
Analog
Input Muxing
SYSTEM RESOURCES
Document Number: 001-46319 Rev. *R
Page 7 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
Figure 3-6. CY8CLED01D01 Logic Block Diagram
SW0
CSA0
DAC0
CSP0
CSN0
Hysteretic Mode
Controller 0
PGND0
External
Gate Drive 0
FN0
Analog Mux
DAC1
FN0[0:3]
Gate Drive 0
GD 0
Comp 13
Comp 12
Comp 11
Comp 9
4
Comp 8
4
Comp 10
Power Peripherals Digital Mux
1 Channel PWM/
PrISM/DMM
Power Peripherals Analog Mux
DAC13
DAC12
DAC11
DAC10
6
DAC9
DAC8
SREGHVIN
From Analog Mux
SREGSW
Auxiliary
Power
Regulator
SREGCSP
SREGCSN
SREGFB
AINX
System Bus
SREGCOMP
Global Digital Interconnect
Global Analog Interconnect
SRAM
1K
SROM
Flash 16K
P2[2]
Sleep and
Watchdog
CPU Core (M8C)
Port 1
P1[0,1,4,5,7]
Port 0
Interrupt
Controller
Port 2
PSoC CORE
P0[3,4,5,7]
Clock Sources
(Includes IMO and ILO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog Ref.
Digital
Block
Array
Digital
Clocks
2 MACs
Analog
Block Array
Decimator Type
2
I2C
POR and LVD
System Resets
Internal
Voltage Ref.
Analog
Input Muxing
SYSTEM RESOURCES
Document Number: 001-46319 Rev. *R
Page 8 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
4. PowerPSoC® Functional Overview
The PowerPSoC family incorporates programmable
system-on-chip technology with the best in class power
electronics controllers and switching devices to create easy to
use power-system-on-chip solutions for lighting applications.
All PowerPSoC family devices are designed to replace
traditional MCUs, system ICs, and the numerous discrete
components that surround them. PowerPSoC devices feature
high performance power electronics including 1 ampere 2 MHz
power FETs, hysteretic controllers, current sense amplifiers, and
PrISM/PWM modulators to create a complete power electronics
solution for LED power management. Configurable power,
analog, digital, and interconnect circuitry enables a high level of
integration in a host of industrial, commercial, and consumer
LED lighting applications.
This architecture integrates programmable analog and digital
blocks to enable you to create customized peripheral
configurations that match the requirements of each individual
application. Additionally, the device includes a 24 MHz CPU,
Flash program memory, SRAM data memory, and configurable
I/O in a range of convenient pinouts and packages.
The PowerPSoC architecture, as illustrated in the block
diagrams, consists of five main areas: PSoC core, digital system,
analog system, system resources, and power peripherals, which
include power FETs, hysteretic controllers, current sense
amplifiers, and PrISM/PWM modulators. Configurable global
busing combines all of the device resources into a complete
custom system. The PowerPSoC family of devices have 10-port
I/Os that connect to the global digital and analog interconnects,
providing access to eight digital blocks and six analog blocks.
5.1 Hysteretic Controllers
The PowerPSoC contains four hysteretic controllers. There is
one hysteretic controller for each channel of the device.
The hysteretic controllers provide cycle by cycle switch control
with fast transient response, which simplifies system design by
requiring no external compensation. The hysteretic controllers
include the following key features:
■
Four independent channels
■
DAC configurable thresholds
■
Wide switching frequency range from 20 kHz to 2 MHz
■
Programmable minimum on and off time
■
Floating load buck, floating load buck-boost and boost topology
controller
The reference inputs (REF_A and REF_B in Figure 5-1.) of the
hysteretic controller are provided by the reference DACs as
illustrated in the top level block diagram (see Figure 3-1. on page 3).
The hysteretic control function output is generated by comparing
the feedback value to two thresholds. Going below the lower
threshold turns the switch ON and exceeding the upper threshold
turns the switch OFF as shown in Figure 5-1. The output current
waveforms are shown in Figure 5-2.
The hysteretic controller also controls the minimum on-time and
off-time. This circuit prevents oscillation at very high frequencies;
which can be very destructive to output switches.
The output to the gate drivers is gated by the Trip, DIM and
Enable signals. The Enable signal is a direct result of the enable
bit in the control register for the hysteretic controller.
5. Power Peripherals
The Trip signal can be any digital signal that follows TTL logic
(logic high and logic low). It is an active high input.
PowerPSoC is designed to operate at voltages from 7 V to 32 V,
drive up to 1 ampere of current using internal MOSFET switches,
and over 1 ampere with external MOSFETs.
The DIM Modulation signal is the output of the dedicated
modulators that are present in the power peripherals, or any
other digital modulation signal.
This family of devices (CY8CLED0xD/G0y) combines up to four
independent channels of constant current drivers. These drivers
feature hysteretic controllers with the Programmable
System-on-Chip (PSoC) that contains an 8-bit microcontroller,
configurable digital and analog peripherals, and embedded flash
memory.
Figure 5-1. Generating Hysteretic Control Function Output
The CY8CLED0xD/G0y is the first product in the PowerPSoC
family to integrate power peripherals to add further integration for
your power electronics applications.The PowerPSoC family of
intelligent power controller ICs are used in lighting applications
that need traditional MCUs and discrete power electronics
support. The power peripherals of the CY8CLED0xD/G0y
include up to four 32 volt power MOSFETs with current ratings
up to 1 ampere each. It also integrates gate drivers that enable
applications to drive external MOSFETs for higher current and
voltage capabilities. The controller is a programmable threshold
hysteretic controller, with user-selectable feedback paths that
uses the IC in current mode floating load buck, floating load
buck-boost, and boost configurations.
Document Number: 001-46319 Rev. *R
Lower Limit
Comparator
Min ON
Timer
REF_A
S
CSA
Q
IFB Upper Limit
Comparator
FN0[x]
R
REF_B
Min Off
Timer
DIM Modulation
Enable
Hyst Out
Trip Function
Page 9 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
Figure 5-2. Current Waveforms
ILED
REF_B
REF_A
ON
DIM
OFF
Hyst Out
The minimum on-time and off-time circuits in the PowerPSoC
prevent oscillations at very high frequencies, which can be very
destructive to output switches.
5.2 Low Side N-Channel FETs
The internal low side N-Channel FETs are designed to enhance
system integration. The low side N-Channel FETs include the
following key features:
5.4.1 PrISM Mode Configuration
■
High resolution operation up to 16 bits
■
Dedicated PrISM module enables customers to use core PSoC
digital blocks for other needs
■
Clocking up to 48 MHz
■
Selectable output signal density
■
Reduced EMI
The PrISM mode compares the output of a pseudo-random
counter with a signal density value. The comparator output
asserts when the count value is less than or equal to the value
in the signal density register.
5.4.2 DMM Mode Configuration
■
High resolution operation up to 16 bits
■
Configurable output frequency and delta sigma modulator
width to trade off repeat rates versus resolution
■
Dedicated DMM module enables customers to use PSoC
digital blocks for other uses
■
Clocking up to 48 MHz
The DMM modulator consists of a 12-bit PWM block and a 4-bit
delta sigma modulator (DSM) block. The width of the PWM, the
width of the DMM, and the clock defines the output frequency.
The duty cycle of the PWM output is dithered by using the DSM
block which has a user-selectable resolution up to 4 bits.
5.4.3 PWM Mode Configuration
■
Drive capability up to 1 A
■
High resolution operation up to 16 bits
■
Switching times of 20 ns (rise and fall times) to ensure high
efficiency (more than 90%)
■
User programmable period from 1 to 65535 clocks
■
Drain source voltage rating 32 V
■
Dedicated PWM module enables customers to use core PSoC
digital blocks for other use
■
Low RDS(ON) to ensure high efficiency
■
Interrupt on rising edge of the output or terminal count
■
Switching frequency up to 2 MHz
■
Precise PWM phase control to manage system current edges
■
Phase synchronization among the four channels
■
PWM output can be aligned to left, right, or center
5.3 External Gate Drivers
These gate drivers enable the use of external FETs with higher
current capabilities or lower RDS(ON). The external gate drivers
directly drive MOSFETs that are used in switching applications.
The gate driver provides multiple programmable drive strength
steps to enable improved EMI management. The external gate
drivers include the following key features:
■
Programmable drive strength options (25%, 50%, 75%, 100%)
for EMI management
■
Rise and fall times at 55 ns with 4 nF load
5.4 Dimming Modulation Schemes
There are three dimming modulation schemes available with the
PowerPSoC. The configurable modulation schemes are:
The PWM features a down counter and a pulse width register.
A comparator output is asserted when the count value is less
than or equal to the value in the pulse width register.
5.5 Current Sense Amplifier
The high side current sense amplifiers provide a differential
sense capability to sense the voltage across current sense
resistors in lighting systems. The current sense amplifier
includes the following key features:
■
Operation with high common mode voltage to 32 V
■
High common mode rejection ratio
Programmable bandwidth to optimize system noise immunity
■
Precise intensity signal modulation (PrISM)
■
■
Delta Sigma modulation mode (DMM)
■
Pulse-width modulation (PWM)
An off-chip resistor Rsense is used for high side current
measurement as shown in Figure 5-3. on page 11. The output of
the current sense amplifier goes to the power peripherals analog
multiplexer where, you select the hysteretic controller to which
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the routing is done. Table 5-1 illustrates example values of
Rsense for different currents.
■
Low gain errors
■
10 us settling time
The method to calculate the Rsense value for a desired average
current is explained in the application note CY8CLED0xx0x:
Topology and Design Guide for Circuits using PowerPSoC AN52699
These DACs are available to provide programmable references
for the various analog and comparator functions and are
controlled by memory mapped registers.
Table 5-1. Rsense Values for Different Currents
DAC[0:7] are embedded in the hysteretic controllers and are
required to set the upper and lower thresholds for channel 0 to 3.
Max Load Current (mA)
Typical Rsense (m)
1000
100
750
130
500
200
350
300
5.8 Built-in Switching Regulator
The switching regulator is used to power the low voltage (5 V
portion of the PowerPSoC) from the input line. This regulator is
based upon a peak current control loop which can support up to
250 mA of output current. The current not being consumed by
PowerPSoC is used to power additional system peripherals. The
key features of the built-in switching regulator include:
Figure 5-3. High Side Current Measurement
CSP0
CSN0
CS0
.
.
.
CSP3
Rsense3
CSN3
Power Peripheral
Analog Mux
Rsense0
DAC [8:13] are connected to the Power Peripherals Analog
Multiplexer and provide programmable references to the
comparator bank. These are used to set trip points which enable
over voltage, over current, and other system event detection.
CS3
■
Ability to self power device from input line
■
Small filter component sizes
■
Fast response to transients
Refer to Table 15-20 for component values.
The 'Ref' signal that forms the reference to the Error Amplifier is
internally generated and there is no user control over it.
Figure 5-4. Built-in Switching Regulator
5.6 Voltage Comparators
Ref
There are six comparators that provide high speed comparator
operation for over voltage, over current, and various other
system event detections. For example, the comparators may be
used for zero crossing detection for an AC input line or
monitoring total DC bus current. Programmable internal analog
routing enables these comparators to monitor various analog
signals. These comparators include the following key features:
■
Error
Amplifier
Osc
Current
Sense
Amplifier
Programmable interrupt generation
■
Low input offset voltage and input bias currents
C IN
SREGSW L
D1
VREGOUT = 5V
Rsense
Rfb1
ESR
Rfb2
C1
SREGCSP
SREGCSN
High speed comparator operation: 100 ns response time
■
VREGIN
SREGHVIN
Logic and
Gate
Drive
Comparator
SREGCOMP
Ccomp
SREGFB
Rcomp
Six precision voltage comparators are available. The differential
positive and negative inputs of the comparators are routed from
the analog multiplexer and the output goes to the digital
multiplexer. A programmable inverter is used to select the output
polarity. User-selectable hysteresis can be enabled or disabled
to trade-off noise immunity versus comparator sensitivity.
5.9 Analog Multiplexer
5.7 Reference DACs
For a full matrix representation of all possible routing using this
MUX, refer to the PowerPSoC Technical Reference Manual.
The reference DACs are used to generate set points for various
analog modules such as Hysteretic controllers and comparators.
The reference DACs include the following key features:
■
8-bit resolution
■
Guaranteed monotonic operation
Document Number: 001-46319 Rev. *R
The PowerPSoC family’s analog MUX is designed to route
signals from the CSA output, function I/O pins and the DACs to
comparator inputs and the current sense inputs of the hysteretic
controllers. Additionally, CSA outputs can be routed to the AINX
block using this MUX.
The CPU configures the Power Peripherals Analog Multiplexer
connections using memory mapped registers. The analog
multiplexer includes the following key features:
■
Signal integrity for minimum signal corruption
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5.10 Digital Multiplexer
Figure 5-6. PowerPSoC in Master/Slave Configuration
PowerPSoC
(Slave 0)
The PowerPSoC family’s digital MUX is a configurable switching
matrix that connects the power peripheral digital resources.
For a full matrix representation of all possible routing using this
MUX, refer to the PowerPSoC Technical Reference Manual.
FN0[x]
DIM
This power peripheral digital multiplexer is independent of the
main PSoC digital buses or global interconnect of the PSoC core.
The digital multiplexer includes the following key features:
■
Hysteretic
Controller
PowerPSoC
(Slave 1)
Connect signals to ensure needed flexibility
5.11 Function Pins (FN0[0:3])
FN0[x]
FN0[0]
The function I/O pins are a set of dedicated control pins used to
perform system level functions with the power peripheral blocks
of the PowerPSoC. These pins are dynamically configurable,
enabling them to perform a multitude of input and output
functions. These I/Os have direct access to the input and output
of the voltage comparators, input of the hysteretic controller, and
output of the digital PWM blocks for the device. The function I/O
pins are register mapped. The microcontroller can control and
read the state of these pins and the interrupt function.
DIM
Hysteretic
Controller
FN0[1]
PowerPSoC
(Master)
PowerPSoC
(Slave 2)
FN0[2]
FN0[3]
FN0[x]
DIM
Hysteretic
Controller
Some of the key system benefits of the function I/O are:
■
Enabling an external higher voltage current-sense amplifier as
shown in Figure 5-5.
■
Synchronizing dimming of multiple PowerPSoC controllers as
shown in Figure 5-6.
■
Programmable fail-safe monitor and dedicated shutdown of
hysteretic controller as shown in Figure 5-7.
Along with the these functions, these I/Os also provide interrupt
functionality, enabling intelligent system responses to power
control lighting system status.
Figure 5-5. External CSA and FET Application
PowerPSoC
(Slave 3)
FN0[x]
DIM
Hysteretic
Controller
Figure 5-7. Event Detection
Event Detect
FN0[0]
Trip
Hysteretic Mode
Controller 0
External
Gate Drive 0
GD0
External
Gate Drive 3
GD3
HVDD
External CSA
+
-
Rsense
VLED > 32V
{
.
.
.
.
.
.
Event Detect
PowerPSoC
.
.
.
FN0[3]
Trip
Hysteretic Mode
Controller 3
DAC0
Hysteretic Mode
Controller 0
FN0[0]
External
Gate Drive 0
GD 0
External FET
DAC1
.
.
.
FN0[1]
FN0[2]
FN0[3]
DAC6
Hysteretic Mode
Controller 3
External
Gate Drive 3
GD 3
DAC7
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6. PSoC Core
The PSoC core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
general purpose I/O(GPIO).
also allow signal multiplexing and performing logic operations.
This configurability frees your designs from the constraints of a
fixed peripheral controller.
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture
microprocessor. The CPU uses an interrupt controller with up to
20 vectors to simplify programming of real time embedded
events. The program execution is timed and protected using the
included sleep and watchdog timers (WDT) time and protect
program execution.
There are four digital blocks in each row. This allows optimum
choice of system resources for your application.
Figure 6-1. Digital System Block Diagram
P o rt 1
P o rt 2
D ig ita l C lo c k s
F ro m C o re
Memory encompasses 16 K of flash for program storage, 1 K of
SRAM for data storage, and up to 2 K of EEPROM emulated
using the flash. Program flash uses four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
D IG IT A L S Y S T E M
Row Input
Configuration
DBB00
DBB01
DCB02
4
DCB03
4
Row Output
Row 0
Configuration
Digital peripheral configurations include:
8
Row Output
The digital system contains eight digital PSoC blocks. Each block
is an 8-bit resource that can be used alone or combined with
other blocks to form 8, 16, 24, and 32-bit peripherals, which are
called user module references.
8
Configuration
6.1 Digital System
T o A n a lo g
S y s te m
T o S y s te m B u s
D ig ita l P S o C B lo c k A r r a y
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz internal main oscillator (IMO) accurate to
4 percent over temperature and voltage. The 24 MHz IMO can
also be doubled to 48 MHz for use by the digital system. A low
power 32 kHz internal low-speed oscillator (ILO) is provided for
the sleep timer and WDT. The clocks, together with
programmable clock dividers (as a system resource), provide the
flexibility to integrate almost any timing requirement into the
PowerPSoC device.
PowerPSoC GPIOs provide connection to the CPU, digital, and
analog resources of the device. Each pin’s drive mode may be
selected from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
P o rt 0
8
8
Row 1
Configuration
Row Input
DBB00
DBB10
DBB11
D
DCB12
4
DCB13
4
G IE [7 :0 ]
G IO [7 :0 ]
G lo b a l D ig ita l
In te rc o n n e c t
G O E [7 :0 ]
G O O [7 :0 ]
6.2 Analog System
The analog system contains six configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PowerPSoC analog functions (most
available as user modules) are:
■
Analog-to-digital converters (up to 2, with 6 to 12-bit resolution,
selectable as incremental, Delta Sigma, and SAR)
Counters (8 to 32 bit)
■
Filters (2 and 4 pole band-pass, low-pass, and notch)
■
Timers (8 to 32 bit)
■
Amplifiers (up to 2, with selectable gain to 48x)
■
UART 8-bit with selectable parity
■
Instrumentation amplifiers (1 with selectable gain to 93x)
■
SPI master and slave
■
Comparators (up to 2, with 16 selectable thresholds)
■
I2C master, slave, and multi-master
■
DACs (up to 2, with 6 to 9-bit resolution)
■
Cyclical redundancy checker/generator (8 to 32 bit)
■
Multiplying DACs (up to 2, with 6 to 9-bit resolution)
■
IrDA
■
■
Pseudo random sequence generators (8 to 32 bit)
High current output drivers (two with 30 mA drive as a PSoC
core resource)
■
1.3 V reference (as a system resource)
■
Modulators
■
Correlators
■
Peak detectors
■
Many other topologies possible
■
DMX512
■
Note The DALI interface is supported through the use of a
combination of the above mentioned user modules. For more
details on the exact configuration and an example project, refer
to the application note, PowerPSoC Firmware Design
Guidelines, Lighting Control Interfaces - AN51012.
The digital blocks can be connected to any GPIO through a
series of global buses that route any signal to any pin. The buses
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Analog blocks are arranged in two columns of three blocks each,
which includes one continuous time (CT) and two switched
capacitor (SC) blocks, as shown in Figure 6-2. on page 14.
Figure 6-2. Analog System Block Diagram
P0[7]
P0[4]
P0[5]
P1[4]
P0[3]
P1[7]
P1[0]
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
Track pad, finger sensing
■
Crosspoint connection between any I/O pin combinations
Like other PSoC devices, PowerPSoC has specific pins
allocated to the reference capacitor (Ref Cap) and modulation
resistor (Mod resistor). These are indicated in the device pinouts
(Section 13). For more details on capacitive sensing, see the
design guide, Getting Started With CapSense. Apart from these,
there are a number of application notes on Capacitive Sensing
on the Cypress webbiest. The PowerPSoC Technical Reference
Manual provides details on the analog system configuration that
enables all I/Os in the device to be CapSense inputs.
P1[5]
6.4 Additional System Resources
P1[1]
P2[2]
AINX
Analog Mux Bus Left
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACM0
ACM1
ACol1Mux
AC1
BCol1Mux
ACol0Mux
Analog Mux Bus Right
CSA Buffered Output
SplitMux Bit
Array
Interface to Digital
System
ACB00
ACB01
ASC10
ASD11
ASD20
ASC21
Vdd
Vss
AGND=VBG
Reference
Generators
System resources provide additional capability useful in
complete systems. Additional resources include a multiplier,
decimator, low voltage detection, and power on reset. Brief
statements describing the merits of each resource follow.
■
Two multiply accumulates (MACs) provide fast 8-bit multipliers
with 32-bit accumulate, to assist in both general math and
digital filters.
■
A decimator provides a custom hardware filter for digital signal
processing applications including creation of delta sigma
ADCs.
■
Low-voltage detection (LVD) interrupts signal the application of
falling voltage levels, while the advanced POR (power on reset)
circuit eliminates the need for a system supervisor.
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. The designer can
generate additional clocks using digital PSoC blocks as clock
dividers.
■
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master applications are
supported.
■
An internal 1.3 V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■
Versatile analog multiplexer system.
Bandgap
Microcontroller Interface (Address Bus, Data Bus, Etc.)
6.3 Analog Multiplexer System
The Analog Mux Bus connects to every GPIO pin in ports 0 to 2.
Pins can be connected to the bus individually or in any
combination. The bus also connects to the analog system for
analysis with comparators and analog-to-digital converters. It
can be split into two sections for simultaneous dual-channel
processing. An additional analog input multiplexer provides a
second path to bring Port 0 pins to the analog array.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
Document Number: 001-46319 Rev. *R
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7. Applications
The PowerPSoC family of devices can be used to add hysteretic current control capability to power applications. The devices can be
used to control current in devices such as LEDs, heating elements, and solenoids. For LED applications, all high-brightness LEDs
(HBLEDs) can be controlled using the PowerPSoC. The following figures show examples of applications in which the PowerPSoC
family of devices adds intelligent power control for power applications.
Figure 7-1. LED Lighting with RGGB Color Mixing Configured as Floating Load Buck Converter
Document Number: 001-46319 Rev. *R
RSENSE
Hysteretic
PWM
Hysteretic
references
Dim
Hysteretic
PWM
Hysteretic
references
Oscillator and
Power
I2C Master and
Slave
Configurable
Analog
Flash, RAM,
and ROM
M8C Core and
IRQ
Configurable
Digital Blocks
Dim
MOD
Dim
HVDD
RSENSE
DAC0
DAC1
Hysteretic
references
MOD
Dim
MOD
DAC0
DAC1
Hysteretic
references
Hysteretic
PWM
DAC0
DAC1
Dual
Hysteretic
mode
PWM
PWM1
HVDD
RSENSE
MOD
HVDD
RSENSE
DAC0
DAC1
HVDD
Auxiliary
Power
Regulator
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Figure 7-2. LED Lighting with RGBA Color Mixing Driving External MOSFETS as Floating Load Buck Converter
HVDD
Dual mode
1
Hysteretic
Gate Drive
References
Rsense
Dual mode
1
Hysteretic
Gate Drive
PWM
References
Dim
MOD
DAC0
DAC1
Dim
MOD
DAC0
DAC1
References
Dual mode
1
Hysteretic
Gate Drive
PWM
DAC0
DAC1
PWM
HVDD
Rsense
Oscillator and
Power
Flash , RAM ,
and ROM
Gate Drive
PWM
References
Dim
I2C Master and
Slave
Configurable
Analog
M8C Core and
IRQ
Configurable
Digital Blocks
Dim
MOD
Dual mode
1
Hysteretic
HVDD
Rsense
DAC0
DAC1
Rsense
MOD
HVDD
Auxiliary
Power
Regulator
Figure 7-3. LED Lighting with a Single Channel Boost Driving Three Floating Load Buck Channels
HVDD
R SENSE
Document Number: 001-46319 Rev. *R
Dim
Oscillator and
Power
I2 C Master and
Slave
Configurable
Analog
Flash, RAM,
and ROM
M8C Core and
IRQ
Configurable
Digital Blocks
R SENSE
Hysteretic
PWM
Hysteretic
references
Dim
MOD
Hysteretic
references
MOD
Dim
Hysteretic
PWM
DAC0
DAC1
Hysteretic
references
MOD
Dim
MOD
DAC0
DAC1
Hysteretic
references
Hysteretic
PWM
DAC0
DAC1
Hysteretic
PWM
R SENSE
DAC0
DAC1
R SENSE
Auxiliary
Power
Regulator
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8. PowerPSoC Device Characteristics
There are two major groups of devices in the PowerPSoC family. One group is a 4-channel 56-pin QFN and the other is a 3-channel
56-pin QFN. These are summarized in the following table.
Table 8-1. PowerPSoC Device Characteristics
Device Group
Internal
Power FETs
External
Gate
Drivers
Digital I/O
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SRAM
Size
Flash Size
CY8CLED04D01-56LTXI
4X1.0 A
4
14
2
8
14
2
2
6
1K
16 K
CY8CLED04D02-56LTXI
4X0.5 A
4
14
2
8
14
2
2
6
1K
16 K
CY8CLED04G01-56LTXI
0
4
14
2
8
14
2
2
6
1K
16 K
CY8CLED03D01-56LTXI
3X1.0 A
3
14
2
8
14
2
2
6
1K
16 K
CY8CLED03D02-56LTXI
3X0.5 A
3
14
2
8
14
2
2
6
1K
16 K
CY8CLED03G01-56LTXI
0
3
14
2
8
14
2
2
6
1K
16 K
CY8CLED02D01-56LTXI
2X1.0 A
2
14
2
8
14
2
2
6
1K
16 K
CY8CLED01D01-56LTXI
1X1.0 A
1
14
2
8
14
2
2
6
1K
16 K
CY8CLED01D01-56LTXQ
1X1.0 A
1
14
2
8
14
2
2
6
1K
16 K
Document Number: 001-46319 Rev. *R
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9. Getting Started
The quickest way to understand the PowerPSoC device is to
read this datasheet and then use the PSoC Designer integrated
development environment (IDE). This datasheet is an overview
of the PowerPSoC integrated circuit and presents specific pin,
register, and electrical specifications. For in depth information,
along with detailed programming information, refer to the
PowerPSoC Technical Reference Manual.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PowerPSoC device datasheets on the
web at www.cypress.com.
9.1 Application Notes
Application notes are an excellent introduction to a wide variety
of possible PowerPSoC designs. Layout guidelines, thermal
management and firmware design guidelines are some of the
topics covered. To view the PowerPSoC application notes, go to
htttp://www.cypress.com/powerpsoc and click on the Application
Notes link.
9.2 Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PowerPSoC development. For more information on the kits or to
purchase a kit from the Cypress web site, go to
htttp://www.cypress.com/powerpsoc and click on the
Development Kits link.
9.3 Training
Free PowerPSoC technical training (on demand, webinars, and
workshops) is available online at www.cypress.com/training. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
9.4 CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PowerPSoC designs. To contact or
become a PSoC Consultant go to www.cypress.com/cypros.
9.5 Technical Support
PowerPSoC application engineers take pride in fast and
accurate response. They can be reached with a 24-hour
guaranteed response at http://www.cypress.com/support/. If you
cannot find an answer to your question, call technical support at
1-800-541-4736.
10. Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
development environment for the Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP, Windows Vista, or Windows 7.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party
assemblers and C compilers.
Document Number: 001-46319 Rev. *R
PSoC Designer also supports C language compilers developed
specifically for the devices in the PowerPSoC family.
10.1 PSoC Designer Software Subsystems
10.1.1 Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PowerPSoC
blocks. Examples of user modules are current sense amplifiers,
PrISM, PWM, DMM, Floating Load Buck, and Boost. Configure
the user modules for your chosen application and connect them
to each other and to the proper pins. Then generate your project.
This prepopulates your project with APIs and libraries that you
can use to program your application.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
10.1.2 Code Generation Tools
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PowerPSoC family of devices. The products
allow you to create complete C programs for the PowerPSoC
family of devices.
The optimizing C compilers provide all the features of C tailored
to the PowerPSoC architecture. They come complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
10.1.3 Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PowerPSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write I/O
registers, read and write CPU registers, set and clear
breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
10.1.4 Online Help System
The online help system displays online, context-sensitive help
for you. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to faqs and an Online
Support Forum to aid the designer in getting started.
Page 18 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
10.2 In-Circuit Emulator
A low cost, high functionality in-circuit emulator (ICE) is available
for development support. This hardware has the capability to
program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PowerPSoC devices.
11. Designing with User Modules
The development process for the PowerPSoC device differs
from that of a traditional fixed function microprocessor. The
configurable power, analog, and digital hardware blocks give the
PowerPSoC architecture a unique flexibility that pays dividends
in managing specification change during development and by
lowering inventory costs. These configurable resources, called
PowerPSoC Blocks, have the ability to implement a wide variety
of user-selectable functions. The PowerPSOC development
process can be summarized in the following four steps:
1. Select components
2. Configure components
3. Organize and connect
4. Generate, Verify and debug
Select Components. In the chip-level view the components are
called “user modules”. User modules make selecting and
implementing peripheral devices simple and come in power,
analog, digital, and mixed signal varieties. The standard user
module library contains over 50 common peripherals such as
current sense amplifiers, PrISM, PWM, DMM, Floating Buck,
Boost, ADCs, DACs, Timers, Counters, UARTs, and other not so
common peripherals such as DTMF generators and Bi-Quad
analog filter sections.
Configure Components. Each of the components selected
establishes the basic register settings that implement the
selected function. They also provide parameters allowing
precise configuration to your particular application. For example,
a PWM User Module configures one or more digital PSoC
blocks, one for each 8 bits of resolution. Configure the
parameters and properties to correspond to your chosen
application. Enter values directly or by selecting values from
drop-down menus.
Document Number: 001-46319 Rev. *R
The chip-level user modules are documented in datasheets that
are viewed directly in PSoC Designer. These datasheets explain
the internal operation of the component and provide
performance specifications. Each datasheet describes the use
of each user module parameter and other information needed to
successfully implement your design.
Organize and Connect. Signal chains can be built at the chip
level by interconnecting user modules to each other and the I/O
pins. In the chip-level view, perform the selection, configuration,
and routing so that you have complete control over the use of all
on-chip resources.
Generate, Verify, and Debug. When ready to test the hardware
configuration or move on to developing code for the project,
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the device to your specification and provides the high level user
module API functions.
The chip-level designs generate software based on your design.
The chip-level view provides application programming interfaces
(APIs) with high level functions to control and respond to
hardware events at run-time and interrupt service routines that
you can adapt as needed.
A complete code development environment allows development
and customization of your applications in C, assembly language,
or both.
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the ICE where it runs at full speed.
Debugger capabilities rival those of systems costing many times
more. In addition to traditional single step, run-to-breakpoint and
watch-variable features, the Debugger provides a large trace
buffer and allows you to define complex breakpoint events that
include monitoring address and data bus values, memory
locations, and external signals.
Page 19 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
12. Pin Information
12.1 CY8CLED04D0x 56-Pin Part Pinout (without OCD)
The CY8CLED04D01 and CY8CLED04D02 PowerPSoC devices are available with the following pinout information. Every port pin
(labeled with a “P” and “FN0”) is capable of Digital I/O.
Table 12-1. CY8CLED04D0x 56-Pin Part Pinout (QFN)
2
3
I/O
I/O
I
I/O
4
I/O
I/O
5
I/O
I
6
I/O
I
7
8
9
10
11
12
13
14
15
16
17
18
19
I/O
I/O
I
I
I
I
20
21
22
23
24
I
25
26
27
28
29
30
I
I
O
31
32
33
34
35
36
37
38
I
O
O
O
39
40
41
42
43
GPIO/I2C SDA (Secondary)/
ISSP SDATA
P2[2]
GPIO/Direct Switch Cap connection
P0[3]
GPIO/Analog Input (Column 0)/
Analog Output (Column 0)
P0[5]
GPIO/Analog Input (Column 0)/
Analog Output (Column 1)/
Capsense Ref Cap
P0[7]
GPIO/Analog Input (Column 0)/
Capsense Ref Cap
P1[1]
GPIO/I2C SCL (Secondary)/ISSP
SCLK
P1[5]
GPIO/I2C SDA (Primary)
P1[7]
GPIO/I2C SCL (Primary)
VSS
Digital Ground
NC
No Connect
NC
No Connect
NC
No Connect
NC
No Connect
XRES
External Reset
VDD
Digital Power Supply
VSS
Digital Ground
AVSS
Analog Ground
AVDD
Analog Power Supply
CSN2
Current Sense Negative Input CSA2
CSP2
Current Sense Positive Input and
Power Supply - CSA2
CSP3
Current Sense Positive Input and
Power Supply - CSA3
CSN3
Current Sense Negative Input 3
SREGCOMP Voltage Regulator Error Amp Comp
SREGFB
Regulator Voltage Mode Feedback
Node
SREGCSN
Current Mode Feedback Negative
SREGCSP
Current Mode Feedback Positive
SREGSW
Switch Mode Regulator OUT
SREGHVIN Switch Mode Regulator IN
GDVDD
Gate Driver Power Supply
GDVSS
Gate Driver Ground
Pin
No. Digital
PGND3[1]
GD3
SW3
PGND2[1]
GD2
SW2
SW1
Power FET Ground 3
External Low Side Gate Driver 3
Power Switch 3
Power FET Ground 2
External Low Side Gate Driver 2
Power Switch 2
Power Switch 1
44
45
46
47
48
49
50
GD1
External Low Side Gate Driver 1
51
PGND1[1]
SW0
Power FET Ground 1
Power Switch 0
52
53
GD0
PGND0[1]
GDVSS
External Low Side Gate Driver 0
Power FETGround 0
Gate Driver Ground
54
55
56
P1[0]
O
QFN Top View
P1[0]
P2[2]
P0[3]
P0[5]
P0[7]
P1[1]
P1[5]
P1[7]
VSS
NC
NC
NC
NC
XRES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Exposed
Pad
PGND0
GD0
SW0
PGND1
GD1
SW1
SW2
GD2
PGND2
SW3
GD3
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PGND3
GDVSS
GDVDD
SREGSW
SREGHVIN
I
P1[4]
VSS
VDD
P0[4]
CSN1
CSP1
CSP0
CSN0
FN0[3]
FN0[2]
FN0[1]
FN0[0]
GDVDD
GDVSS
I/O
Description
56
55
54
53
52
51
50
49
48
47
46
45
44
43
1
Name
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Rows
Figure 12-1. CY8CLED04D0x 56-Pin PowerPSoC Device
Type
Analog
Power
Columns Peripherals
VDD
VSS
AVSS
AVDD
CSN2
CSP2
CSP3
CSN3
SREGCOMP
SREGFB
SREGCSN
SREGCSP
Pin
No. Digital
* Connect Exposed Pad to PGNDx
Type
Analog
Power
Rows Columns Peripherals
I/O
I/O
I/O
I/O
I
Name
GDVDD
FN0[0]
FN0[1]
FN0[2]
FN0[3]
CSN0
CSP0
CSP1
I
I/O
I/O
I
CSN1
P0[4]
I
VDD
VSS
P1[4]
Description
Gate Driver Power Supply
Function I/O
Function I/O
Function I/O
Function I/O
Current Sense Negative Input 0
Current Sense Positive Input and
Power Supply - CSA0
Current Sense Positive Input and
Power Supply - CSA1
Current Sense Negative Input 1
GPIO/Analog Input (Column 1) /
Bandgap Output
Digital Power Supply
Digital Ground
GPIO / External Clock Input
Note
1. All PGNDx pins must be connected to the ground plane on the PCB irrespective of whether the corresponding PowerPSoC channel is used or not.
Document Number: 001-46319 Rev. *R
Page 20 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
12.2 CY8CLED04G01 56-Pin Part Pinout (without OCD)
The CY8CLED04G01 PowerPSoC device is available with the following pinout information. Every port pin (labeled with a “P” and
“FN0”) is capable of Digital I/O.
Table 12-2. CY8CLED04G01 56-Pin Part Pinout (QFN)
Type
Analog
Power
Columns Peripherals
I
I/O
4
I/O
I/O
5
I/O
I
6
I/O
I
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O
I/O
I
I
I
I
21
22
23
24
I
25
26
27
28
29
30
I
I
O
31
32
33
34
35
36
37
38
I
P1[0]
P2[2]
P0[3]
P0[5]
P0[7]
P1[1]
P1[5]
P1[7]
VSS
NC
NC
NC
NC
XRES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Exposed
Pad
PGND3[3]
O
O
O
O
GD3
DNC[2]
PGND2[3]
GD2
DNC[2]
DNC[2]
Power FET Ground 3
External Low Side Gate Driver 3
Do Not Connect
Power FET Ground 2
External Low Side Gate Driver 2
Do Not Connect
Do Not Connect
44
45
46
47
48
49
50
GD1
External Low Side Gate Driver 1
51
PGND1[3]
DNC[2]
Power FET Ground 1
Do Not Connect
52
53
GD0
PGND0[3]
GDVSS
External Low Side Gate Driver 0
Power FET Ground 0
Gate Driver Ground
54
55
56
Name
GDVDD
FN0[0]
FN0[1]
FN0[2]
FN0[3]
CSN0
CSP0
CSP1
I
I/O
PGND0
GD0
DNC
PGND1
GD1
DNC
DNC
GD2
PGND2
DNC
GD3
PGND3
GDVSS
GDVDD
Type
I/O
I/O
I/O
I/O
I
I/O
42
41
40
39
38
37
36
35
34
33
32
31
30
29
* Connect Exposed Pad to PGNDx
Analog
Power
Rows Columns Peripherals
39
40
41
42
43
QFN Top View
SREGHVIN
I/O
I/O
SREGCSP
SREGSW
2
3
GPIO/I2C SDA (Secondary)/
ISSP SDATA
P2[2]
GPIO/Direct Switch Cap connection
P0[3]
GPIO/Analog Input (Column 0)/
Analog Output (Column 0)
P0[5]
GPIO/Analog Input (Column 0)/
Analog Output (Column 1)/
Capsense Ref Cap
P0[7]
GPIO/Analog Input (Column 0)/
Capsense Ref Cap
P1[1]
GPIO/I2C SCL (Secondary)/
ISSP SCLK
P1[5]
GPIO/I2C SDA (Primary)
P1[7]
GPIO/I2C SCL (Primary)
VSS
Digital Ground
NC
No Connect
NC
No Connect
NC
No Connect
NC
No Connect
XRES
External Reset
VDD
Digital Power Supply
VSS
Digital Ground
AVSS
Analog Ground
AVDD
Analog Power Supply
CSN2
Current Sense Negative Input 2
CSP2
Current Sense Positive Input and
Power Supply - CSA2
CSP3
Current Sense Positive Input and
Power Supply - CSA3
CSN3
Current Sense Negative Input 3
SREGCOMP Voltage Regulator Error Amp Comp
SREGFB
Regulator Voltage Mode Feedback
Node
SREGCSN
Current Mode Feedback Negative
SREGCSP
Current Mode Feedback Positive
SREGSW
Switch Mode Regulator OUT
SREGHVIN Switch Mode Regulator IN
GDVDD
Gate Driver Power Supply
Pin
GDVSS
Gate Driver Ground
No. Digital
P1[0]
SREGCOMP
SREGFB
SREGCSN
I
Figure 12-2. CY8CLED04G01 56-Pin PowerPSoC Device
P1[4]
VSS
VDD
P0[4]
CSN1
CSP1
CSP0
CSN0
FN0[3]
FN0[2]
FN0[1]
FN0[0]
GDVDD
GDVSS
I/O
Description
56
55
54
53
52
51
50
49
48
47
46
45
44
43
1
Name
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Rows
VDD
VS S
AVS S
AVD D
CSN 2
CSP 2
CSP 3
CSN 3
Pin
No. Digital
I
CSN1
P0[4]
I
VDD
VSS
P1[4]
Description
Gate Driver Power Supply
Function I/O
Function I/O
Function I/O
Function I/O
Current Sense Negative Input 0
Current Sense Positive Input and
Power Supply - CSA0
Current Sense Positive Input and
Power Supply - CSA1
Current Sense Negative Input 1
GPIO/Analog Input (Column 1) /
Bandgap Output
Digital Power Supply
Digital Ground
GPIO / External Clock Input
Notes
2. Do Not Connect (DNC) pins must be left unconnected, or floating. Connecting these pins to power or ground may cause improper operation or failure of the device.
3. All PGNDx pins must be connected to the ground plane on the PCB irrespective of whether the corresponding PowerPSoC channel is used or not.
Document Number: 001-46319 Rev. *R
Page 21 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
12.3 CY8CLED04DOCD1 56-Pin Part Pinout (with OCD)
The CY8CLED04DOCD1 PowerPSoC device is available with the following pinout information. Every port pin (labeled with a “P” and
“FN0”) is capable of Digital I/O.
Table 12-3. CY8CLED04DOCD1 56-Pin Part Pinout (QFN)
I
6
I/O
I
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O
I/O
I
I
I/O
I/O
I/O
I/O
I
I
21
22
23
24
I
25
26
27
28
29
30
I
I
O
31
32
33
34
35
36
37
38
I
O
O
O
O
PGND3[4]
GD3
SW3
PGND2[4]
GD2
SW2
SW1
Power FET Ground 3
External Low Side Gate Driver 3
Power Switch 3
Power FET Ground 2
External Low Side Gate Driver 2
Power Switch 2
Power Switch 1
44
45
46
47
48
49
50
GD1
External Low Side Gate Driver 1
51
PGND1[4]
SW0
Power FET Ground 1
Power Switch 0
52
53
GD0
PGND0[4]
GDVSS
External Low Side Gate Driver 0
Power FET Ground 0
Gate Driver Ground
54
55
56
GDVDD
GDVSS
44
43
Name
GDVDD
FN0[0]
FN0[1]
FN0[2]
FN0[3]
CSN0
CSP0
CSP1
I
I/O
PGND3
GDVSS
GDVDD
Type
I/O
I/O
I/O
I/O
I
I/O
PGND0
GD0
SW0
PGND1
GD1
SW1
SW2
GD2
PGND2
SW3
GD3
* Connect Exposed Pad to PGNDx
Analog
Power
Rows Columns Peripherals
39
40
41
42
43
Exposed
Pad
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SREGSW
SREGHVIN
I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
25
26
27
28
5
P1[0]
P2[2]
P0[3]
P0[5]
P0[7]
P1[1]
P1[5]
P1[7]
VSS
OCDE
OCDO
CCLK
HCLK
XRES
SREGCSN
SREGCSP
I/O
CSN0
FN0[3]
FN0[2]
FN0[1]
FN0[0]
I/O
CSN1
CSP1
CSP0
4
52
51
50
49
48
47
46
45
I
I/O
17
18
19
20
21
22
23
24
I/O
I/O
QFN Top View
AVSS
AVDD
CSN2
CSP2
CSP3
2
3
GPIO/I2C SDA (Secondary)/
ISSP SDATA
P2[2]
GPIO/Direct Switch Cap connection
P0[3]
GPIO/Analog Input (Column 0)/
Analog Output (Column 0)
P0[5]
GPIO/Analog Input (Column 0)/
Analog Output (Column 1) /
Capsense Ref Cap
P0[7]
GPIO/Analog Input (Column 0)/
Capsense Ref Cap
P1[1]
GPIO/I2C SCL (Secondary)/
ISSP SCLK
P1[5]
GPIO/I2C SDA (Primary)
P1[7]
GPIO/I2C SCL (Primary)
VSS
Digital Ground
OCDE
On Chip Debugger Port
OCDO
On Chip Debugger Port
CCLK
On Chip Debugger Port
HCLK
On Chip Debugger Port
XRES
External Reset
VDD
Digital Power Supply
VSS
Digital Ground
AVSS
Analog Ground
AVDD
Analog Power Supply
CSN2
Current Sense Negative Input 2
CSP2
Current Sense Positive Input and
Power Supply - CSA2
CSP3
Current Sense Positive Input and
Power Supply - CSA3
CSN3
Current Sense Negative Input 3
SREGCOMP Voltage Regulator Error Amp Comp
SREGFB
Regulator Voltage Mode Feedback
Node
SREGCSN
Current Mode Feedback Negative
SREGCSP
Current Mode Feedback Positive
SREGSW
Switch Mode Regulator OUT
SREGHVIN Switch Mode Regulator IN
GDVDD
Gate Driver Power Supply
Pin
GDVSS
Gate Driver Ground
No. Digital
P1[0]
P1[4]
VSS
VDD
P0[4]
I
Figure 12-3. CY8CLED04DOCD1 56-Pin PowerPSoC Device
56
55
54
53
I/O
Description
15
16
1
Name
CSN3
SREGCOMP
SREGFB
Type
Analog
Power
Rows Columns Peripherals
VDD
VSS
Pin
No. Digital
I
CSN1
P0[4]
I
VDD
VSS
P1[4]
Description
Gate Driver Power Supply
Function I/O
Function I/O
Function I/O
Function I/O
Current Sense Negative Input 0
Current Sense Positive Input and
Power Supply - CSA0
Current Sense Positive Input and
Power Supply - CSA1
Current Sense Negative Input 1
GPIO/Analog Input (Column 1) /
Bandgap Output
Digital Power Supply
Digital Ground
GPIO / External Clock Input
Note
4. All PGNDx pins must be connected to the ground plane on the PCB irrespective of whether the corresponding PowerPSoC channel is used or not.
Document Number: 001-46319 Rev. *R
Page 22 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
12.4 CY8CLED03D0x 56-Pin Part Pinout (without OCD)
The CY8CLED03D01 and CY8CLED03D02 PowerPSoC devices are available with the following pinout information. Every port pin
(labeled with a “P” and “FN0”) is capable of Digital I/O.
Table 12-4. CY8CLED03D0x 56-Pin Part Pinout (QFN)
Figure 12-4. CY8CLED03D0x 56-Pin PowerPSoC Device
Power
Rows Columns Peripherals
I/O
I/O
I
I/O
4
I/O
I/O
5
I/O
I
6
I/O
I
7
8
9
10
11
12
13
14
15
16
17
18
19
I/O
I/O
I
I
I
I
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
I
I
I
O
Rows
O
O
Power FET Ground 3
Do Not Connect
Do Not Connect
Power FET Ground 2
External Low Side Gate Driver 2
Power Switch 2
Power Switch 1
44
45
46
47
48
49
50
GD1
External Low Side Gate Driver 1
51
PGND1
SW0
Power FET Ground 1
Power Switch 0
52
53
GD0
PGND0[6]
GDVSS
External Low Side Gate Driver 0
Power FETGround 0
Gate Driver Ground
54
55
56
[6]
39
40
41
42
43
PGND3[6]
DNC[5]
DNC[5]
PGND2[6]
GD2
SW2
SW1
O
QFN Top View
P1[4]
VSS
VDD
P0[4]
CSN1
CSP1
CSP0
CSN0
FN0[3]
FN0[2]
FN0[1]
FN0[0]
GDVDD
GDVSS
2
3
GPIO/I2C SDA (Secondary)/
ISSP SDATA
P2[2]
GPIO/Direct Switch Cap connection
P0[3]
GPIO/Analog Input (Column 0)/
Analog Output (Column 0)
P0[5]
GPIO/Analog Input (Column 0)/
Analog Output (Column 1)/
Capsense Ref Cap
P0[7]
GPIO/Analog Input (Column 0)/
Capsense Ref Cap
P1[1]
GPIO/I2C SCL (Secondary)/
ISSP SCLK
P1[5]
GPIO/I2C SDA (Primary)
P1[7]
GPIO/I2C SCL (Primary)
VSS
Digital Ground
NC
No Connect
NC
No Connect
NC
No Connect
NC
No Connect
XRES
External Reset
VDD
Digital Power Supply
VSS
Digital Ground
AVSS
Analog Ground
AVDD
Analog Power Supply
CSN2
Current Sense Negative Input CSA2
CSP2
Current Sense Positive Input and
Power Supply - CSA2
DNC[5]
Do Not Connect
DNC[5]
Do Not Connect
SREGCOMP Voltage Regulator Error Amp Comp
SREGFB
Regulator Voltage Mode Feedback
Node
SREGCSN
Current Mode Feedback Negative
SREGCSP
Current Mode Feedback Positive
SREGSW
Switch Mode Regulator OUT
SREGHVIN Switch Mode Regulator IN
GDVDD
Gate Driver Power Supply
Pin
GDVSS
Gate Driver Ground
No. Digital
P1[0]
P1[0]
P2[2]
P0[3]
P0[5]
P0[7]
P1[1]
P1[5]
P1[7]
VSS
NC
NC
NC
NC
XRES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
56
55
54
53
52
51
50
49
48
47
46
45
44
43
I
Exposed
Pad
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I/O
Description
VDD
VSS
AVSS
AVDD
CSN2
CSP2
DNC
DNC
SREGCOMP
SREGFB
SREGCSN
SREGCSP
1
Name
PGND3
GDVSS
GDVDD
Type
Analog
Power
Columns Peripherals
Name
GDVDD
FN0[0]
FN0[1]
FN0[2]
FN0[3]
CSN0
CSP0
CSP1
I
I/O
PGND0
GD0
SW0
PGND1
GD1
SW1
SW2
GD2
PGND2
DNC
DNC
* Connect Exposed Pad to PGNDx
I/O
I/O
I/O
I/O
I
I/O
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SREGSW
SREGHVIN
Type
Pin
No. Digital Analog
I
CSN1
P0[4]
I
VDD
VSS
P1[4]
Description
Gate Driver Power Supply
Function I/O
Function I/O
Function I/O
Function I/O
Current Sense Negative Input 0
Current Sense Positive Input and
Power Supply - CSA0
Current Sense Positive Input and
Power Supply - CSA1
Current Sense Negative Input 1
GPIO/Analog Input (Column 1) /
Bandgap Output
Digital Power Supply
Digital Ground
GPIO / External Clock Input
Notes
5. Do Not Connect (DNC) pins must be left unconnected, or floating. Connecting these pins to power or ground may cause improper operation or failure of the device.
6. All PGNDx pins must be connected to the ground plane on the PCB irrespective of whether the corresponding PowerPSoC channel is used or not.
Document Number: 001-46319 Rev. *R
Page 23 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
12.5 CY8CLED03G01 56-Pin Part Pinout (without OCD)
The CY8CLED03G01 PowerPSoC device is available with the following pinout information. Every port pin (labeled with a “P” and
“FN0”) is capable of Digital I/O.
Table 12-5. CY8CLED03G01 56-Pin Part Pinout (QFN)
2
3
I/O
I/O
I
I/O
4
I/O
I/O
5
I/O
I
6
I/O
I
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O
I/O
I
I
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
I
I
I
I
I
O
QFN Top View
P1[0]
P2[2]
P0[3]
P0[5]
P0[7]
P1[1]
P1[5]
P1[7]
VSS
NC
NC
NC
NC
XRES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Exposed
Pad
O
O
PGND3[8]
DNC[7]
DNC[7]
PGND2[8]
GD2
DNC[7]
DNC[7]
Power FET Ground 3
Do Not Connect
Do Not Connect
Power FET Ground 2
External Low Side Gate Driver 2
Do Not Connect
Do Not Connect
44
45
46
47
48
49
50
GD1
External Low Side Gate Driver 1
51
Power FET Ground 1
Do Not Connect
52
53
External Low Side Gate Driver 0
Power FET Ground 0
Gate Driver Ground
54
55
56
PGND1
DNC[7]
O
[8]
GD0
PGND0[8]
GDVSS
Name
GDVDD
FN0[0]
FN0[1]
FN0[2]
FN0[3]
CSN0
CSP0
CSP1
I
I/O
PGND0
GD0
DNC
PGND1
GD1
DNC
DNC
GD2
PGND2
DNC
DNC
PGND3
GDVSS
GDVDD
Type
I/O
I/O
I/O
I/O
I
I/O
42
41
40
39
38
37
36
35
34
33
32
31
30
29
* Connect Exposed Pad to PGNDx
Analog
Power
Rows Columns Peripherals
39
40
41
42
43
GPIO/I2C SDA (Secondary)/
ISSP SDATA
P2[2]
GPIO/Direct Switch Cap connection
P0[3]
GPIO/Analog Input (Column 0)/
Analog Output (Column 0)
P0[5]
GPIO/Analog Input (Column 0)/
Analog Output (Column 1)/
Capsense Ref Cap
P0[7]
GPIO/Analog Input (Column 0)/
Capsense Ref Cap
P1[1]
GPIO/I2C SCL (Secondary)/
ISSP SCLK
P1[5]
GPIO/I2C SDA (Primary)
P1[7]
GPIO/I2C SCL (Primary)
VSS
Digital Ground
NC
No Connect
NC
No Connect
NC
No Connect
NC
No Connect
XRES
External Reset
VDD
Digital Power Supply
VSS
Digital Ground
AVSS
Analog Ground
AVDD
Analog Power Supply
CSN2
Current Sense Negative Input 2
CSP2
Current Sense Positive Input and
Power Supply - CSA2
DNC[7]
Do Not Connect
DNC[7]
Do Not Connect
SREGCOMP Voltage Regulator Error Amp Comp
SREGFB
Regulator Voltage Mode Feedback
Node
SREGCSN
Current Mode Feedback Negative
SREGCSP
Current Mode Feedback Positive
SREGSW
Switch Mode Regulator OUT
SREGHVIN Switch Mode Regulator IN
GDVDD
Gate Driver Power Supply
Pin
GDVSS
Gate Driver Ground
No. Digital
P1[0]
SREGSW
SREGHVIN
I
Figure 12-5. CY8CLED03G01 56-Pin PowerPSoC Device
P1[4]
VSS
VDD
P0[4]
CSN1
CSP1
CSP0
CSN0
FN0[3]
FN0[2]
FN0[1]
FN0[0]
GDVDD
GDVSS
I/O
Description
56
55
54
53
52
51
50
49
48
47
46
45
44
43
1
Name
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Rows
Type
Analog
Power
Columns Peripherals
VDD
VSS
AVSS
AVDD
CSN2
CSP2
DNC
DNC
SREGCOMP
SREGFB
SREGCSN
SREGCSP
Pin
No. Digital
I
CSN1
P0[4]
I
VDD
VSS
P1[4]
Description
Gate Driver Power Supply
Function I/O
Function I/O
Function I/O
Function I/O
Current Sense Negative Input 0
Current Sense Positive Input and
Power Supply - CSA0
Current Sense Positive Input and
Power Supply - CSA1
Current Sense Negative Input 1
GPIO/Analog Input (Column 1) /
Bandgap Output
Digital Power Supply
Digital Ground
GPIO / External Clock Input
Notes
7. Do Not Connect (DNC) pins must be left unconnected, or floating. Connecting these pins to power or ground may cause improper operation or failure of the device.
8. All PGNDx pins must be connected to the ground plane on the PCB irrespective of whether the corresponding PowerPSoC channel is used or not.
Document Number: 001-46319 Rev. *R
Page 24 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
12.6 CY8CLED02D01 56-Pin Part Pinout (without OCD)
The CY8CLED02D01 PowerPSoC devices are available with the following pinout information. Every port pin (labeled with a “P” and
“FN0”) is capable of Digital I/O.
Table 12-6. CY8CLED02D01 56-Pin Part Pinout (QFN)
Figure 12-6. CY8CLED02D01 56-Pin PowerPSoC Device
Power
Rows Columns Peripherals
I/O
I/O
I
I/O
4
I/O
I/O
5
I/O
I
6
I/O
I
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I/O
I/O
I
I
25
26
27
28
29
30
I
I
I
I
O
Rows
PGND3[10]
31
32
33
34
35
36
37
38
O
39
40
41
42
43
O
DNC[9]
DNC[9]
PGND2[10]
DNC[9]
DNC[9]
SW1
Power FET Ground 3
Do Not Connect
Do Not Connect
Power FET Ground 2
Do Not Connect
Do Not Connect
Power Switch 1
44
45
46
47
48
49
50
GD1
External Low Side Gate Driver 1
51
PGND1[10]
SW0
Power FET Ground 1
Power Switch 0
52
53
GD0
PGND0[10]
GDVSS
External Low Side Gate Driver 0
Power FETGround 0
Gate Driver Ground
54
55
56
QFN Top View
P1[4]
VSS
VDD
P0[4]
CSN1
CSP1
CSP0
CSN0
FN0[3]
FN0[2]
FN0[1]
FN0[0]
GDVDD
GDVSS
2
3
GPIO/I2C SDA (Secondary)/
ISSP SDATA
P2[2]
GPIO/Direct Switch Cap connection
P0[3]
GPIO/Analog Input (Column 0)/
Analog Output (Column 0)
P0[5]
GPIO/Analog Input (Column 0)/
Analog Output (Column 1)/
Capsense Ref Cap
P0[7]
GPIO/Analog Input (Column 0)/
Capsense Ref Cap
P1[1]
GPIO/I2C SCLK (Secondary)/
ISSP SCLK
P1[5]
GPIO/I2C SDA (Primary)
P1[7]
GPIO/I2C SCL (Primary)
VSS
Digital Ground
NC
No Connect
NC
No Connect
NC
No Connect
NC
No Connect
XRES
External Reset
VDD
Digital Power Supply
VSS
Digital Ground
AVSS
Analog Ground
AVDD
Analog Power Supply
DNC[9]
Do Not Connect
DNC[9]
Do Not Connect
DNC[9]
Do Not Connect
DNC[9]
Do Not Connect
SREGCOMP Voltage Regulator Error Amp Comp
SREGFB
Regulator Voltage Mode Feedback
Node
SREGCSN
Current Mode Feedback Negative
SREGCSP
Current Mode Feedback Positive
SREGSW
Switch Mode Regulator OUT
SREGHVIN Switch Mode Regulator IN
GDVDD
Gate Driver Power Supply
Pin
GDVSS
Gate Driver Ground
No. Digital
P1[0]
P1[0]
P2[2]
P0[3]
P0[5]
P0[7]
P1[1]
P1[5]
P1[7]
VSS
NC
NC
NC
NC
XRES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
56
55
54
53
52
51
50
49
48
47
46
45
44
43
I
Exposed
Pad
15
16
17
18
19
20
21
22
23
24
25
26
27
28
I/O
Description
VDD
VSS
AVSS
AVDD
DNC
DNC
DNC
DNC
SREGCOMP
SREGFB
SREGCSN
SREGCSP
1
Name
PGND3
GDVSS
GDVDD
Type
Analog
Power
Columns Peripherals
Name
GDVDD
FN0[0]
FN0[1]
FN0[2]
FN0[3]
CSN0
CSP0
CSP1
I
I/O
PGND0
GD0
SW0
PGND1
GD1
SW1
DNC
DNC
PGND2
DNC
DNC
* Connect Exposed Pad to PGNDx
I/O
I/O
I/O
I/O
I
I/O
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SREGSW
SREGHVIN
Type
Pin
No. Digital Analog
I
CSN1
P0[4]
I
VDD
VSS
P1[4]
Description
Gate Driver Power Supply
Function I/O
Function I/O
Function I/O
Function I/O
Current Sense Negative Input 0
Current Sense Positive Input and
Power Supply - CSA0
Current Sense Positive Input and
Power Supply - CSA1
Current Sense Negative Input 1
GPIO/Analog Input (Column 1) /
Bandgap Output
Digital Power Supply
Digital Ground
GPIO / External Clock Input
Notes
9. Do Not Connect (DNC) pins must be left unconnected, or floating. Connecting these pins to power or ground may cause improper operation or failure of the device.
10. All PGNDx pins must be connected to the ground plane on the PCB irrespective of whether the corresponding PowerPSoC channel is used or not.
Document Number: 001-46319 Rev. *R
Page 25 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
12.7 CY8CLED01D01 56-Pin Part Pinout (without OCD)
The CY8CLED01D01 PowerPSoC device is available with the following pinout information. Every port pin (labeled with a “P” and
“FN0”) is capable of Digital I/O.
Table 12-7. CY8CLED01D01 56-Pin Part Pinout (QFN)
2
3
I/O
I/O
I
I/O
4
I/O
I/O
5
I/O
I
6
I/O
I
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I/O
I/O
I
I
25
26
27
28
29
30
GPIO/I2C SDA (Secondary)/
ISSP SDATA
P2[2]
GPIO/Direct Switch Cap connection
P0[3]
GPIO/Analog Input (Column 0)/
Analog Output (Column 0)
P0[5]
GPIO/Analog Input (Column 0)/
Analog Output (Column 1)/
Capsense Ref Cap
P0[7]
GPIO/Analog Input (Column 0)/
Capsense Ref Cap
P1[1]
GPIO/I2C SCLK (Secondary)/
ISSP SCLK
P1[5]
GPIO/I2C SDA (Primary)
P1[7]
GPIO/I2C SCL (Primary)
VSS
Digital Ground
NC
No Connect
NC
No Connect
NC
No Connect
NC
No Connect
XRES
External Reset
VDD
Digital Power Supply
VSS
Digital Ground
AVSS
Analog Ground
AVDD
Analog Power Supply
DNC[11]
Do Not Connect
DNC[11]
Do Not Connect
DNC[11]
Do Not Connect
DNC[11]
Do Not Connect
SREGCOMP Voltage Regulator Error Amp Comp
SREGFB
Regulator Voltage Mode Feedback
Node
SREGCSN
Current Mode Feedback Negative
SREGCSP
Current Mode Feedback Positive
SREGSW
Switch Mode Regulator OUT
SREGHVIN Switch Mode Regulator IN
GDVDD
Gate Driver Power Supply
Pin
GDVSS
Gate Driver Ground
No. Digital
P1[0]
I
I
I
I
O
QFN Top View
P1[0]
P2[2]
P0[3]
P0[5]
P0[7]
P1[1]
P1[5]
P1[7]
VSS
NC
NC
NC
NC
XRES
Exposed
Pad
PGND0
GD0
SW0
PGND1
DNC
DNC
DNC
DNC
PGND2
DNC
DNC
PGND3
GDVSS
GDVDD
Type
Analog
Power
Rows Columns Peripherals
31
32
33
34
35
36
37
DNC[11]
DNC[11]
PGND2[12]
DNC[11]
DNC[11]
DNC[11]
Power FET Ground 3
Do Not Connect
Do Not Connect
Power FET Ground 2
Do Not Connect
Do Not Connect
Do Not Connect
44
45
46
47
48
49
50
38
39
40
DNC[11]
PGND1[12]
SW0
Do Not Connect
Power FET Ground 1
Power Switch 0
51
52
53
I/O
I
GD0
PGND0[12]
GDVSS
External Low Side Gate Driver 0
Power FET Ground 0
Gate Driver Ground
54
55
56
I/O
I
O
42
41
40
39
38
37
36
35
34
33
32
31
30
29
* Connect Exposed Pad to PGNDx
PGND3[12]
41
42
43
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SREGSW
SREGHVIN
I
Figure 12-7. CY8CLED01D01 56-Pin PowerPSoC Device
P1[4]
VSS
VDD
P0[4]
DNC
DNC
CSP0
CSN0
FN0[3]
FN0[2]
FN0[1]
FN0[0]
GDVDD
GDVSS
I/O
Description
56
55
54
53
52
51
50
49
48
47
46
45
44
43
1
Name
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Rows
Type
Analog
Power
Columns Peripherals
VDD
VSS
AVSS
AVDD
DNC
DNC
DNC
DNC
SREGCOMP
SREGFB
SREGCSN
SREGCSP
Pin
No. Digital
I/O
I/O
I/O
I/O
I
Name
Description
GDVDD
FN0[0]
FN0[1]
FN0[2]
FN0[3]
CSN0
CSP0
Gate Driver Power Supply
Function I/O
Function I/O
Function I/O
Function I/O
Current Sense Negative Input 0
Current Sense Positive Input and
Power Supply - CSA0
[11]
DNC
Do Not Connect
DNC[11] Do Not Connect
P0[4]
GPIO/Analog Input (Column 1) /
Bandgap Output
VDD
Digital Power Supply
VSS
Digital Ground
P1[4]
GPIO / External Clock Input
Notes
11. Do Not Connect (DNC) pins must be left unconnected, or floating. Connecting these pins to power or ground may cause improper operation or failure of the device.
12. All PGNDx pins must be connected to the ground plane on the PCB irrespective of whether the corresponding PowerPSoC channel is used or not.
Document Number: 001-46319 Rev. *R
Page 26 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
13. Register General Conventions
13.1 Abbreviations Used
The register conventions specific to this section are listed in
Table 13-1.
Table 13-1. Register Conventions
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
13.2 Register Naming Conventions
The register naming convention specific to the PSoC core
section of PowerPSoC blocks and their registers is:
<Prefix>mn<Suffix>
where m = row index, n = column index
Document Number: 001-46319 Rev. *R
Therefore, ASD13CR3 is a register for an analog PowerPSoC
block in row 1 column 3.
The register naming convention specific to the power peripheral
section of PowerPSoC blocks and their registers is:
<Prefix>x<Suffix>
where x = number of channel
Therefore, CSA0_CR is a register for a power peripheral
PowerPSoC block in for current sense amplifier, channel 0.
13.3 Register Mapping Tables
The PowerPSoC device has a total register address space of
512 bytes. The register space is also referred to as I/O space and
is broken into two parts. The XIO bit in the flag register (CPU_F)
determines which bank you are currently in. When the XIO bit is
set, you are said to be in the “extended” address space or the
“configuration” registers.
More detailed description of the registers are found in the
PowerPSoC TRM. The TRM can be found at
http://www.cypress.com/powerpsoc and clicking on the
Technical Reference Manual link.
Page 27 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
13.4 Register Map Bank 0 Table
Name
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
FN0DR
FN0IE
FN0GS
FN0DM2
PDMUX_S1
PDMUX_S2
PDMUX_S3
PDMUX_S4
PDMUX_S5
PDMUX_S6
CHBOND_CR
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0
DBB10DR0
DBB10DR1
DBB10DR2
DBB10CR0
DBB11DR0
DBB11DR1
DBB11DR2
DBB11CR0
DCB12DR0
DCB12DR1
DCB12DR2
DCB12CR0
DCB13DR0
DCB13DR1
DCB13DR2
DCB13CR0
Addr
(0,Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Access
Name
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
DPWM0PCF
DPWM0PDH
DPWM0PDL
DPWM0PWH
DPWM0PWL
DPWM0PCH
DPWM0PCL
DPWM0GCFG
DPWM1PCF
DPWM1PDH
DPWM1PDL
DPWM1PWH
DPWM1PWL
DPWM1PCH
DPWM1PCL
DPWM1GCFG
DPWM2PCF
DPWM2PDH
DPWM2PDL
DPWM2PWH
DPWM2PWL
DPWM2PCH
DPWM2PCL
DPWM2GCFG
DPWM3PCF
DPWM3PDH
DPWM3PDL
DPWM3PWH
DPWM3PWL
DPWM3PCH
DPWM3PCL
DPWM3GCFG
AMX_IN
AMUX_CFG
RW
RW
RW
RW
RW
RW
RW
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
ARF_CR
CMP_CR0
ASY_CR
CMP_CR1
PAMUX_S1
PAMUX_S2
PAMUX_S3
PAMUX_S4
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
DPWM0PCFG
DPWM1PCFG
DPWM2PCFG
DPWM3PCFG
DPWMINTFLG
DPWMINTMSK
DPWMSYNC
Document Number: 001-46319 Rev. *R
Addr
(0,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
Name
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
VDAC6_CR
VDAC6_DR0
VDAC6_DR1
VDAC4_CR
VDAC4_DR0
VDAC4_DR1
VDAC5_CR
VDAC5_DR0
VDAC5_DR1
MUL1_X
MUL1_Y
MUL1_DH
MUL1_DL
ACC1_DR1
ACC1_DR0
ACC1_DR3
ACC1_DR2
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
RDI1RI
RDI1SYN
RDI1IS
RDI1LT0
RDI1LT1
RDI1RO0
RDI1RO1
Addr
(0,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
Access
Name
RW
RW
RW
RW
RW
RW
RW
RW
VDAC0_CR
VDAC0_DR0
VDAC0_DR1
VDAC1_CR
VDAC1_DR0
VDAC1_DR1
VDAC2_CR
VDAC2_DR0
VDAC2_DR1
VDAC3_CR
VDAC3_DR0
VDAC3_DR1
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
W
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
CUR_PP
STK_PP
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2
CPU_F
RW
RW
RW
RW
RW
RW
RW
DAC_D
CPU_SCR1
CPU_SCR0
Addr
(0,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
RW
#
#
Page 28 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
13.5 Register Map Bank 1 Table: User Space
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
FN0DM0
FN0DM1
FN0IC0
FN0IC1
DBB00FN
DBB00IN
DBB00OU
DBB01FN
DBB01IN
DBB01OU
DCB02FN
DCB02IN
DCB02OU
DCB03FN
DCB03IN
DCB03OU
DBB10FN
DBB10IN
DBB10OU
DBB11FN
DBB01IN
DBB01OU
DCB12FN
DCB12IN
DCB12OU
DCB13FN
DCB13IN
DCB13OU
Addr
(1,Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
GDRV2_CR
Addr
(1,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
GDRV3_CR
7E
7F
Access
Name
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
CSA0_CR
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
CSA1_CR
CSA2_CR
CSA3_CR
CLK_CR0
CLK_CR1
ABF_CR0
AMD_CR0
CMP_GO_EN
AMD_CR1
ALT_CR0
ALT_CR1
CLK_CR2
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
GDRV0_CR
GDRV1_CR
RW
RW
RW
Document Number: 001-46319 Rev. *R
Access
Name
RW
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
RW
RW
RW
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
AMUX_CLK
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
RDI1RI
RDI1SYN
RDI1IS
RDI1LT0
RDI1LT1
RDI1RO0
RDI1RO1
RW
Addr
(1,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
DAC_CR
Addr
(1,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
CPU_SCR1
CPU_SCR0
FE
FF
Access
Name
RW
RW
RW
RW
RW
RW
RW
RW
CMPCH0_CR
CMPCH2_CR
CMPCH4_CR
CMPCH6_CR
CMPBNK8_CR
CMPBNK9_CR
CMPBNK10_CR
CMPBNK11_CR
CMPBNK12_CR
CMPBNK13_CR
RW
RW
RW
RW
RW
RW
RW
RW
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
HYSCTLR0CR
HYSCTLR1CR
HYSCTLR2CR
HYSCTLR3CR
MUX_CR0
MUX_CR1
MUX_CR2
SREG_TST
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP
DEC_CR2
IMO_TR
ILO_TR
BDG_TR
RW
RW
RW
RW
RW
RW
RW
RW
CPU_F
RW
RW
RW
RW
RW
RW
RW
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
RW
RW
RW
RW
RL
RW
#
#
Page 29 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
14. Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8CLED04D0X, CY8CLED04G01, CY8CLED03D0X,
CY8CLED03G01, CY8CLED02D01, and CY8CLED01D01 of the PowerPSoC device family. For the most up to date electrical
specifications, confirm that you have the most recent datasheet by going to the web at http://www.cypress.com/powerpsoc.
Specifications for Industrial rated devices are valid for –40 °C TA 85 °C, TJ 115 °C and for Extended Temperature rated devices
for –40 °C TA 105 °C, TJ 125 °C, except where noted.
14.1 Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. Not all user guidelines are production tested.
Table 14-1. Absolute Maximum Ratings
Symbol
TSTG
Description
Storage temperature
Min
–55
Typ
–
Max
+115
Units
°C
TA
Ambient temperature with power applied
–40
–40
–
–
+85
+105
°C
°C
VDD,
AVDD,
GDVDD
VIO
Supply voltage on VDD, AVDD, and
GDVDD
–0.5
–
+6.0
V
VSS – 0.5
–
VDD + 0.5
V
VIO2
VFET
DC voltage applied to tristate
VSS – 0.5
Maximum voltage from power Switch
–
(SWx) to Power FET Ground (PGNDx)
Maximum voltage on SREGHVIN Pin
–
relative to VSS
Maximum voltage applied to CSA pins
–0.5
relative to VSS
Maximum input differential voltage across
–1.0
CSA input
Maximum current into any port pin
–50
configured as analog driver
Maximum current into any port and
–25
function pin
Latch up current
200
Electrostatic discharge voltage
2000
Ramp rate for the SREGHVIN pin
–
–
–
VDD + 0.5
36[13]
V
V
–
36[13]
V
–
36[13]
V
–
1.0
V
–
+50
mA
–
+50
mA
–
–
–
–
–
32
mA
V
V/s
VREGIN
VCSP,VCSN
VSENSE
IMAIO
IMIO
LU
ESD
SRREGIN
DC input voltage
SRCSP
Ramp rate for the CSPx pins
SRHVDD-FLB High voltage supply ramp rate for floating
load buck configuration
–
–
–
–
3.2
15
V/s
V/ms
SRVDD-EXT
–
–
0.2
V/s
External VDD supply ramp rate (VDD,
AVDD, and GDVDD pins)
Notes
Higher storage temperatures
reduces data retention time.
Recommended storage
temperature is 0 °C to 50 °C.
TJ 115 °C (industrial rated)
TJ 125 °C (extended
temperature rated)
Relative to VSS, AVSS, and
GDVSS respectively
Applies only to GPIO and FN0
pins
PGNDx is connected to GDVSS
JESD78A Conformal
Human Body Model ESD.
For other topologies, to enable
operation with faster ramp rates,
or if the LED string voltage is
< 6.5 V, see the PowerPSoC
Technical Reference Manual.
Applies only when powered by a
source other than the Built-in
Switching Regulator
Note
13. Stresses beyond the “Absolute Maximum Ratings” on page 30 may cause permanent damage to the device. You must ensure that the absolute maximum ratings are
NEVER exceeded. Functional operation is not implied under any conditions beyond the “Electrical Characteristics” on page 31 onwards. Extended exposure to
“Absolute Maximum Ratings” on page 30 may affect reliability of the device.
Document Number: 001-46319 Rev. *R
Page 30 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
14.2 Operating Temperature
Symbol
TA
Description
Ambient temperature
Min
–40
–40
Typ
–
–
Max
+85
+105
Units
°C
°C
TJ
Junction temperature
–40
–40
–
–
+115
+125
°C
°C
Notes
TJ 115 °C (Industrial rated)
TJ 125 °C (extended temperature
rated)
Industrial rated
Extended Temperature rated
15. Electrical Characteristics
15.1 System Level
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for Extended Temperature rated devices. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
Table 15-1. System Level Operating Specifications
Symbol
fSW
tD,MAX
D
E
Description
Circuit switching frequency range for
hysteretic control loop
Maximum delay time from CSA input to
FET state change
Output duty cycle for hysteretic controllers
Power converter efficiency
Min
0.02
Typ
–
Max
2
Units
MHz
Notes
–
–
100
ns
–
–
115
ns
5
90
–
95
95
–
%
%
HVDD = 24 V, ID = 1 A, fSW = 2 MHz
(Industrial rated)
HVDD = 24 V, ID = 1 A, fSW = 2 MHz
(Extended Temperature rated)
fSW < 0.25 MHz
HVDD = 24 V, ID = 1 A, fSW = 2 MHz
15.2 Chip Level
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for Extended Temperature rated devices. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
Note See the PowerPSoC Technical Reference Manual for more information on the DPWMxPCF register
Table 15-2. Chip Level DC Specifications
Symbol
VDD, AVDD,
GDVDD
HVDD
HVPINS
IVDD
IAVDD
Description
Digital, analog, and gate driver supply
voltage range
Power converter high voltage supply range
Voltage range for the CSPx and
SREGHVIN pins
Supply current (VDD pins),
IMO = 24 MHz
Supply current (AVDD pin)
Document Number: 001-46319 Rev. *R
Min
4.75
Typ
–
Max
5.25
7
7
–
–
32
32
–
16
50
–
–
25
Units
Notes
V
All should be powered from the same
source.
V
V
Not all pins need to be at the same
voltage level.
mA Conditions are VDD = 5 V, TJ = 25 °C,
CPU = 3 MHz, SYSCLK doubler
disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 93.75 kHz,
analog power = off.
mA Conditions are VDD = 5 V, TJ = 25 °C,
Page 31 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
Table 15-2. Chip Level DC Specifications (continued)
Symbol
IGDVDD
Description
Supply current per channel (GDVDD pins)
ISB
Sleep (mode) current with POR, LVD,
sleep timer, and WDT.
Min
–
–
Typ
–
–
Max
25
100
Units
Notes
mA Internal Power FET at 2 MHz
mA External Gate Driver at 1 MHz,
CL = 4 nF at VDD = 5 V
A TJ 25 °C, Built-in Switching
Regulator disabled,
DPWMxPCF = 0, Power Peripherals
disabled, analog power = off
A TJ 115 °C (Industrial rated) and
TJ 125 °C (Extended Temperature
rated), Built-in Switching Regulator
disabled, DPWMxPCF = 0, Power
Peripherals disabled,
analog power = OFF
–
18
25
–
30
550
Min
Typ
Max
Units
Notes
24.96
MHz
–
MHz
–
Table 15-3. Chip Level AC Specifications
Symbol
Description
fIMO24[15]
Internal main oscillator frequency for
24 MHz
23.04
24
fCPU1
CPU frequency
0.093
24
24.96
fBLK
Digital PSoC Block frequency
0
48
49.92[14]
f32K1
Internal low-speed oscillator frequency
15
32
64
kHz
f32K_U
Internal low-speed oscillator (ILO)
untrimmed frequency
5
–
–
kHz
After a reset and before the M8C
starts to run, the ILO is not trimmed.
See the System Resets section of
the PowerPSoC Technical
Reference Manual for details on
timing this.
DCILO
Internal low speed oscillator duty cycle
20
50
80
%
–
Jitter32K
32 kHz period jitter
–
100
–
ns
–
Jitter24M1
24 MHz period jitter (IMO) peak-to-peak
–
600
–
ps
–
tPOWERUP
Time from end of POR to CPU executing
code
–
30
100
ms
Power up from 0 V. See the System
Resets section of the PowerPSoC
Technical Reference Manual.
MHz Refer to “PSoC Core Digital Block
Specifications” on page 48.
Figure 15-1. 24 MHz Period Jitter (IMO) Timing Diagram
Notes
14. See the individual user module datasheets for information on maximum frequencies for user modules.
15. The accuracy of the internal 24/48 MHz clocks is ± 5% over temperature variation and a voltage range of 5.0 V ± 0.25 V. No external components are required to
achieve this level of accuracy. Refer to the Internal Main Oscillator (IMO) section in the PowerPSoC Technical Reference Manual.
Document Number: 001-46319 Rev. *R
Page 32 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
15.3 Power Peripheral Low Side N-Channel FET
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for Extended Temperature rated devices. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
Table 15-4. Low Side N-Channel FET DC Specifications
Min
Typ
Max
Units
VDS
Symbol
Operating drain to source voltage
–
–
32
V
VDS,INST
Instantaneous drain source voltage
–
–
36
V
ID
Average drain current
–
–
–
–
1
0.5
A
A
CY8CLED04/3/2/1D01 devices
CY8CLED04/3D02 devices
IDMAX
Maximum instantaneous repetitive pulsed
current
–
–
3
A
–
–
1.5
A
Less than 33% duty cycle for an
average current of 1 A,
fSW = 0.1 MHz.
CY8CLED04/3/2/1D01 devices
Less than 33% duty cycle for an
average current of 0.5 A,
fSW = 0.1 MHz. CY8CLED04/3D02
devices
–
–
0.5
–
–
1
RDS(ON)
Description
Drain to source ON resistance
Notes
ID = 1 A, GDVDD = 5 V, TJ = 25 °C
CY8CLED04/3/2/1D01 devices
ID = 0.5 A, GDVDD = 5 V, TJ = 25 °C
CY8CLED04/3D02 devices
IDSS
Switching node to PGND leakage
–
–
–
–
10
250
A
A
TJ = 25 °C
TJ 115 °C (Industrial rated) and TJ
125 °C (Extended Temperature
rated)
ISFET
Supply current per channel - FET (internal gate
driver)
–
–
6.25
mA
fSW = 2 MHz
Min
Typ
Max
Units
Table 15-5. Low Side N-Channel FET AC Specifications
Symbol
Description
Notes
tR
Rise time
–
–
20
ns
ID = 1 A, RD = 32
tF
Fall time
–
–
20
ns
ID = 1 A, RD = 32
Figure 15-2. Low Side N-Channel FET Test Circuit for IDSS, tR, and tF
RD
ID
RG
V INPUT
VG
Document Number: 001-46319 Rev. *R
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15.4 Power Peripheral External Power FET Driver
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for Extended Temperature rated devices. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
Table 15-6. Power FET Driver DC Specifications
Min
Typ
Max
Units
VOHN
Symbol
N-channel FET driver output voltage -drive
high
Description
VDD – 0.45
VDD – 0.10
–
–
–
–
V
V
IOH = 100 mA
IOH = 10 mA
Notes
VOLN
N-channel FET driver output voltage -drive
low
–
–
–
–
0.45
0.1
V
V
IOL = 100 mA
IOL = 10 mA
ISFETDRV
Supply current per channel - external FET
driver
–
–
25
mA
CL = 4 nF
FSW = 1 MHz
Min
Typ
Max
Units
Table 15-7. Power FET Driver AC Specifications
Symbol
Description
tR
Rise time
–
45
55
ns
tF
Fall time
–
45
55
ns
tP(LH)
Propagation delay (low-to-high)
–
–
10
ns
tP(HL)
Propagation delay (high-to-low))
–
–
10
ns
Notes
CL = 4 nF
15.5 Power Peripheral Hysteretic Controller
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for Extended Temperature rated devices. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
Table 15-8. Hysteretic Controller DC Specifications
Symbol
VIO
Description
Comparator input offset voltage
VICM
Input common mode voltage range
VHYS
Hysteresis voltage
ISHYST
Supply current - hysteretic controller
Document Number: 001-46319 Rev. *R
Min
Typ
Max
Units
Notes
–
–
–
–
7.5
10
mV
mV
–
–
15
mV
1 V VICM 3 V (industrial rated)
1 v vicm 3 v (extended
temperature rated)
0 V VICM VDD
0
–
VDD
V
4.5
–
11
mV
4.5
–
13
mV
–
2
–
mA
1.5 V VICM 2.5 V (industrial
rated)
1.5 V VICM 2.5 V (extended
temperature rated)
Includes two power peripheral
comparators and one reference
DAC, fSW = 2 MHz
Page 34 of 55
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CY8CLED02D01/CY8CLED01D01
Table 15-9. Hysteretic Controller AC Specifications
Symbol
Description
Min
Typ
Max
Units
MONOSHOT<1:0> = 00
10
–
30
ns
MONOSHOT<1:0> = 01
20
–
60
ns
MONOSHOT<1:0> = 10
40
–
110
ns
MONOSHOT<1:0> = 11
–
–
–
ns
Notes
tON / tOFF Minimum ON/OFF timer
Timers disabled
15.6 Power Peripheral Comparator
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for Extended Temperature rated devices. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
Table 15-10. Comparator DC Specifications
Min
Typ
Max
Units
Notes
VIN
Symbol
Input voltage range
0
–
VDD
V
–
VIO
Comparator input offset voltage
–
–
–
–
7.5
10
mV
mV
–
–
15
mV
1 V VICM 3 V (Industrial rated)
1 V VICM 3 V (Extended Temperature rated)
0 V VICM VDD
2.5
4.5
–
–
30
11
mV
mV
4.5
–
13
mV
–
mV
–
VHYS
Description
Hysteresis voltage
0 V < VICM < VDD
1.5 V VICM 2.5 V (Industrial
rated)
1.5 V VICM 2.5 V (Extended
Temperature rated)
VOVDRV
Overdrive voltage
5
–
ISCOMP
Supply current - comparator
–
–
650
A
–
VICM,COMP Comparator input common mode voltage
range
0
–
VDD
V
–
Min
Typ
Max
Units
–
150
–
ns
Table 15-11. Comparator AC Specifications
Symbol
tD
Description
Comparator delay time (FN0[x] pin to
FN0[x] pin)
Notes
VOVDRV = 5 mV, CL = 10 pF at
VDD = 5 V
Figure 15-3. Comparator Timing Diagram
Document Number: 001-46319 Rev. *R
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15.7 Power Peripheral Current Sense Amplifier
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for Extended Temperature rated devices. Typical parameters
apply to VDD of 5 V and HVDD of 32 V at 25 °C. These are for design guidance only.
Table 15-12. Current Sense Amplifier DC Specifications
Symbol
Min
Typ
Max
Units
Notes
7
–
32
V
Either terminal of the amplifier must
not exceed this range for functionality
VICM(Tolerant) Non functional operating range
0
–
32
VSENSE
Input differential voltage range
0
–
150
mV
IS,CSA
Supply current - CSA
–
–
1
mA
IBIASP
Input bias current (+)
–
–
600
A
IBIASN
Input bias current (-)
–
–
1
A
PSRHV
Power supply rejection (CSP pin)
–
–
–25
dB
fSW < 2 MHz
K
Gain
19.7
20
20.3
V/V
19.4
20
20.6
V/V
VSENSE = 50 mV to 130 mV (Industrial
rated)
VSENSE = 50 mV to 130 mV (Extended
Temperature rated)
VICM
Description
Input common mode voltage operating
range
Absolute maximum rating for VSENSE
should never be exceeded. See
Absolute Maximum Ratings on page
30
VIOS
Input offset
–
2
4
mV
CIN_CSP
CSP input capacitance
–
–
5
pF
CIN_CSN
CSN input capacitance
–
–
2
pF
Min
Typ
Max
Units
Enabling CSA causes an incremental
draw of 1 mA on the AVDD rail.
VSENSE = 50 mV to 130 mV
Table 15-13. Current Sense Amplifier AC Specifications
Symbol
Description
tSETTLE
Output settling time to 1% of final value
–
–
5
s
tPOWERUP
Power up time to 1% of final value
–
–
5
s
Notes
Figure 15-4. Current Sense Amplifier Timing Diagram
VINPUT
VCSP
VCSN
VINPUT -50 mV
t SETTLE
VINPUT -150 mV
t SETTLE
tDELAY
t ACTIVATE
VCSP ,VCSN
tPOWERUP
K*100 mV
OUT
K*25 mV
0V
Not Valid
time
Document Number: 001-46319 Rev. *R
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15.8 Power Peripheral PWM/PrISM/DMM Specification Table
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for Extended Temperature rated devices. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only. See the PowerPSoC Technical Reference Manual for more information on
PWM/PrISM/DMM.
Table 15-14. PWM/PrISM/DMM DC Specifications
Symbol
IS,Modulation
Description
Min
Typ
Max
Units
Notes
Supply current - PWM, PrISM,
or DMM
–
–
5
mA
Min
Typ
Max
Units
Notes
Table 15-15. PWM/PrISM/DMM AC Specifications
Symbol
Description
PWM Mode
fRANGE16
PWM output frequency range
16-bit period
24,000,000/(256*216)
–
48,000,000/216
Hz
Period value = 216 –1,
Min: N = 255, Max: N = 0
fRANGE8
PWM output frequency range
8-bit period
24,000,000/(256*28)
–
48,000,000/28
Hz
Period value = 28 –1, Min:
N = 255, Max: N = 0
–
48,000,000/2
Hz
Min: N = 255, Maqx: N =
0, M = 2 to 16
24,000,000/
(256*Max DMM Period)
–
48,000,000/(Mi
n DMM Period)
Hz
Min DMM Period:
2 (Right Aligned),
3 (Center Aligned),
4(Left Aligned)
Max DMM Period:
212 (Right Aligned),
8190 (Center Aligned),
212 (Left Aligned)
(1/16)*(Min
fRANGE,Dimming)
–
(15/16)*(Max
fRANGE,Dimming)
Hz
PrISM Mode
fRANGE
PrISM output frequency range 24,000,000/(256*(2M–1)
DMM Mode
fRANGE,Dimming DMM dimming frequency range
fRANGE,Dither
DMM dither frequency range
Document Number: 001-46319 Rev. *R
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15.9 Power Peripheral Reference DAC Specification
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for Extended Temperature rated devices. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
Table 15-16. Reference DAC DC Specifications
Symbol
Description
Min
Typ
Max
Units
–
–
600
A
Integral non linearity
–1
–1.5
–
–
1
1.5
LSB
LSB
Mode 0
Mode 1
DNL
Differential non linearity
–0.5
–
0.5
LSB
Mode 0 and Mode1
AERROR
Gain error
–5
–7
–
–
5
7
LSB
LSB
Mode 0
Mode 1
OSERROR
Offset error
–
–
1
LSB
Mode 0 and Mode1
VDACFS
Fullscale voltage - reference DAC
–
–
–
–
2.6
1.3
LSB
LSB
Mode 0
Mode 1
VDACMM
Fullscale voltage mismatch (pair of
reference DACs - even and odd)
–
–
–
–
–
–
–
–
9
14
10.5
15.5
LSB
LSB
LSB
LSB
Mode 0 (DAC0 through DAC7)
Mode 1 (DAC0 through DAC7)
Mode 0 (DAC8 through DAC13)
Mode 1 (DAC8 through DAC13)
Description
Min
Typ
Max
Units
tSETTLE
Output settling time to 0.5 LSB of final value
–
–
10
s
Mode 0 and Mode1
tSTARTUP
Startup time to within 0.5 LSB of final value
–
–
10.5
s
Mode 0 and Mode1
ISDAC
Supply current - reference DAC
INL
Notes
Mode 0 and Mode1
Table 15-17. Reference DAC AC Specifications
Symbol
Notes
15.10 Power Peripheral Built-in Switching Regulator
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for Extended Temperature rated devices. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
Table 15-18. Built-in Switching Regulator DC Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
7
8
–
–
32
32
V
V
Industrial rated
Extended temperature rated
See Absolute Maximum Ratings on
page 30
4.8
5.0
5.2
V
Does not include VRIPPLE
–
–
100
mV
VREGIN
Input supply voltage range
VREGOUT
Output voltage range
VRIPPLE
Output ripple
VUVLO
Under voltage lockout voltage
5.5
–
6.5
V
VREGIN < VUVLO: Power down mode
VREGIN > VUVLO: Active mode
ILOAD
DC output current -active mode
0.01
–
250
mA
–
IS,BSR
Supply current - built-in switching regulator
–
–
4
mA
–
ISB,HV
Standby current (high voltage)
–
–
250
A
–
IINRUSH
Inrush current
–
–
1.2
A
–
–
1.5
A
VREGIN = 32 V, SRREGIN = 32 V/ms
(Industrial rated)
VREGIN = 32 V, SRREGIN = 32 V/ms
(Extended Temperature rated)
RDS(ON),PFET PFET drain to source ON resistance
–
2.5
–
LineREG
–
1
–
mV
Line regulation
Document Number: 001-46319 Rev. *R
ILOAD = 250 mA, VREGIN = 7 V to 32 V
Page 38 of 55
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Table 15-18. Built-in Switching Regulator DC Specifications (continued)
Symbol
Description
Min
Typ
Max
Units
Notes
LoadREG
Load regulation
–
1
–
mV
VREGIN = 24 V, ILOAD = 2.5 mA to
250 mA
PSRR
Power supply rejection ratio
–
–60
–
dB
VRIPPLE = 0.2 * VREGIN,
fRIPPLE = 1 kHz to 10 kHz
EBSR
Built-in switching regulator efficiency
80
–
–
%
VREGIN = 24 V, ILOAD = 250 mA
Min
0.956
–
–
–
–
–
Typ
1
10
–
–
–
–
Max
1.04
–
1
100
1
50
Units
MHz
s
ms
s
ms
s
Notes
–
–
–
–
–
–
–
–
32
V/s
See Absolute Maximum Ratings on
page 30
Table 15-19. Built-in Switching Regulator AC Specifications
Symbol
fSW
tRESP
tSU
tPD
tPD_ACT
tACT_PD
SRREGIN
Description
Switching frequency
Response time to within 0.5% of final value
Startup time
Power down time
Time from power down to active mode
Time from active mode to power down
mode
Ramp rate for the SREGHVIN pin
Table 15-20. Built-in Switching Regulator Recommended Components
Component
Name
Rfb1
Rfb2
Ccomp
Rcomp
L
Rsense
C1
Cin
D1
Value
Unit
Notes
2
0.698
2200
20
47
0.5
10
1
40/0.5
k
k
pF
k
H
F
F
V/A
Tolerance 1% and 0.05-W rated or better
Tolerance 1% and 0.05-W rated or better
Tolerance 20% and 6.3-V rated or better
Tolerance 5% and 0.05-W rated or better
Tolerance 20% or better, Saturation current rating of 1.5 A or higher
Tolerance 1% and 0.05 W (ILOAD = 0.250 A) rated or better
Ceramic, X7R grade, Minimum ESR of 0.1 , 6.3-V rated
Ceramic, X7R grade, 50-V rated (VREGIN = 32 V)
Schottky diode - Reverse voltage 40 V, average rectified forward current
0.5 A (VREGIN = 32 V)
Note If the built-in switching regulator is not being used in a design, it must be configured as per the following instructions to ensure
it is disabled in a safe state.
SREGFB: 5 V
SREGCSN: 5 V
SREGCSP: 5 V
SREGCOMP: Floating
SREGHVIN: VDD rail
SREGSW: Floating/Tie to SREGHVIN
If the switching regulator is disabled through wiring its input pins (as previously explained) then it must be disabled through software
as well (bit SREG_TST[0] = 1), which is set in the Global Resources in the Interconnect View of PSoC Designer.
Document Number: 001-46319 Rev. *R
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Figure 15-5. Built-in Switching Regulator Timing Diagram
VREGIN
VREGIN
tSU
5
VREGOUT
tPD
tPD_ACT
Time
Powerdown
MODE
Figure 15-6. Built-in Switching Regulator
VSS
Ref
Error
Amplifier
Osc
VREGIN
SREGHVIN
Logic and
Gate
Drive
Comparator
Current
Sense
Amp
C IN
SREGSW L
D1
VREGOUT = 5V
Rsense
Rfb1
ESR
Rfb2
C1
SREGCSP
SREGCSN
SREGCOMP
Ccomp
SREGFB
Document Number: 001-46319 Rev. *R
Rcomp
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15.11 General Purpose I/O / Function Pin I/O
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for Extended Temperature rated devices. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
Table 15-21. GPIO/FN0 Pin I/O DC Specifications
Symbol
RPU
RPD
VOH
Description
Pull-up resistor
Pull-down resistor
High output level
Min
4
4
VDD – 1.0
Typ
5.6
5.6
–
Max
8
8
–
Units
k
k
V
Low output level
–
–
0.75
V
IOH
High level source current
10
–
–
mA
IOL
Low level sink current
25
–
–
mA
VIL
VIH
VH
IIL
CIN
COUT
Input low level
Input high level
Input hysterisis
Input leakage (absolute value)
Capacitive load on pins as input
Capacitive load on pins as output
–
2.1
–
–
–
–
–
–
60
1
3.5
3.5
0.8
–
–
10
10
V
V
mV
nA
pF
pF
Notes
–
–
IOH = 10 mA, 80 mA maximum
combined IOH budget
IOL = 25 mA, 200 mA maximum
combined IOL budget
VOH = VDD–1.0 V, see the limitations of the total current in the note
for VOH
VOL = 0.75 V, see the limitations of
the total current in the note for VOL
–
–
–
Gross tested to 1 A
TJ = 25 °C.
TJ = 25 °C.
VOL
Min
Typ
Max
Units
Notes
Normal strong mode
Table 15-22. GPIO/FN0 Pin I/O AC Specifications
Symbol
Description
fGPIO
GPIO operating frequency
0
–
12
MHz
tRiseF
Rise time, normal strong mode, Cload = 50 pF
3
–
18
ns
tFallF
Fall time, normal strong mode, Cload = 50 pF
2
–
18
ns
tRiseS
Rise time, slow strong mode, Cload = 50 pF
10
27
–
ns
tFallS
Fall time, slow strong mode, Cload = 50 pF
10
22
–
ns
10% – 90%
Figure 15-7. GPIO/Function I/O Timing Diagram
Document Number: 001-46319 Rev. *R
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15.12 PSoC Core Operational Amplifier Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for Extended Temperature rated devices. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block.
Table 15-23. Operational Amplifier DC Specifications
Symbol
Min
Typ
Max
Units
–
–
–
–
–
–
1.6
1.6
1.3
1.3
1.2
1.2
10
15
8
13
7.5
12
mV
mV
mV
mV
mV
mV
TCVOSOA Average input offset voltage drift
–
7.0
35.0
V / °C
IEBOA
Input leakage current (Port 0 analog pins)
–
20
–
pA
Gross tested to 1 A.
CINOA
Input capacitance (Port 0 analog pins)
–
4.5
9.5
pF
TJ = 25 °C.
VCMOA
Common mode voltage range
Common mode voltage range (high power or
high opamp bias)
The common-mode input voltage
range is measured through an
analog output buffer. The specification includes the limitations
imposed by the characteristics of
the analog output buffer.
VOSOA
Description
Input offset voltage (absolute value)
Power = low, opamp bias = high
Power = medium, opamp bias = high
Power = high, opamp bias = high
0.0
–
0.5
–
VDD
VDD – 0.5
V
V
60
60
80
–
–
–
–
–
–
dB
dB
dB
VOHIGHOA High output voltage swing (internal signals)
Power = low, opamp bias = high
Power = medium, opamp bias = high
Power = high, opamp bias = high
VDD – 0.2
VDD – 0.2
VDD – 0.5
–
–
–
–
–
–
V
V
V
VOLOWOA Low output voltage swing (internal signals)
Power = low, opamp bias = high
Power = medium, opamp bias = high
Power = high, opamp bias = high
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
GOLOA
ISOA
PSRROA
Open loop gain
Power = low, opamp bias = high
Power = medium, opamp bias = high
Power = high, opamp bias = high
Industrial rated
Extended temperature rated
Industrial rated
Extended temperature rated
Industrial rated
Extended temperature rated
–
–
–
–
Supply current (including associated analog
output buffer)
Power = low, opamp bias = low
Power = low, opamp bias = high
Power = medium, opamp bias = low
Power = medium, opamp bias = high
Power = high, opamp bias = low
Power = high, opamp bias = high
–
–
–
–
–
–
400
500
800
1200
2400
4600
800
900
1000
1600
3200
6400
A
A
A
A
A
A
Supply voltage rejection ratio
52
80
–
dB
Document Number: 001-46319 Rev. *R
Notes
VSS VIN (VDD – 2.25) or (VDD –
1.25 V) VIN VDD.
Page 42 of 55
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CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
Table 15-24. Operational Amplifier AC Specifications
Symbol
Description
tROA
Rising settling time from 80% of V to 0.1% of
V (10 pF load, Unity Gain)
Power = low, opamp bias = low
Power = medium, opamp bias = high
Power = high, opamp bias = high
tSOA
Falling settling time from 20% of V to 0.1% of
V (10 pF load, unity gain)
Power = low, opamp bias = low
Power = medium, opamp bias = high
Power = high, opamp bias = high
SRROA
Rising slew rate (20% to 80%)
(10 pF load, unity gain)
Power = low, opamp bias = low
Power = medium, opamp bias = high
Power = high, opamp bias = high
SRFOA
Falling slew rate (20% to 80%)
(10 pF load, unity gain)
Power = low, opamp bias = low
Power = medium, opamp bias = high
Power = high, opamp bias = high
Gain bandwidth product
BWOA
Power = low, opamp bias = low
Power = medium, opamp bias = high
Power = high, opamp bias = high
ENOA
Noise at 1 kHz (power = medium,
opamp bias = high)
Min
Typ
Max
Units
–
–
–
–
–
–
3.9
0.72
0.62
s
s
s
Notes
–
–
–
–
–
–
–
–
5.9
0.92
0.72
s
s
s
–
0.15
1.7
6.5
–
–
–
–
–
–
V/s
V/s
V/s
–
0.01
0.5
4.0
–
–
–
–
–
–
V/s
V/s
V/s
0.75
3.1
5.4
–
–
–
–
100
–
–
–
–
MHz
MHz
MHz
nV/r-Hz
–
–
15.13 PSoC Core Low Power Comparator
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for Extended Temperature rated devices. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
Table 15-25. Low Power Comparator DC Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
0.2
–
VDD – 1
V
–
VREFLPC
Low power comparator (LPC) reference
voltage range
ISLPC
LPC supply current
–
10
40
A
–
VOSLPC
LPC voltage offset
–
2.5
40
mV
–
Min
–
Typ
–
Max
50
Units
s
Table 15-26. Low Power Comparator AC Specifications
Symbol
tRLPC
Description
LPC response time
Document Number: 001-46319 Rev. *R
Notes
50 mV overdrive comparator
reference set within VREFLPC.
Page 43 of 55
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15.14 PSoC Core Analog Output Buffer
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for Extended Temperature rated devices. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
Table 15-27. Analog Output Buffer DC Specifications
Symbol
VOSOB
Description
Input offset voltage (absolute value)
Min
–
–
Typ
3
3
Max
12
18
Units
mV
mV
TCVOSOB Average input offset voltage drift
VCMOB
Common-mode input voltage range
ROUTOB
Output resistance
Power = low
Power = high
VOHIGHOB High output voltage swing
(load = 32 ohms to VDD/2)
Power = low
Power = high
–
0.5
+6
–
–
VDD – 1.0
V/°C
V
–
–
0.6
0.6
–
–
0.5 x VDD +
1.1
0.5 x VDD +
1.1
–
–
–
–
V
V
–
–
–
–
0.5 x VDD –
1.3
0.5 x VDD –
1.3
V
V
–
–
52
1.1
2.6
64
5.1
8.8
–
mA
mA
dB
Min
Typ
Max
Units
VOLOWOB Low output voltage swing
(load = 32 ohms to VDD/2)
Power = low
Power = high
ISOB
PSRROB
Supply current including bias cell (no load)
Power = low
Power = high
Supply voltage rejection ratio
Notes
Industrial rated
Extended Temperature
rated
–
–
–
–
–
–
(0.5 x VDD – 1.3) VOUT
(VDD – 2.3).
Table 15-28. Analog Output Buffer AC Specifications
Symbol
tROB
tSOB
Description
Rising settling time to 0.1%, 1 V Step, 100 pF
load
Power = low
Power = high
Falling settling time to 0.1%, 1 V Step, 100 pF
load
Power = low
Power = high
Document Number: 001-46319 Rev. *R
Notes
–
–
–
–
–
2.5
2.5
s
s
–
–
–
–
–
2.2
2.2
s
s
Page 44 of 55
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CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
Table 15-28. Analog Output Buffer AC Specifications (continued)
Symbol
SRROB
SRFOB
BWOBSS
BWOBLS
Description
Rising slew rate (20% to 80%), 1 V step,
100 pF load
Power = low
Power = high
Falling slew rate (80% to 20%), 1 V step,
100 pF load
Power = low
Power = high
Small signal bandwidth, 20 mVpp, 3 dB BW,
100 pF load
Power = low
Power = high
Large signal bandwidth, 1 Vpp, 3 dB BW,
100 pF load
Power = low
Power = high
Document Number: 001-46319 Rev. *R
Min
Typ
Max
Units
Notes
–
0.65
0.65
–
–
–
–
V/s
V/s
–
0.65
0.65
–
–
–
–
V/s
V/s
–
0.8
0.8
–
–
–
–
MHz
MHz
–
300
300
–
–
–
–
kHz
kHz
Page 45 of 55
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15.15 PSoC Core Analog Reference
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for extended temperature rated devices. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the analog continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 15-29. Analog Reference DC Specifications
Symbol
Description
BG
Bandgap voltage reference
–
AGND = VDD/2[16]
–
AGND = 2 x BandGap[16]
BandGap[16]
–
AGND =
–
AGND = 1.6 x BandGap[16]
–
AGND Block to Block Variation
(AGND = VDD/2)[16]
–
RefHi = VDD/2 + BandGap
–
RefHi = 3 x BandGap
–
RefHi = 3.2 x BandGap
–
RefLo = VDD/2 – BandGap
–
RefLo = BandGap
Min
Typ
Max
Units
1.28
1.27
1.30
1.30
1.32
1.33
V
V
Industrial rated
Extended
Temperature
rated
VDD/2 – 0.04
VDD/2 – 0.02
VDD/2 – 0.01
VDD/2
VDD/2 + 0.007
VDD/2 + 0.02
V
V
Industrial rated
Extended
Temperature
rated
2 x BG – 0.048
2 x BG – 0.030
2 x BG + 0.024
V
BG – 0.009
BG + 0.008
BG + 0.016
V
1.6 x BG – 0.022 1.6 x BG – 0.010 1.6 x BG + 0.018
Notes
V
–0.034
0.000
0.034
V
VDD/2 + BG –
0.10
VDD/2 + BG
VDD/2 + BG +
0.10
V
3 x BG – 0.06
3 x BG
3 x BG + 0.06
V
3.2 x BG – 0.112
3.2 x BG
3.2 x BG + 0.076
V
VDD/2 – BG –
0.04
VDD/2 – BG –
0.06
VDD/2 – BG +
0.024
VDD/2 – BG
VDD/2 – BG +
0.04
VDD/2 – BG +
0.06
V
Industrial rated
V
Extended
Temperature
rated
BG – 0.06
BG
BG + 0.06
V
15.16 PSoC Core Analog Block
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for Extended Temperature rated devices. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
Table 15-30. Analog Block DC Specifications
Min
Typ
Max
Units
RCT
Symbol
Resistor unit value (continuous time)
Description
–
12.2
–
k
CSC
Capacitor unit value (switched
capacitor)
–
80
–
fF
Notes
Notes
16. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3 V ± 0.02 V.
Document Number: 001-46319 Rev. *R
Page 46 of 55
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CY8CLED02D01/CY8CLED01D01
15.17 PSoC Core POR and LVD
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for Extended Temperature rated devices. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PowerPSoC Technical Reference
Manual for more information on the VLT_CR register.
Table 15-31. POR and LVD DC Specifications
Symbol
Description
VPPOR2
VDD Value for PPOR Trip
PORLEV[1:0] = 10b
VLVD6
VLVD7
VDD Value for LVD Trip
VM[2:0] = 110b
VM[2:0] = 111b
Min
Typ
Max
Units
–
4.55
4.70
V
4.62
4.71
4.73
4.81
4.83
4.95
V
V
Notes
–
–
15.18 PSoC Core Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for Extended Temperature rated devices. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
Table 15-32. Programming DC Specifications
Description
Min
Typ
Max
Units
Notes
IDDP
Symbol
Supply current during programming or verify
–
15
30
mA
–
VILP
Input low voltage during programming or verify
VIHP
Input high voltage during programming or
verify
IILP
–
–
0.8
V
–
2.1
–
–
V
–
Input current when applying VILP to P1[0] or
P1[1] during programming or verify
–
–
0.2
mA
Driving internal pull down
resistor.
IIHP
Input current when applying VIHP to P1[0] or
P1[1] during programming or verify
–
–
1.5
mA
Driving internal pull down
resistor.
VOLV
Output low voltage during programming or
verify
–
–
VSS + 0.75
V
–
VOHV
Output high voltage during programming or
verify
VDD – 1.0
–
VDD
V
–
50,000
–
–
–
Erase/write cycles per
block.
1,800,000
–
–
–
Erase/write cycles.
10
–
–
Years
FlashENPB Flash endurance (per block)
FlashENT
FlashDR
Flash endurance (total)[17]
Flash data retention
[18]
–
Notes
17. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36 x 1 blocks of 50,000 maximum cycles each, 36 x 2
blocks of 25,000 maximum cycles each, or 36 x 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 x 50,000 and that no single block
ever sees more than 50,000 cycles)
18. Guaranteed for –40 °C TA 85 °C for Industrial rated devices and –40 °C TA 105 °C for Extended Temperature rated devices.
Document Number: 001-46319 Rev. *R
Page 47 of 55
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CY8CLED02D01/CY8CLED01D01
Table 15-33. Programming AC Specifications
Symbol
tRSCLK
tFSCLK
tSSCLK
tHSCLK
fSCLK
tERASEB
tWRITE
tDSCLK
tERASEALL
Description
Rise time of SCLK
Fall time of SCLK
Data set up time to falling edge of SCLK
Data hold time from falling edge of SCLK
Frequency of SCLK
Flash erase time (block)
Flash block write time
Data out delay from falling edge of SCLK
Flash erase time (bulk)
Min
1
1
40
40
0
–
–
–
–
Typ
–
–
–
–
–
10
40
–
40
Max
20
20
–
–
8
–
–
50
–
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ms
tPROGRAM_HOT
tPROGRAM_COLD
Flash block erase + flash block write time
Flash block erase + flash block write time
–
–
–
–
100[19]
200[19]
ms
ms
Notes
–
–
–
–
–
–
–
–
Erase all blocks and
protection fields
immediately
0 °C Tj 100 °C
–40 °C Tj 0 °C
15.19 PSoC Core Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for Extended Temperature rated devices. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
Table 15-34. Digital Block AC Specifications
Function
Timer
Min
50[20]
–
–
50[20]
–
–
Typ
–
–
–
–
–
–
Max
–
49.92
24.96
–
49.92
24.96
Units
ns
MHz
MHz
ns
MHz
MHz
20
50[20]
50[20]
–
–
–
–
–
–
–
–
–
–
49.92
49.92
ns
ns
ns
MHz
MHz
Notes
–
–
–
–
–
–
–
–
–
–
–
–
Input clock frequency
–
–
24.96
MHz
–
Input clock frequency
–
–
8.32
Transmitter
Input clock frequency
–
Width of SS_ Negated between transmissions 50[20]
Input clock frequency
–
–
–
–
4.16
–
24.96
–
–
49.92
Receiver
Input clock frequency with VDD 4.75 V, 2 stop
bits
Input clock frequency
–
–
24.96
Input clock frequency with VDD 4.75 V, 2 stop
bits
–
–
49.92
MHz Maximum data rate at
4.1 MHz due to 2 x over clocking.
MHz
–
ns
–
MHz Maximum data rate at
3.08 MHz due to 8 x over clocking.
MHz Maximum data rate at
6.15 MHz due to 8 x over clocking.
MHz Maximum data rate at
3.08 MHz due to 8 x over clocking.
MHz Maximum data rate at
6.15 MHz due to 8 x over clocking.
Counter
Dead Band
CRCPRS
(PRS Mode)
CRCPRS
(CRC Mode)
SPIM
SPIS
Description
Capture pulse width
Input frequency, no capture
Input frequency, with capture
Enable pulse width
Input frequency, no enable input
Input frequency, enable input
Kill pulse width:
Asynchronous restart mode
Synchronous restart mode
Disable mode
Input frequency
Input clock frequency
Notes
19. For the full industrial range, you must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer
to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
20. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-46319 Rev. *R
Page 48 of 55
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15.20 PSoC Core I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V,
TJ 115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ 125 °C for Extended Temperature rated devices. Typical parameters
apply to 5 V at 25 °C. These are for design guidance only.
Table 15-35. AC Characteristics of the I2C SDA and SCL Pins
Symbol
Description
Standard Mode
Fast Mode
Units
Notes
400
kHz
–
Min
Max
Min
Max
0
100
0
fSCLI2C
SCL clock frequency
tHDSTAI2C
Hold time (repeated) START condition. After
this period, the first clock pulse is generated.
4.0
–
0.6
–
s
–
tLOWI2C
LOW period of the SCL clock
4.7
–
1.3
–
s
–
tHIGHI2C
HIGH period of the SCL clock
4.0
–
0.6
–
s
–
tSUSTAI2C
Setup time for a repeated START condition
4.7
–
0.6
–
s
–
tHDDATI2C
Data hold time
0
–
0
–
s
–
tSUDATI2C
Data setup time
250
–
100[21]
–
ns
–
tSUSTOI2C
Setup time for STOP condition
4.0
–
0.6
–
s
–
tBUFI2C
Bus free time between a STOP and START
condition
4.7
–
1.3
–
s
–
tSPI2C
Pulse width of spikes are suppressed by the
input filter.
–
–
0
50
ns
–
Figure 15-8. Definition of Timing for Fast/Standard Mode on the I2C Bus
Note
21. A fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement tSUDATI2 250 ns must then be met. This is automatically the case
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line trmax + tSUDATI2 = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL line is released.
Document Number: 001-46319 Rev. *R
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16. Ordering Information
Table 16-1. Device Key Features and Ordering Information
PowerPSoC Part Number
No. of Pins
Package
Channels
Voltage
Internal
FETs
56 QFN
56 QFN
56 QFN
56 QFN
56 QFN
56 QFN
56 QFN
56 QFN
56 QFN
56 QFN
8 mm × 8 mm
8 mm × 8 mm
8 mm × 8 mm
8 mm × 8 mm
8 mm × 8 mm
8 mm × 8 mm
8 mm × 8 mm
8 mm × 8 mm
8 mm × 8 mm
8 mm × 8 mm
4
4
4
4
3
3
3
2
1
1
32 V
32 V
32 V
32 V
32 V
32 V
32 V
32 V
32 V
32 V
4 × 1.0 A
4 × 0.5 A
0
4 × 1.0 A
3 × 1.0 A
3 × 0.5 A
0
2 × 1.0 A
1 × 1.0 A
1 × 1.0 A
CY8CLED04D01-56LTXI
CY8CLED04D02-56LTXI
CY8CLED04G01-56LTXI
CY8CLED04DOCD1-56LTXI
CY8CLED03D01-56LTXI
CY8CLED03D02-56LTXI
CY8CLED03G01-56LTXI
CY8CLED02D01-56LTXI
CY8CLED01D01-56LTXI
CY8CLED01D01-56LTXQ
Gate Drivers
for External
Low Side
N-FETs
4
4
4
4
3
3
3
2
1
1
16.1 Ordering Code Definitions
CY 8 C LED0x xxx (xxxx) - xx xxxx
Package Type:
LTX=QFN Pb-free
Thermal Rating:
I = Industrial
Q = Extended Temperature
Pin Count
OCD1 = On Chip Debugger
Part Number: D01 = Internal 1.0 A FETs, D02 = Internal 0.5 A FETs,
G01 = No Internal FETs
Family Code: 4 = 4 Channel, 3 = 3 Channel, 2 = 2 Channel, 1 = 1 Channel
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 001-46319 Rev. *R
Page 50 of 55
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CY8CLED02D01/CY8CLED01D01
17. Packaging Information
Packaging Dimensions
This section illustrates the package specification for the CY8CLED04D0X, CY8CLED04G01, CY8CLED03D0X, CY8CLED03G01,
CY8CLED02D01, and CY8CLED01D01 along with the thermal impedance for the package and solder reflow peak temperatures.
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
Figure 17-1. 56-Pin QFN (8 × 8 × 1.0 mm)
51-85187 *G
17.1 Thermal Impedance
Package
Typical JA [22]
56 QFN[23]
16.6 °C/W
17.2 Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to
achieve good solderability.
Package
Minimum Peak
Temperature[24]
Maximum Peak
Temperature
56 QFN
240 °C
260 °C
Notes
22. TJ = TA + POWER x JA
23. To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane. The thermal model for Cypress’s
PowerPSoC family was simulated using a JESD51-7 standard FR4 PCB with four metal layers, 2 oz copper weight on outer layers, and 1 oz on inner layers. Thermal
via array below the device is laid out according to package manufacturers’ recommendations.
24. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
Document Number: 001-46319 Rev. *R
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18. Acronyms
Acronym
Acronym
Description
AC
alternating current
ADC
analog-to-digital converter
API
application programming interface
CPU
central processing unit
CSA
current sense amplifier
CT
continuous time
DAC
digital-to-analog converter
DALI
digital addressable lighting interface
DC
direct current
DMM
delta sigma modulation mode
DMX
digital multiplexing
DSM
delta sigma modulator
DTMF
dual-tone multi frequency
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only
memory
Description
PrISM
precise intensity signal modulation
PSoC
programmable system-on-chip™
PWM
pulse width modulator
QFN
quad flat no leads package
RGBA
red, green, blue, amber
RGGB
red, green, green, blue
SAR
successive approximation register
SC
switched capacitor
SCL
serial I2C
SCLK
serial issp clock
SDA
serial i2c data
SDATA
serial issp data
SPI
serial peripheral interface
SRAM
static random access memory
TRM
technical reference manual
UART
universal asynchronous receiver/transmitter
USB
universal serial bus
WDT
watch dog timer
EMI
electromagnetic interference
FAQ
frequently asked questions
FET
field effect transistor
19. Document Conventions
FSR
full scale range
19.1 Units of Measure
GPIO
general purpose i/o
GUI
graphical user interface
HBM
human body model
IC
integrated circuit
ICE
in-circuit emulator
IDE
integrated development environment
ILO
internal low-speed oscillator
IMO
internal main oscillator
ISSP
in-system serial programming
I/O
input/output
IPOR
imprecise power on reset
LED
light emitting diode
LSB
least-significant bit
LVD
low voltage detect
MCU
microcontroller
MOSFET
metal-oxide-semiconductor field effect transistor
MSB
most-significant bit
OCD
on chip debugger
PC
program counter
POR
power on reset
PPOR
precision power on reset
PowerPSoC
power programmable system-on-chip™
Document Number: 001-46319 Rev. *R
Symbol
°C
dB
Hz
pp
V
KB
ppm
sps
W
A
Kbit
KHz
K
MHz
M
A
F
H
s
V
Vrms
Unit of Measure
degrees Celsius
decibels
Hertz
peak-to-peak
sigma:one standard deviation
volt
ohm
1024 bytes
parts per million
samples per second
watt
ampere
1024 bits
kilohertz
kilohm
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolt
microvolts root-mean-square
Page 52 of 55
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CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
Symbol
W
mA
ms
mV
mW
nA
ns
nV
pA
pF
ps
fF
Unit of Measure
microwatt
milliampere
millisecond
millivolt
milliwatt
nanoampere
nanosecond
nanovolt
picoampere
picofarads
picoseconds
femtofarad
Document Number: 001-46319 Rev. *R
Page 53 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
20. Document History Page
Document Title: CY8CLED04D01/CY8CLED04D02/CY8CLED04G01/CY8CLED03D01/CY8CLED03D02/CY8CLED03G01/
CY8CLED02D01/CY8CLED01D01, PowerPSoC® Intelligent LED Driver
Document Number: 001-46319
Orig. of
Submission
Revision ECN No.
Description of Change
Change
Date
**
2506500
ANWA/
05/20/08
New datasheet.
DSG
*A
2575708
ANWA/
10/01/08
1) Updated Logic Block Diagram with AINX label and SREGFB pin.
AESA
2) Updated Current Sense Amplifier Specification Table.
3) Updated External Gate Driver Specification Table.
4) Updated Register Table.
*B
2662774
KJV
02/19/09
Extensive changes made to content and electrical specifications.
*C
2665155 KJV/PYRS
02/25/09
Updated Notes in electrical specifications.
*D
2671254 KJV/PYRS
03/10/09
Updated sections 8, 9, and 10 on pages 14, 15, and 16.
*E
2683506
VED
04/03/09
Release to the external web site.
*F
2698529 KJV/PYRS
04/27/09
Updated Figure 15-2., and Figure 15-4..
*G
2735072
KJV
07/10/09
Added 1 and 2 channel part information.
*H
2765369
KJV
09/17/09
Updated electrical specifications.
*I
2870389 FRE/PYRS
02/01/10
Updated Absolute Maximum Ratings, DC GPIO, AC Chip-Level, and AC
Programming Specifications as follows:
Added VREGINMAX absolute maximum specification.
Modified tWRITE specification.
Added IOH, IOL, DCILO, f32K_U, tPOWERUP, tERASEALL, tPROGRAM_HOT,
and tPROGRAM_COLD specifications
Updated package diagram
*J
2952677 FRE/UKK
06/15/10
Datasheet reviewed and updated with a view to improve clarity, readability and
customer-friendliness. This includes language, consistency in terminology to
match software and other PowerPSoC documentation, changes to reflect
major changes in software such as removal of system level design addition of
links to relevant collateral such as kits, technical reference manuals and application notes.
*K
3031567 FRE/UKK
09/16/10
Removed DALI in Page 1 and Page 13, and added the DALI note in Page 13.
Added a note to Section 15.10 after Table 15-20 on page 38.
Updated as per the new Cypress Style and datasheet template.
*L
3073506
KJV
11/08/2010 Updated datasheet to add Extended Temperature rated device
CY8CLED01D01-56LTXQ
*M
3178540
KJV
02/28/2011 Updated certain specifications for Extended Temperature rated device
*N
3244595
KJV
05/04/2011 Updated description for Symbol VREGIN and VCSP,VCSN in Table 14-1. Updated
Figure 15-6.
*O
3355306
KJV
08/29/2011 Replaced Table 16-20 with Table 15-20 in Built-in Switching Regulator
*P
3597060
GULA
04/24/2012 Updated Packaging Information (51-85187 from Rev *E to *F).
Completing Sunset Review.
*Q
4374000
SNVN
05/08/2014 Added D1 and updated notes for the other components in Table 15-20.
Updated links to reference documents in Current Sense Amplifier, Digital
System, and Analog Multiplexer System sections.
Added note for FIMO24 parameter in Table 15-3.
Updated links in Worldwide Sales and Design Support based on the template.
*R
4727870
SNVN
04/16/2015 Updated Electrical Characteristics:
Updated Table 15-34 (Updated details in Description column).
Updated Packaging Information:
spec 51-85187 – Changed revision from *F to *G.
Updated Note 23.
Completing Sunset Review.
Document Number: 001-46319 Rev. *R
Page 54 of 55
CY8CLED04D01/CY8CLED04D02/CY8CLED04G01
CY8CLED03D01/CY8CLED03D02/CY8CLED03G01
CY8CLED02D01/CY8CLED01D01
21. Sales, Solutions, and Legal Information
21.1 Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
cypress.com/go/plc
Memory
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/psoc
Technical Support
cypress.com/go/support
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2008-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-46319 Rev. *R
Revised April 16, 2015
Page 55 of 55
PSoC Designer™, Programmable System-on-Chip™, and PrISM™ are trademarks and PSoC® and, PowerPSoC® are registered trademarks of Cypress Semiconductor Corp. All other trademarks
or registered trademarks referenced herein are property of the respective corporations.