ATMEL AT24C256C-XHL-T

Features
• Low-voltage and Standard-voltage Operation
 VCC = 1.7V to 5.5V
• Internally Organized as 32,768 x 8
• Two-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• Write Protect Pin for Hardware and Software Data Protection
Two-wire
Serial EEPROM
• 64-byte Page Write Mode (Partial Page Writes Allowed)
256K (32,768 x 8)
• 1 MHz (5.0V, 2.7V, 2.5V), and 400kHz (1.7V) Compatibility
• Self-timed Write Cycle (5ms Max)
• High Reliability
Atmel AT24C256C
 Endurance: One Million Write Cycles
 Data Retention: 40 Years
• Lead-free/Halogen-free Devices Available
• 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead UDFN and 8-ball VFBGA Packages
• Die Sales: Wafer Form, Waffle Pack and Bumped Wafers
Description
The AT24C256C provides 262,144-bits of serial electrically erasable and
programmable read-only memory (EEPROM) organized as 32,768 words of eight
bits each. The device’s cascadable feature allows up to eight devices to share a
common two-wire bus. The device is optimized for use in many industrial and
commercial applications where low-power and low-voltage operation are essential.
The devices are available in space-saving 8-lead JEDEC SOIC, 8-lead TSSOP,
8-lead UDFN, and 8-ball VFBGA packages. In addition, this device operates from
1.7V to 5.5V.
Table 1.
Pin Configurations
Pin Name
A0 – A2
8-lead SOIC
Function
Address Inputs
SDA
Serial Data
SCL
Serial Clock Input
WP
Write Protect
GND
Ground
A0
A1
A2
GND
8-lead TSSOP
1
8
VCC
2
7
3
6
4
5
WP
SCL
SDA
8-lead UDFN
A0
A1
A2
GND
1
8
VCC
2
7
3
6
4
5
WP
SCL
SDA
8-ball VFBGA
VCC 8
1 A0
VCC 8
1
WP 7
SCL 6
SDA 5
2 A1
WP 7
SCL 6
SDA 5
2
3 A2
4 GND
Bottom View
3
4
A0
A1
A2
GND
Bottom View
8568C–SEEPR–5/10
1.
Absolute Maximum Ratings*
Operating Temperature .......................... −55°C to +125°C
Storage Temperature ........................... −65°C to + 150°C
Voltage on Any Pin
with Respect to Ground ............................... − 1.0 V +7.0V
Maximum Operating Voltage ................................... 6.25V
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or
any other conditions beyond those indicated in
the operational sections of this specification are
not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.
DC Output Current ................................................ 5.0 mA
Figure 1-1.
Block Diagram
VCC
GND
WP
START
STOP
LOGIC
SERIAL
CONTROL
LOGIC
LOAD
DEVICE
ADDRESS
COMPARATOR
A2
A1
A0
R/W
EN
H.V. PUMP/TIMING
COMP
LOAD
DATA RECOVERY
INC
DATA WORD
ADDR/COUNTER
Y DEC
X DEC
SCL
SDA
EEPROM
SERIAL MUX
DOUT/ACK
LOGIC
DIN
DOUT
2
Atmel AT24C256C
8568C–SEEPR–5/10
Atmel AT24C256C
2.
Pin Descriptions
SERIAL CLOCK (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and
negative-edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open drain driven and may
be wire-ORed with any number of other open-drain or open-collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are
hardwired (directly to GND or to VCC) for compatibility with other Atmel® AT24Cxx devices. When the pins are
hardwired, as many as eight 256K devices may be addressed on a single bus system. (Device addressing is
discussed in detail under “Device Addressing”) A device is selected when a corresponding hardware and software
match is true. If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND.
However, due to capacitive coupling that may appear during customer applications, Atmel recommends always
connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or
less.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When
WP is connected directly to VCC, all write operations to the memory are inhibited. If the pin is left floating, the WP
pin will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer
applications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor,
Atmel recommends using 10kΩ or less.
3
8568C–SEEPR–5/10
3.
Memory Organization
Atmel AT24C256C, 256K SERIAL EEPROM: The 256K is internally organized as 512 pages of 64-bytes each.
Random word addressing requires a 15-bit data word address.
Table 3-1.
Pin Capacitance(1)
Applicable over recommended operating range from: TA = 25°C, f = 1.0MHz, VCC = +1.7V
Symbol
Test Condition
Max
Units
Conditions
CI/O
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
CIN
Input Capacitance (A0, A1, SCL)
6
pF
VIN = 0V
Note:
1. This parameter is characterized and is not 100% tested
Table 3-2.
DC Characteristics
Applicable over recommended operating range from: TAI = − 40°C to +85°C, VCC = +1.7V to +5.5V (unless otherwise noted)
Symbol
Test Condition
Min
Typ
1.7
Max
Units
5.5
V
VCC1
Supply Voltage
ICC1
Supply Current
VCC = 5.0V
READ at 400kHz
1.0
2.0
mA
ICC2
Supply Current
VCC = 5.0V
WRITE at 400kHz
2.0
3.0
mA
Standby Current
(1.7V option)
VCC = 1.7V
1.0
µA
ISB1
6.0
µA
VIN = VCC or VSS
VCC = 5.0V
ILI
Input Leakage
Currentt VCC = 5.0V
VIN = VCC or VSS
0.10
3.0
µA
ILO
Output Leakage
Currentt VCC = 5.0V
VOUT = VCC or VSS
0.05
3.0
µA
VIL
Input Low Level(1)
-0.6
VCC x 0.3
V
VCC x 0.7
VCC + 0.5
V
(1)
VIH
Input High Level
VOL2
Output Low Level
VCC = 3.0V
IOL = 2.1mA
0.4
V
VOL1
Output Low Level
VCC = 1.7V
IOL = 0.15mA
0.2
V
Note:
4
Parameter
1. VIL min and VIH max are reference only and are not tested
Atmel AT24C256C
8568C–SEEPR–5/10
Atmel AT24C256C
Table 3-3.
AC Characteristics (Industrial Temperature)
Applicable over recommended operating range from:
TAI = − 40°C to +85°C, VCC = +1.7V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2.
1.7V
Symbol
2.5, 5.0V
Parameter
Units
Min
Max
Min
400
Max
fSCL
Clock Frequency, SCL
tLOW
Clock Pulse Width Low
1.3
0.4
µs
tHIGH
Clock Pulse Width High
0.6
0.4
µs
tI
Noise Suppression Time(1)
tAA
Clock Low to Data Out Valid
0.05
tBUF
Time the bus must be free before a new transmission can start(1)
1.3
0.5
µs
tHD.STA
Start Hold Time
0.6
0.25
µs
tSU.STA
Start Set-up Time
0.6
0.25
µs
tHD.DAT
Data In Hold Time
0
0
µs
tSU.DAT
Data In Set-up Time
100
100
ns
100
0.9
50
ns
0.55
µs
0.3
µs
300
100
ns
Inputs Rise Time
(1)
0.05
kHz
0.3
(1)
tR
1000
tF
Inputs Fall Time
tSU.STO
Stop Set-up Time
0.6
0.25
µs
tDH
Data Out Hold Time
50
50
ns
tWR
Write Cycle Time
5
Endurance(1)
25°C, Page Mode, 3.3V
1,000,000
Note:
5
ms
Write Cycles
1. This parameter is ensured by characterization and is not 100% tested
2. AC measurement conditions:
- RL (connects to VCC): 1.3kΩ (2.5V, 5.5V), 10kΩ (1.7V)
- Input pulse voltages: 0.3VCC to 0.7VCC
- Input rise and fall times: ≤ 50ns
- Input and output timing reference voltages: 0.5VCC
5
8568C–SEEPR–5/10
4.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the
SDA pin may change only during SCL low time periods (refer to Figure 2). Data changes during SCL high periods
will indicate a start or stop condition as defined below.
Figure 4-1.
Data Validity
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any
other command (refer to Figure 2-2).
Figure 4-2.
Start and Stop Definition
SDA
SCL
START
STOP
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the
stop command will place the EEPROM in a standby power mode (refer to Figure 3).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a “0” during the ninth clock cycle to acknowledge that it has received each word.
STANDBY MODE: The Atmel® AT24C256C features a low-power standby mode that is enabled upon power-up
and after the receipt of the stop bit and the completion of any internal operations.
6
Atmel AT24C256C
8568C–SEEPR–5/10
Atmel AT24C256C
SOFTWARE RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol
reset by following these steps:
a)
b)
c)
Create a start bit condition,
Clock nine cycles,
Create another start bit followed by stop bit condition as shown below.
The device is ready for next communication after above steps has been completed.
Figure 4-3.
Software Reset
Dummy Clock Cycles
Start bit
SCL
1
2
3
Start bit
8
Stop bit
9
SDA
Figure 4-4.
Bus Timing
tHIGH
tF
tR
tLOW
SCL
tSU.STA
tLOW
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA IN
tAA
tDH
tBUF
SDA OUT
7
8568C–SEEPR–5/10
Figure 4-5.
Write Cycle Timing
SCL
SDA
ACK
8th BIT
WORDn
(1)
twr
START
CONDITION
STOP
CONDITION
Note:
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of
the internal clear/write cycle
Figure 4-6.
Output Acknowledge
1
SCL
8
9
DATA IN
DATA OUT
START
8
ACKNOWLEDGE
Atmel AT24C256C
8568C–SEEPR–5/10
Atmel AT24C256C
5.
Device Addressing
The 256K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read
or write operation (refer to Figure 8). The device address word consists of a mandatory “1”, “0” sequence for the
first four most significant bits as shown. This is common to all two-wire EEPROM devices.
Figure 5-1.
1
MSB
Device Addressing
0
1
0
A2
A1
A0
R/W
LSB
The next three bits are the A2, A1, A0 device address bits to allow as many as eight devices on the same bus.
These bits must compare to their corresponding hardwired input pins. The A2, A1, and A0 pins use an internal
proprietary circuit that biases them to a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is
high, and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the device will
return to a standby state.
DATA SECURITY: The Atmel® AT24C256C has a hardware data protection scheme that allows the user to write
protect the whole memory when the WP pin is at VCC.
9
8568C–SEEPR–5/10
6.
Write Operations
BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the
first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0”. The addressing
device, such as a microcontroller, must then terminate the write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this
write cycle and the EEPROM will not respond until the write is complete (refer to Figure 9).
Figure 6-1.
Note:
Byte Write
* = DON’T CARE bit
PAGE WRITE: The 256K EEPROM is capable of 64-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after
the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the
microcontroller can transmit up to 63 more data words. The EEPROM will respond with a “0” after each data word
received. The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 10).
Figure 6-2.
Note:
Page Write
* = DON’T CARE bit
The data word address lower six bits are internally incremented following the receipt of each data word. The
higher data word address bits are not incremented, retaining the memory page row location. When the word
address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the
same page. If more than 64 data words are transmitted to the EEPROM, the data word address will “roll over” and
previous data will be overwritten. The address “roll over” during write is from the last byte of the current page to
the first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are
disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device
address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has
completed will the EEPROM respond with a “0”, allowing the read or write sequence to continue.
10
Atmel AT24C256C
8568C–SEEPR–5/10
Atmel AT24C256C
7.
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in
the device address word is set to “1”. There are three read operations: current address read, random address
read, and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed
during the last read or write operation, incremented by one. This address stays valid between operations as long
as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page,
to the first byte of the first page.
Once the device address with the read/write select bit set to “1” is clocked in and acknowledged by the EEPROM,
the current address data word is serially clocked out. The microcontroller does not respond with an input “0” but
does generate a following stop condition (refer to Figure 11).
Figure 7-1.
Current Address Read
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address.
Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the
microcontroller must generate another start condition. The microcontroller now initiates a current address read by
sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and
serially clocks out the data word. The microcontroller does not respond with a “0” but does generate a following
stop condition. (Refer to Figure 12)
Figure 7-2.
Note:
Random Read
* = DON’T CARE bit
11
8568C–SEEPR–5/10
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read.
After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM
receives an acknowledge, it will continue to increment the data word address and serially clock out sequential
data words. When the memory address limit is reached, the data word address will “roll over” and the sequential
read will continue. The sequential read operation is terminated when the microcontroller does not respond with a
“0” but does generate a following stop condition (refer to Figure 13).
Figure 7-3.
12
Sequential Read
Atmel AT24C256C
8568C–SEEPR–5/10
Atmel AT24C256C
8.
Ordering Code Detail
AT 2 4 C 2 5 6 C - S S H L - B
Atmel Designator
Shipping Carrier Option
B or blank = Bulk (tubes)
T = Tape and reel
Product Family
Operating Voltage
L
Device Density
256 = 256K
Device Revision
= 1.7V to 5.5V
Package Device Grade or
Wafer/Die Thickness
H
= Green, NiPdAu lead finish,
Industrial Temperature Range
(-40°C to +85°C)
U = Green, matte Sn lead finish,
Industrial Temperature Range
(-40°C to +85°C)
11 = 11mil wafer thickness
Package Option
SS = JEDEC SOIC
X = TSSOP
MA = UDFN
C = VFBGA
WWU = Wafer unsawn
WDT = Die in Tape and Reel
13
8568C–SEEPR–5/10
9.
Part Markings
Atmel AT24C256C-SSHL
Top Mark
Seal Year
| Seal Week
|
|
|
|---|---|---|---|---|---|---|---|
A
T
M
L
H
Y
W
W
|---|---|---|---|---|---|---|---|
2
E
C
L
* LOT NUMBER
|---|---|---|---|---|---|---|---|
|
PIN 1 INDICATOR (DOT)
Y = SEAL YEAR
6: 2006
0:
7: 2007
1:
8: 2008
2:
9: 2009
3:
2010
2011
2012
2013
WW = SEAL WEEK
02 = Week 2
04 = Week 4
:: : :::: :
:: : :::: ::
50 = Week 50
52 = Week 52
Lot Number to Use ALL Characters in Marking
BOTTOM MARK
No Bottom Mark
Y = SEAL YEAR
6: 2006
0:
7: 2007
1:
8: 2008
2:
9: 2009
3:
2010
2011
2012
2013
Atmel AT24C256C-XHL
Top Mark
PIN 1 INDICATOR (DOT)
|
|---|---|---|---|
*
H
Y
W
W
|---|---|---|---|---|
2
E
C
L
|---|---|---|---|---|
Bottom Mark
|---|---|---|---|---|---|---|
X
X
|---|---|---|---|---|---|---|
A
A
A
A
A
A
A
<- PIN 1 INDICATOR
WW
02
04
::
::
50
52
=
=
=
:
:
=
=
SEAL
Week
Week
::::
::::
Week
Week
WEEK
2
4
:
::
50
52
WW
02
04
::
::
50
52
=
=
=
:
:
=
=
SEAL
Week
Week
::::
::::
Week
Week
WEEK
2
4
:
::
50
52
XX = Country of Origin
Atmel AT24C256C-MAHL
Top Mark
Seal Year
| Seal Week
|
|
|
|---|---|---|---|---|---|---|---|
A
T
M
L
H
Y
W
W
|---|---|---|---|---|---|---|---|
2
E
C
L
LOT NUMBER
|---|---|---|---|---|---|---|---|
*
|
PIN 1 INDICATOR (DOT)
14
Y = SEAL YEAR
6: 2006
0:
7: 2007
1:
8: 2008
2:
9: 2009
3:
2010
2011
2012
2013
Atmel AT24C256C
8568C–SEEPR–5/10
Atmel AT24C256C
Atmel AT24C256C-CUL
Top Mark
Line 1 ----------->
Line 2 ----------->
2ECU
YMTC
| <---
PIN 1 INDICATOR (DOT)
Y = ONE DIGIT YEAR CODE
4: 2004
7: 2007
5: 2005
8: 2008
6: 2006
9: 2009
M
A
B
"
J
K
L
=
=
=
"
=
=
=
SEAL MONTH (USE ALPHA DESIGNATOR A-L)
JANUARY
FEBRUARY
""""""""
OCTOBER
NOVEMBER
DECEMBER
TC = TRACE CODE
15
8568C–SEEPR–5/10
10.
Ordering Codes
Atmel AT24C256C Ordering Information
Ordering Code
Voltage
Package
Operating Range
AT24C256C-SSHL-B
AT24C256C-SSHL-T(2)
AT24C256C-XHL-B(1)
AT24C256C-XHL-T(2)
AT24C256C-MAHL-T(2)
AT24C256C-CUL-T(2)
1.7V to 5.5V
1.7V to 5.5V
1.7V to 5.5V
1.7V to 5.5V
1.7V to 5.5V
1.7V to 5.5V
8S1
8S1
8A2
8A2
8MA2
8U2-1
Lead-free/Halogen-free
Industrial Temperature (−40°C to 85°C)
AT24C256C-WWU11L(3)
1.7V to 5.5V
Die Sale
Industrial Temperature (−40°C to 85°C)
(1)
Note:
1. Bulk delivery in tubes (SOIC and TSSOP 100/tube)
2. Tape and reel delivery (SOIC 4k/reel, TSSOP, UDFN and VFBGA 5k/reel)
3. Contact Atmel Sales for Wafer sales
Package Type
16
8S1
8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8A2
8-lead, 4.40mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
8MA2
8-lead, 2.00mm x 3.00mm Body, 0.50mm Pitch, Dual No Lead Package (UDFN)
8U2-1
8-ball, die Ball Grid Array Package (VFBGA)
Atmel AT24C256C
8568C–SEEPR–5/10
Atmel AT24C256C
11.
Packaging Information
8S1 – JEDEC SOIC
END VIEW
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
A
1.35
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.05
E1
3.81
–
3.99
E
5.79
–
6.20
e
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
L
NOTE
1.27 BSC
0.40
–
1.27
0°
–
8°
5/19/10
TITLE
Package Drawing Contact:
8S1, 8-lead (0.150” Wide Body), Plastic Gull
packagedrawings@atmel.com Wing Small Outline (JEDEC SOIC)
GPC
SWB
DRAWING NO.
8S1
REV.
F
17
8568C–SEEPR–5/10
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
D
A
b
e
A2
NOM
MAX
NOTE
3.00
3.10
2, 5
3, 5
6.40 BSC
E1
4.30
4.40
4.50
A
–
–
1.20
A2
0.80
1.00
1.05
b
0.19
–
0.30
e
L
Side View
L1
4
0.65 BSC
0.45
0.60
0.75
1.00 REF
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions,
tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall
not exceed 0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed
0.25 mm (0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess
of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.
Minimum space between protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/19/10
TITLE
Package Drawing Contact:
8A2, 8-lead 4.4mm Body, Plastic Thin
packagedrawings@atmel.com Shrink Small Outline Package (TSSOP)
18
2.90
E
D
Notes:
MIN
GPC
TNR
DRAWING NO.
8A2
REV.
E
Atmel AT24C256C
8568C–SEEPR–5/10
Atmel AT24C256C
8MA2 – UDFN
E
1
8
Pin 1 ID
2
7
3
6
4
5
D
C
A2
A
A1
E2
b (8x)
8
1
Pin#1 ID
(R0.10)
7
0.35
COMMON DIMENSIONS
(Unit of Measure = mm)
2
D2
6
3
5
4
e (6x)
K
L (8x)
Notes: 1. This drawing is for general information only. Refer to
JEDEC Drawing MO-229 for proper dimensions,
tolerances, datums, etc.
2. The terminal #1 ID is a laser-marked feature.
3. Dimensions b applies to metalized terminal and is
measured between 0.15 mm and 0.30 mm from the
terminal tip. If the terminal has the optional radius on the
other end of the terminal, the dimension should not be
measured in that radius area.
SYMBOL
MIN
D
NOM
MAX
2.00 BSC
E
3.00 BSC
D2
1.40
1.50
1.60
E2
1.20
1.30
1.40
A
0.50
0.55
0.60
A1
0.00
0.02
0.05
A2
–
–
0.55
0.152 REF
C
L
NOTE
0.30
e
0.40
0.35
0.50 BSC
b
0.18
0.25
0.30
K
0.20
–
–
3
4/15/08
TITLE
Package Drawing Contact:
packagedrawings@atmel.com
8MA2, 8-pad, 2 x 3 x 0.6 mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No
Lead Package (UDFN)
GPC
YNZ
DRAWING NO.
REV.
8MA2
A
19
8568C–SEEPR–5/10
8U2-1 – VFBGA
// 0.10 C
0.10 (4X)
D
A1 Ball Pad Corner
0.08 C
C
A
Øb
Ø0.15 M C A B
Ø0.08 M C
e
A1
B
A2
A
Top View
Side View
A1 BALL PAD CORNER
2
1
A
COMMON DIMENSIONS
(Unit of Measure = mm)
B
e
C
D
(e1)
d
SYMBOL
MIN
NOM
MAX
A
0.81
0.91
1.00
A1
0.15
0.20
0.25
A2
0.40
0.45
0.50
(d1)
b
0.25
0.30
0.35
Bottom View
D
2.35 BSC
8 SOLDER BALLS
E
3.73 BSC
e
0.75 BSC
e1
0.74 BSC
d
0.75 BSC
d1
0.80 REF
Notes: 1. This drawing is for general information.
2. Dimension 'b' is measured at the maximum solder ball
diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
NOTE
2/25/08
Package Drawing Contact:
packagedrawings@atmel.com
20
TITLE
GPC
8U2-1, 8 ball, 2.35 x 3.73 mm Body,
0.75 mm pitch, VFBGA Package (dBGA2)
GWW
DRAWING NO.
REV.
8U2-1
C
Atmel AT24C256C
8568C–SEEPR–5/10
Atmel AT24C256C
Appendix A. Revision History
Doc. Rev.
Date
Comments
8568C
05/2010
Update 8S1 and 8A2 package drawings.
8568B
03/2010
Part Markings and ordering detail/codes updated.
8568A
09/2009
Initial document release
21
8568C–SEEPR–5/10
He ad q ua rt e rs
In t er n at io n al
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P ro d u ct Co n t a ct
Technical Support
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8568C–SEEPR–5/10