SCAN18373T Transparent Latch with TRI-STATE ® Outputs General Description Features The SCAN18373T is a high speed, low-power transparent latch featuring separate data inputs organized into dual 9-bit bytes with byte-oriented latch enable and output enable control signals. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), and Test Clock (TCK). n n n n n n Connection Diagram n n n n IEEE 1149.1 (JTAG) Compliant Buffered active-low latch enable TRI-STATE outputs for bus-oriented applications 9-bit data busses for parity applications Reduced-swing outputs source 24 mA/sink 48 mA Guaranteed to drive 50Ω transmission line to TTL input levels of 0.8V and 2.0V TTL compatible inputs 25 mil pitch Cerpack packaging Includes CLAMP and HIGHZ instructions Standard Microcircuit Drawing (SMD) 5962-9311801 Pin Names Description AI(0–8), BI(0–8) Data Inputs ALE, BLE Latch Enable Inputs AOE1, BOE1 TRI-STATE Output Enable Inputs AO(0–8), BO(0–8) TRI-STATE Latch Outputs Truth Tables Inputs AO (0–8) ALE AOE1 AI (0–8) X H X H L L L H L H H L L X Inputs Z AO0 BO (0–8) BLE BOE1 BI (0–8) X H X H L L L H L H H L L X BO0 Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance AO0 = Previous AO before H-to-L transition of ALE BO0 = Previous BO before H-to-L transition of BLE Functional Description DS100321-1 The SCAN18373T consists of two sets of nine D-type latches with TRI-STATE standard outputs. When the Latch Enable (ALE or BLE) input is HIGH, data on the inputs (AI(0–8) or BI(0–8) ) enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its input changes. When Latch Enable is LOW, the latches store the information that was present on the inputs a set-up time preceding the HIGH-to-LOW transition of the TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100321 www.national.com SCAN18373T Transparent Latch with TRI-STATE Outputs September 1998 Functional Description 2-state mode. When Output Enable is HIGH, the standard outputs are in the high impedance mode, but this does not interfere with entering new data into the latches. (Continued) Latch Enable. The TRI-STATE standard outputs are controlled by the Output Enable (AOE1 or BOE1) input. When Output Enable is LOW, the standard outputs are in the Logic Diagram DS100321-13 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Block Diagrams Byte-A DS100321-2 www.national.com 2 Block Diagrams (Continued) Tap Controller DS100321-3 Byte-B DS100321-4 Note 1: BSR stands for Boundary Scan Register. 3 www.national.com Description of Boundary-Scan Circuitry The INSTRUCTION register is an eight-bit register which captures the value 00111101. The two least significant bits of this captured value (01) are required by IEEE Std 1149.1. The upper six bits are unique to the SCAN18373T device. SCAN CMOS Test Access Logic devices do not include the IEEE 1149.1 optional identification register. Therefore, this unique captured value can be used as a “pseudo ID” code to confirm that the correct device is placed in the appropriate location in the boundary scan chain. The scan cells used in the BOUNDARY-SCAN register are one of the following two types depending upon their location. Scan cell TYPE1 is intended to solely observe system data, while TYPE2 has the additional ability to control system data. (See IEEE Standard 1149.1 for a further description of scan cell TYPE1 and for a further description of scan cell TYPE2.) Scan cell TYPE1 is located on each system input pin while scan cell TYPE2 is located at each system output pin as well as at each of the two internal active-high output enable signals. AOE controls the activity of the A-outputs while BOE controls the activity of the B-outputs. Each will activate their respective outputs by loading a logic high. Instruction Register Scan Chain Definition The BYPASS register is a single bit shift register stage identical to scan cell TYPE1. It captures a fixed logic low. Bypass Register Scan Chain Definition Logic 0 DS100321-10 MSB → LSB Instruction Code DS100321-9 Instruction 00000000 EXTEST 10000001 SAMPLE/PRELOAD 10000010 CLAMP 00000011 HIGHZ All Others BYPASS Scan Cell TYPE1 DS100321-7 www.national.com 4 Description of Boundary-Scan Circuitry (Continued) Scan Cell TYPE2 DS100321-8 5 www.national.com Description of Boundary-Scan Circuitry (Continued) Boundary-Scan Register Scan Chain Definition (42 Bits in Length) DS100321-25 www.national.com 6 Description of Boundary-Scan Circuitry (Continued) Boundary-Scan Register Definition Index Bit No. Pin No. Pin Type 41 AOE1 Pin Name 3 Input TYPE1 40 ACP 54 Input TYPE1 39 AOE Internal TYPE2 38 BOE1 26 Input TYPE1 37 BCP 31 Input TYPE1 36 BOE Internal TYPE2 35 AI0 55 Input TYPE1 34 AI1 53 Input TYPE1 33 AI2 52 Input TYPE1 32 AI3 50 Input TYPE1 31 AI4 49 Input TYPE1 30 AI5 47 Input TYPE1 29 AI6 46 Input TYPE1 28 AI7 44 Input TYPE1 27 AI8 43 Input TYPE1 26 BI0 42 Input TYPE1 25 BI1 41 Input TYPE1 24 BI2 39 Input TYPE1 23 BI3 38 Input TYPE1 22 BI4 36 Input TYPE1 21 BI5 35 Input TYPE1 20 BI6 33 Input TYPE1 19 BI7 32 Input TYPE1 18 BI8 30 Input TYPE1 17 AO0 2 Output TYPE2 16 AO1 4 Output TYPE2 15 AO2 5 Output TYPE2 14 AO3 7 Output TYPE2 13 AO4 8 Output TYPE2 12 AO5 10 Output TYPE2 11 AO6 11 Output TYPE2 10 AO7 13 Output TYPE2 9 AO8 14 Output TYPE2 8 BO0 15 Output TYPE2 7 BO1 16 Output TYPE2 6 BO2 18 Output TYPE2 5 BO3 19 Output TYPE2 4 BO4 21 Output TYPE2 3 BO5 22 Output TYPE2 2 BO6 24 Output TYPE2 1 BO7 25 Output TYPE2 0 BO8 27 Output TYPE2 7 Scan Cell Type Control Signals A–in B–in A–out B–out www.national.com Absolute Maximum Ratings (Note 2) ESD (Min) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Output Diode Current (IOK) VO = −0.5V VO = VCC +0.5V DC Output Voltage (VO) DC Output Source/Sink Current (IO) DC VCC or Ground Current Per Output Pin Junction Temperature Cerpack Storage Temperature 2000V Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) SCAN Products Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Military Minimum Input Edge Rate dV/dt VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −20 mA +20 mA −20 mA +20 mA −0.5V to VCC + 0.5V ± 70 mA 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of SCAN circuits outside databook specifications. ± 70 mA +175˚C −65˚C to +150˚C DC Electrical Characteristics Symbol Parameter Military TA = VCC (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH VOL IIN Minimum High 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low 4.5 0.8 Input Voltage 5.5 0.8 Minimum High 4.5 3.15 Output Voltage 5.5 4.15 4.5 2.4 5.5 2.4 Maximum Low 4.5 0.1 Output Voltage 5.5 0.1 4.5 0.55 5.5 0.55 5.5 ± 1.0 Maximum Input V VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA V V VIN = VIL or VIH IOH = −24 mA IOUT = 50 µA V VIN = VIL or VIH IOL = 48 mA µA VI = VCC, GND VI = VCC VI = GND VI = GND Leakage Current IIN Maximum Input Leakage 5.5 Minimum Input Leakage 5.5 (Note 3) Minimum Dynamic Output Current 5.5 IOHD IOZ Maximum Output TDI, TMS IOLD 3.7 µA −385 µA −160 µA 63 mA VOLD = 0.8V Max −27 mA VOHD = 2.0V Min 5.5 ± 10.0 µA VI (OE) = VIL, VIH 5.5 −100 mA Min VO = 0V 5.5 168 µA 5.5 930 µA VO = Open TDI, TMS = VCC VO = Open Leakage Current IOS Output Short Circuit Current ICC Maximum Quiescent Supply Current TDI, TMS = GND www.national.com 8 DC Electrical Characteristics (Continued) Military TA = Parameter VCC (V) Maximum ICC per Input 5.5 2.0 mA 5.5 2.15 mA Symbol Units −55˚C to +125˚C Conditions Guaranteed Limits ICCt VI = VCC − 2.1V VI = VCC − 2.1V TDI/TMS Pin, Test One with the Other Floating Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: All outputs loaded; thresholds associated with output under test. Note 5: Maximum test duration 2.0 ms, one output loaded at a time. Noise Specifications Symbol Military TA = −55˚C to +125˚C VCC (V) Parameter Fig. No. Units Guaranteed Limits VOLP Maximum High 0.8 Output Noise 5.0 V (Notes 6, 7) VOLV Minimum Low -0.8 Output Noise 5.0 V (Notes 6, 7) Note 6: Maximum number of outputs that can switch simultaneously is n. (n−1) outputs are switched LOW and one output held LOW. Note 7: Maximum number of outputs that can switch simultaneously is n. (n−1) outputs are switched HIGH and one output held HIGH. AC Electrical Characteristics Normal Operation Military Symbol Parameter tPLH, Propagation tPHL Delay, D to Q tPLH, Propagation tPHL Delay, LE to Q tPLZ, Disable Time VCC (V) (Note 8) TA = −55˚C to +125˚C CL = 50 pF 5.0 5.0 5.0 tPHZ tPZL, Enable Time 5.0 tPZH Min Max 2.5 11.0 2.5 11.5 2.5 12.0 2.5 13.0 1.5 11.0 1.5 10.3 2.0 13.5 2.0 11.5 Units Fig. No. ns ns ns ns Note 8: Voltage Range 5.0 is 5.0V ± 0.5V. AC Operating Requirements Normal Operation Symbol Parameter VCC (V) (Note 9) Setup Time, H or L 5.0 Military TA = −55˚C to +125˚C CL = 50 pF Units Fig. No. Guaranteed Minimum tS 3.0 9 ns www.national.com AC Operating Requirements (Continued) Normal Operation Symbol Military TA = −55˚C to +125˚C CL = 50 pF VCC (V) (Note 9) Parameter Units Fig. No. Guaranteed Minimum Data to LE tH Hold Time, H or L 5.0 1.5 ns 5.0 5.0 ns LE to Data tW LE Pulse Width Note 9: Voltage Range 5.0 is 5.0V ± 0.5V. AC Electrical Characteristics Scan Test Operation Military Parameter VCC (V) (Note 10) tPLH, Propagation Delay 5.0 tPHL TCK to TDO Symbol TA = −55˚C to +125˚C CL = 50 pF Min tPLZ, Disable Time tPHZ TCK to TDO tPZL, Enable Time tPZH TCK to TDO 5.0 5.0 Max 3.5 15.8 3.5 15.8 2.5 12.8 2.5 12.8 3.0 16.7 3.0 16.7 tPLH, Propagation Delay 5.0 21.7 tPHL TCK to Data Out 5.0 21.7 during Update-DR State 5.0 tPLH, Propagation Delay 5.0 22.0 tPHL TCK to Data Out 5.0 22.0 5.5 23.0 5.5 23.0 during Update-IR State tPLH, Propagation Delay tPHL TCK to Data Out during Test Logic 5.0 Units ns ns ns ns ns ns 5.0 Reset State tPLZ, Propagation Delay 4.0 19.6 tPHZ TCK to Data Out 4.0 19.6 5.0 22.4 5.0 22.4 5.0 23.3 5.0 23.3 5.0 22.6 5.0 22.6 during Update-DR State tPLZ, Propagation Delay tPHZ TCK to Data Out 5.0 5.0 ns ns during Update-IR State tPLZ, Propagation Delay tPHZ TCK to Data Out 5.0 ns during Test Logic Reset State tPZL, Propagation Delay tPZH TCK to Data Out 5.0 during Update-DR State www.national.com 10 ns Fig. No. AC Electrical Characteristics (Continued) Scan Test Operation Military Symbol Parameter tPZL, Propagation Delay tPZH TCK to Data Out VCC (V) (Note 10) TA = −55˚C to +125˚C CL = 50 pF 5.0 Min Max 6.5 26.2 6.5 26.2 7.0 27.4 7.0 27.4 Units Fig. No. ns during Update-IR State tPZL, Propagation Delay tPZH TCK to Data Out 5.0 ns during Test Logic Reset State Note 10: Voltage Range 5.0 is 5.0V ± 0.5V. All propagation delays involving TCK are measured from the falling edge of TCK. AC Operating Requirements Scan Test Operation Military Symbol VCC (V) (Note 11) Parameter TA = −55˚C to +125˚C CL = 50 pF Units Fig. No. Guaranteed Minimum tS Setup Time, 5.0 3.0 ns 5.0 5.5 ns 5.0 3.0 ns 5.0 4.5 ns 5.0 3.0 ns 5.0 3.0 ns 5.0 3.0 ns 5.0 4.0 ns 5.0 8.0 ns 5.0 2.0 ns 5.0 4.0 ns 5.0 4.5 ns H 12.0 ns L 5.0 Data to TCK (Note 13) tH Hold Time, TCK to Data (Note 13) tS Setup Time, H or L AOE1, BOE1 to TCK (Note 15) tH Hold Time, H or L TCK to AOE1, BOE1 (Note 15) tS Setup Time, H or L Internal AOE, BOE, to TCK (Note 14) tH Hold Time, H or L TCK to Internal AOE, BOE (Note 14) tS Setup Time ALE, BLE (Note 12) to TCK tH Hold Time TCK to ALE, BLE (Note 12) tS Setup Time, H or L TMS to TCK tH Hold Time, H or L TCK to TMS tS Setup Time, H or L TDI to TCK tH Hold Time, H or L TCK to TDI tW fmax Pulse Width TCK Maximum TCK 5.0 5.0 25 MHz Clock Frequency 11 www.national.com AC Operating Requirements (Continued) Scan Test Operation Military Symbol Parameter VCC (V) (Note 11) TA = −55˚C to +125˚C CL = 50 pF Units Fig. No. Guaranteed Minimum Tpu Wait Time, Power Up to TCK 5.0 100 ns Tdn Power Down Delay 0.0 100 ms Note 11: Voltage Range 5.0 is 5.0V ± 0.5V. All Input Timing Delays involving TCK are measured from the rising edge of TCK. Note 12: Timing pertains to BSR 37 and 40 only. Note 13: This delay represents the timing relationship between the data input and TCK at the associated scan cells numbered 0-8, 9-17, 18-26 and 27-35. Note 14: This delay represents the timing relationship between AOE/BOE and TCK for scan cells 36 and 39 only. Note 15: Timing pertains to BSR 38 and 41 only. Capacitance Symbol www.national.com Parameter Max Units CIN Input Pin Capacitance 5.0 pF COUT Output Pin Capacitance 15.0 pF CPD Power Dissipation Capacitance 35.0 pF 12 Conditions VCC = 5.0V VCC = 5.0V VCC = 5.0V 13 SCAN18373T Transparent Latch with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Ceramic Flatpak (F) NS Package Number WA56A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. 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