ISP1563 Hi-Speed Universal Serial Bus PCI Host Controller Rev. 01 — 14 July 2005 Product data sheet 1. General description The ISP1563 is a Peripheral Component Interconnect (PCI)-based, single-chip Universal Serial Bus (USB) Host Controller. It integrates two Original USB Open Host Controller Interface (OHCI) cores, one Hi-Speed USB Enhanced Host Controller Interface (EHCI) core, and four transceivers that are compliant with Hi-Speed USB and Original USB. The functional parts of the ISP1563 are fully compliant with Universal Serial Bus Specification Rev. 2.0, Open Host Controller Interface Specification for USB Rev. 1.0a, Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0, PCI Local Bus Specification Rev. 2.2, and PCI Bus Power Management Interface Specification Rev. 1.1. The integrated high performance USB transceivers allow the ISP1563 to handle all Hi-Speed USB transfer speed modes: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The ISP1563 provides four downstream ports, allowing simultaneous connection of USB devices at different speeds. The ISP1563 provides downstream port status indicators, green and amber LEDs, to allow user-rich messages of the Root Hub downstream ports status, without requiring detailed port information in the internal registers. The ISP1563 is fully compatible with various operating system drivers, such as Microsoft Windows standard OHCI and EHCI drivers that are present in Windows XP, Windows 2000 and Red Hat Linux. The ISP1563 directly interfaces to any 32-bit, 33 MHz PCI bus. Its PCI pins can source 3.3 V. The PCI interface fully complies with PCI Local Bus Specification Rev. 2.2. The ISP1563 is ideally suited for use in Hi-Speed USB host-enabled motherboards, Hi-Speed USB host PCI add-on card applications, mobile applications, and embedded solutions. To facilitate motherboard development, the ISP1563 can use the available 48 MHz clock signal to reduce the total cost of a solution. To reduce Electro-Magnetic Interference (EMI), however, it is recommended that the 12 MHz crystal is used in PCI add-on card designs. ISP1563 Philips Semiconductors HS USB PCI Host Controller 2. Features ■ Complies with Universal Serial Bus Specification Rev. 2.0 ■ Supports data transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) ■ Two Original USB OHCI cores comply with Open Host Controller Interface Specification for USB Rev. 1.0a ■ One Hi-Speed USB EHCI core complies with Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 ■ Supports PCI 32-bit, 33 MHz interface compliant with PCI Local Bus Specification Rev. 2.2, with support for D3cold standby and wake-up modes; all I/O pins are 3.3 V standard ■ Compliant with PCI Bus Power Management Interface Specification Rev. 1.1 for all hosts (EHCI and OHCI), and supports all power states: D0, D1, D2, D3hot and D3cold ■ Four downstream ports with support for downstream port indicator LEDs: amber and green ■ Configurable two or four port root hubs ■ CLKRUN support for mobile applications, such as internal notebook design ■ Configurable subsystem ID and subsystem Vendor ID through external EEPROM ■ Digital and analog power separation for better EMI and Electro-Static Discharge (ESD) protection ■ Supports hot Plug and Play and remote wake-up of peripherals ■ Supports individual power switching and individual overcurrent protection for downstream ports ■ Supports partial dynamic port-routing capability for downstream ports that allows sharing of the same physical downstream ports between the Original USB Host Controller and the Hi-Speed USB Host Controller ■ Supports legacy PS/2 keyboard and mouse ■ Uses 12 MHz crystal oscillator to reduce system cost and EMI emissions ■ Supports dual power supply: PCI Vaux(3V3) and VCC ■ Operates at +3.3 V power supply input ■ Low power consumption ■ Full industrial operating temperature range from −40 °C to +85 °C ■ Full-scan design with high fault coverage (93 % to 95 %) ensures high quality ■ Available in LQFP128 package. 3. Applications ■ ■ ■ ■ ■ ■ Digital consumer appliances Notebook PCI add-on card PC motherboard Set-Top Box (STB) Web appliances. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 2 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 4. Ordering information Table 1: Ordering information Type number ISP1563BM Package Name Description Version LQFP128 plastic low profile quad flat package; 128 leads; body 14 × 14 × 1.4 mm SOT420-1 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 3 of 107 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x Rev. 01 — 14 July 2005 32-bit, 33 MHz PCI bus AD[31:0] 20, 22 to 25, 30 to 32, 36 to 41, 43, 44, 60 to 62, 65, 66, 68, 69, 32 71, 74, 75, 77 to 82 C/BE#[3:0] 33, 45, PCI CORE 58, 72 REQ# 19 PCI MASTER GNT# 18 IDSEL 34 PCI SLAVE INTA# 14 FRAME# 46 DEVSEL# 49 IRDY# 47 CLKRUN# 52 PAR 57 123 104, 111, 120, 128 3 4 LEGACY KEYBOARD AND MOUSE SUPPORT IRQ1 IRQ12 8 KBIRQ1 9 MUIRQ12 7 A20OUT ISP1563 VOLTAGE REGULATOR (Vaux) CONFIGURATION SPACE 12 11, 85 6, 95 Vaux(1V8) core CONFIGURATION FUNCTION 0 CONFIGURATION FUNCTION 1 OHCI (FUNCTION 0) OHCI (FUNCTION 1) EHCI (FUNCTION 2) RAM RAM RAM 99 5 CONFIGURATION FUNCTION 2 STOP# 51 PCICLK 122 GLOBAL CONTROL PERR# 54 SERR# 55 TRDY# 48 121 10, 27, 56, 73, 84, 98, 100, 102, 107, 109, 116, 118, 124, 126 CORE RESET_N Philips Semiconductors 13 PME# 1 VDDA_AUX SDA 5. Block diagram 9397 750 14224 Product data sheet SMI# SEL48M SCL VI(VAUX3V3) AUX1V8 VCC(I/O)_AUX RREF SEL2PORTS GNDA 17 RST# 15 POR PORT ROUTER 21, 35, 50, VCC(I/O) 67, 83 VI(VREG3V3) REG1V8 26 VOLTAGE REGULATOR 28, 53, 70 ORIGINAL USB ATX Hi-SPEED USB ATX ATX2 ORIGINAL USB ATX Hi-SPEED USB ATX ATX3 ORIGINAL USB ATX Hi-SPEED USB ATX ATX4 ORIGINAL USB ATX Hi-SPEED USB ATX 86 87 004aaa510 XOSC PLL 105 91 92 106 108 110 96 93 94 97 101 103 114 63 64 115 125 127 112 89 90 113 117 119 OC2_N OC1_N OC3_N OC4_N AMB2 AMB1 AMB3 AMB4 GRN1 GRN2 GRN3 GRN4 DM1 DP1 DM3 DP3 DM2 DP2 DM4 DP4 PWE1_N PWE2_N PWE3_N PWE4_N ISP1563 Fig 1. Block diagram. GNDD HS USB PCI Host Controller 4 of 107 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. XTAL2 2, 16, 29, 42, 59, 76, 88 ATX1 VCC(I/O) DETECT XTAL1 VCC core ISP1563 Philips Semiconductors HS USB PCI Host Controller 6. Pinning information 97 128 6.1 Pinning 1 96 ISP1563BM 64 65 33 32 004aaa511 Fig 2. Pin configuration. 6.2 Pin description Table 2: Pin description Symbol [1] Pin Type Description PME# 1 O PCI Power Management Event; used by a device to request a change in the device or system power state PCI pad; 3.3 V signaling; open-drain GNDD 2 - digital ground IRQ1 3 O system keyboard interrupt; when not in use, pull-down to ground through a 10 kΩ resistor 3.3 V output pad; 3 ns slew rate control; CMOS; open-drain IRQ12 4 O system mouse interrupt; when not in use, pull-down to ground through a 10 kΩ resistor 3.3 V output pad; 3 ns slew rate control; CMOS; open-drain SEL2PORTS 5 I select two or four ports: • • LOW: four ports selected HIGH: two ports selected. 3.3 V input pad; push-pull; CMOS VCC(I/O)_AUX 6 - 3.3 V auxiliary supply voltage; used to power pads; add a 100 nF decoupling capacitor A20OUT 7 O legacy gate 20 output; when not in use, pull-down to ground through a 10 kΩ resistor KBIRQ1 8 I MUIRQ12 9 I legacy mouse interrupt input; when not in use, pull-down to ground through a 10 kΩ resistor [2] GNDA 10 - analog ground 3.3 V output pad; 3 ns slew rate control; CMOS; open-drain legacy keyboard interrupt input; when not in use, pull-down to ground through a 10 kΩ resistor [2] 3.3 V input pad; push-pull; CMOS 3.3 V input pad; push-pull; CMOS 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 5 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 2: Pin description…continued Symbol [1] Pin Type Description AUX1V8 11 - 1.8 V auxiliary output voltage; only for voltage conditioning; cannot be used to supply power to external components; connected to 100 nF and 20 µF capacitors VI(VAUX3V3) 12 - 3.3 V auxiliary input supply voltage; add a 100 nF decoupling capacitor SMI# 13 O System Management Interrupt; when not in use, pull-up to 3.3 V through a 10 kΩ resistor 3.3 V output pad; 3 ns slew rate control; CMOS; open-drain INTA# 14 O PCI interrupt RST# 15 I GNDD 16 - digital ground PCICLK 17 I PCI system clock (33 MHz) GNT# 18 I/O PCI pad; 3.3 V signaling; open-drain PCI reset; used to bring PCI-specific registers, sequencers and signals to a consistent state 3.3 V input pad; push-pull; CMOS PCI pad; 3.3 V signaling PCI grant; indicates to the agent that access to the bus is granted PCI pad; 3.3 V signaling REQ# 19 I/O PCI request; indicates to the arbitrator that the agent wants to use the bus PCI pad; 3.3 V signaling AD[31] 20 I/O bit 31 of multiplexed PCI address and data PCI pad; 3.3 V signaling VCC(I/O) 21 - 3.3 V supply voltage; used to power pads; add a 100 nF decoupling capacitor AD[30] 22 I/O bit 30 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[29] 23 I/O bit 29 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[28] 24 I/O bit 28 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[27] 25 I/O bit 27 of multiplexed PCI address and data VI(VREG3V3) 26 - 3.3 V regulator input supply voltage; add a 100 nF decoupling capacitor GNDA 27 - analog ground REG1V8 28 - 1.8 V regulator output voltage; only for voltage conditioning; cannot be used to supply power to external components; connected to 100 nF and 20 µF capacitors GNDD 29 - digital ground AD[26] 30 I/O PCI pad; 3.3 V signaling bit 26 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[25] 31 I/O bit 25 of multiplexed PCI address and data PCI pad; 3.3 V signaling 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 6 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 2: Pin description…continued Symbol [1] Pin Type Description AD[24] 32 I/O bit 24 of multiplexed PCI address and data PCI pad; 3.3 V signaling C/BE#[3] 33 I/O byte 3 of multiplexed PCI bus command and byte enable PCI pad; 3.3 V signaling IDSEL 34 I PCI initialization device select; used as a chip select during configuration read and write transactions PCI pad; 3.3 V signaling VCC(I/O) 35 - 3.3 V supply voltage; used to power pads; add a 100 nF decoupling capacitor AD[23] 36 I/O bit 23 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[22] 37 I/O bit 22 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[21] 38 I/O bit 21 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[20] 39 I/O AD[19] 40 I/O bit 20 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 19 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[18] 41 I/O bit 18 of multiplexed PCI address and data PCI pad; 3.3 V signaling GNDD 42 - AD[17] 43 I/O digital ground bit 17 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[16] 44 I/O bit 16 of multiplexed PCI address and data PCI pad; 3.3 V signaling C/BE#[2] 45 I/O byte 2 of multiplexed PCI bus command and byte enable FRAME# 46 I/O PCI cycle frame; driven by the master to indicate the beginning and duration of an access IRDY# 47 I/O PCI initiator ready; indicates the ability of the initiating agent to complete the current data phase of a transaction TRDY# 48 I/O PCI target ready; indicates the ability of the target agent to complete the current data phase of a transaction DEVSEL# 49 I/O PCI pad; 3.3 V signaling PCI pad; 3.3 V signaling PCI pad; 3.3 V signaling PCI pad; 3.3 V signaling PCI device select; indicates if any device is selected on the bus PCI pad; 3.3 V signaling VCC(I/O) 50 - 3.3 V supply voltage; used to power pads; add a 100 nF decoupling capacitor STOP# 51 I/O PCI stop; indicates that the current target is requesting the master to stop the current transaction PCI pad; 3.3 V signaling 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. 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Rev. 01 — 14 July 2005 7 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 2: Pin description…continued Symbol [1] Pin Type Description CLKRUN# 52 I/O PCI CLKRUN signal; pull-down to ground through a 10 kΩ resistor PCI pad; 3.3 V signaling; open-drain REG1V8 53 - 1.8 V regulator output voltage; only for voltage conditioning; cannot be used to supply power to external components; add a 100 nF decoupling capacitor PERR# 54 I/O PCI parity error; used to report data parity errors during all PCI transactions, except a Special Cycle PCI pad; 3.3 V signaling SERR# 55 I/O PCI system error; used to report address parity errors and data parity errors on the Special Cycle command, or any other system error in which the result will be catastrophic PCI pad; 3.3 V signaling; open-drain GNDA 56 - analog ground PAR 57 I/O PCI parity PCI pad; 3.3 V signaling C/BE#[1] 58 I/O byte 1 of multiplexed PCI bus command and byte enable PCI pad; 3.3 V signaling GNDD 59 - AD[15] 60 I/O digital ground bit 15 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[14] 61 I/O bit 14 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[13] 62 I/O AMB4 63 I/O bit 13 of multiplexed PCI address and data PCI pad; 3.3 V signaling amber LED indicator output for the USB downstream port 4; this pin acts as an input only during the power-up sequence and thereafter, acts as an output: • • HIGH: FFh in the PMC register; supports D3cold LOW: EFh in the PMC register; does not support D3cold. 3.3 V bidirectional pad; three-state output; 3 ns slew-rate control; input; CMOS; open-drain GRN4 64 O green LED indicator output for the USB downstream port 4; the LED is off by default; the LED can be programmed to enable it to blink 3.3 V output pad; 3 ns slew rate control; CMOS; open-drain AD[12] 65 I/O bit 12 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[11] 66 I/O bit 11 of multiplexed PCI address and data VCC(I/O) 67 - 3.3 V supply voltage; used to power pads; add a 100 nF decoupling capacitor AD[10] 68 I/O PCI pad; 3.3 V signaling bit 10 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[9] 69 I/O bit 9 of multiplexed PCI address and data PCI pad; 3.3 V signaling 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 8 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 2: Pin description…continued Symbol [1] Pin Type Description REG1V8 70 - 1.8 V regulator output voltage; only for voltage conditioning; cannot be used to supply power to external components; add a 100 nF decoupling capacitor AD[8] 71 I/O bit 8 of multiplexed PCI address and data PCI pad; 3.3 V signaling C/BE#[0] 72 I/O byte 0 of multiplexed PCI bus command and byte enable PCI pad; 3.3 V signaling GNDA 73 - AD[7] 74 I/O analog ground bit 7 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[6] 75 I/O bit 6 of multiplexed PCI address and data GNDD 76 - digital ground AD[5] 77 I/O bit 5 of multiplexed PCI address and data AD[4] 78 I/O PCI pad; 3.3 V signaling PCI pad; 3.3 V signaling bit 4 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[3] 79 I/O bit 3 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[2] 80 I/O bit 2 of multiplexed PCI address and data PCI pad; 3.3 V signaling AD[1] 81 I/O AD[0] 82 I/O bit 1 of multiplexed PCI address and data PCI pad; 3.3 V signaling bit 0 of multiplexed PCI address and data PCI pad; 3.3 V signaling VCC(I/O) 83 - 3.3 V supply voltage; used to power pads; add a 100 nF decoupling capacitor GNDA 84 - analog ground AUX1V8 85 - 1.8 V auxiliary output voltage; only for voltage conditioning; cannot be used to supply power to external components; add a 100 nF decoupling capacitor XTAL1 86 AI crystal oscillator input; this can also be a 12 MHz or 48 MHz clock input XTAL2 87 AO crystal oscillator output (12 MHz); leave open when clock is used GNDD 88 - digital ground AMB3 89 I/O amber LED indicator output for the USB downstream port 3; the LED is off by default and can be programmed to enable it to blink; input as port indicator enable during reset; by default, pull up is enabled; if no LEDs are used, then connect this pin to ground, that is, no port indicator support 3.3 V bidirectional pad; three-state output; 3 ns slew-rate control; input; CMOS; open-drain GRN3 90 O green LED indicator output for the USB downstream port 3; the LED is off by default and can be programmed to enable it to blink 3.3 V output pad; 3 ns slew rate control; CMOS; open-drain 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 9 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 2: Pin description…continued Symbol [1] Pin Type Description AMB2 91 O amber LED indicator output for the USB downstream port 2; the LED is off by default and can be programmed to enable it to blink GRN2 92 O AMB1 93 O GRN1 94 O green LED indicator output for the USB downstream port 1; the LED is off by default and can be programmed to enable it to blink VCC(I/O)_AUX 95 - 3.3 V auxiliary supply voltage; used to power pads; add a 100 nF decoupling capacitor OC1_N 96 I 3.3 V output pad; 3 ns slew rate control; CMOS; open-drain green LED indicator output for the USB downstream port 2; the LED is off by default and can be programmed to enable it to blink 3.3 V output pad; 3 ns slew rate control; CMOS; open-drain amber LED indicator output for the USB downstream port 1; the LED is off by default and can be programmed to enable it to blink 3.3 V output pad; 3 ns slew rate control; CMOS; open-drain 3.3 V output pad; 3 ns slew rate control; CMOS; open-drain overcurrent sense input for the USB downstream port 1 (digital) 3.3 V input pad; push-pull; CMOS PWE1_N 97 O power enable for the USB downstream port 1 GNDA 98 - analog ground RREF 99 AI/O analog connection for the external resistor (12 kΩ ± 1 %) GNDA 100 - analog ground DM1 101 AI/O D−; analog connection for the USB downstream port 1; leave this pin open when not in use GNDA 102 - analog ground DP1 103 AI/O D+; analog connection for the USB downstream port 1; leave this pin open when not in use VDDA_AUX 104 - auxiliary analog supply voltage; add a 100 nF decoupling capacitor OC2_N 105 I overcurrent sense input for the USB downstream port 2 (digital) PWE2_N 106 O 3.3 V output pad; 3 ns slew rate control; CMOS; open-drain 3.3 V input pad; push-pull; CMOS power enable for the USB downstream port 2 3.3 V output pad; 3 ns slew rate control; CMOS; open-drain GNDA 107 - analog ground DM2 108 AI/O D−; analog connection for the USB downstream port 2; leave this pin open when not in use GNDA 109 - analog ground DP2 110 AI/O D+; analog connection for the USB downstream port 2; leave this pin open when not in use VDDA_AUX 111 - auxiliary analog supply voltage; add a 100 nF decoupling capacitor OC3_N 112 I overcurrent sense input for the USB downstream port 3 (digital) 3.3 V input pad; push-pull; CMOS PWE3_N 113 O OC4_N 114 I power enable for the USB downstream port 3 3.3 V output pad; 3 ns slew rate control; CMOS; open-drain overcurrent sense input for the USB downstream port 4 (digital) 3.3 V input pad; push-pull; CMOS 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 10 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 2: Pin description…continued Symbol [1] Pin Type Description PWE4_N 115 O power enable for the USB downstream port 4 3.3 V output pad; 3 ns slew rate control; CMOS; open-drain GNDA 116 - analog ground DM3 117 AI/O D−; analog connection for the USB downstream port 3; leave this pin open when not in use GNDA 118 - analog ground DP3 119 AI/O D+; analog connection for the USB downstream port 3; leave this pin open when not in use VDDA_AUX 120 - auxiliary analog supply voltage; add a 100 nF decoupling capacitor SEL48M 121 I selection between 12 MHz crystal and 48 MHz oscillator: • • LOW: 12 MHz crystal is used HIGH: 48 MHz clock is used. 3.3 V input pad; push-pull; CMOS SCL 122 I2C-bus clock; pull-up to 3.3 V through a 10 kΩ resistor [3] I/O I2C-bus pad; clock signal SDA 123 I2C-bus data; pull-up to 3.3 V through a 10 kΩ resistor [3] I/O I2C-bus pad; data signal GNDA 124 - analog ground DM4 125 AI/O D−; analog connection for the USB downstream port 4; leave this pin open when not in use GNDA 126 - analog ground DP4 127 AI/O D+; analog connection for the USB downstream port 4; leave this pin open when not in use VDDA_AUX 128 - auxiliary analog supply voltage; add a 100 nF decoupling capacitor [1] Symbol names ending with ‘#’, for example, NAME#, represent active LOW signals for PCI pins. Symbol names ending with underscore N, for example, NAME_N, represent active LOW signals for USB pins. [2] If legacy support is not used, connect this pin to ground. [3] Connect to ground if I2C-bus is not used. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 11 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 7. Functional description 7.1 OHCI Host Controller An OHCI Host Controller transfers data to devices at the Original USB defined bit rate of 12 Mbit/s or 1.5 Mbit/s. 7.2 EHCI Host Controller The EHCI Host Controller transfers data to a Hi-Speed USB compliant device at the Hi-Speed USB defined bit rate of 480 Mbit/s. When the EHCI Host Controller has the ownership of a port, the OHCI Host Controllers are not allowed to modify the port register. All additional port bit definitions required for the Enhanced Host Controller are not visible to the OHCI Host Controller. 7.3 Dynamic port-routing logic The port-routing feature allows sharing of the same physical downstream ports between the Original USB Host Controller and the Hi-Speed USB Host Controller. This requirement of the Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 provides four downstream ports, and these ports are multiplexed with the ports of the two OHCIs. The first and third downstream ports are always connected to the first OHCI, and the second and fourth downstream ports are always connected to the second OHCI. The EHCI is responsible for the port-routing switching mechanism. Two register bits are used for ownership switching. During power-on and system reset, the default ownership of all downstream ports is the OHCI. The Enhanced Host Controller Driver (HCD) controls the ownership during normal functionality. 7.4 Hi-Speed USB analog transceivers The Hi-Speed USB analog transceivers directly interface to the USB cables through integrated termination resistors. These transceivers can transmit and receive serial data at all data rates: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). 7.5 LED indicators for downstream ports The system designer can program two optional port indicators, a green LED and an amber LED, to indicate the status of the Host Controller. These port indicators are implemented according to the USB specification. All LED indicators are open-drain output. 7.6 Power management The ISP1563 provides an advanced power management capability interface that is compliant with PCI Bus Power Management Interface Specification Rev. 1.1. Power is controlled and managed by the interaction between drivers and PCI registers. For a detailed description on power management, see Section 10. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 12 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 7.7 Legacy support The ISP1563 provides legacy support for a USB keyboard and mouse. This means that the keyboard and mouse should be able to work even before the Operating System (OS) boot-up, with the necessary support in the Basic Input Output System (BIOS). Section 11.2 provides a detailed description on the legacy support in the ISP1563. 7.8 Phase-Locked Loop (PLL) A 12 MHz-to-30 MHz and 48 MHz clock multiplier PLL is integrated on-chip. This allows the use of a low-cost 12 MHz crystal, which also minimizes EMI. No external components are required for the PLL to operate. 7.9 Power-On Reset (POR) Figure 3 shows a possible curve of VCC(I/O) with dips at t2 to t3 and t4 to t5. At t0, POR will start with 1. At t1, the detector passes through the trip level. Another delay will be added before POR drops to 0 to ensure that the length of the generated detector pulse, POR, is large enough to reset asynchronous flip-flops. If the dip is too short (t4 to t5 < 11 µs), POR will not react and will stay LOW. VCC(I/O) VPOR(trip) t0 t1 t2 t3 t4 t5 POR 004aaa664 VPOR(trip) is typically 1.2 V. Fig 3. Power-on reset. 7.10 Power supply Figure 4 shows the ISP1563 power supply connection. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 13 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller ISP1563 26 VI(VREG3V3) PCI 3.3 V 100 nF 21, 35, 50, 67, 83 12 VCC(I/O) PCI 3.3 V 100 nF VI(VAUX3V3) PCI Vaux(3V3)(1) 100 nF 6, 95 VCC(I/O)_AUX PCI Vaux(3V3)(1) 100 nF 104, 111, 120, 128 VDDA_AUX PCI Vaux(3V3)(1) 100 nF 11 AUX1V8 100 nF 20 µF 85 AUX1V8 100 nF 28 REG1V8 100 nF 20 µF 53, 70 REG1V8 100 nF 2, 10, 16, 27, 29, 42, 56, 59, 73, 76, 84, 88, 98, 100, 102, 107, 109, 116, 118, 124, 126 004aaa666 GND (1) If Vaux(3V3) is not present on PCI, the pin should be connected to PCI 3.3 V. Fig 4. Power supply connection. 8. PCI 8.1 PCI interface The PCI interface has three functions. The first function (#0) and the second function (#1) are for the OHCI Host Controllers, and the third function (#2) is for the EHCI Host Controller. All functions support both master and target accesses, and share the same PCI interrupt signal INTA#. These functions provide memory-mapped, addressable operational registers as required in Open Host Controller Interface Specification for USB Rev. 1.0a and Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 14 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Additionally, function #0 provides legacy keyboard and mouse support to comply with Open Host Controller Interface Specification for USB Rev. 1.0a. Each function has its own configuration space. The PCI enumerator should allocate the memory address space for each of these functions. Power management is implemented in each PCI function and all power states are provided. This allows the system to achieve low power consumption by switching off the functions that are not required. 8.1.1 PCI configuration space PCI Local Bus Specification Rev. 2.2 requires that each of the three PCI functions of the ISP1563 provides its own PCI configuration registers, which can vary in size. In addition to the basic PCI configuration header registers, these functions implement capability registers to support power management. The registers of each of these functions are accessed by the respective driver. Section 8.2 provides a detailed description of the various PCI configuration registers. 8.1.2 PCI initiator and target A PCI initiator initiates PCI transactions to the PCI bus. A PCI target responds to PCI transactions as a slave. In the case of the ISP1563, the two Open Host Controllers and the Enhanced Host Controller function as both initiators or targets of PCI transactions issued by the host CPU. All USB Host Controllers have their own operational registers that can be accessed by the system driver software. Drivers use these registers to configure the Host Controller hardware system, issue commands to it, and monitor the status of the current hardware operation. The Host Controller plays the role of a PCI target. All operational registers of the Host Controllers are the PCI transaction targets of the CPU. Normal USB transfers require the Host Controller to access system memory fields, which are allocated by USB HCDs and PCI drivers. The Host Controller hardware interacts with the HCD by accessing these buffers. The Host Controller works as an initiator in this case, and becomes a PCI master. 8.2 PCI configuration registers The OHCI USB Host Controllers and the EHCI USB Host Controller contain two sets of software-accessible hardware registers: PCI configuration registers and memory-mapped Host Controller registers. A set of configuration registers is implemented for each of the three PCI functions of the ISP1563, see Table 3. Remark: In addition to the normal PCI header, from offset index 00h to 3Fh, implementation-specific registers are defined to support power management and function-specific features. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 15 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 3: PCI configuration space registers of OHCI1, OHCI2 and EHCI Address Bits 31 to 24 Bits 23 to 16 Bits 15 to 8 Reset value [1] Bits 7 to 0 Func0 OHCI1 Func1 OHCI2 Func2 EHCI PCI configuration header registers 00h Device ID[15:0] Vendor ID[15:0] 1561 1131h 1561 1131h 1562 1131h 04h Status[15:0] Command[15:0] 0210 0000h 0210 0000h 0210 0000h Revision ID[7:0] 0C03 1011h 0C03 1011h 0C03 2011h CacheLine Size[7:0] 0080 0000h 0080 0000h 0080 0000h Base Address 0[31:0] 0000 0000h 0000 0000h 0000 0000h reserved 0000 0000h 0000 0000h 0000 0000h 1561 1131h 1561 1131h 1562 1131h - - - 0000 00DCh 0000 00DCh 0000 00DCh 0000 0000h 0000 0000h 0000 0000h 08h Class Code[23:0] 0Ch reserved Header Type[7:0] 10h Latency Timer[7:0] 14h 18h 1Ch 20h 24h 28h 2Ch Subsystem ID[15:0] 30h Subsystem Vendor ID[15:0] reserved 34h reserved 38h Capabilities Pointer[7:0] reserved 3Ch Max_Lat[7:0] 40h Min_Gnt[7:0] reserved Interrupt Pin[7:0] Interrupt Line[7:0] 2A01 0100h 2A01 0100h 1002 0100h Retry Timeout TRDY Timeout 0000 8000h 0000 8000h 0000 8000h Enhanced Host Controller-specific PCI registers 60h FLADJ[7:0] SBRN[7:0] - - 00XX 2020h [2] Next_Item_Ptr [7:0] Cap_ID[7:0] D282 0001h D282 0001h FF82 0001h 0000 XX00h 0000 XX00h 0000 XX00h [3] PORTWAKECAP[15:0] Power management registers DCh E0h PMC[15:0] Data[7:0] PMCSR_BSE [7:0] PMCSR[15:0] [1] Reset values that are highlighted, for example, 0, indicate read and write accesses; and reset values that are not highlighted, for example, 0, indicate read-only. [2] XX is 1Fh for four ports and 07h for two ports. [3] See Section 8.2.3.4. The HCD does not usually interact with the PCI configuration space. The configuration space is used only by the PCI enumerator to identify the USB Host Controller and assign appropriate system resources by reading the Vendor ID (VID) and the Device ID (DID). 8.2.1 PCI configuration header registers The Enhanced Host Controller implements the normal PCI header register values, except the values for the memory-mapping base address register, serial bus number and Device ID. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 16 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 8.2.1.1 Vendor ID register This read-only register identifies the manufacturer of the device. PCI Special Interest Group (PCI-SIG) assigns valid vendor identifiers to ensure the uniqueness of the identifier. The bit description is shown in Table 4. Table 4: VID - Vendor ID register (address 00h) bit description Legend: * reset value 8.2.1.2 Bit Symbol Access Value Description 15 to 0 VID[15:0] R 1131h* Vendor ID: This read-only register value is assigned to Philips Semiconductors by PCI-SIG as 1131h. Device ID register This is a 2 B read-only register that identifies a particular device. The identifier is allocated by Philips Semiconductors. Table 5 shows the bit description of the register. Table 5: DID - Device ID register (address 02h) bit description Legend: * reset value Bit Symbol 15 to 0 [1] 8.2.1.3 DID[15:0] Access Value Description R 156Xh* [1] Device ID: This register value is defined by Philips Semiconductors to identify the USB Host Controller IC product. X is 1h for OHCI1 and OHCI2; X is 2h for EHCI. Command register This is a 2 B register that provides coarse control over the ability of a device to generate and respond to PCI cycles. The bit allocation of the Command register is given in Table 6. When logic 0 is written to this register, the device is logically disconnected from the PCI bus for all accesses, except configuration accesses. All devices are required to support this base level of functionality. Individual bits in the Command register may or may not support this base level of functionality. Table 6: Command register (address 04h) bit allocation Bit 15 14 13 11 10 Reset Access Bit 9 8 FBBE SERRE 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Symbol Symbol 12 reserved [1] SCTRL PER VGAPS MWIE SC BM MS IOS Reset 0 0 0 0 0 0 0 0 Access R R/W R R/W R R/W R/W R/W [1] The reserved bits should always be written with the reset value. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 17 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 7: Command register (address 04h) bit description Bit Symbol Description 15 to 10 reserved - 9 FBBE Fast Back-to-Back Enable: This bit controls whether a master can do fast back-to-back transactions to various devices. The initialization software must set this bit if all targets are fast back-to-back capable. 0 — Fast back-to-back transactions are only allowed to the same agent (value after RST#) 1 — The master is allowed to generate fast back-to-back transactions to different agents. 8 SERRE SERR# Enable: This bit is an enable bit for the SERR# driver. All devices that have an SERR# pin must implement this bit. Address parity errors are reported only if this bit and the PER bit are logic 1. 0 — Disable the SERR# driver 1 — Enable the SERR# driver. 7 SCTRL Stepping Control: This bit controls whether a device does address and data stepping. Devices that never do stepping must clear this bit. Devices that always do stepping must set this bit. Devices that can do either, must make this bit read and write, and initialize it to logic 1 after RST#. 6 PER Parity Error Response: This bit controls the response of a device to parity errors. When the bit is set, the device must take its normal action when a parity error is detected. When the bit is logic 0, the device sets DPE (bit 15 in the Status register) when an error is detected, but does not assert PERR# and continues normal operation. The state of this bit after RST# is logic 0. Devices that check parity must implement this bit. Devices are required to generate parity, even if parity checking is disabled. 5 VGAPS VGA Palette Snoop: This bit controls how Video Graphics Array (VGA) compatible and graphics devices handle accesses to VGA palette registers. 0 — The device should treat palette write accesses like all other accesses. 1 — Palette snooping is enabled, that is, the device does not respond to palette register writes and snoops data. VGA compatible devices should implement this bit. 4 MWIE Memory Write and Invalidate Enable: This is an enable bit for using the Memory Write and Invalidate command. 0 — Memory Writes must be used instead. State after RST# is logic 0. 1 — Masters may generate the command. This bit must be implemented by master devices that can generate the Memory Write and Invalidate command. 3 SC Special Cycles: Controls the action of a device on Special Cycle operations. 0 — Causes the device to ignore all Special Cycle operations. State after RST# is logic 0. 1 — Allows the device to monitor Special Cycle operations. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 18 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 7: Command register (address 04h) bit description…continued Bit Symbol Description 2 BM Bus Master: Controls the ability of a device to act as a master on the PCI bus. 0 — Disables the device from generating PCI accesses. State after RST# is logic 0. 1 — Allows the device to behave as a bus master. 1 MS Memory Space: Controls the response of a device to Memory Space accesses. 0 — Disables the device response. State after RST# is logic 0. 1 — Allows the device to respond to Memory Space accesses. 0 IOS I/O Space: Controls the response of a device to I/O space accesses. 0 — Disables the device response. State after RST# is logic 0. 1 — Allows the device to respond to I/O space accesses. 8.2.1.4 Status register The Status register is a 2 B read-only register used to record status information on PCI bus-related events. For bit allocation, see Table 8. Table 8: Status register (address 06h) bit allocation Bit 15 14 13 12 11 DPE SSE RMA RTA STA Reset 0 0 0 0 0 0 1 0 Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 FBBC reserved 66MC CL Reset 0 0 0 1 0 0 0 0 Access R R R R R R R R Symbol Symbol Table 9: 9 DEVSELT[1:0] 8 MDPE reserved Status register (address 06h) bit description Bit Symbol Description 15 DPE Detected Parity Error: This bit must be set by the device whenever it detects a parity error, even if the parity error handling is disabled. 14 SSE Signaled System Error: This bit must be set whenever the device asserts SERR#. Devices that never assert SERR# do not need to implement this bit. 13 RMA Received Master Abort: This bit must be set by a master device whenever its transaction, except for Special Cycle, is terminated with Master-Abort. All master devices must implement this bit. 9397 750 14224 Product data sheet 10 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 19 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 9: Status register (address 06h) bit description…continued Bit Symbol Description 12 RTA Received Target Abort: This bit must be set by a master device whenever its transaction is terminated with Target-Abort. All master devices must implement this bit. 11 STA Signaled Target Abort: This bit must be set by a target device whenever it terminates a transaction with Target-Abort. Devices that never signal Target-Abort do not need to implement this bit. 10 to 9 DEVSELT DEVSEL Timing: These bits encode the timing of DEVSEL#. There are three [1:0] allowable timing to assert DEVSEL#: 00b — Fast 01b — Medium 10b — Slow 11b — Reserved. These bits are read-only and must indicate the slowest time that a device asserts DEVSEL# for any bus command, except Configuration Read and Configuration Write. 8 MDPE Master Data Parity Error: This bit is implemented by bus masters. It is set when the following three conditions are met: • The bus agent asserted PERR# itself, on a read; or observed PERR# asserted, on a write. • The agent setting the bit acted as the bus master for the operation in which error occurred. • PER (bit 6 in the Command register) is set. 7 FBBC Fast Back-to-Back Capable: This read-only bit indicates whether the target is capable of accepting fast back-to-back transactions when the transactions are not to the same agent. This bit can be set to logic 1, if the device can accept these transactions; and must be set to logic 0 otherwise. 6 reserved - 5 66MC 66 MHz Capable: This read-only bit indicates whether this device is capable of running at 66 MHz. 0 — 33 MHz 1 — 66 MHz. 4 CL Capabilities List: This read-only bit indicates whether this device implements the pointer for a new capabilities linked list at offset 34h. 0 — No new capabilities linked list is available 1 — The value read at offset 34h is a pointer in configuration space to a linked list of new capabilities. 3 to 0 8.2.1.5 reserved - Revision ID register This 1 B read-only register indicates a device-specific revision identifier. The value is chosen by the vendor. This field is a vendor-defined extension of the Device ID. The Revision ID register bit description is given in Table 10. Table 10: REVID - Revision ID register (address 08h) bit description Legend: * reset value Bit Symbol Access Value Description 7 to 0 REVID[7:0] R 11h* Revision ID: This byte specifies the design revision number of functions. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 20 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 8.2.1.6 Class Code register Class Code is a 24-bit read-only register used to identify the generic function of the device, and in some cases, a specific register-level programming interface. Table 11 shows the bit allocation of the register. The Class Code register is divided into three byte-size fields. The upper byte is a base class code that broadly classifies the type of function the device performs. The middle byte is a sub-class code that identifies more specifically the function of the device. The lower byte identifies a specific register-level programming interface, if any, so that device-independent software can interact with the device. Table 11: Class Code register (address 09h) bit allocation Bit 23 22 21 20 Symbol 19 18 17 16 BCC[7:0] Reset 0Ch Access R R R R R R R R Bit 15 14 13 12 11 10 9 8 Symbol SCC[7:0] Reset 03h Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 R R R R Symbol RLPI[7:0] X0h [1] Reset Access [1] R R R R X is 1h for OHCI1 and OHCI2; X is 2h for EHCI. Table 12: 8.2.1.7 Class Code register (address 09h) bit description Bit Symbol Description 23 to 16 BCC[7:0] Base Class Code: 0Ch is the base class code assigned to this byte. It implies a serial bus controller. 15 to 8 SCC[7:0] Sub-Class Code: 03h is the sub-class code assigned to this byte. It implies the USB Host Controller. 7 to 0 RLPI[7:0] Register-Level Programming Interface: 10h is the programming interface code assigned to OHCI, which is USB 1.1 specification compliant. 20h is the programming interface code assigned to EHCI, which is USB 2.0 specification compliant. CacheLine Size register The CacheLine Size register is a read and write single-byte register that specifies the system CacheLine size in units of DWords. This register must be implemented by master devices that can generate the Memory Write and Invalidate command. The value in this register is also used by master devices to determine whether to use Read, Read Line or Read Multiple commands to access the memory. Slave devices that want to allow memory bursting using a CacheLine-wrap addressing mode must implement this register to know when a burst sequence wraps to the beginning of the CacheLine. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 21 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller This field must be initialized to logic 0 on activation of RST#. Table 13 shows the bit description of the CacheLine Size register. Table 13: CLS - CacheLine Size register (address 0Ch) bit description Legend: * reset value 8.2.1.8 Bit Symbol Access Value Description 7 to 0 CLS[7:0] R/W 00h* CacheLine Size: This byte identifies the system CacheLine size. Latency Timer register This register specifies, in units of PCI bus clocks, the value of the Latency Timer for the PCI bus master. Table 14 shows the bit description of the Latency Timer register. Table 14: LT - Latency Timer register (address 0Dh) bit description Legend: * reset value 8.2.1.9 Bit Symbol Access Value Description 7 to 0 LT[7:0] R/W 00h* Latency Timer: This byte identifies the latency timer. Header Type register The Header Type register identifies the layout of the second part of the predefined header; beginning at byte 10h in configuration space. It also identifies whether the device contains multiple functions. For bit allocation, see Table 15. Table 15: Header Type register (address 0Eh) bit allocation Bit 7 Symbol 6 5 4 MFD 3 2 1 0 HT[6:0] Reset 1 0 0 0 0 0 0 0 Access R R R R R R R R Table 16: Header Type register (address 0Eh) bit description Bit Symbol Description 7 MFD Multi-Function Device: This bit identifies a multifunction device. 0 — The device has single function. 1 — The device has multiple functions. 6 to 0 8.2.1.10 HT[6:0] Header Type: These bits identify the layout of the part of the predefined header, beginning at byte 10h in configuration space. Base Address register 0 Power-up software must build a consistent address map before booting the machine to an operating system. This means it must determine how much memory is in the system, and how much address space the I/O controllers in the system require. After determining this information, power-up software can map the I/O controllers into reasonable locations and proceed with system boot. To do this mapping in a device-independent manner, the base registers for this mapping are placed in the predefined header portion of configuration space. Bit 0 in all Base Address registers is read-only and used to determine whether the register maps into memory or I/O space. Base Address registers that map to memory space must return logic 0 in bit 0. Base Address registers that map to I/O space must return logic 1 in bit 0. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 22 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller The bit description of the BAR 0 register is given in Table 17. Table 17: BAR 0 - Base Address register 0 (address 10h) bit description Legend: * reset value 8.2.1.11 Bit Symbol Access 31 to 0 BAR 0[31:0] R/W Value Description 0000 0000h* Base Address to Memory-Mapped Host Controller Register Space: The memory size required by OHCI and EHCI are 4 kB and 256 B, respectively. Therefore, BAR 0[31:12] is assigned to the two OHCI ports, and BAR 0[31:8] is assigned to the EHCI port. Subsystem Vendor ID register The Subsystem Vendor ID register is used to uniquely identify the expansion board or subsystem where the PCI device resides. This register allows expansion board vendors to distinguish their boards, even though the boards may have the same Vendor ID and Device ID. Subsystem Vendor IDs are assigned by PCI-SIG to maintain uniqueness. The bit description of the Subsystem Vendor ID register is given in Table 18. Table 18: SVID - Subsystem Vendor ID register (address 2Ch) bit description Legend: * reset value Bit Symbol 15 to 0 SVID[15:0] 8.2.1.12 Access Value Description R 1131h* Subsystem Vendor ID: 1131h is the subsystem Vendor ID assigned to Philips Semiconductors. Subsystem ID register Subsystem ID values are vendor specific. The bit description of the Subsystem ID register is given in Table 19. Table 19: SID - Subsystem ID register (address 2Eh) bit description Legend: * reset value Bit Symbol 15 to 0 SID[15:0] [1] 8.2.1.13 Access Value Description R 156Xh* [1] Subsystem ID: For the ISP1563, Philips Semiconductors has defined OHCI functions as 1561h, and the EHCI function as 1562h. X is 1h for OHCI1 and OHCI2; X is 2h for EHCI. Capabilities Pointer register This register is used to point to a linked list of new capabilities implemented by the device. This register is only valid if CL (bit 4 in the Status register) is set. If implemented, bit 1 and bit 0 are reserved and should be set to 00b. Software should mask these bits off before using this register as a pointer in configuration space to the first entry of a linked list of new capabilities. The bit description of the register is given in Table 20. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 23 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 20: CP - Capabilities Pointer register (address 34h) bit description Legend: * reset value 8.2.1.14 Bit Symbol Access Value Description 7 to 0 CP[7:0] R DCh* Capabilities Pointer: EHCI efficiently manages power using this register. This Power Management register is allocated at offset DCh. Only one Host Controller is needed to manage power in the ISP1563. Interrupt Line register This is a 1 B register used to communicate interrupt line routing information. This register must be implemented by any device or device function that uses an interrupt pin. The interrupt allocation is done by the BIOS. The Power On Self Test (POST) software needs to write the routing information to this register because it initializes and configures the system. The value in this register specifies which input of the system interrupt controller(s) the interrupt pin of the device is connected. This value is used by device drivers and operating systems to determine priority and vector information. Values in this register are system architecture specific. The bit description of the register is given in Table 21. Table 21: IL - Interrupt Line register (address 3Ch) bit description Legend: * reset value 8.2.1.15 Bit Symbol Access Value Description 7 to 0 IL[7:0] R/W 00h* Interrupt Line: Indicates which IRQ is used to report interrupt from the ISP1563. Interrupt Pin register This 1 B register is use to specify which interrupt pin the device or device function uses. A value of 1h corresponds to INTA#, 2h corresponds to INTB#, 3h corresponds to INTC#, and 4h corresponds to INTD#. Devices or functions that do not use interrupt pin must set this register to logic 0. The bit description is given in Table 22. Table 22: IP - Interrupt Pin register (address 3Dh) bit description Legend: * reset value 8.2.1.16 Bit Symbol Access Value Description 7 to 0 IP[7:0] R 01h* Interrupt Pin: INTA# is the default interrupt pin used by the ISP1563. Min_Gnt and Max_Lat registers The Minimum Grant (Min_Gnt) and Maximum Latency (Max_Lat) registers are used to specify the desired settings of the device for latency timer values. For both registers, the value specifies a period of time in units of 250 ns. Logic 0 indicates that the device has no major requirements for setting latency timers. The Min_Gnt register bit description is given in Table 23. Table 23: Min_Gnt - Minimum Grant register (address 3Eh) bit description Legend: * reset value Bit Symbol 7 to 0 MIN_GNT R [7:0] [1] Access Value Description 0Xh* [1] Min_Gnt: It is used to specify how long a burst period the device needs, assuming a clock rate of 33 MHz. X is 1h for OHCI1 and OHCI2; X is 2h for EHCI. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 24 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller The Max_Lat register bit description is given in Table 24. Table 24: Max_Lat - Maximum Latency register (address 3Fh) bit description Legend: * reset value Bit Symbol 7 to 0 [1] 8.2.1.17 MAX_LAT[7:0] Access Value R XXh* [1] Description Max_Lat: It is used to specify how often the device needs to gain access to the PCI bus. XX is 2Ah for OHCI1 and OHCI2; XX is 10h for EHCI. TRDY Timeout register This is a read and write register at address 40h. The default and recommended value is 00h; TRDY Timeout disabled. This value can, however, be modified. It is an implementation-specific register, and not a standard PCI configuration register. The TRDY timer is 13 bits. The lower 5 bits are fixed as logic 0 and the upper 8 bits are determined by the TRDY Timeout register value. The time-out is calculated by multiplying the 13-bit timer with the PCI CLK cycle time. This register determines the maximum TRDY delay without asserting the UE (Unrecoverable Error) bit. If TRDY is longer than the delay determined by this register value, then the UE bit will be set. 8.2.1.18 Retry Timeout register The default value of this read and write register is 80h, and is located at address 41h. This value can, however, be modified. Programming this register as 00h means that retry time-out is disabled. This is an implementation-specific register, and not a standard PCI configuration register. The time-out is determined by multiplying the register value with the PCI CLK cycle time. This register determines the maximum number of PCI retires before the UE bit is set. If the number of retries is longer than the delay determined by this register value, then the UE bit will be set. 8.2.2 Enhanced Host Controller-specific PCI registers In addition to the PCI configuration header registers, EHCI needs some additional PCI configuration space registers to indicate the serial bus release number, downstream port wake-up event capability, and adjust the USB bus frame length for Start-of-Frame (SOF). The EHCI-specific PCI registers are given in Table 25. Table 25: 8.2.2.1 EHCI-specific PCI registers Offset Register 60h Serial Bus Release Number (SBRN) 61h Frame Length Adjustment (FLADJ) 62h to 63h Port Wake Capability (PORTWAKECAP) SBRN register The Serial Bus Release Number (SBRN) register is a 1 B register, and the bit description is given in Table 26. This register contains the release number of the USB specification with which this USB Host Controller module is compliant. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 25 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 26: SBRN - Serial Bus Release Number register (address 60h) bit description Legend: * reset value 8.2.2.2 Bit Symbol Access Value Description 7 to 0 SBRN[7:0] R 20h* Serial Bus Specification Release Number: This register value is to identify Serial Bus Specification Rev. 2.0. All other combinations are reserved. FLADJ register This feature is used to adjust any offset from the clock source that generates the clock that drives the SOF counter. When a new value is written to these six bits, the length of the frame is adjusted. The bit allocation of the Frame Length Adjustment (FLADJ) register is given in Table 27. Table 27: FLADJ - Frame Length Adjustment register (address 61h) bit allocation Bit 7 Reset Access [1] 6 5 4 3 reserved [1] Symbol 2 1 0 FLADJ[5:0] 0 0 1 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The reserved bits should always be written with the reset value. 8.2.2.3 Table 28: FLADJ - Frame Length Adjustment register (address 61h) bit description Bit Symbol 7 to 6 reserved - 5 to 0 FLADJ[5:0] Frame Length Timing Value: Each decimal value change to this register corresponds to 16 high-speed bit times. The SOF cycle time (number of SOF counter clock periods to generate a SOF micro frame length) is equal to 59488 + value in this field. The default value is decimal 32 (20h), which gives a SOF cycle time of 60000. Description FLADJ value SOF cycle time (480 MHz) 0 (00h) 59488 1 (01h) 59504 2 (02h) 59520 : : 31 (1Fh) 59984 32 (20h) 60000 : : 62 (3Eh) 60480 63 (3Fh) 60496 PORTWAKECAP register Port Wake Capability (PORTWAKECAP) is a 2 B register used to establish a policy about which ports are for wake events; see Table 29. Bit positions 15 to 1 in the mask correspond to a physical port implemented on the current EHCI controller. Logic 1 in a bit position indicates that a device connected below the port can be enabled as a wake-up device and the port may be enabled for disconnect or connect, or overcurrent events as wake-up events. This is an information only mask register. The bits in this register do not affect the actual operation of the EHCI Host Controller. The system-specific policy can be 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 26 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller established by BIOS initializing this register to a system-specific value. The system software uses the information in this register when enabling devices and ports for remote wake-up. Table 29: PORTWAKECAP - Port Wake Capability register (address 62h) bit description Legend: * reset value Bit Symbol Access Value Description 15 to 0 PORTWAKECAP[15:0] R/W Port Wake-Up Capability Mask: EHCI does not implement this feature. 001Fh* 8.2.3 Power management registers Table 30: 8.2.3.1 Power Management registers Offset Register Value read from address 34h + 0h Capability Identifier (Cap_ID) Value read from address 34h + 1h Next Item Pointer (Next_Item_Ptr) Value read from address 34h + 2h Power Management Capabilities (PMC) Value read from address 34h + 4h Power Management Control/Status (PMCSR) Value read from address 34h + 6h Power Management Control/Status PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) Value read from address 34h + 7h Data Cap_ID register The Capability Identifier (Cap_ID) register when read by the system software as 01h indicates that the data structure currently being pointed to is the PCI Power Management data structure. Each function of a PCI device may have only one item in its capability list with Cap_ID set to 01h. The bit description of the register is given in Table 31. Table 31: Cap_ID - Capability Identifier register bit description Address: Value read from address 34h + 0h Legend: * reset value 8.2.3.2 Bit Symbol Access Value Description 7 to 0 CAP_ID[7:0] R 01h* ID: This field when 01h identifies the linked list item as being PCI Power Management registers. Next_Item_Ptr register The Next Item Pointer (Next_Item_Ptr) register describes the location of the next item in the function’s capability list. The value given is an offset into the function’s PCI configuration space. If the function does not implement any other capabilities defined by the PCI-SIG for inclusion in the capabilities list, or if power management is the last item in the list, then this register must be set to 00h. See Table 32. Table 32: Next_Item_Ptr - Next Item Pointer register bit description Address: Value read from address 34h + 1h Legend: * reset value Bit Symbol 7 to 0 NEXT_ITEM_ R PTR[7:0] Access Value 00h* Description Next Item Pointer: This field provides an offset into the function’s PCI configuration space pointing to the location of the next item in the function’s capability list. If there are no additional items in the Capabilities List, this register is set to 00h. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 27 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 8.2.3.3 PMC register The Power Management Capabilities (PMC) register is a 2 B register, and the bit allocation is given in Table 33. This register provides information on the capabilities of the function related to power management. Table 33: PMC - Power Management Capabilities register bit allocation Address: Value read from address 34h + 2h Bit 15 14 13 Symbol 12 11 1 X [1] PME_S[4:0] 10 9 8 D2_S D1_S AUX_C X [1] 1 0 Reset 1 1 X [1] Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 DSI reserved PMI Symbol AUX_C[2:0] VER[2:0] Reset 1 0 0 0 0 0 1 0 Access R R R R R R R R [1] X is 0 for OHCI1 and OHCI2; X is 1 for EHCI. Table 34: PMC - Power Management Capabilities register bit description Address: Value read from address 34h + 2h Bit Symbol Description 15 to 11 PME_S[4:0] PME_Support: These bits indicate the power states in which the function may assert PME#. Logic 0 for any bit indicates that the function is not capable of asserting the PME# signal while in that power state. PME_S[0] — PME# can be asserted from D0 PME_S[1] — PME# can be asserted from D1 PME_S[2] — PME# can be asserted from D2 PME_S[3] — PME# can be asserted from D3hot PME_S[4] — PME# can be asserted from D3cold. 10 D2_S D2_Support: If this bit is logic 1, this function supports the D2 Power Management State. Functions that do not support D2 must always return logic 0 for this bit. 9 D1_S D1_Support: If this bit is logic 1, this function supports the D1 Power Management State. Functions that do not support D1 must always return logic 0 for this bit. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 28 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 34: PMC - Power Management Capabilities register bit description…continued Address: Value read from address 34h + 2h Bit Symbol Description 8 to 6 AUX_C[2:0] Auxiliary_Current: This three-bit field reports the Vaux(3V3) auxiliary current requirements for the PCI function. If the Data register is implemented by this function: • • A read from this field needs to return a value of 000b. The Data register takes precedence over this field for Vaux(3V3) current requirement reporting. If the PME# generation from D3cold is not supported by the function (PMC[15] = 0), this field must return a value of 000b when read. For functions that support PME# from D3cold and do not implement the Data register, the bit assignments corresponding to the maximum current required for Vaux(3V3) are: 111b — 375 mA 110b — 320 mA 101b — 270 mA 100b — 220 mA 011b — 160 mA 010b — 100 mA 001b — 55 mA 000b — 0 (self powered). 5 DSI Device Specific Initialization: This bit indicates whether special initialization of this function is required, beyond the standard PCI configuration header, before the generic class device driver is able to use it. This bit is not used by some operating systems. For example, Microsoft Windows and Windows NT do not use this bit to determine whether to use D3. Instead, it is determined using the capabilities of the driver. Logic 1 indicates that the function requires a device-specific initialization sequence, following transition to D0 un-initialized state. 4 reserved - 3 PMI PME Clock: 0 — Indicates that no PCI clock is required for the function to generate PME#. 1 — Indicates that the function relies on the presence of the PCI clock for the PME# operation. Functions that do not support the PME# generation in any state must return logic 0 for this field. 2 to 0 VER[2:0] Version: A value of 010b indicates that this function complies with PCI Power Management Interface Specification Rev. 1.1. The logic level of the AMB4 pin at power-on determines the default value of the PMC registers. If this pin is pulled up to 3.3 V, the ISP1563 will report that it supports PME generation in D3cold (bit 15 (PME_S4) will be set to 1). If this pin is left open or is pulled down, the ISP1563 will report that it does not support PME generation in D3cold (bit 15 (PME_S4) will be reset to 0). 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 29 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 8.2.3.4 PMCSR register The Power Management Control/Status (PMCSR) register is a 2 B register used to manage the Power Management State of the PCI function, as well as to allow and monitor Power Management Events (PMEs). The bit allocation of the register is given in Table 35. Table 35: PMCSR - Power Management Control/Status register bit allocation Address: Value read from address 34h + 4h Bit 15 Symbol 14 PMES 13 12 11 DS[1:0] 10 9 8 D_S[3:0] PMEE Reset X [1] 0 0 0 0 0 0 X [1] Access R/W R R R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit reserved [2] Symbol Reset Access PS[1:0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W [1] Sticky bit, if the function supports PME# from D3cold, then X is indeterminate at the time of initial operating system boot; X is 0 if the function does not support PME# from D3cold. [2] The reserved bits should always be written with the reset value. Table 36: PMCSR - Power Management Control/Status register bit description Address: Value read from address 34h + 4h Bit Symbol Description 15 PMES PME Status: This bit is set when the function normally assert the PME# signal independent of the state of the PMEE bit. Writing logic 1 to this bit clears it and causes the function to stop asserting PME#, if enabled. Writing logic 0 has no effect. This bit defaults to logic 0, if the function does not support the PME# generation from D3cold. If the function supports the PME# generation from D3cold, then this bit is sticky and must be explicitly cleared by the operating system each time the operating system is initially loaded. 14 to 13 DS[1:0] Data Scale: This two-bit read-only field indicates the scaling factor when interpreting the value of the Data register. The value and meaning of this field vary, depending on which data value is selected by the D_S field. This field is a required component of the Data register (offset 7) and must be implemented, if the Data register is implemented. If the Data register is not implemented, this field must return 00b when PMCSR is read. 12 to 9 Data_Select: This four-bit field selects the data that is reported through the Data register and the D_S field. This field is a required component of the Data register (offset 7) and must be implemented, if the Data register is implemented. If the Data register is not implemented, this field must return 00b when PMCSR is read. D_S[3:0] 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 30 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 36: PMCSR - Power Management Control/Status register bit description…continued Address: Value read from address 34h + 4h Bit Symbol Description 8 PMEE PME Enabled: Logic 1 allows the function to assert PME#. When it is logic 0, PME# assertion is disabled. This bit defaults to logic 0, if the function does not support the PME# generation from D3cold. If the function supports PME# from D3cold, then this bit is sticky and must be explicitly cleared by the operating system each time the operating system is initially loaded. 7 to 2 reserved - 1 to 0 PS[1:0] Power State: This two-bit field is used to determine the current power state of the EHCI function and to set the function into a new power state. The definition of the field values is given as: 00b — D0 01b — D1 10b — D2 11b — D3hot. If the software attempts to write an unsupported, optional state to this field, the write operation must complete normally on the bus; however, the data is discarded and no status change occurs. 8.2.3.5 PMCSR_BSE register The PMCSR PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) register supports PCI bridge-specific functionality and is required for all PCI-to-PCI bridges. The bit allocation of this register is given in Table 37. Table 37: PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit allocation Address: Value read from address 34h + 6h Bit 7 6 BPCC_EN B2_B3# Reset 0 0 0 0 Access R R R R Symbol 5 4 2 1 0 0 0 0 0 R R R R reserved 9397 750 14224 Product data sheet 3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 31 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 38: PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit description Address: Value read from address 34h + 6h Bit Symbol Description 7 BPCC_EN Bus Power/Clock Control Enable: 1 — Indicates that the bus power or clock control mechanism as defined in Table 39 is enabled. 0 — Indicates that the bus or power control policies as defined in Table 39 are disabled. When the Bus Power or Clock Control mechanism is disabled, the bridge’s PMCSR Power State (PS) field cannot be used by the system software to control the power or clock of the bridge’s secondary bus. 6 B2_B3# B2/B3 support for D3hot: The state of this bit determines the action that is to occur as a direct result of programming the function to D3hot. 1 — Indicates that when the bridge function is programmed to D3hot, its secondary bus’s PCI clock will be stopped (B2). 0 — Indicates that when the bridge function is programmed to D3hot, its secondary bus will have its power removed (B3). This bit is only meaningful if bit 7 (BPCC_EN) is logic 1. 5 to 0 reserved Table 39: - PCI bus power and clock control Originating device’s Secondary bus Resultant actions by bridge (either direct or indirect) bridge PM state [1] PM state [1] D0 B0 none D1 B1 none D2 B2 clock stopped on secondary bus D3hot B2, B3 clock stopped and PCI VCC removed from secondary bus (B3 only); for definition of B2_B3#, see Table 38. D3cold B3 none [1] 8.2.3.6 PM: Power Management. Data register The Data register is an optional, 1 B register that provides a mechanism for the function to report state dependent operating data, such as power consumed or heat dissipated. Table 40 shows the bit description of the register. Table 40: Data register bit description Address: Value read from address 34h + 7h Legend: * reset value Bit Symbol Access 7 to 0 DATA[7:0] R Value Description 00h* DATA: This register is used to report the state dependent data requested by the D_S field of the PMCSR register. The value of this register is scaled by the value reported by the DS field of the PMCSR register. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 32 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 9. I2C-bus interface A simple I2C-bus interface is provided in the ISP1563 to read customized vendor ID, product ID and some other configuration bits from an external EEPROM. The I2C-bus interface is for bidirectional communication between ICs using two serial bus wires: SDA (data) and SCL (clock). Both lines are driven by open-drain circuits and must be connected to the positive supply voltage through pull-up resistors, when in use; otherwise, they must be connected to ground. 9.1 Protocol The I2C-bus protocol defines the following conditions: • • • • Bus free: both SDA and SCL are HIGH START: a HIGH-to-LOW transition on SDA, while SCL is HIGH STOP: a LOW-to-HIGH transition on SDA, while SCL is HIGH Data valid: after a START condition, data on SDA is stable during the HIGH period of SCL; data on SDA may only change while SCL is LOW. Each device on the I2C-bus has a unique slave address, which the master uses to select a device for access. The master starts a data transfer using a START condition and ends it by generating a STOP condition. Transfers can only be initiated when the bus is free. The receiver must acknowledge each byte by using a LOW level on SDA during the ninth clock pulse on SCL. For detailed information, refer to The I2C-bus Specification, Version 2.1. 9.2 Hardware connections The ISP1563 can be connected to an external EEPROM through the I2C-bus interface. The hardware connections are shown in Figure 5. Vaux(3V3) Vaux(3V3) RP RP SCL SDA SCL A0 SDA A1 I2C-bus ISP1563 USB HOST 24C01 A2 EEPROM or equivalent 004aaa512 Fig 5. EEPROM connection diagram. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 33 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller The slave address that the ISP1563 uses to access the EEPROM is 1010000b. Page mode addressing is not supported. Therefore, pins A0, A1 and A2 of the EEPROM must be connected to ground (logic 0). 9.3 Information loading from EEPROM Figure 6 shows the content of the EEPROM memory. If the EEPROM is not present, the default values of Device ID, Vendor ID, subsystem VID and subsystem DID assigned to Philips Semiconductors by PCI-SIG will be loaded. For default values, see Table 3. address 0 subsystem vendor ID (L) 1 subsystem vendor ID (H) 2 subsystem device ID (L) - OHCI 3 subsystem device ID (H) - OHCI 4 subsystem device ID (L) - EHCI 5 subsystem device ID (H) - EHCI 6 reserved - FFh 7 signature 15h - loads subsystem vendor ID, device ID 1Ah - loads default values defined by Philips Semiconductors 004aaa124 L = LOW; H = HIGH. Fig 6. Information loading from EEPROM. 10. Power management 10.1 PCI bus power states The PCI bus can be characterized by one of the four Power Management States: B0, B1, B2 and B3. B0 state (PCI clock = 33 MHz, PCI bus power = on) — This corresponds to the bus being fully operational. B1 state (PCI clock = intermittent clock operation mode, PCI bus power = on) — When a PCI bus is in B1, PCI VCC is still applied to all devices on the bus. No bus transactions, however, are allowed to take place on the bus. The B1 state indicates a perpetual idle state on the PCI bus. B2 state (PCI clock = stop, PCI bus power = on) — PCI VCC is still applied on the bus, but the clock is stopped and held in the LOW state. B3 state (PCI clock = stop, PCI bus power = off) — PCI VCC is removed from all devices on the PCI bus segment. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 34 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 10.2 USB bus states Reset state — When the USB bus is in the reset state, the USB system is stopped. Operational state — When the USB bus is in the active state, the USB system is operating normally. Suspend state — When the USB bus is in the suspend state, the USB system is stopped. Resume state — When the USB bus is in the resume state, the USB system is operating normally. 11. USB Host Controller registers Each Host Controller contains a set of on-chip operational registers that are mapped to un-cached memory of the system addressable space. This memory space must begin on a DWord (32-bit) boundary. The size of the allocated space is defined by the initial value in the Base Address register 0. HCDs must interact with these registers to implement USB and legacy support functionality. After the PCI enumeration driver finishes the PCI device configuration, the new base address of these memory-mapped operational registers is defined in BAR 0. The HCD can access these registers by using the address of base address value + offset. Table 41 contains a list of Host Controller registers. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 35 of 107 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Address [1] Philips Semiconductors 9397 750 14224 Product data sheet Table 41: USB Host Controller registers Reset value [2] OHCI register Reset value [2] EHCI register Func0 OHCI1 (2P) Func0 OHCI1 Func1 OHCI2 Func1 (1P) (2P) OHCI2 (1P) Func2 EHCI (4P) Func2 EHCI (2P) Rev. 01 — 14 July 2005 0000 0110h 0000 0110h 0000 0010h 0000 0010h CAPLENGTH/HCIVERSION 0100 0020h 0100 0020h 04h HcControl 0000 0000h 0000 0000h 0000 0000h 0000 0000h HCSPARAMS 000X 2294h [3] 000X 2192h [3] 08h HcCommandStatus 0000 0000h 0000 0000h 0000 0000h 0000 0000h HCCPARAMS 0000 0012h 0000 0012h 0Ch HcInterruptStatus 0000 0000h 0000 0000h 0000 0000h 0000 0000h HCSP-PORTROUTE1[31:0] 0000 1010h 0000 0010h 10h HcInterruptEnable 0000 0000h 0000 0000h 0000 0000h 0000 0000h HCSP-PORTROUTE2[59:32] 0000 0000h 0000 0000h 14h HcInterruptDisable 0000 0000h 0000 0000h 0000 0000h 0000 0000h reserved - - 18h HcHCCA 0000 0000h 0000 0000h 0000 0000h 0000 0000h reserved - - 1Ch HcPeriodCurrentED 0000 0000h 0000 0000h 0000 0000h 0000 0000h reserved - - 20h HcControlHeadED 0000 0000h 0000 0000h 0000 0000h 0000 0000h USBCMD 0008 0000h 0008 0000h 24h HcControlCurrentED 0000 0000h 0000 0000h 0000 0000h 0000 0000h USBSTS 0000 1000h 0000 1000h 28h HcBulkHeadED 0000 0000h 0000 0000h 0000 0000h 0000 0000h USBINTR 0000 0000h 0000 0000h 2Ch HcBulkCurrentED 0000 0000h 0000 0000h 0000 0000h 0000 0000h FRINDEX 0000 0000h 0000 0000h 30h HcDoneHead 0000 0000h 0000 0000h 0000 0000h 0000 0000h reserved - - 34h HcFmInterval 0000 2EDFh 0000 2EDFh 0000 2EDFh 0000 2EDFh PERIODICLISTBASE 0000 0000h 0000 0000h 38h HcFmRemaining 0000 0000h 0000 0000h 0000 0000h 0000 0000h ASYNCLISTADDR 0000 0000h 0000 0000h 3Ch HcFmNumber 0000 0000h 0000 0000h 0000 0000h 0000 0000h reserved - - 40h HcPeriodicStart 0000 0000h 0000 0000h 0000 0000h 0000 0000h reserved - - 44h HcLSThreshold 0000 0628h 0000 0628h 0000 0628h 0000 0628h reserved - - 48h HcRhDescriptorA FF00 0902h FF00 0901h FF00 0902h FF00 0901h reserved - - 4Ch HcRhDescriptorB 0006 0000h 0002 0000h 0006 0000h 0002 0000h reserved - - 50h HcRhStatus 0000 0000h 0000 0000h 0000 0000h 0000 0000h reserved - - 54h HcRhPortStatus[1] 0000 0000h 0000 0000h 0000 0000h 0000 0000h reserved - - 58h HcRhPortStatus[2] 0000 0000h - 0000 0000h - reserved - - 5Ch reserved - - - - reserved - - 60h reserved - - - - CONFIGFLAG 0000 0000h 0000 0000h 64h reserved - - - - PORTSC1 0000 2000h 0000 2000h 68h reserved - - - - PORTSC2 0000 2000h 0000 2000h 6Ch reserved - - - - PORTSC3 0000 2000h - ISP1563 HcRevision HS USB PCI Host Controller 36 of 107 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. 00h xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx USB Host Controller registers…continued Address [1] OHCI register Reset value [2] Reset value [2] EHCI register Func0 OHCI1 (2P) Func0 OHCI1 Func1 OHCI2 Func1 (1P) (2P) OHCI2 (1P) Philips Semiconductors 9397 750 14224 Product data sheet Table 41: Func2 EHCI (4P) Func2 EHCI (2P) 70h reserved - - - - PORTSC4 0000 2000h - 100h HceControl 0000 0000h 0000 0000h 0000 0000h 0000 0000h - - - 104h HceInput 0000 0000h 0000 0000h 0000 0000h 0000 0000h - - - 108h HceOutput 0000 0000h 0000 0000h 0000 0000h 0000 0000h - - - 10Ch HceStatus 0000 0000h 0000 0000h 0000 0000h 0000 0000h - - - [1] The number of downstream ports, 2 or 4, is configured using pin SEL2PORTS. [2] Reset values that are highlighted, for example, 0, are the ISP1563 implementation-specific reset values; and reset values that are not highlighted, for example, 0, are compliant with OHCI and EHCI specifications. [3] See Section 11.1.2. Rev. 01 — 14 July 2005 ISP1563 HS USB PCI Host Controller 37 of 107 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. ISP1563 Philips Semiconductors HS USB PCI Host Controller For the OHCI Host Controller, these registers are divided into two types: one set of operational registers for the USB operation and one set of legacy support registers for the legacy keyboard and mouse operation. For the Enhanced Host Controller, there are two types of registers: one set of read-only capability registers and one set of read and write operational registers. 11.1 OHCI USB Host Controller operational registers OHCI HCDs need to communicate with these registers to implement USB data transfers. Based on their functions, these registers are classified into four partitions: • • • • Control and Status Memory Pointer Frame Counter Root Hub. 11.1.1 HcRevision register Table 42: HcRevision - Host Controller Revision register bit allocation Address: Value read from func0 or func1 of address 10h + 00h Bit 31 30 29 28 Symbol 27 26 25 24 reserved Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 23 22 21 20 19 18 17 16 Symbol reserved Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 15 14 13 12 11 10 9 8 Symbol reserved L Reset 0 0 0 0 0 0 0 X [1] Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 Symbol REV[7:0] Reset 0 0 0 1 0 0 0 0 Access R R R R R R R R [1] X is 1 for OHCI1 (2P) and OHCI1 (1P); X is 0 for OHCI2 (2P) and OHCI2 (1P). 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 38 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 43: HcRevision - Host Controller Revision register bit description Address: Value read from func0 or func1 of address 10h + 00h Bit Symbol Description 31 to 9 reserved - 8 L Legacy: 0 — Does not support legacy devices 1 — Supports legacy keyboard and mouse. 7 to 0 REV[7:0] Revision: This read-only field contains the BCD representation of the version of the HCI specification that is implemented by this Host Controller. For example, a value of 11h corresponds to version 1.1. All of the Host Controller implementations that are compliant with this specification must have a value of 10h. 11.1.2 HcControl register This register defines the operating modes for the Host Controller. All the fields in this register, except for HCFS and RWC, are modified only by the HCD. The bit allocation is given in Table 44. Table 44: HcControl - Host Controller Control register bit allocation Address: Value read from func0 or func1 of address 10h + 04h Bit 31 30 29 28 Symbol Reset Access Bit Access Bit Access Bit Access [1] 24 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 reserved [1] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved [1] RWE RWC IR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Symbol Reset 25 0 Symbol Reset 26 0 Symbol Reset 27 reserved [1] BLE CLE IE PLE 0 HCFS[1:0] 0 0 0 0 0 0 CBSR[1:0] 0 R/W R/W R/W R/W R/W R/W R/W R/W The reserved bits should always be written with the reset value. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 39 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 45: HcControl - Host Controller Control register bit description Address: Value read from func0 or func1 of address 10h + 04h Bit Symbol Description 31 to 11 reserved - 10 RWE Remote Wake-up Enable: This bit is used by the HCD to enable or disable the remote wake-up feature on detecting upstream resume signaling. When this bit and RD (bit 3 in the HcInterruptStatus register) are set, a remote wake-up is signaled to the host system. Setting this bit has no impact on the generation of hardware interrupt. 9 RWC Remote Wake-up Connected: This bit indicates whether the Host Controller supports remote wake-up signaling. If remote wake-up is supported and used by the system, it is the responsibility of the system firmware to set this bit during POST. The Host Controller clears the bit on a hardware reset but does not alter it on a software reset. Remote wake-up signaling of the host system is host-bus-specific and is not described in this specification. 8 IR Interrupt Routing: This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. If clear, all interrupts are routed to the normal host bus interrupt mechanism. If set, interrupts are routed to the System Management Interrupt. The HCD clears this bit on a hardware reset, but it does not alter this bit on a software reset. The HCD uses this bit as a tag to indicate the ownership of the Host Controller. 7 to 6 HCFS[1:0] Host Controller Functional State for USB: 00b — USBRESET 01b — USBRESUME 10b — USBOPERATIONAL 11b — USBSUSPEND A transition to USBOPERATIONAL from another state causes SOF generation to begin 1 ms later. The HCD may determine whether the Host Controller has begun sending SOFs by reading SF (bit 2 of HcInterruptStatus). This field may be changed by the Host Controller only when in the USBSUSPEND state. The Host Controller may move from the USBSUSPEND state to the USBRESUME state after detecting the resume signaling from a downstream port. The Host Controller enters USBSUSPEND after a software reset; it enters USBRESET after a hardware reset. The latter also resets the Root Hub and asserts subsequent reset signaling to downstream ports. 5 BLE Bulk List Enable: This bit is set to enable the processing of the bulk list in the next Frame. If cleared by the HCD, processing of the bulk list does not occur after the next SOF. The Host Controller checks this bit whenever it wants to process the list. When disabled, the HCD may modify the list. If HcBulkCurrentED is pointing to an Endpoint Descriptor (ED) to be removed, the HCD must advance the pointer by updating HcBulkCurrentED before re-enabling processing of the list. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 40 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 45: HcControl - Host Controller Control register bit description…continued Address: Value read from func0 or func1 of address 10h + 04h Bit Symbol Description 4 CLE Control List Enable: This bit is set to enable the processing of the control list in the next frame. If cleared by the HCD, processing of the control list does not occur after the next SOF. The Host Controller must check this bit whenever it wants to process the list. When disabled, the HCD may modify the list. If HcControlCurrentED is pointing to an ED to be removed, the HCD must advance the pointer by updating HcControlCurrentED before re-enabling processing of the list. 3 IE Isochronous Enable: This bit is used by the HCD to enable or disable processing of isochronous EDs. While processing the periodic list in a frame, the Host Controller checks the status of this bit when it finds an isochronous ED (F = 1). If set (enabled), the Host Controller continues processing the EDs. If cleared (disabled), the Host Controller halts processing of the periodic list (which now contains only isochronous EDs) and begins processing the bulk or control lists. Setting this bit is guaranteed to take effect in the next frame and not the current frame. 2 PLE Periodic List Enable: This bit is set to enable the processing of the periodic list in the next frame. If cleared by the HCD, processing of the periodic list does not occur after the next SOF. The Host Controller must check this bit before it starts processing the list. 1 to 0 CBSR[1:0] Control Bulk Service Ratio: This specifies the service ratio of control EDs over bulk EDs. Before processing any of the nonperiodic lists, the Host Controller must compare the ratio specified with its internal count on how many nonempty control EDs are processed, in determining whether to continue serving another control ED or switch to bulk EDs. The internal count must be retained when crossing the frame boundary. After a reset, the HCD is responsible to restore this value. 00b — 1 : 1 01b — 2 : 1 10b — 3 : 1 11b — 4 : 1. 11.1.3 HcCommandStatus register The HcCommandStatus register is used by the Host Controller to receive commands issued by the HCD. It also reflects the current status of the Host Controller. To the HCD, it appears as a ‘write to set’ register. The Host Controller must ensure that bits written as logic 1 become set in the register while bits written as logic 0 remain unchanged in the register. The HCD may issue multiple distinct commands to the Host Controller without concern for corrupting previously issued commands. The HCD has normal read access to all bits. The SOC[1:0] field (bits 17 and 16 in the HcCommandStatus register) indicates the number of frames with which the Host Controller has detected the scheduling overrun error. This occurs when the periodic list does not complete before EOF. When a scheduling overrun error is detected, the Host Controller increments the counter and sets SO (bit 0 in the HcInterruptStatus register). Table 46 shows the bit allocation of the HcCommandStatus register. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 41 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 46: HcCommandStatus - Host Controller Command Status register bit allocation Address: Value read from func0 or func1 of address 10h + 08h Bit 31 30 29 28 Symbol Reset Access Bit Access Bit Access Bit Access [1] 24 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 reserved [1] SOC[1:0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved [1] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 reserved [1] OCR BLF CLF HCR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Symbol Reset 25 0 Symbol Reset 26 0 Symbol Reset 27 reserved [1] The reserved bits should always be written with the reset value. Table 47: HcCommandStatus - Host Controller Command Status register bit description Address: Value read from func0 or func1 of address 10h + 08h Bit Symbol Description 31 to 18 reserved - 17 to 16 SOC[1:0] Scheduling Overrun Count: The bit is incremented on each scheduling overrun error. It is initialized to 00b and wraps around at 11b. It must be incremented when a scheduling overrun is detected, even if SO (bit 0 in HcInterruptStatus) is already set. This is used by the HCD to monitor any persistent scheduling problems. 15 to 4 reserved - 3 OCR Ownership Change Request: This bit is set by an OS HCD to request a change of control of the Host Controller. When set, the Host Controller must set OC (bit 30 in HcInterruptStatus). After the changeover, this bit is cleared and remains so until the next request from the OS HCD. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 42 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 47: HcCommandStatus - Host Controller Command Status register bit description…continued Bit Symbol Description 2 BLF Bulk List Filled: This bit is used to indicate whether there are any Transfer Descriptors (TDs) on the bulk list. It is set by the HCD whenever it adds a TD to an ED in the bulk list. When the Host Controller begins to process the head of the bulk list, it checks Bulk-Filled (BF). If BLF is logic 0, the Host Controller does not need to process the bulk list. If BLF is logic 1, the Host Controller needs to start processing the bulk list and set BF to logic 0. If the Host Controller finds a TD on the list, then the Host Controller needs to set BLF to logic 1, causing the bulk list processing to continue. If no TD is found on the bulk list, and if the HCD does not set BLF, then BLF is still logic 0 when the Host Controller completes processing the bulk list and the bulk list processing stops. 1 CLF Control List Filled: This bit is used to indicate whether there are any TDs on the control list. It is set by the HCD whenever it adds a TD to an ED in the control list. When the Host Controller begins to process the head of the control list, it checks CLF. If CLF is logic 0, the Host Controller does not need to process the control list. If Control-Filled (CF) is logic 1, the Host Controller needs to start processing the control list and set CLF to logic 0. If the Host Controller finds a TD on the list, then the Host Controller needs to set CLF to logic 1, causing the control list processing to continue. If no TD is found on the control list, and if the HCD does not set CLF, then CLF is still logic 0 when the Host Controller completes processing the control list and the control list processing stops. 0 HCR Host Controller Reset: This bit is set by the HCD to initiate a software reset of the Host Controller. Regardless of the functional state of the Host Controller, it moves to the USBSUSPEND state in which most of the operational registers are reset, except those stated otherwise; for example, IR (bit 8) in the HcControl register, and no host bus accesses are allowed. This bit is cleared by the Host Controller on completing the reset operation. The reset operation must be completed within 10 µs. This bit, when set, should not cause a reset to the Root Hub and no subsequent reset signaling should be asserted to its downstream ports. 11.1.4 HcInterruptStatus register This is a 4 B register that provides the status of the events that cause hardware interrupts. The bit allocation of the register is given in Table 48. When an event occurs, the Host Controller sets the corresponding bit in this register. When a bit becomes set, a hardware interrupt is generated, if the interrupt is enabled in the HcInterruptEnable register (see Table 50) and the MIE (Master Interrupt Enable) bit is set. The HCD may clear specific bits in this register by writing logic 1 to the bit positions to be cleared. The HCD may not set any of these bits. The Host Controller does not clear the bit. Table 48: HcInterruptStatus - Host Controller Interrupt Status register bit allocation Address: Value read from func0 or func1 of address 10h + 0Ch Bit Symbol 31 30 29 28 reserved [1] OC 0 0 0 0 R/W R/W R/W R/W Reset Access 26 25 24 0 0 0 0 R/W R/W R/W R/W reserved [1] 9397 750 14224 Product data sheet 27 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 43 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Bit 23 22 21 20 Symbol Reset Access Bit 17 16 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 Symbol 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 reserved [1] RHSC FNO UE RD SF WDH SO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Access Bit Reset Access [1] 18 reserved [1] Reset Symbol 19 reserved [1] The reserved bits should always be written with the reset value. Table 49: HcInterruptStatus - Host Controller Interrupt Status register bit description Address: Value read from func0 or func1 of address 10h + 0Ch Bit Symbol Description 31 reserved - 30 OC Ownership Change: This bit is set by the Host Controller when the HCD sets OCR (bit 3) in the HcCommandStatus register. This event, when unmasked, will always immediately generate a System Management Interrupt (SMI). This bit is forced to logic 0 when the SMI# pin is not implemented. 29 to 7 reserved - 6 RHSC Root Hub Status Change: This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed. 5 FNO Frame Number Overflow: This bit is set when the MSB of HcFmNumber (bit 15) changes value, or after HccaFrameNumber is updated. 4 UE Unrecoverable Error: This bit is set when the Host Controller detects a system error not related to USB. The Host Controller should not proceed with any processing nor signaling before the system error is corrected. The HCD clears this bit after the Host Controller is reset. 3 RD Resume Detected: This bit is set when the Host Controller detects that a device on the USB is asserting resume signaling. This bit is set by the transition from no resume signaling to resume signaling. This bit is not set when the HCD sets the USBRESUME state. 2 SF Start-of-Frame: At the start of each frame, this bit is set by the Host Controller and an SOF token is generated at the same time. 1 WDH Write-back Done Head: This bit is immediately set after the Host Controller has written HcDoneHead to HccaDoneHead. Further, updates of HccaDoneHead occur only after this bit is cleared. The HCD should only clear this bit after it has saved the content of HccaDoneHead. 0 SO Scheduling Overrun: This bit is set when USB schedules for current frame overruns and after the update of HccaFrameNumber. A scheduling overrun increments the SOC[1:0] field (bits 17 to 16 of HcCommandStatus). 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 44 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 11.1.5 HcInterruptEnable register Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control which events generate a hardware interrupt. A hardware interrupt is requested on the host bus if the following conditions occur: • A bit is set in the HcInterruptStatus register. • The corresponding bit in the HcInterruptEnable register is set. • The MIE (Master Interrupt Enable) bit is set. Writing logic 1 to a bit in this register sets the corresponding bit, whereas writing logic 0 to a bit in this register leaves the corresponding bit unchanged. On a read, the current value of this register is returned. The bit allocation is given in Table 50. Table 50: HcInterruptEnable - Host Controller Interrupt Enable register bit allocation Address: Value read from func0 or func1 of address 10h + 10h Bit 31 Symbol Reset Access Bit 30 29 28 25 24 MIE OC 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 Symbol Access Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved [1] Symbol Reset 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 reserved [1] RHSC FNO UE RD SF WDH SO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Access Bit Reset Access [1] 26 reserved [1] reserved [1] Reset Symbol 27 The reserved bits should always be written with the reset value. Table 51: HcInterruptEnable - Host Controller Interrupt Enable register bit description Address: Value read from func0 or func1 of address 10h + 10h Bit Symbol Description 31 MIE Master Interrupt Enable: 0 — Ignore 1 — Enables interrupt generation by events specified in other bits of this register. 30 OC Ownership Change: 0 — Ignore 1 — Enables interrupt generation because of Ownership Change. 29 to 7 reserved - 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 45 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 51: HcInterruptEnable - Host Controller Interrupt Enable register bit description…continued Bit Symbol Description 6 RHSC Root Hub Status Change: 0 — Ignore 1 — Enables interrupt generation because of Root Hub Status Change. 5 FNO Frame Number Overflow: 0 — Ignore 1 — Enables interrupt generation because of Frame Number Overflow. 4 UE Unrecoverable Error: 0 — Ignore 1 — Enables interrupt generation because of Unrecoverable Error. 3 RD Resume Detect: 0 — Ignore 1 — Enables interrupt generation because of Resume Detect. 2 SF Start-of-Frame: 0 — Ignore 1 — Enables interrupt generation because of Start-of-Frame. 1 WDH Write-back Done Head: 0 — Ignore 1 — Enables interrupt generation because of HcDoneHead Write-back. 0 SO Scheduling Overrun: 0 — Ignore 1 — Enables interrupt generation because of Scheduling Overrun. 11.1.6 HcInterruptDisable register Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the HcInterruptEnable register. Therefore, writing logic 1 to a bit in this register clears the corresponding bit in the HcInterruptEnable register, whereas writing logic 0 to a bit in this register leaves the corresponding bit in the HcInterruptEnable register unchanged. On a read, the current value of the HcInterruptEnable register is returned. The register contains 4 B, and the bit allocation is given in Table 52. Table 52: HcInterruptDisable - Host Controller Interrupt Disable register bit allocation Address: Value read from func0 or func1 of address 10h + 14h Bit Symbol Reset Access Bit 31 MIE 30 29 28 Access OC 25 24 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 reserved [1] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 9397 750 14224 Product data sheet 26 reserved [1] Symbol Reset 27 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 46 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Bit 15 14 13 12 Symbol Reset 9 8 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 reserved [1] RHSC FNO UE RD SF WDH SO 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Reset Access [1] 10 0 Access Symbol 11 reserved [1] The reserved bits should always be written with the reset value. Table 53: HcInterruptDisable - Host Controller Interrupt Disable register bit description Address: Value read from func0 or func1 of address 10h + 14h Bit Symbol Description 31 MIE Master Interrupt Enable: 0 — Ignore 1 — Disables interrupt generation because of events specified in other bits of this register. This field is set after a hardware or software reset. Interrupts are disabled. 30 OC Ownership Change: 0 — Ignore 1 — Disables interrupt generation because of Ownership Change. 29 to 7 reserved - 6 RHSC Root Hub Status Change: 0 — Ignore 1 — Disables interrupt generation because of Root Hub Status Change. 5 FNO Frame Number Overflow: 0 — Ignore 1 — Disables interrupt generation because of Frame Number Overflow. 4 UE Unrecoverable Error: 0 — Ignore 1 — Disables interrupt generation because of Unrecoverable Error. 3 RD Resume Detect: 0 — Ignore 1 — Disables interrupt generation because of Resume Detect. 2 SF Start-of-Frame: 0 — Ignore 1 — Disables interrupt generation because of Start-of-Frame. 1 WDH Write-back Done Head: 0 — Ignore 1 — Disables interrupt generation because of HcDoneHead Write-back. 0 SO Scheduling Overrun: 0 — Ignore 1 — Disables interrupt generation because of Scheduling Overrun. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 47 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 11.1.7 HcHCCA register The HcHCCA register contains the physical address of the Host Controller Communication Area (HCCA). The bit allocation is given in Table 54. The HCD determines the alignment restrictions by writing all 1s to HcHCCA and reading the content of HcHCCA. The alignment is evaluated by examining the number of zeroes in the lower order bits. The minimum alignment is 256 B; therefore, bits 0 through 7 will always return logic 0 when read. This area is used to hold the control structures and the Interrupt table that are accessed by both the Host Controller and the HCD. Table 54: HcHCCA - Host Controller Communication Area register bit allocation Address: Value read from func0 or func1 of address 10h + 18h Bit 31 30 29 28 Symbol 26 25 24 HCCA[23:16] Reset Access Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 Symbol HCCA[15:8] Reset Access Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 Symbol HCCA[7:0] Reset Access Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 reserved [1] Symbol Reset Access [1] 27 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The reserved bits should always be written with the reset value. Table 55: HcHCCA - Host Controller Communication Area register bit description Address: Value read from func0 or func1 of address 10h + 18h Bit Symbol Description 31 to 8 HCCA[23:0] Host Controller Communication Area Base Address: This is the base address of the HCCA. 7 to 0 reserved - 11.1.8 HcPeriodCurrentED register The HcPeriodCurrentED register contains the physical address of the current isochronous or interrupt ED. Table 56 shows the bit allocation of the register. Table 56: HcPeriodCurrentED - Host Controller Period Current Endpoint Descriptor register bit allocation Address: Value read from func0 or func1 of address 10h + 1Ch Bit 31 30 29 28 Reset 0 0 0 0 Access R R R R Symbol 26 25 24 0 0 0 0 R R R R PCED[27:20] 9397 750 14224 Product data sheet 27 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 48 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Bit 23 22 21 20 18 17 16 Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 15 14 13 12 11 10 9 8 Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Symbol 19 PCED[19:12] Symbol PCED[11:4] Symbol PCED[3:0] reserved Table 57: HcPeriodCurrentED - Host Controller Period Current Endpoint Descriptor register bit description Address: Value read from func0 or func1 of address 10h + 1Ch Bit Symbol Description 31 to 4 PCED[27:0] Period Current ED: This is used by the Host Controller to point to the head of one of the periodic lists that must be processed in the current frame. The content of this register is updated by the Host Controller after a periodic ED is processed. The HCD may read the content in determining which ED is being processed at the time of reading. 3 to 0 reserved - 11.1.9 HcControlHeadED register The HcControlHeadED register contains the physical address of the first ED of the control list. The bit allocation is given in Table 58. Table 58: HcControlHeadED - Host Controller Control Head Endpoint Descriptor register bit allocation Address: Value read from func0 or func1 of address 10h + 20h Bit 31 30 29 Symbol 28 27 26 25 24 CHED[27:20] Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 23 22 21 20 19 18 17 16 Symbol CHED[19:12] Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 15 14 13 12 11 10 9 8 Symbol CHED[11:4] Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 Symbol CHED[3:0] reserved Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 49 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 59: HcControlHeadED - Host Controller Control Head Endpoint Descriptor register bit description Address: Value read from func0 or func1 of address 10h + 20h Bit Symbol Description 31 to 4 CHED[27:0] Control Head ED: The Host Controller traverses the control list, starting with the HcControlHeadED pointer. The content is loaded from HCCA during the initialization of the Host Controller. 3 to 0 reserved - 11.1.10 HcControlCurrentED register The HcControlCurrentED register contains the physical address of the current ED of the control list. The bit allocation is given in Table 60. Table 60: HcControlCurrentED - Host Controller Control Current Endpoint Descriptor register bit allocation Address: Value read from func0 or func1 of address 10h + 24h Bit 31 30 29 28 Symbol 27 26 25 24 CCED[27:20] Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 23 22 21 20 19 18 17 16 Symbol CCED[19:12] Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 15 14 13 12 11 10 9 8 Symbol CCED[11:4] Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 Symbol CCED[3:0] reserved Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Table 61: HcControlCurrentED - Host Controller Control Current Endpoint Descriptor register bit description Address: Value read from func0 or func1 of address 10h + 24h Bit Symbol Description 31 to 4 CCED[27:0] Control Current ED: This pointer is advanced to the next ED after serving the current ED. The Host Controller needs to continue processing the list from where it was left in the last frame. When it reaches the end of the control list, the Host Controller checks CLF (bit 1 of HcCommandStatus). If set, it copies the content of HcControlHeadED to HcControlCurrentED and clears the bit. If not set, it does nothing. The HCD is allowed to modify this register only when CLE (bit 4 of HcControl) is cleared. When set, the HCD only reads the instantaneous value of this register. Initially, this is set to logic 0 to indicate the end of the control list. 3 to 0 reserved - 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 50 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 11.1.11 HcBulkHeadED register This is a four-byte register, and the bit allocation is given in Table 62. The register contains the physical address of the first ED of the bulk list. Table 62: HcBulkHeadED - Host Controller Bulk Head Endpoint Descriptor register bit allocation Address: Value read from func0 or func1 of address 10h + 28h Bit 31 30 29 28 Symbol 26 25 24 BHED[27:20] Reset Access Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 Symbol BHED[19:12] Reset Access Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 Symbol BHED[11:4] Reset Access Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Symbol reserved [1] BHED[3:0] Reset Access [1] 27 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The reserved bits should always be written with the reset value. Table 63: HcBulkHeadED - Host Controller Bulk Head Endpoint Descriptor register bit description Address: Value read from func0 or func1 of address 10h + 28h Bit Symbol Description 31 to 4 BHED[27:0] Bulk Head ED: The Host Controller traverses the bulk list starting with the HcBulkHeadED pointer. The content is loaded from HCCA during the initialization of the Host Controller. 3 to 0 reserved - 11.1.12 HcBulkCurrentED register This register contains the physical address of the current endpoint of the bulk list. The endpoints are ordered according to their insertion to the list because the bulk list must be served in a round-robin fashion. The bit allocation is given in Table 64. Table 64: HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit allocation Address: Value read from func0 or func1 of address 10h + 2Ch Bit 31 30 29 28 0 0 0 0 R/W R/W R/W R/W Symbol Reset Access 26 25 24 0 0 0 0 R/W R/W R/W R/W BCED[27:20] 9397 750 14224 Product data sheet 27 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 51 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Bit 23 22 21 20 18 17 16 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Symbol BCED[19:12] Reset Access Bit Symbol BCED[11:4] Reset Access Bit Symbol reserved [1] BCED[3:0] Reset Access [1] 19 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The reserved bits should always be written with the reset value. Table 65: HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit description Address: Value read from func0 or func1 of address 10h + 2Ch Bit Symbol 31 to 4 BCED[27:0] Bulk Current ED: This is advanced to the next ED after the Host Controller has served the current ED. The Host Controller continues processing the list from where it left off in the last frame. When it reaches the end of the bulk list, the Host Controller checks CLF (bit 1 of HcCommandStatus). If the CLF bit is not set, nothing is done. If the CLF bit is set, it copies the content of HcBulkHeadED to HcBulkCurrentED and clears the CLF bit. The HCD can modify this register only when BLE (bit 5 in the HcControl register) is cleared. When HcControl is set, the HCD reads the instantaneous value of this register. This is initially set to logic 0 to indicate the end of the bulk list. Description 3 to 0 reserved - 11.1.13 HcDoneHead register The HcDoneHead register contains the physical address of the last completed TD that was added to the Done queue. In normal operation, the HCD need not read this register because its content is periodically written to the HCCA. Table 66 contains the bit allocation of the register. Table 66: HcDoneHead - Host Controller Done Head register bit allocation Address: Value read from func0 or func1 of address 10h + 30h Bit 31 30 29 28 Symbol Reset Access Bit Access 25 24 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 DH[19:12] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 9397 750 14224 Product data sheet 26 0 Symbol Reset 27 DH[27:20] © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 52 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Bit 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Symbol DH[11:4] Reset Access Bit Symbol DH[3:0] Reset Access [1] reserved [1] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The reserved bits should always be written with the reset value. Table 67: HcDoneHead - Host Controller Done Head register bit description Address: Value read from func0 or func1 of address 10h + 30h Bit Symbol Description 31 to 4 DH[27:0] Done Head: When a TD is completed, the Host Controller writes the content of HcDoneHead to the NextTD field of the TD. The Host Controller then overwrites the content of HcDoneHead with the address of this TD. This is set to logic 0 whenever the Host Controller writes the content of this register to HCCA. 3 to 0 reserved - 11.1.14 HcFmInterval register This register contains a 14-bit value that indicates the bit time interval in a frame, that is, between two consecutive SOFs, and a 15-bit value indicating the full-speed maximum packet size that the Host Controller may transmit or receive, without causing a scheduling overrun. The HCD may carry out minor adjustment on FI (Frame Interval) by writing a new value over the present at each SOF. This provides the possibility for the Host Controller to synchronize with an external clocking resource and to adjust any unknown local clock offset. The bit allocation of the register is given in Table 68. Table 68: HcFmInterval - Host Controller Frame Interval register bit allocation Address: Value read from func0 or func1 of address 10h + 34h Bit 31 Symbol FIT Reset Access Bit 30 29 28 Access Bit Access 24 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 FSMPS[7:0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved [1] FI[13:8] 0 0 1 0 1 1 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 9397 750 14224 Product data sheet 25 0 Symbol Reset 26 0 Symbol Reset 27 FSMPS[14:8] © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 53 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Bit 7 6 5 4 3 2 1 0 1 1 0 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Symbol FI[7:0] Reset Access [1] The reserved bits should always be written with the reset value. Table 69: HcFmInterval - Host Controller Frame Interval register bit description Address: Value read from func0 or func1 of address 10h + 34h Bit Symbol Description 31 FIT Frame Interval Toggle: The HCD toggles this bit whenever it loads a new value to Frame Interval. 30 to 16 FSMPS[14:0] FS Largest Data Packet: This field specifies the value that is loaded into the largest data packet counter at the beginning of each frame. The counter value represents the largest amount of data in bits that can be sent or received by the Host Controller in a single transaction at any given time, without causing a scheduling overrun. The field value is calculated by the HCD. 15 to 14 reserved - 13 to 0 FI[13:0] Frame Interval: This specifies the interval between two consecutive SOFs in bit times. The nominal value is set to 11,999. The HCD should store the current value of this field before resetting the Host Controller to reset this field to its nominal value. The HCD can then restore the stored value on completing the reset sequence. 11.1.15 HcFmRemaining register The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in the current frame. Table 70 contains the bit allocation of this 4 B register. Table 70: HcFmRemaining - Host Controller Frame Remaining register bit allocation Address: Value read from func0 or func1 of address 10h + 38h Bit Symbol Reset Access Bit 31 30 29 28 Access Bit FRT Access 24 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 reserved [1] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved [1] FR[13:8] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 9397 750 14224 Product data sheet 25 0 Symbol Reset 26 reserved [1] Symbol Reset 27 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 54 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Bit 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Symbol FR[7:0] Reset Access [1] The reserved bits should always be written with the reset value. Table 71: HcFmRemaining - Host Controller Frame Remaining register bit description Address: Value read from func0 or func1 of address 10h + 38h Bit Symbol Description 31 FRT Frame Remaining Toggle: This bit is loaded from FIT (bit 31 of HcFmInterval) whenever FR[13:0] reaches 0. This bit is used by the HCD for the synchronization between FI[13:0] (bits 13 to 0 of HcFmInterval) and FR[13:0]. 30 to 14 reserved - 13 to 0 Frame Remaining: This counter is decremented at each bit time. When it reaches 0, it is reset by loading the FI[13:0] value specified in HcFmInterval at the next bit time boundary. When entering the USBOPERATIONAL state, the Host Controller reloads the content with FI[13:0] of HcFmInterval and uses the updated value from the next SOF. FR[13:0] 11.1.16 HcFmNumber register This register is a 16-bit counter, and the bit allocation is given in Table 72. It provides a timing reference among events happening in the Host Controller and the HCD. The HCD may use the 16-bit value specified in this register and generate a 32-bit frame number, without requiring frequent access to the register. Table 72: HcFmNumber - Host Controller Frame Number register bit allocation Address: Value read from func0 or func1 of address 10h + 3Ch Bit 31 30 29 28 Symbol Reset Access Bit Access Bit Access Bit Access [1] 24 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 reserved [1] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved [1] FN[13:8] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Symbol Reset 25 0 Symbol Reset 26 R/W Symbol Reset 27 reserved [1] FN[7:0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The reserved bits should always be written with the reset value. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 55 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 73: HcFmNumber - Host Controller Frame Number register bit description Address: Value read from func0 or func1 of address 10h + 3Ch Bit Symbol Description 31 to 14 reserved - 13 to 0 FN[13:0] Frame Number: Incremented when HcFmRemaining is reloaded. It must be rolled over to 0h after FFFFh. Automatically incremented when entering the USBOPERATIONAL state. The content is written to HCCA after the Host Controller has incremented Frame Number at each frame boundary and sent an SOF but before the Host Controller reads the first ED in that frame. After writing to HCCA, the Host Controller sets SF (bit 2 of HcInterruptStatus). 11.1.17 HcPeriodicStart register This register has a 14-bit programmable value that determines when is the earliest time for the Host Controller to start processing the periodic list. For bit allocation, see Table 74. Table 74: HcPeriodicStart - Host Controller Periodic Start register bit allocation Address: Value read from func0 or func1 of address 10h + 40h Bit 31 30 29 28 Symbol Reset Access Bit Access Bit Access Bit Access [1] 24 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 reserved [1] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved [1] P_S[13:8] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Symbol Reset 25 0 Symbol Reset 26 0 Symbol Reset 27 reserved [1] P_S[7:0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The reserved bits should always be written with the reset value. Table 75: HcPeriodicStart - Host Controller Periodic Start register bit description Address: Value read from func0 or func1 of address 10h + 40h Bit Symbol Description 31 to 14 reserved - 13 to 0 P_S[13:0] Periodic_Start: After a hardware reset, this field is cleared. It is then set by the HCD during the Host Controller initialization. The value is roughly calculated as 10 % of HcFmInterval. A typical value is 3E67h. When HcFmRemaining reaches the value specified, processing of the periodic lists have priority over control or bulk processing. The Host Controller, therefore, starts processing the interrupt list after completing the current control or bulk transaction that is in progress. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 56 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 11.1.18 HcLSThreshold register This register contains an 11-bit value used by the Host Controller to determine whether to commit to the transfer of a maximum of 8 B low-speed packet before EOF. Neither the Host Controller nor the HCD can change this value. For bit allocation, see Table 76. Table 76: HcLSThreshold - Host Controller LS Threshold register bit allocation Address: Value read from func0 or func1 of address 10h + 44h Bit 31 30 29 28 Reset Access Bit 26 25 24 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 reserved [1] Symbol Reset Access Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved [1] Symbol Reset Access Bit LST[11:8] 0 0 0 0 0 1 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Symbol LST[7:0] Reset Access [1] 27 reserved [1] Symbol 0 0 1 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The reserved bits should always be written with the reset value. Table 77: HcLSThreshold - Host Controller LS Threshold register bit description Address: Value read from func0 or func1 of address 10h + 44h Bit Symbol Description 31 to 12 reserved - 11 to 0 LST[11:0] LS Threshold: This field contains a value that is compared to the FR[13:0] field, before initiating a low-speed transaction. The transaction is started only if FR ≥ this field. The value is calculated by the HCD, considering the transmission and setup overhead. 11.1.19 HcRhDescriptorA register This register is the first of two registers describing the characteristics of the Root Hub. Reset values are implementation-specific. Table 78 shows the bit allocation of the HcRhDescriptorA register. Table 78: HcRhDescriptorA - Host Controller Root Hub Descriptor A register bit allocation Address: Value read from func0 or func1 of address 10h + 48h Bit 31 30 29 Symbol Reset Access 28 26 25 24 POTPGT[7:0] 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 9397 750 14224 Product data sheet 27 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 57 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Bit 23 22 21 20 Symbol Reset Access Bit 19 18 17 16 reserved [1] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved [1] NOCP OCPM DT NPS PSM 0 0 0 0 1 0 0 1 R/W R/W R/W R/W R/W R R/W R/W 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 X [2] X [3] Access R R R R R R R R Symbol Reset Access Bit Symbol NDP[7:0] [1] The reserved bits should always be written with the reset value. [2] X is 1 for OHCI1 (2P) and OHCI2 (2P); X is 0 for OHCI1 (1P) and OHCI2 (1P). [3] X is 0 for OHCI1 (2P) and OHCI2 (2P); X is 1 for OHCI1 (1P) and OHCI2 (1P). Table 79: HcRhDescriptorA - Host Controller Root Hub Descriptor A register bit description Address: Value read from func0 or func1 of address 10h + 48h Bit Symbol Description 31 to 24 POTPGT Power On To Power Good Time: This byte specifies the duration the HCD [7:0] must wait before accessing a powered-on port of the Root Hub. It is implementation-specific. The unit of time is 2 ms. The duration is calculated as POTPGT × 2 ms. 23 to 13 reserved - 12 No Overcurrent Protection: This bit describes how the overcurrent status for Root Hub ports are reported. When this bit is cleared, the OCPM bit specifies global or per-port reporting. NOCP 0 — Overcurrent status is collectively reported for all downstream ports 1 — No overcurrent protection supported. 11 OCPM Overcurrent Protection Mode: This bit describes how the overcurrent status for Root Hub ports are reported. At reset, this fields reflects the same mode as Power Switching Mode. This field is valid only if the NOCP bit is cleared. 0 — Overcurrent status is collectively reported for all downstream ports 1 — Overcurrent status is reported on a per-port basis. 10 DT Device Type: This bit specifies that the Root Hub is not a compound device. The Root Hub is not permitted to be a compound device. This field should always read logic 0. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 58 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 79: HcRhDescriptorA - Host Controller Root Hub Descriptor A register bit description…continued Address: Value read from func0 or func1 of address 10h + 48h Bit Symbol Description 9 NPS No Power Switching: This bit is used to specify whether power switching is supported or ports are always powered. It is implementation-specific. When this bit is cleared, the PSM bit specifies global or per-port switching. 0 — Ports are power switched 1 — Ports are always powered on when the Host Controller is powered on. 8 PSM Power Switching Mode: This bit is used to specify how the power switching of Root Hub ports is controlled. It is implementation-specific. This field is valid only if the NPS bit is cleared. 0 — All ports are powered at the same time. 1 — Each port is individually powered. This mode allows port power to be controlled by either the global switch or per-port switching. If the PPCM (Port Power Control Mask) bit is set, the port responds only to port power commands (Set/Clear Port Power). If the port mask is cleared, then the port is controlled only by the global power switch (Set/Clear Global Power). 7 to 0 NDP[7:0] Number Downstream Ports: These bits specify the number of downstream ports supported by the Root Hub. It is implementation-specific. The minimum number of ports is 1. The maximum number of ports supported by OHCI is 15. 11.1.20 HcRhDescriptorB register The HcRhDescriptorB register (see Table 80) is the second of two registers describing the characteristics of the Root Hub. These fields are written during initialization to correspond to the system implementation. Reset values are implementation-specific. Table 80: HcRhDescriptorB - Host Controller Root Hub Descriptor B register bit allocation Address: Value read from func0 or func1 of address 10h + 4Ch Bit 31 30 29 28 Symbol Reset Access Bit Access Bit Access Bit Access [1] 24 0 0 0 0 0 0 0 R/W R/W R/W R/W R R/W R/W R/W 23 22 21 20 19 18 17 16 PPCM[7:0] 0 0 0 0 0 X [1] 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 DR[15:8] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Symbol Reset 25 0 Symbol Reset 26 PPCM[15:0] Symbol Reset 27 DR[7:0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W X is 0 for one port, and 1 for two ports. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 59 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 81: HcRhDescriptorB - Host Controller Root Hub Descriptor B register bit description Address: Value read from func0 or func1 of address 10h + 4Ch Bit Symbol Description 31 to 16 PPCM[15:0] Port Power Control Mask: Each bit indicates whether a port is affected by a global power control command when Power Switching Mode is set. When set, only the power state of the port is affected by per-port power control (Set/Clear Port Power). When cleared, the port is controlled by the global power switch (Set/Clear Global Power). If the device is configured to global switching mode (Power Switching Mode = 0), this field is not valid. Bit 0 — reserved Bit 1 — Ganged-power mask on port 1 Bit 2 — Ganged-power mask on port 2. 15 to 0 DR[15:0] Device Removable: Each bit is dedicated to a port of the Root Hub. When cleared, the attached device is removable. When set, the attached device is not removable. Bit 0 — reserved Bit 1 — Device attached to port 1 Bit 2 — Device attached to port 2. 11.1.21 HcRhStatus register This register is divided into two parts. The lower word of the DWord represents the Hub Status field, and the upper word represents the Hub Status Change field. Reserved bits should always be written as logic 0. Table 82 contains the bit allocation of the register. Table 82: HcRhStatus - Host Controller Root Hub Status register bit allocation Address: Value read from func0 or func1 of address 10h + 50h Bit 31 Symbol 30 29 Access Bit 26 Access Bit 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 CCIC LPSC 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved [1] DRWE Reset Access Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 OCI LPS reserved [1] Symbol Reset Access 24 0 reserved [1] Reset 25 R/W Symbol [1] 27 reserved [1] CRWE Reset Symbol 28 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R R/W The reserved bits should always be written with the reset value. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 60 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 83: HcRhStatus - Host Controller Root Hub Status register bit description Address: Value read from func0 or func1 of address 10h + 50h Bit Symbol Description 31 CRWE On write, Clear Remote Wake-up Enable: 0 — No effect 1 — Clears DRWE (Device Remote Wake-up Enable). 30 to 18 reserved - 17 CCIC Overcurrent Indicator Change: This bit is set by hardware when a change has occurred to the OCI bit of this register. 0 — No effect 1 — The HCD clears this bit. 16 LPSC On read, Local Power Status Change: The Root Hub does not support the local power status feature. Therefore, this bit is always logic 0. On write, Set Global Power: In global power mode (Power Switching Mode = 0), logic 1 is written to this bit to turn on power to all ports (clear Port Power Status). In per-port power mode, it sets Port Power Status only on ports whose Port Power Control Mask bit is not set. Writing logic 0 has no effect. 15 DRWE On read, Device Remote Wake-up Enable: This bit enables bit Connect Status Change (CSC) as a resume event, causing a state transition from USBSUSPEND to USBRESUME and setting the Resume Detected interrupt. 0 — CSC is not a remote wake-up event 1 — CSC is a remote wake-up event. On write, Set Remote Wake-up Enable: Writing logic 1 sets DRWE (Device Remote Wake-up Enable). Writing logic 0 has no effect. 14 to 2 reserved - 1 OCI Overcurrent Indicator: This bit reports overcurrent conditions when global reporting is implemented. When set, an overcurrent condition exists. When cleared, all power operations are normal. If the per-port overcurrent protection is implemented, this bit is always logic 0. 0 LPS On read, Local Power Status: The Root Hub does not support the local power status feature. Therefore, this bit is always read as logic 0. On write, Clear Global Power: In global power mode (Power Switching Mode = 0), logic 1 is written to this bit to turn off power to all ports (clear Port Power Status). In per-port power mode, it clears Port Power Status only on ports whose Port Power Control Mask bit is not set. Writing logic 0 has no effect. 11.1.22 HcRhPortStatus[4:1] register The HcRhPortStatus[4:1] register is used to control and report port events on a per-port basis. NumberDownstreamPorts represent the number of HcRhPortStatus registers that are implemented in hardware. The lower word reflects the port status. The upper word reflects the status change bits. Some status bits are implemented with special write behavior. If a transaction, token through handshake, is in progress when a write to change port status occurs, the resulting port status change is postponed until the transaction completes. Always write logic 0 to the reserved bits. The bit allocation of the register is given in Table 84. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 61 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 84: HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit allocation Address: Value read from func0 or func1 of address 10h + 54h Bit 31 30 29 28 Symbol Reset Access Bit Access Bit Access Bit Access [1] 24 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 reserved [1] PRSC OCIC PSSC PESC CSC 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved [1] LSDA PPS 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 reserved [1] PRS POCI PSS PES CCS 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Symbol Reset 25 0 Symbol Reset 26 0 Symbol Reset 27 reserved [1] The reserved bits should always be written with the reset value. Table 85: HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit description Address: Value read from func0 or func1 of address 10h + 54h Bit Symbol Description 31 to 21 reserved - 20 PRSC Port Reset Status Change: This bit is set at the end of the 10 ms port reset signal. The HCD can write logic 1 to clear this bit. Writing logic 0 has no effect. 0 — Port reset is not complete 1 — Port reset is complete. 19 OCIC Port Overcurrent Indicator Change: This bit is valid only if overcurrent conditions are reported on a per-port basis. This bit is set when the Root Hub changes the POCI (Port Overcurrent Indicator) bit. The HCD can write logic 1 to clear this bit. Writing logic 0 has no effect. 0 — No change in POCI 1 — POCI has changed. 18 PSSC Port Suspend Status Change: This bit is set when the resume sequence is completed. This sequence includes the 20 ms resume pulse, LS EOP and 3 ms re-synchronization delay. The HCD can write logic 1 to clear this bit. Writing logic 0 has no effect. This bit is also cleared when Reset Status Change is set. 0 — Resume is not completed 1 — Resume is completed. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 62 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 85: HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit description…continued Address: Value read from func0 or func1 of address 10h + 54h Bit Symbol Description 17 PESC Port Enable Status Change: This bit is set when hardware events cause the PES (Port Enable Status) bit to be cleared. Changes from the HCD writes do not set this bit. The HCD can write logic 1 to clear this bit. Writing logic 0 has no effect. 0 — No change in PES 1 — Change in PES. 16 CSC Connect Status Change: This bit is set whenever a connect or disconnect event occurs. The HCD can write logic 1 to clear this bit. Writing logic 0 has no effect. If CCS (Current Connect Status) is cleared when a Set Port Reset, Set Port Enable or Set Port Suspend write occurs, this bit is set to force the driver to re-evaluate the connection status because these writes should not occur if the port is disconnected. 0 — No change in CCS 1 — Change in CCS. Remark: If the DeviceRemovable[NDP] bit is set, this bit is set only after a Root Hub reset to inform the system that the device is attached. 15 to 10 reserved - 9 LSDA On read, Low-Speed Device Attached: This bit indicates the speed of the device attached to this port. When set, a low-speed device is attached to this port. When cleared, a full-speed device is attached to this port. This bit is valid only when CCS is set. 0 — Port is not suspended 1 — Port is suspended. On write, Clear Port Power: The HCD can clear the PPS (Port Power Status) bit by writing logic 1 to this bit. Writing logic 0 has no effect. 8 PPS On read, Port Power Status: This bit reflects the port power status, regardless of the type of power switching implemented. This bit is cleared if an overcurrent condition is detected. The HCD can set this bit by writing Set Port Power or Set Global Power. The HCD can clear this bit by writing Clear Port Power or Clear Global Power. Power Switching Mode and PortPowerControlMask[NDP] determine which power control switches are enabled. In global switching mode (Power Switching Mode = 0), only Set/Clear Global Power controls this bit. In the per-port power switching (Power Switching Mode = 1), if the PortPowerControlMask[NDP] bit for the port is set, only Set/Clear Port Power commands are enabled. If the mask is not set, only Set/Clear Global Power commands are enabled. When port power is disabled, bits CCS (Current Connect Status), PES (Port Enable Status), PSS (Port Suspend Status) and PRS (Port Reset Status) should be reset. 0 — Port power is off 1 — Port power is on. On write, Set Port Power: The HCD can write logic 1 to set the PPS bit. Writing logic 0 has no effect. Remark: This bit always reads logic 1 if power switching is not supported. 7 to 5 reserved - 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 63 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 85: HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit description…continued Address: Value read from func0 or func1 of address 10h + 54h Bit Symbol Description 4 PRS On read, Port Reset Status: When this bit is set by a write to Set Port Reset, port reset signaling is asserted. When reset is completed and PRSC is set, this bit is cleared. 0 — Port reset signal is inactive 1 — Port reset signal is active. On write, Set Port Reset: The HCD can set the port reset signaling by writing logic 1 to this bit. Writing logic 0 has no effect. If CCS is cleared, this write does not set PRS (Port Reset Status) but instead sets CCS. This informs the driver that it attempted to reset a disconnected port. 3 POCI On read, Port Overcurrent Indicator: This bit is valid only when the Root Hub is configured to show overcurrent conditions are reported on a per-port basis. If the per-port overcurrent reporting is not supported, this bit is set to logic 0. If cleared, all power operations are normal for this port. If set, an overcurrent condition exists on this port. 0 — No overcurrent condition 1 — Overcurrent condition detected. On write, Clear Suspend Status: The HCD can write logic 1 to initiate a resume. Writing logic 0 has no effect. A resume is initiated only if PSS (Port Suspend Status) is set. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 64 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 85: HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit description…continued Address: Value read from func0 or func1 of address 10h + 54h Bit Symbol Description 2 PSS On read, Port Suspend Status: This bit indicates whether the port is suspended or is in the resume sequence. It is set by a Set Suspend State write and cleared when PSSC (Port Suspend Status Change) is set at the end of the resume interval. This bit is not set if CCS (Current Connect Status) is cleared. This bit is also cleared when PRSC is set at the end of the port reset or when the Host Controller is placed in the USBRESUME state. If an upstream resume is in progress, it will propagate to the Host Controller. 0 — Port is not suspended 1 — Port is suspended. On write, Set Port Suspend: The HCD can set the PSS (Port Suspend Status) bit by writing logic 1 to this bit. Writing logic 0 has no effect. If CCS is cleared, this write does not set PSS; instead it sets CSS. This informs the driver that it attempted to suspend a disconnected port. 1 PES On read, Port Enable Status: This bit indicates whether the port is enabled or disabled. The Root Hub may clear this bit when an overcurrent condition, disconnect event, switched-off power or operational bus error is detected. This change also causes Port Enabled Status Change to be set. The HCD can set this bit by writing Set Port Enable and clear it by writing Clear Port Enable. This bit cannot be set when CCS (Current Connect Status) is cleared. This bit is also set on completing a port reset when Reset Status Change is set or on completing a port suspend when Suspend Status Change is set. 0 — Port is disabled 1 — Port is enabled. On write, Set Port Enable: The HCD can set PES (Port Enable Status) by writing logic 1. Writing logic 0 has no effect. If CCS is cleared, this write does not set PES, but instead sets CSC (Connect Status Change). This informs the driver that it attempted to enable a disconnected port. 0 CCS On read, Current Connect Status: This bit reflects the current state of the downstream port. 0 — No device connected 1 — Device connected. On write, Clear Port Enable: The HCD can write logic 1 to this bit to clear the PES (Port Enable Status) bit. Writing logic 0 has no effect. The CCS bit is not affected by any write. Remark: This bit always reads logic 1 when the attached device is nonremovable (DeviceRemovable[NDP]). 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 65 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 11.2 USB legacy support registers The ISP1563 supports legacy keyboard and mouse. Four operational registers are used to provide the legacy support. Each of these registers is located on a 32-bit boundary. The offset of these registers is relative to the base address of the Host Controller operational registers with HceControl located at offset 100h. Table 86: Legacy support registers Offset Register Description 100h HceControl used to enable and control the emulation hardware and report various status information 104h HceInput emulation of the legacy Input Buffer register 108h HceOutput emulation of the legacy Output Buffer register in which the software writes keyboard and mouse data 10Ch HceStatus emulation of the legacy Status register Table 87: Emulated registers I/O address Cycle type Register contents accessed or modified Side effects 60h IN HceOutput IN from port 60h sets OUT_FULL (bit 0) in HceStatus to logic 0 60h OUT HceInput OUT to port 60h sets IN_FULL (bit 1) to logic 1 and CMD_DATA (bit 3) to logic 0 in HceStatus 64h IN HceStatus IN from port 64h returns current value of HceStatus with no other side effect 64h OUT HceInput OUT to port 64h sets IN_FULL to logic 0 and CMD_DATA to logic 1 in HceStatus 11.2.1 HceControl register Table 88 shows the bit allocation of the register. Table 88: HceControl - Host Controller Emulation Control register bit allocation Address: Value read from func0 or func1 of address 10h + 100h Bit 31 30 29 28 Symbol Reset Access Bit Access Bit Access 24 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 reserved [1] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved [1] A20S 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 9397 750 14224 Product data sheet 25 0 Symbol Reset 26 0 Symbol Reset 27 reserved [1] © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 66 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Bit Symbol 7 6 5 4 3 2 1 0 IRQ12A IRQ1A GA20S EIRQEN IRQEN C_P EI EE 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R R/W Reset Access [1] The reserved bits should always be written with the reset value. Table 89: HceControl - Host Controller Emulation Control register bit description Address: Value read from func0 or func1 of address 10h + 100h Bit Symbol Description 31 to 9 reserved - 8 A20S A20 State: This bit indicates the current state of Gate A20 on the keyboard controller. It is used to compare against value written to 60h when GA20S is active. 7 IRQ12A IRQ12 Active: This bit indicates that a positive transition on IRQ12 from the keyboard controller has occurred. 0 — No effect 1 — Sets IRQ12 to logic 0 (inactive). 6 IRQ1A IRQ1 Active: This bit indicates that a positive transition on IRQ1 from the keyboard controller has occurred. 0 — No effect 1 — Sets IRQ11 to logic 0 (inactive). 5 GA20S Gate A20 Sequence: This bit is set by the Host Controller when a data value of D1h is written to I/O port 64h and cleared on a write to I/O port 64h of any value other than D1h. 4 EIRQEN External IRQ Enable: When this bit is set to logic 1, IRQ1 and IRQ12 from the keyboard controller cause an emulation interrupt. This bit is independent of the setting of the EE bit in this register. 3 IRQEN IRQ Enable: When this bit is set, the Host Controller generates IRQ1 or IRQ12 as long as OUT_FULL (bit 0 in HceStatus) is logic 1. If AUX_OUT_FULL (bit 5 in HceStatus) is logic 0, then IRQ1 is generated; if it is logic 1, then IRQ12 is generated. 2 C_P Character Pending: When this bit is set, an emulation interrupt is generated when OUT_FULL is set to logic 0. 1 EI Emulation Interrupt: This bit shows the emulation interrupt condition. 0 — Legacy emulation enabled 1 — Legacy emulation disabled. 0 EE Emulation Enable: When this bit is set to logic 1, the Host Controller is enabled for legacy emulation. The Host Controller decodes accesses to I/O registers 60h and 64h and enables interrupts on IRQ1 or IRQ12, or both. The Host Controller also generates an emulation interrupt at appropriate times to invoke the emulation software. 11.2.2 HceInput register The HceInput register is a 4 B register, and the bit allocation is given in Table 90. I/O data that is written to ports 60h and 64h is captured in this register, when emulation is enabled. This register may be directly read or written by accessing it in the Host Controller’s operational register space. When directly accessed in a memory cycle, reads and writes of this register have no side effects. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 67 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 90: HceInput - Host Controller Emulation Input register bit allocation Address: Value read from func0 or func1 of address 10h + 104h Bit 31 30 29 28 Symbol Reset Access Bit 26 25 24 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 reserved [1] Symbol Reset Access Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved [1] Symbol Reset Access Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Symbol IN_DATA[7:0] Reset Access [1] 27 reserved [1] The reserved bits should always be written with the reset value. Table 91: HceInput - Host Controller Emulation Input register bit description Address: Value read from func0 or func1 of address 10h + 104h Bit Symbol Description 31 to 8 reserved - 7 to 0 IN_DATA[7:0] Input Data: This register holds data that is written to I/O ports 60h or 64h. 11.2.3 HceOutput register Data placed in this register by the emulation software is returned when I/O port 60h is read and emulation is enabled. On a read of this location, OUT_FULL (bit 0 in HceStatus) is set to logic 0. The bit allocation is given in Table 92. Table 92: HceOutput - Host Controller Emulation Output register bit allocation Address: Value read from func0 or func1 of address 10h + 108h Bit 31 30 29 28 Symbol Reset Access Bit Access 25 24 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 reserved [1] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 9397 750 14224 Product data sheet 26 0 Symbol Reset 27 reserved [1] © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 68 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Bit 15 14 13 12 Symbol Reset Access Bit 10 9 8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Symbol OUT_DATA[7:0] Reset Access [1] 11 reserved [1] The reserved bits should always be written with the reset value. Table 93: HceOutput - Host Controller Emulation Output register bit description Address: Value read from func0 or func1 of address 10h + 108h Bit Symbol Description 31 to 8 reserved - 7 to 0 OUT_DATA[7:0] Output Data: This register holds the data that is returned when an I/O read of port 60h is requested by application software. 11.2.4 HceStatus register The contents of the HceStatus register are returned on an I/O read of port 64h when emulation is enabled. Reads from and writes to port 60h and writes to port 64h can cause changes in this register. Emulation software can directly access this register through its memory address in the Host Controller’s operational register space. Accessing this register through its memory address produces no side effects. Table 94 shows the bit allocation. Table 94: HceStatus - Host Controller Emulation Status register bit allocation Address: Value read from func0 or func1 of address 10h + 10Ch Bit 31 30 29 28 Symbol Reset Access Bit 25 24 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 reserved [1] Reset Access Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved [1] Symbol Reset 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 PARITY TIMEOUT AUX_OUT _FULL INH_SW CMD_DATA FLAG IN_FULL OUT_FULL 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Access Bit Reset Access [1] 26 R/W Symbol Symbol 27 reserved [1] The reserved bits should always be written with the reset value. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 69 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 95: HceStatus - Host Controller Emulation Status register bit description Address: Value read from func0 or func1 of address 10h + 10Ch Bit Symbol Description 31 to 8 reserved - 7 PARITY Parity: This bit indicates parity error on keyboard and mouse data. 6 TIMEOUT Time-out: This bit indicates a time-out. 5 AUX_OUT_ FULL Auxiliary Output Full: IRQ12 is asserted whenever this bit is set to logic 1, OUT_FULL is set to logic 1, and the IRQEN bit is set. 4 INH_SW Inhibit Switch: This bit reflects the state of the keyboard inhibit switch. If set, the keyboard is active. 3 CMD_DATA Cmd Data: The Host Controller sets this bit to logic 0 on an I/O write to port 60h and to logic 1 on an I/O write to port 64h. 2 FLAG Flag: Nominally used as a system flag by software to indicate a warm or cold boot. 1 IN_FULL Input Full: Except in the case of a Gate A20 sequence, this bit is set to logic 1 on an I/O write to address 60h or 64h. While this bit is set to logic 1 and emulation is enabled, an emulation interrupt condition exists. 0 OUT_FULL Output Full: The Host Controller sets this bit to logic 0 on a read of I/O port 60h. If IRQEN is set, AUX_OUT_FULL determines which IRQ is activated. While this bit is logic 0 and C_P in HceControl is set to logic 1, an emulation interrupt condition exists. 11.3 EHCI controller capability registers Other than the OHCI Host Controller, there are some registers in EHCI that define the capability of EHCI. The address range of these registers is located before the operational registers. 11.3.1 CAPLENGTH/HCIVERSION register The bit allocation of this 4 B register is given in Table 96. Table 96: CAPLENGTH/HCIVERSION - Capability Registers Length/Host Controller Interface Version Number register bit allocation Address: Value read from func2 of address 10h + 00h Bit 31 30 29 Symbol Reset 28 27 26 25 24 0 0 1 HCIVERSION[15:8] 0 0 0 0 0 Access R R R R R R R R Bit 23 22 21 20 19 18 17 16 0 0 0 Symbol Reset HCIVERSION[7:0] 0 0 0 0 0 Access R R R R R R R R Bit 15 14 13 12 11 10 9 8 Symbol reserved Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 70 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Bit 7 6 5 4 Reset 0 0 1 0 Access R R R R Symbol 3 2 1 0 0 0 0 0 R R R R CAPLENGTH[7:0] Table 97: CAPLENGTH/HCIVERSION - Capability Registers Length/Host Controller Interface Version Number register bit description Address: Value read from func2 of address 10h + 00h Bit Symbol Description 31 to 16 HCIVERSION[15:0] Host Controller Interface Version Number: This field contains a BCD encoded version number of the interface to which the Host Controller interface conforms. 15 to 8 reserved - 7 to 0 CAPLENGTH[7:0] Capability Register Length: This is used as an offset. It is added to the register base to find the beginning of the operational register space. 11.3.2 HCSPARAMS register The Host Controller Structural Parameters (HCSPARAMS) register is a set of fields that are structural parameters. The bit allocation is given in Table 98. Table 98: HCSPARAMS - Host Controller Structural Parameters register bit allocation Address: Value read from func2 of address 10h + 04h Bit 31 30 29 28 27 26 25 24 Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 23 22 21 20 19 18 17 16 Symbol reserved Symbol DPN[3:0] reserved P_INDICAT OR Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 15 14 13 12 11 10 9 8 Symbol N_CC[3:0] N_PCC[3:0] Reset 0 0 1 0 0 0 1 0 Access R R R R R R R R 7 6 4 3 2 1 0 Bit Symbol PRR 5 reserved PPC N_PORTS[3:0] Reset 1 0 0 1 0 1 0 0 Access R R R R R R R R 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 71 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 99: HCSPARAMS - Host Controller Structural Parameters register bit description Address: Value read from func2 of address 10h + 04h Bit Symbol Description 31 to 24 reserved - 23 to 20 DPN[3:0] Debug Port Number: This field identifies which of the Host Controller ports is the debug port. A nonzero value in this field indicates the presence of a debug port. The value in this register must not be greater than N_PORTS. 19 to 17 reserved - 16 P_INDICATOR Port Indicators: This bit indicates whether the ports support port indicator control. When this bit is logic 1, the port status and control registers include a read and writable field to control the state of the port indicator. This bit is set by the AMB3 pin during reset. 15 to 12 N_CC[3:0] Number of Companion Controller: This field indicates the number of companion controllers associated with this Hi-Speed USB Host Controller. A value of zero in this field indicates there are no companion Host Controllers. Port-ownership hand-off is not supported. Only high-speed devices are supported on the Host Controller root ports. A value larger than zero in this field indicates there are companion Original USB Host Controller(s). Port-ownership hand-offs are supported. 11 to 8 N_PCC[3:0] Number of Ports per Companion Controller: This field indicates the number of ports supported per companion Host Controller. It is used to indicate the port routing configuration to the system software. For example, if N_PORTS has a value of 6 and N_CC has a value of 2, then N_PCC can have a value of 3. The convention is that the first N_PCC ports are assumed to be routed to companion controller 1, the next N_PCC ports to companion controller 2, and so on. In the previous example, N_PCC could have been 4, in which case the first four are routed to companion controller 1, and the last two are routed to companion controller 2. The number in this field must be consistent with N_PORTS and N_CC. 7 PRR Port Routing Rules: This field indicates the method used to map ports to the companion controllers. 0 — The first N_PCC ports are routed to the lowest numbered function companion Host Controller, the next N_PCC ports are routed to the next lowest function companion controller, and so on. 1 — The port routing is explicitly enumerated by the first N_PORTS elements of the HCSP-PORTROUTE array. 6 to 5 reserved - 4 PPC Port Power Control: This field indicates whether the Host Controller implementation includes port power control. Logic 1 indicates the port has port power switches. Logic 0 indicates the port does not have port power switches. The value of this field affects the functionality of the Port Power field in each port status and control register. 3 to 0 N_PORTS[3:0] N_Ports: This field specifies the number of physical downstream ports implemented on this Host Controller. The value of this field determines how many port registers are addressable in the operational register space. Valid values are in the range of 1h to Fh. Logic 0 in this field is undefined. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 72 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 11.3.3 HCCPARAMS register The Host Controller Capability Parameters (HCCPARAMS) register is a 4 B register, and the bit allocation is given in Table 100. Table 100: HCCPARAMS - Host Controller Capability Parameters register bit allocation Address: Value read from func2 of address 10h + 08h Bit 31 30 29 28 Symbol Reset 27 26 25 24 0 0 0 0 reserved 0 0 0 0 Access R R R R R R R R Bit 23 22 21 20 19 18 17 16 0 0 0 0 Symbol Reset reserved 0 0 0 0 Access R R R R R R R R Bit 15 14 13 12 11 10 9 8 Symbol reserved Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Bit 7 6 5 4 3 2 1 0 PFLF 64AC Symbol IST[3:0] reserved Reset 0 0 0 1 0 0 1 0 Access R R R R R R R R Table 101: HCCPARAMS - Host Controller Capability Parameters register bit description Address: Value read from func2 of address 10h + 08h Bit Symbol Description 31 to 8 reserved - 7 to 4 IST[3:0] Isochronous Scheduling Threshold: Default = implementation dependent. This field indicates, relative to the current position of the executing Host Controller, where software can reliably update the isochronous schedule. When IST[3] is logic 0, the value of the least significant three bits indicates the number of micro frames a Host Controller can hold a set of isochronous data structures, one or more, before flushing the state. When IST[3] is logic 1, the host software assumes the Host Controller may cache an isochronous data structure for an entire frame. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 73 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 101: HCCPARAMS - Host Controller Capability Parameters register bit description…continued Bit Symbol Description 3 to 2 reserved - 1 PFLF Programmable Frame List Flag: Default = implementation dependent. If this bit is cleared, the system software must use a frame list length of 1024 elements with the Host Controller. The USBCMD register FLS[1:0] (bits 3 and 2) is read-only and should be cleared. If PFLF is set, the system software can specify and use a smaller frame list and configure the host through the FLS bit. The frame list must always be aligned on a 4 kB page boundary to ensure that the frame list is always physically contiguous. 0 64AC 64-bit Addressing Capability: This field contains the addressing range capability. 0 — Data structures using 32-bit address memory pointers 1 — Data structures using 64-bit address memory pointers. 11.3.4 HCSP-PORTROUTE register The HCSP-PORTROUTE (Companion Port Route Description) register is an optional read-only field that is valid only if PRR (bit 7 in the HCSPARAMS register) is logic 1. Its address is value read from func2 of address 10h + 0Ch. This field is a 15-element nibble array, and each 4 bits is one array element. Each array location corresponds one-to-one with a physical port provided by the Host Controller. For example, PORTROUTE[0] corresponds to the first PORTSC port, PORTROUTE[1] to the second PORTSC port, and so on. The value of each element indicates to which of the companion Host Controllers this port is routed. Only the first N_PORTS elements have valid information. A value of zero indicates that the port is routed to the lowest numbered function companion Host Controller. A value of one indicates that the port is routed to the next lowest numbered function companion Host Controller, and so on. 11.4 Operational registers of Enhanced USB Host Controller 11.4.1 USBCMD register The USB Command (USBCMD) register indicates the command to be executed by the serial Host Controller. Writing to this register causes a command to be executed. Table 102 shows the bit allocation. Table 102: USBCMD - USB Command register bit allocation Address: Value read from func2 of address 10h + 20h Bit 31 30 29 28 Symbol Reset Access Bit Access 25 24 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 ITC[7:0] 0 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 9397 750 14224 Product data sheet 26 0 Symbol Reset 27 reserved [1] © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 74 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Bit 15 14 13 12 Symbol Reset 9 8 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 LHCR IAAD ASE PSE HCRESET RS 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Bit Reset Access [1] 10 0 Access Symbol 11 reserved [1] FLS[1:0] The reserved bits should always be written with the reset value. Table 103: USBCMD - USB Command register bit description Address: Value read from func2 of address 10h + 20h Bit Symbol Description 31 to 24 reserved - 23 to 16 ITC[7:0] Interrupt Threshold Control: Default = 08h. This field is used by the system software to select the maximum rate at which the Host Controller will issue interrupts. If software writes an invalid value to this register, the results are undefined. Valid values are: 00h — reserved 01h — 1 micro frame 02h — 2 micro frames 04h — 4 micro frames 08h — 8 micro frames (equals 1 ms) 10h — 16 micro frames (equals 2 ms) 20h — 32 micro frames (equals 4 ms) 40h — 64 micro frames (equals 8 ms). Software modifications to this field while HCH (bit 12 in the USBSTS register) is zero results in undefined behavior. 15 to 8 reserved - 7 LHCR Light Host Controller Reset: This control bit is not required. It allows the driver software to reset the EHCI controller, without affecting the state of the ports or the relationship to the companion Host Controllers. If not implemented, a read of this field will always return zero. If implemented, on read: 0 — Indicates that the Light Host Controller Reset has completed and it is ready for the host software to reinitialize the Host Controller 1 — Indicates that the Light Host Controller Reset has not yet completed. 6 IAAD Interrupt on Asynchronous Advance Doorbell: This bit is used as a doorbell by software to notify the Host Controller to issue an interrupt the next time it advances the asynchronous schedule. Software must write logic 1 to this bit to ring the doorbell. When the Host Controller has evicted all appropriate cached schedule states, it sets IAA (bit 5 in the USBSTS register). If IAAE (bit 5 in the USBINTR register) is logic 1, then the Host Controller will assert an interrupt at the next interrupt threshold. The Host Controller sets this bit to logic 1 after it sets IAA. Software should not set this bit when the asynchronous schedule is inactive because this results in an undefined value. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 75 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 103: USBCMD - USB Command register bit description…continued Address: Value read from func2 of address 10h + 20h Bit Symbol Description 5 ASE Asynchronous Schedule Enable: Default = 0. This bit controls whether the Host Controller skips processing the asynchronous schedule. 0 — Do not process the asynchronous schedule 1 — Use the ASYNCLISTADDR register to access the asynchronous schedule. 4 PSE Periodic Schedule Enable: Default = 0. This bit controls whether the Host Controller skips processing the periodic schedule. 0 — Do not process the periodic schedule 1 — Use the PERIODICLISTBASE register to access the periodic schedule. 3 to 2 FLS[1:0] Frame List Size: Default = 00b. This field is read and write only if PFLF (bit 1 in the HCCPARAMS register) is set to logic 1. This field specifies the size of the frame list. The size the frame list controls which bits in the Frame Index register should be used for the frame list current index. 00b — 1024 elements (4096 B) 01b — 512 elements (2048 B) 10b — 256 elements (1024 B) for small environments 11b — reserved. 1 HCRESET Host Controller Reset: This control bit is used by the software to reset the Host Controller. The effects of this on Root Hub registers are similar to a chip hardware reset. Setting this bit causes the Host Controller to reset its internal pipelines, timers, counters, state machines, and so on, to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. This reset does not affect the PCI Configuration registers. All operational registers, including port registers and port state machines are set to their initial values. Port ownership reverts to the companion Host Controller(s). The software must reinitialize the Host Controller to return it to an operational state. This bit is cleared by the Host Controller when the reset process is complete. Software cannot terminate the reset process early by writing logic 0 to this register. Software should check that bit HCH is logic 0 before setting this bit. Attempting to reset an actively running Host Controller results in undefined behavior. 0 RS Run/Stop: 1 = Run. 0 = Stop. When set, the Host Controller executes the schedule. The Host Controller continues execution as long as this bit is set. When this bit is cleared, the Host Controller completes the current and active transactions in the USB pipeline, and then halts. Bit HCH indicates when the Host Controller has finished the transaction and has entered the stopped state. Software should check that bit HCH is logic 1 before setting this bit. 11.4.2 USBSTS register The USB Status (USBSTS) register indicates pending interrupts and various states of the Host Controller. The status resulting from a transaction on the serial bus is not indicated in this register. Software clears the register bits by writing ones to them. The bit allocation is given in Table 104. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 76 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 104: USBSTS - USB Status register bit allocation Address: Value read from func2 of address 10h + 24h Bit 31 30 29 28 Symbol Reset Access Bit Access Bit Symbol 26 25 24 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 reserved [1] Symbol Reset 27 reserved [1] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved [1] ASS PSSTAT RECL HCH Reset 0 0 0 1 0 0 0 0 Access R R R R R/W R/W R/W R/W Bit 7 6 5 4 3 2 1 0 IAA HSE FLR PCD USBERRIN T USBINT reserved [1] Symbol Reset Access [1] 0 0 0 0 0 0 0 0 R/W R/W R R/W R/W R/W R/W R/W The reserved bits should always be written with the reset value. Table 105: USBSTS - USB Status register bit description Address: Value read from func2 of address 10h + 24h Bit Symbol Description 31 to 16 reserved - 15 ASS Asynchronous Schedule Status: Default = 0. The bit reports the current real status of the asynchronous schedule. If this bit is logic 0, the status of the asynchronous schedule is disabled. If this bit is logic 1, the status of the asynchronous schedule is enabled. The Host Controller is not required to immediately disable or enable the asynchronous schedule when software changes ASE (bit 5 in the USBCMD register). When this bit and the ASE bit have the same value, the asynchronous schedule is either enabled (1) or disabled (0). 14 PSSTAT Periodic Schedule Status: Default = 0. This bit reports the current status of the periodic schedule. If this bit is logic 0, the status of the periodic schedule is disabled. If this bit is logic 1, the status of the periodic schedule is enabled. The Host Controller is not required to immediately disable or enable the periodic schedule when software changes PSE (bit 4 in the USBCMD register). When this bit and the PSE bit have the same value, the periodic schedule is either enabled (1) or disabled (0). 13 RECL Reclamation: Default = 0. This is a read-only status bit that is used to detect an empty asynchronous schedule. 12 HCH HCHalted: Default = 1. This bit is logic 0 when RS (bit 0 of the USBCMD register) is logic 1. The Host Controller sets this bit to logic 1 after it has stopped executing because the RS bit is set to logic 0, either by software or by the Host Controller hardware. For example, on an internal error. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 77 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 105: USBSTS - USB Status register bit description…continued Address: Value read from func2 of address 10h + 24h Bit Symbol Description 11 to 6 reserved - 5 IAA Interrupt on Asynchronous Advance: Default = 0. The system software can force the Host Controller to issue an interrupt the next time the Host Controller advances the asynchronous schedule by writing logic 1 to IAAD (bit 6 in the USBCMD register). This status bit indicates the assertion of that interrupt source. 4 HSE Host System Error: The Host Controller sets this bit when a serious error occurs during a host system access, involving the Host Controller module. In a PCI system, conditions that set this bit include PCI parity error, PCI master abort and PCI target abort. When this error occurs, the Host Controller clears RS (bit 0 in the USBCMD register) to prevent further execution of the scheduled TDs. 3 FLR Frame List Rollover: The Host Controller sets this bit to logic 1 when the frame list index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size, as programmed in FLS[1:0] (bits 3 and 2 of the USBCMD register), is 1024, the Frame Index register rolls over every time bit 13 of the FRINDEX register toggles. Similarly, if the size is 512, the Host Controller sets this bit to logic 1 every time bit 12 of the FRINDEX register toggles. 2 PCD Port Change Detect: The Host Controller sets this bit to logic 1 when any port (where PO (bit 13 of PORTSC) is cleared) changes to logic 1, or FPR (bit 6 of PORTSC) changes to logic 1 as a result of a J-K transition detected on a suspended port. This bit is allowed to be maintained in the auxiliary power well. Alternatively, it is also acceptable that on a D3-to-D0 transition of the EHCI Host Controller device, this bit is loaded with the logical OR of all of the PORTSC change bits, including force port resume, overcurrent change, enable or disable change, and connect status change. 1 USBERRINT USB Error Interrupt: The Host Controller sets this bit when an error condition occurs because of completing a USB transaction. For example, error counter underflow. If the Transfer Descriptor (TD) on which the error interrupt occurred also had its IOC bit set, both this bit and the USBINT bit are set. For details, refer to the Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0. 0 USBINT USB Interrupt: The Host Controller sets this bit on completing a USB transaction, which results in the retirement of a TD that had its IOC bit set. The Host Controller also sets this bit when a short packet is detected, that is, the actual number of bytes received was less than the expected number of bytes. For details, refer to the Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0. 11.4.3 USBINTR register The USB Interrupt Enable (USBINTR) register enables and disables reporting of the corresponding interrupt to the software. When a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt sources that are disabled in this register still appear in the USBSTS to allow the software to poll for events. The USBSTS register bit allocation is given in Table 106. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 78 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 106: USBINTR - USB Interrupt Enable register bit allocation Address: Value read from func2 of address 10h + 28h Bit 31 30 29 28 Symbol Reset Access Bit Access Bit Access Bit Access [1] 24 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 reserved [1] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved [1] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 IAAE HSEE FLRE PCIE USBERR INTE USBINTE reserved [1] Symbol Reset 25 0 Symbol Reset 26 0 Symbol Reset 27 reserved [1] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The reserved bits should always be written with the reset value. Table 107: USBINTR - USB Interrupt Enable register bit description Address: Value read from func2 of address 10h + 28h Bit Symbol Description 31 to 6 reserved - 5 IAAE Interrupt on Asynchronous Advance Enable: When this bit and IAA (bit 5 in the USBSTS register) are set, the Host Controller issues an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing bit IAA. 4 HSEE Host System Error Enable: When this bit and HSE (bit 4 in the USBSTS register) are set, the Host Controller issues an interrupt. The interrupt is acknowledged by software clearing bit HSE. 3 FLRE Frame List Rollover Enable: When this bit and FLR (bit 3 in the USBSTS register) are set, the Host Controller issues an interrupt. The interrupt is acknowledged by software clearing bit FLR. 2 PCIE Port Change Interrupt Enable: When this bit and PCD (bit 2 in the USBSTS register) are set, the Host Controller issues an interrupt. The interrupt is acknowledged by software clearing bit PCD. 1 USBERRI NTE USB Error Interrupt Enable: When this bit and USBERRINT (bit 1 in the USBSTS register) are set, the Host Controller issues an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing bit USBERRINT. 0 USBINTE USB Interrupt Enable: When this bit and USBINT (bit 0 in the USBSTS register) are set, the Host Controller issues an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing bit USBINT. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 79 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 11.4.4 FRINDEX register The Frame Index (FRINDEX) register is used by the Host Controller to index into the periodic frame list. The register updates every 125 µs; once each micro frame. Bits N to 3 are used to select a particular entry in the periodic frame list during periodic schedule execution. The number of bits used for the index depends on the size of the frame list as set by the system software in FLS[1:0] (bits 3 to 2) of the USBCMD register. This register must be written as a DWord. Byte writes produce undefined results. This register cannot be written unless the Host Controller is in the halted state, as indicated by HCH (bit 12 in the USBSTS register). A write to this register while RS (bit 0 in the USBCMD register) is set produces undefined results. Writes to this register also affect the SOF value. The bit allocation is given in Table 108. Table 108: FRINDEX - Frame Index register bit allocation Address: Value read from func2 of address 10h + 2Ch Bit 31 30 29 28 Symbol Reset Access Bit Access Bit Access Bit Access [1] 24 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 reserved [1] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved [1] FRINDEX[13:8] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Symbol Reset 25 0 Symbol Reset 26 0 Symbol Reset 27 reserved [1] FRINDEX[7:0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The reserved bits should always be written with the reset value. Table 109: FRINDEX - Frame Index register bit description Address: Value read from func2 of address 10h + 2Ch Bit Symbol 31 to 14 reserved Description - 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 80 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 109: FRINDEX - Frame Index register bit description…continued Address: Value read from func2 of address 10h + 2Ch Bit Symbol Description 13 to 0 FRINDEX [13:0] Frame Index: Bits in this register are used for the frame number in the SOF packet and as the index into the frame list. The value in this register increments at the end of each time frame. For example, micro frame. The bits used for the frame number in the SOF token are taken from bits 13 to 3 of this register. Bits N to 3 are used for the frame list current index. This means that each location of the frame list is accessed eight times (frames or micro frames) before moving to the next index. The following illustrates values of N based on the value of FLS[1:0] (bits 3 to 2 in the USBCMD register). FLS[1:0] Number elements N 00b 1024 12 01b 512 11 10b 256 10 11b reserved - 11.4.5 PERIODICLISTBASE register The Periodic Frame List Base Address (PERIODLISTBASE) register contains the beginning address of the periodic frame list in the system memory. If the Host Controller is in 64-bit mode, as indicated by logic 1 in 64AC (bit 0 in the HCCSPARAMS register), the most significant 32 bits of every control data structure address comes from the CTRLDSSEGMENT register. The system software loads this register before starting the schedule execution by the Host Controller. The memory structure referenced by this physical memory pointer is assumed as 4 kB aligned. The contents of this register are combined with the FRINDEX register to enable the Host Controller to step through the periodic frame list in sequence. The bit allocation is given in Table 110. Table 110: PERIODICLISTBASE - Periodic Frame List Base Address register bit allocation Address: Value read from func2 of address 10h + 34h Bit 31 30 29 28 Symbol Reset Access Bit Access Bit Access 24 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 BA[11:4] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved [1] BA[3:0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 9397 750 14224 Product data sheet 25 0 Symbol Reset 26 BA[19:12] Symbol Reset 27 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 81 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Bit 7 6 5 4 Symbol Reset Access [1] 3 2 1 0 reserved [1] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The reserved bits should always be written with the reset value. Table 111: PERIODICLISTBASE - Periodic Frame List Base Address register bit description Address: Value read from func2 of address 10h + 34h Bit Symbol Description 31 to 12 BA[19:0] Base Address: These bits correspond to memory address signals 31 to 12, respectively. 11 to 0 reserved - 11.4.6 ASYNCLISTADDR register This 32-bit register contains the address of the next asynchronous queue head to be executed. If the Host Controller is in 64-bit mode, as indicated by logic 1 in 64AC (bit 0 of the HCCPARAMS register), the most significant 32 bits of every control data structure address comes from the CTRLDSSEGMENT register. Bits 4 to 0 of this register always return zeros when read. The memory structure referenced by the physical memory pointer is assumed as 32 B (cache aligned). For bit allocation, see Table 112. Table 112: ASYNCLISTADDR - Current Asynchronous List Address register bit allocation Address: Value read from func2 of address 10h + 38h Bit 31 30 29 28 Symbol Reset Access Bit Access Bit Access Bit Access [1] 24 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 LPL[11:4] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved [1] LPL[3:0] 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 reserved [1] Symbol Reset 25 R/W Symbol Reset 26 LPL[19:12] Symbol Reset 27 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The reserved bits should always be written with the reset value. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 82 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 113: ASYNCLISTADDR - Current Asynchronous List Address register bit description Address: Value read from func2 of address 10h + 38h Bit Symbol Description 31 to 12 LPL[19:0] Link Pointer List: These bits correspond to memory address signals 31 to 12, respectively. This field may only reference a Queue Head (QH). 11 to 0 reserved - 11.4.7 CONFIGFLAG register The bit allocation of the Configure Flag (CONFIGFLAG) register is given in Table 114. Table 114: CONFIGFLAG - Configure Flag register bit allocation Address: Value read from func2 of address 10h + 60h Bit 31 30 29 28 Reset Access Bit 26 25 24 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 23 22 21 20 19 18 17 16 reserved [1] Symbol Reset Access Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved [1] Symbol Reset Access Bit 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 reserved [1] Symbol Reset Access [1] 27 reserved [1] Symbol 0 CF 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The reserved bits should always be written with the reset value. Table 115: CONFIGFLAG - Configure Flag register bit description Address: Value read from func2 of address 10h + 60h Bit Symbol Description 31 to 1 reserved - 0 CF Configure Flag: The host software sets this bit as the last action in its process of configuring the Host Controller. This bit controls the default port-routing control logic. 0 — Port routing control logic default-routes each port to an implementation dependent classic Host Controller 1 — Port routing control logic default-routes all ports to this Host Controller. 11.4.8 PORTSC registers 1, 2, 3, 4 The Port Status and Control (PORTSC) register is in the auxiliary power well. It is only reset by hardware when the auxiliary power is initially applied or in response to a Host Controller reset. The initial conditions of a port are: 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 83 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller • No device connected • Port disabled. If the port has power control, software cannot change the state of the port until it sets the port power bits. Software must not attempt to change the state of the port until power is stable on the port; maximum delay is 20 ms from the transition. For bit allocation, see Table 116. Table 116: PORTSC 1, 2, 3, 4 - Port Status and Control, 1, 2, 3, 4 register bit allocation Address: Value read from func2 of address 10h + 64h + (4 × Port Number − 1) where Port Number is 1, 2, 3, 4 Bit 31 30 29 28 Reset Access Bit Symbol 27 26 25 24 reserved [1] Symbol 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 19 18 17 16 23 22 21 20 reserved [1] WKOC_E WKDSCNN T_E WKCNNT_ E 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 reserved [1] PR Reset Access Bit Symbol PIC[1:0] PO PP PTC[3:0] LS[1:0] Reset 0 0 1 0 0 0 0 0 Access R R R/W R/W R/W R/W R/W R Bit 7 6 5 4 3 2 1 0 SUSP FPR OCC OCA PEDC PED ECSC ECCS 0 0 0 0 0 0 0 0 R/W R/W R R R/W R/W R/W R Symbol Reset Access [1] The reserved bits should always be written with the reset value. Table 117: PORTSC 1, 2, 3, 4 - Port Status and Control, 1, 2, 3, 4 register bit description Address: Value read from func2 of address 10h + 64h + (4 × Port Number − 1) where Port Number is 1, 2, 3, 4 Bit Symbol 31 to 23 reserved Description - 22 WKOC_E Wake on Overcurrent Enable: Default = 0. Setting this bit enables the port to be sensitive to overcurrent conditions as wake-up events. [1] 21 WKDSC NNT_E Wake on Disconnect Enable: Default = 0. Setting this bit enables the port to be sensitive to device disconnects as wake-up events. [1] 20 WKCNN T_E Wake on Connect Enable: Default = 0. Setting this bit enables the port to be sensitive to device connects as wake-up events. [1] 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 84 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 117: PORTSC 1, 2, 3, 4 - Port Status and Control, 1, 2, 3, 4 register bit description…continued Address: Value read from func2 of address 10h + 64h + (4 × Port Number − 1) where Port Number Bit Symbol 19 to 16 PTC[3:0] Description Port Test Control: Default = 0000b. When this field is logic 0, the port is not operating in test mode. A nonzero value indicates that it is operating in test mode and test mode is indicated by the value. The encoding of the test mode bits are: 0000b — Test mode disabled 0001b — Test J_STATE 0010b — Test K_STATE 0011b — Test SE0_NAK 0100b — Test packet 0101b — Test FORCE_ENABLE 0110b to 1111b — reserved. 15 to 14 PIC[1:0] Port Indicator Control: Default = 0. Writing to this field has no effect if P_INDICATOR (bit 16) in the HCSPARAMS register is logic 0. If P_INDICATOR is logic 1, then the bit encoding is: 00b — Port indicators are off 01b — Amber 10b — Green 11b — Undefined. For a description on how these bits are implemented, refer to Universal Serial Bus Specification Rev. 2.0. [1] 13 PO Port Owner: Default = 1. This bit unconditionally goes to logic 0 when CF (bit 0) in the CONFIGFLAG register makes logic 0 to logic 1 transition. This bit unconditionally goes to logic 1 when the CF bit is logic 0. The system software uses this field to release ownership of the port to a selected Host Controller, if the attached device is not a high-speed device. Software writes logic 1 to this bit, if the attached device is not a high-speed device. Logic 1 in this bit means that a companion Host Controller owns and controls the port. 12 PP Port Power: The function of this bit depends on the value of PPC (bit 4) in the HCSPARAMS register. If PPC = 0 and PP = 1 — The Host Controller does not have port power control switches. Always powered. If PPC = 1 and PP = 1 or 0 — The Host Controller has port power control switches. This bit represents the current setting of the switch: logic 0 = off, logic 1 = on. When PP is logic 0, the port is nonfunctional and will not report any status. When an overcurrent condition is detected on a powered port and PPC is logic 1, the PP bit in each affected port may be changed by the Host Controller from logic 1 to logic 0, removing power from the port. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 85 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 117: PORTSC 1, 2, 3, 4 - Port Status and Control, 1, 2, 3, 4 register bit description…continued Address: Value read from func2 of address 10h + 64h + (4 × Port Number − 1) where Port Number Bit Symbol 11 to 10 LS[1:0] Description Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. These bits are used to detect low-speed USB devices before the port reset and enable sequence. This field is valid only when the Port Enable bit is logic 0, and the Current Connect Status bit is set to logic 1. 00b — SE0: Not a low-speed device, perform EHCI reset 01b — K-state: Low-speed device, release ownership of port 10b — J-state: Not a low-speed device, perform EHCI reset 11b — Undefined: Not a low-speed device, perform EHCI reset. If bit PP is logic 0, this field is undefined. 9 reserved - 8 PR Port Reset: Logic 1 means the port is in reset. Logic 0 means the port is not in reset. Default = 0. When software sets this bit from logic 0, the bus reset sequence as defined in Universal Serial Bus Specification Rev. 2.0 is started. Software clears this bit to terminate the bus reset sequence. Software must hold this bit at logic 1 until the reset sequence, as specified in Universal Serial Bus Specification Rev. 2.0, is completed. Remark: When software sets this bit, it must also clear the Port Enable bit. Remark: When software clears this bit, there may be a delay before the bit status changes to logic 0 because it will not read logic 0 until the reset is completed. If the port is in high-speed mode after reset is completed, the Host Controller will automatically enable this port; it can set the Port Enable bit. A Host Controller must terminate the reset and stabilize the state of the port within 2 ms of software changing this bit from logic 1 to logic 0. For example, if the port detects that the attached device is high-speed during a reset, then the Host Controller must enable the port within 2 ms of software clearing this bit. HCH (bit 12 in the USBSTS register) must be logic 0 before software attempts to use this bit. The Host Controller may hold Port Reset asserted when the HCH bit is set. [1] 7 SUSP Suspend: Default = 0. Logic 1 means the port is in the suspend state. Logic 0 means the port is not suspended. The PED (Port Enabled) bit and this bit define the port states as follows: PED = 0 and SUSP = X — Port is disabled PED = 1 and SUSP = 0 — Port is enabled PED = 1 and SUSP = 1 — port is suspended. When in the suspend state, downstream propagation of data is blocked on this port, except for the port reset. If a transaction was in progress when this bit was set, blocking occurs at the end of the current transaction. In the suspend state, the port is sensitive to resume detection. The bit status does not change until the port is suspended and there may be a delay in suspending a port, if there is a transaction currently in progress on the USB. Attempts to clear this bit are ignored by the Host Controller. The Host Controller will unconditionally set this bit to logic 0 when: • • Software changes the FPR (Force Port Resume) bit to logic 0. Software changes the PR (Port Reset) bit to logic 1. If the host software sets this bit when the Port Enabled bit is logic 0, the results are undefined. [1] 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 86 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 117: PORTSC 1, 2, 3, 4 - Port Status and Control, 1, 2, 3, 4 register bit description…continued Address: Value read from func2 of address 10h + 64h + (4 × Port Number − 1) where Port Number Bit Symbol Description 6 FPR Force Port Resume: Logic 1 means resume detected or driven on the port. Logic 0 means no resume (K-state) detected or driven on the port. Default = 0. Software sets this bit to drive the resume signaling. The Host Controller sets this bit if a J-to-K transition is detected, while the port is in the suspend state. When this bit changes to logic 1 because a J-to-K transition is detected, PCD (bit 2 in register USBSTS) is also set to logic 1. If software sets this bit to logic 1, the Host Controller must not set bit PCD. When the EHCI controller owns the port, the resume sequence follows the sequence given in Universal Serial Bus Specification Rev. 2.0. The resume signaling (full-speed ‘K’) is driven on the port as long as this bit remains set. Software must time the resume and clear this bit after the correct amount of time has elapsed. Clearing this bit causes the port to return to high-speed mode, forcing the bus below the port into a high-speed idle. This bit will remain at logic 1, until the port has switched to the high-speed idle. The Host Controller must complete this transition within 2 ms of software clearing this bit. [1] 5 OCC Overcurrent Change: Default = 0. This bit is set to logic 1 when there is a change in overcurrent active. Software clears this bit by setting this bit to logic 1. 4 OCA Overcurrent Active: Default = 0. If set to logic 1, this port has an overcurrent condition. If set to logic 0, this port does not have an overcurrent condition. This bit will automatically change from logic 1 to logic 0 when the overcurrent condition is removed. 3 PEDC Port Enable/Disable Change: Logic 1 means the port enabled or disabled status has changed. Logic 0 means no change. Default = 0. For the root hub, this bit is set only when a port is disabled because of the appropriate conditions existing at the EOF2 point. For definition of port error, refer to Chapter 11 of Universal Serial Bus Specification Rev. 2.0. Software clears this bit by setting it. [1] 2 PED Port Enabled/Disabled: Logic 1 means enable. Logic 0 means disable. Default = 0. Ports can only be enabled by the Host Controller as a part of the reset and enable sequence. Software cannot enable a port by writing logic 1 to this field. The Host Controller will only set this bit when the reset sequence determines that the attached device is a high-speed device. Ports can be disabled by either a fault condition or by host software. The bit status does not change until the port state has changed. There may be a delay in disabling or enabling a port because of other Host Controller and bus events. When the port is disabled, downstream propagation of data is blocked on this port, except for reset. [1] 1 ECSC Connect Status Change: Logic 1 means change in ECCS. Logic 0 means no change. Default = 0. This bit indicates a change has occurred in the ECCS of the port. The Host Controller sets this bit for all changes to the port device connect status, even if the system software has not cleared an existing connect status change. For example, the insertion status changes two times before the system software has cleared the changed condition, hub hardware will be setting an already-set bit, that is, the bit will remain set. Software clears this bit by writing logic 1 to it. [1] 0 ECCS Current Connect Status: Logic 1 indicates a device is present on port. Logic 0 indicates no device is present. Default = 0. This value reflects the current state of the port and may not directly correspond to the event that caused the ECSC bit to be set. [1] [1] These fields read logic 0, if the PP bit is logic 0. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 87 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 12. Power consumption Table 118 shows the power consumption. Table 118: Power consumption when SEL2PORTS is LOW Power pins group Conditions Total current on pins VCC(I/O)_AUX + VI(VAUX3V3) + VDDA_AUX + VCC(I/O) + VI(VREG3V3) [1] Auxiliary current on pins VCC(I/O)_AUX + VI(VAUX3V3) + VDDA_AUX Current on pins VCC(I/O) + VI(VREG3V3) Typ Unit 57 mA one high-speed device connected to the ISP1563 79 mA two high-speed devices connected to the ISP1563 97 mA three high-speed devices connected to the ISP1563 117 mA four high-speed devices connected to the ISP1563 135 mA 42 mA no device connected to the no device connected to the ISP1563 [2] ISP1563 [2] one high-speed device connected to the ISP1563 64 mA two high-speed devices connected to the ISP1563 82 mA three high-speed devices connected to the ISP1563 102 mA four high-speed devices connected to the ISP1563 120 mA no device connected to the ISP1563 15 mA one high-speed device connected to the ISP1563 15 mA two high-speed devices connected to the ISP1563 15 mA three high-speed devices connected to the ISP1563 15 mA four high-speed devices connected to the ISP1563 15 mA [1] When the SEL2PORTS pin is HIGH, that is, when only two ports are available, the respective current values for the total power are lower by approximately 10 mA than the respective values when SEL2PORTS is LOW. [2] When one to four full-speed or low-speed power devices are connected, the power consumption is comparable to the power consumption when no high-speed devices are connected. There is a difference of only about 2 mA. Table 119 shows the power consumption in S1 and S3 suspend modes. Table 119: Power consumption: S1 and S3 Power state Typ Unit S1 36 mA S3 11 [1] [2] mA [1] When I2C-bus and legacy support are present. [2] For details, refer to the ISP1563 errata. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 88 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 13. Limiting values Table 120: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCC(I/O) Conditions Min Max Unit supply voltage to I/O pins −0.5 +4.6 V VI(VREG3V3) supply voltage to internal regulator −0.5 +4.6 V VCC(I/O)_AUX auxiliary supply voltage to I/O pins −0.5 +4.6 V VI(VAUX3V3) auxiliary supply voltage to internal regulator −0.5 +4.6 V VDDA_AUX auxiliary supply voltage for analog block −0.5 +4.6 V Ilu latch-up current VI < 0 V or VI > VCC(I/O) - 100 mA Vesd electrostatic discharge voltage all pins (ILI < 1 µA) −4 +4 kV Tstg storage temperature −40 +125 °C 14. Recommended operating conditions Table 121: Recommended operating conditions Symbol Parameter Min Typ Max Unit VCC(I/O) supply voltage to I/O pins Conditions 3.0 3.3 3.6 V VI(VREG3V3) supply voltage to internal regulator 3.0 3.3 3.6 V VCC(I/O)_AUX auxiliary supply voltage to I/O pins 3.0 3.3 3.6 V VI(VAUX3V3) auxiliary supply voltage to internal regulator 3.0 3.3 3.6 V VDDA_AUX auxiliary supply voltage for analog block 3.0 3.3 3.6 V VI(3V3) input voltage on 3.3 V buffers 0 - VCC(I/O) + 0.5 V V Tamb ambient temperature −40 - +85 °C 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 89 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 15. Static characteristics Table 122: Static characteristics: I2C-bus interface (SDA and SCL) VCC(I/O) = 3.0 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter VIH Conditions Min Typ Max Unit HIGH-level input voltage 2.1 - - V VIL LOW-level input voltage - - 0.9 V Vhys hysteresis voltage 0.15 - - V VOL LOW-level output voltage - - 0.4 V ICC(susp) suspend supply current - 1 - µA Min Typ Max Unit IOL = 3 mA Table 123: Static characteristics: digital pins VCC(I/O) = 3.0 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V Vhys hysteresis voltage 0.4 - 0.7 V VOL LOW-level output voltage - - 0.4 V VOH HIGH-level output voltage 2.4 - - V Min Typ Max Unit IOL = 3 mA Table 124: Static characteristics: PCI interface block VCC(I/O) = 3.0 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions VIH HIGH-level input voltage 2.0 - 5.5 V VIL LOW-level input voltage 0 - 0.9 V VIPU input pull-up voltage 2.1 - - V ILI input leakage current 0 V < VI < VCC(I/O) −10 - +10 µA VOH HIGH-level output voltage IO = 500 µA 2.7 - - V IO = 1500 µA VOL LOW-level output voltage - - 0.3 V CIN input pin capacitance - - 10 pF Cclk clock capacitance 5 - 12 pF CIDSEL IDSEL pin capacitance - - 8 pF Table 125: Static characteristics: USB interface block (pins DM1 to DM4 and DP1 to DP4) VDDA_AUX = 3.0 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit squelch detection threshold (differential signal amplitude) squelch detected - - 100 mV no squelch detected 150 - - mV disconnect detection threshold (differential signal amplitude) disconnect detected 625 - - mV disconnect not detected - - 525 mV −50 - +500 mV Input levels for high-speed VHSSQ VHSDSC VHSCM data signaling common mode voltage range 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 90 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 125: Static characteristics: USB interface block (pins DM1 to DM4 and DP1 to DP4)…continued VDDA_AUX = 3.0 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit −10 - +10 mV Output levels for high-speed VHSOI idle state VHSOH data signaling HIGH 360 - 440 mV VHSOL data signaling LOW −10 - +10 mV VCHIRPJ Chirp J level (differential voltage) 700 [1] - 1100 mV Chirp K level (differential voltage) −900 [1] - −500 mV VCHIRPK Input levels for full-speed and low-speed VIH HIGH-level input voltage (drive) 2.0 - - V VIHZ HIGH-level input voltage (floating) 2.7 - 3.6 V VIL LOW-level input voltage - - 0.8 V VDI differential input sensitivity 0.2 - - V VCM differential common mode range 0.8 - 2.5 V |VDP − VDM| Output levels for full-speed and low-speed VOH HIGH-level output voltage 2.8 - 3.6 V VOL LOW-level output voltage 0 - 0.3 V VOSE1 SE1 0.8 - - V VCRS output signal crossover point voltage 1.3 - 2.0 V [1] High-speed termination resistor disabled, pull-up resistor connected. Only during reset, when both the hub and device are capable of high-speed operation. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 91 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 16. Dynamic characteristics Table 126: Dynamic characteristics: system clock timing Symbol Parameter Conditions Min Typ Max Unit - 10 - µs Reset tW(RESET_N) pulse width on pin RESET_N crystal oscillator running Crystal oscillator PCI clock fclk external clock input [1] 31 - 33 MHz crystal [2] - 12 - MHz oscillator - 48 - MHz RS series resistance - - 100 Ω CL load capacitance - 18 - pF External clock input VI input voltage 1.65 1.8 1.95 V J external clock jitter - - 50 ppm tCR, tCF rise time and fall time - - 3 ns δclk clock duty factor - 50 - % Min Typ Max Unit - 0 250 ns [1] Recommended accuracy of the clock frequency is 50 ppm for the crystal and oscillator. [2] Suggested values for external capacitors when using a crystal are 22 pF to 27 pF. Table 127: Dynamic characteristics: I2C-bus interface (SDA and SCL) VCC(I/O) = 3.0 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol output fall time VIH to VIL tCF [1] Parameter Conditions 10 < Cb < 400 [1] The capacitive load for each bus line (Cb) is specified in pF. To meet the specification for VOL and the maximum rise time (300 ns), use an external pull-up resistor with RUP(max) = 850/Cb kΩ and RUP(min) = (VCC(I/O) − 0.4)/3 kΩ. Table 128: Dynamic characteristics: PCI interface block VCC(I/O) = 3.0 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit SRout output slew rate (rise, fall) standard load 1 - 4 V/ns [1] Standard load is 10 pF together with a pull-up and pull-down resistor of 10 kΩ. Table 129: Dynamic characteristics: high-speed source electrical characteristics VDDA_AUX = 3.0 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Driver characteristics tHSR high-speed differential rise time 10 % to 90 % 500 - - ps tHSF high-speed differential fall time 90 % to 10 % 500 - - ps ZHSDRV drive output resistance; also serves as includes the RS a high-speed termination resistor 40.5 45 49.5 Ω 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 92 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Table 129: Dynamic characteristics: high-speed source electrical characteristics…continued VDDA_AUX = 3.0 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Clock timing tHSDRAT high-speed data rate 479.76 - 480.24 Mbit/s tHSFRAM micro frame interval 124.9375 - 125.0625 µs tHSRFI consecutive micro frame interval difference 1 - four high-speed bit times ns Table 130: Dynamic characteristics: full-speed source electrical characteristics VDDA_AUX = 3.0 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Driver characteristics tFR rise time CL = 50 pF; 10 % to 90 % of |VOH − VOL| 4 - 20 ns tFF fall time CL = 50 pF; 90 % to 10 % of |VOH − VOL| 4 - 20 ns tFRFM differential rise and fall time matching 90 - 111.1 % −2 - +5 ns 160 - 175 ns 82 - - ns −40 - +100 ns Data timing; see Figure 10 tFDEOP source jitter for differential transition to SE0 transition full-speed timing tFEOPT source SE0 interval of EOP tFEOPR receiver SE0 interval of EOP tLDEOP source jitter for differential transition to SE0 transition tLEOPT source SE0 interval of EOP 1.25 - 1.5 µs tLEOPR receiver SE0 interval of EOP 670 - - ns tFST width of SE0 interval during the differential transaction - - 14 ns Min Typ Max Unit low-speed timing Table 131: Dynamic characteristics: low-speed source electrical characteristics VDDA_AUX = 3.0 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Driver characteristics tLR rise time 75 - 300 ns tLF fall time 75 - 300 ns tLRFM rise and fall time matching 90 - 125 % 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 93 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 16.1 Timing Table 132: PCI clock and I/O timing Symbol Parameter Conditions Min Typ Max Unit PCI clock timing; see Figure 7 Tcyc(PCICLK) PCICLK cycle time 30 - 32 ns tHIGH(PCICLK) PCICLK HIGH time 11 - - ns tLOW(PCICLK) PCICLK LOW time 11 - - ns SRPCICLK PCICLK slew rate 1 - 4 V/ns SRRST# RST# slew rate 50 - - mV/ns 7 - - ns 10 - - ns 0 - - ns 2 - 11 ns 2 - 12 ns PCI input timing; see Figure 8 tsu(PCICLK)bs setup time to PCICLK (bus signal) tsu(PCICLK)ptp setup time to PCICLK (point-to-point) th(PCICLK) input hold time from PCICLK [1] PCI output timing; see Figure 9 tval(PCICLK)bs PCICLK to signal valid delay (bus signal) tval(PCICLK)ptp PCICLK to signal valid delay (point-to-point) tdZ(act) float to active delay 2 - - ns td(act)Z active to float delay - - 28 ns reset active time after CLK stable 1 - - ms [1] PCI reset timing trst [1] REQ# and GNT# are point-to-point signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All others are bus signals. Tcyc(PCICLK) tHIGH(PCICLK) tLOW(PCICLK) 0.6VCC(I/O) 0.5VCC(I/O) minimum value 0.4VCC(I/O) 0.4VCC(I/O) 0.3VCC(I/O) 0.2VCC(I/O) 004aaa604 Fig 7. PCI clock. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 94 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 0.6VCC(I/O) 0.4VCC(I/O) CLK tsu(PCICLK)bs; tsu(PCICLK)ptp 0.2VCC(I/O) th(PCICLK) 0.6VCC(I/O) INPUT DELAY 0.4VCC(I/O) inputs valid 0.2VCC(I/O) 004aaa605 Fig 8. PCI input timing. 0.6VCC(I/O) 0.4VCC(I/O) CLK 0.2VCC(I/O) tval(PCICLK)bs; tval(PCICLK)ptp 0.615VCC(I/O) (falling edge) OUTPUT DELAY 0.285VCC(I/O) (rising edge) OUTPUT tdZ(act) td(act)Z 004aaa606 Fig 9. PCI output timing. tUSBbit +3.3 V crossover point extended crossover point differential data lines 0V differential data to SE0/EOP skew N × tUSBbit + t DEOP source EOP width: t EOPT receiver EOP width: t EOPR 004aaa704 tUSBbit is the bit duration time (USB data). tDEOP is the source jitter for differential transition to SE0 transition. Full-speed timing symbols have a subscript prefix ‘F’; low-speed timing symbols have a subscript prefix ‘L’. Fig 10. USB source differential data-to-EOP transition skew and EOP width. 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 95 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 17. Package outline LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 14 x 1.4 mm SOT420-1 c y X A 65 64 96 97 ZE e E HE A A2 A 1 (A 3) θ wM Lp bp pin 1 index L detail X 33 32 128 1 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.23 0.13 0.20 0.09 14.1 13.9 14.1 13.9 0.4 HD HE 16.15 16.15 15.85 15.85 L Lp v w y 1 0.75 0.45 0.2 0.07 0.08 Z D(1) Z E(1) 0.95 0.65 0.95 0.65 θ 7o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT420-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-11-03 03-02-20 MS-026 Fig 11. Package outline SOT420-1 (LQFP128). 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 96 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 18. Soldering 18.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 18.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 °C to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: • below 225 °C (SnPb process) or below 245 °C (Pb-free process) – for all BGA, HTSSON..T and SSOP..T packages – for packages with a thickness ≥ 2.5 mm – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. • below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 18.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 97 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 °C and 320 °C. 18.5 Package related soldering information Table 133: Suitability of surface mount IC packages for wave and reflow soldering methods Package [1] Soldering method Wave Reflow [2] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable [4] suitable PLCC [5], SO, SOJ suitable suitable not recommended [5] [6] suitable SSOP, TSSOP, VSO, VSSOP not recommended [7] suitable CWQCCN..L [8], PMFP [9], WQCCN..L [8] not suitable LQFP, QFP, TQFP [1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. [2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. [3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 9397 750 14224 Product data sheet not suitable © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 98 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. [6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. [9] Hot bar soldering or manual soldering is suitable for PMFP packages. 19. Abbreviations Table 134: Abbreviations Acronym Description BIOS Basic Input Output System CMOS Complementary Metal-Oxide Semiconductor DID Device ID EEPROM Electrically Erasable Programmable Read-Only Memory EHCI Enhanced Host Controller Interface EMI Electro-Magnetic Interference ESD Electro-Static Discharge HC Host Controller HCCA Host Controller Communication Area HCD Host Controller Driver OHCI Open Host Controller Interface OS Operating System PCI Peripheral Component Interconnect PCI-SIG PCI-Special Interest Group PLL Phase-Locked Loop PM Power Management PMC Power Management Capabilities PME Power Management Event PMCSR Power Management Control/Status POR Power-On Reset POST Power On Self Test STB Set-Top Box USB Universal Serial Bus VGA Video Graphics Array VID Vendor ID 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 99 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 20. References [1] Universal Serial Bus Specification Rev. 2.0 [2] Open Host Controller Interface Specification for USB Rev. 1.0a [3] Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 [4] PCI Local Bus Specification Rev. 2.2 [5] PCI Bus Power Management Interface Specification Rev. 1.1 [6] The I2C-bus Specification, Version 2.1. 21. Revision history Table 135: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes ISP1563_1 20050714 Product data sheet - 9397 750 14224 - 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 100 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 22. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 23. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 24. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 25. Trademarks Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — wordmark and logo are trademarks of Koninklijke Philips Electronics N.V. 26. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 101 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 27. Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Ordering information . . . . . . . . . . . . . . . . . . . . .3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 PCI configuration space registers of OHCI1, OHCI2 and EHCI . . . . . . . . . . . . . . . . . . . . . . .16 VID - Vendor ID register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 DID - Device ID register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Command register (address 04h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Command register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Status register (address 06h) bit allocation . . .19 Status register (address 06h) bit description . .19 REVID - Revision ID register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .20 Class Code register (address 09h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Class Code register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 CLS - CacheLine Size register (address 0Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . .22 LT - Latency Timer register (address 0Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .22 Header Type register (address 0Eh) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Header Type register (address 0Eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 BAR 0 - Base Address register 0 (address 10h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .23 SVID - Subsystem Vendor ID register (address 2Ch) bit description . . . . . . . . . . . . . .23 SID - Subsystem ID register (address 2Eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .23 CP - Capabilities Pointer register (address 34h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .24 IL - Interrupt Line register (address 3Ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 IP - Interrupt Pin register (address 3Dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Min_Gnt - Minimum Grant register (address 3Eh) bit description . . . . . . . . . . . . . .24 Max_Lat - Maximum Latency register (address 3Fh) bit description . . . . . . . . . . . . . .25 EHCI-specific PCI registers . . . . . . . . . . . . . . .25 SBRN - Serial Bus Release Number register (address 60h) bit description . . . . . . . . . . . . . .26 FLADJ - Frame Length Adjustment register (address 61h) bit allocation . . . . . . . . . . . . . . . 26 Table 28: FLADJ - Frame Length Adjustment register (address 61h) bit description . . . . . . . . . . . . . . 26 Table 29: PORTWAKECAP - Port Wake Capability register (address 62h) bit description . . . . . . . 27 Table 30: Power Management registers . . . . . . . . . . . . . 27 Table 31: Cap_ID - Capability Identifier register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 32: Next_Item_Ptr - Next Item Pointer register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 33: PMC - Power Management Capabilities register bit allocation . . . . . . . . . . . . . . . . . . . . 28 Table 34: PMC - Power Management Capabilities register bit description . . . . . . . . . . . . . . . . . . . 28 Table 35: PMCSR - Power Management Control/Status register bit allocation . . . . . . . . . . . . . . . . . . . . 30 Table 36: PMCSR - Power Management Control/Status register bit description . . . . . . . . . . . . . . . . . . . 30 Table 37: PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit allocation . . . . 31 Table 38: PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit description . . . 32 Table 39: PCI bus power and clock control . . . . . . . . . . . 32 Table 40: Data register bit description . . . . . . . . . . . . . . 32 Table 41: USB Host Controller registers . . . . . . . . . . . . . 36 Table 42: HcRevision - Host Controller Revision register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 43: HcRevision - Host Controller Revision register bit description . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 44: HcControl - Host Controller Control register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 45: HcControl - Host Controller Control register bit description . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 46: HcCommandStatus - Host Controller Command Status register bit allocation . . . . . 42 Table 47: HcCommandStatus - Host Controller Command Status register bit description . . . . 42 Table 48: HcInterruptStatus - Host Controller Interrupt Status register bit allocation . . . . . . . 43 Table 49: HcInterruptStatus - Host Controller Interrupt Status register bit description . . . . . . 44 Table 50: HcInterruptEnable - Host Controller Interrupt Enable register bit allocation . . . . . . . 45 Table 51: HcInterruptEnable - Host Controller Interrupt Enable register bit description . . . . . 45 Table 52: HcInterruptDisable - Host Controller Interrupt Disable register bit allocation . . . . . . 46 Table 53: HcInterruptDisable - Host Controller continued >> 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 102 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Interrupt Disable register bit description . . . . .47 Table 54: HcHCCA - Host Controller Communication Area register bit allocation . . . . . . . . . . . . . . . .48 Table 55: HcHCCA - Host Controller Communication Area register bit description . . . . . . . . . . . . . . .48 Table 56: HcPeriodCurrentED - Host Controller Period Current Endpoint Descriptor register bit allocation . . . . . . . . . . . . . . . . . . . .48 Table 57: HcPeriodCurrentED - Host Controller Period Current Endpoint Descriptor register bit description . . . . . . . . . . . . . . . . . . .49 Table 58: HcControlHeadED - Host Controller Control Head Endpoint Descriptor register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Table 59: HcControlHeadED - Host Controller Control Head Endpoint Descriptor register bit description . . . . . . . . . . . . . . . . . . . . . . . . .50 Table 60: HcControlCurrentED - Host Controller Control Current Endpoint Descriptor register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Table 61: HcControlCurrentED - Host Controller Control Current Endpoint Descriptor register bit description . . . . . . . . . . . . . . . . . . . . . . . . .50 Table 62: HcBulkHeadED - Host Controller Bulk Head Endpoint Descriptor register bit allocation . . . .51 Table 63: HcBulkHeadED - Host Controller Bulk Head Endpoint Descriptor register bit description . . .51 Table 64: HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Table 65: HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit description . . . . . . . . . . . . . . . . . . . . . . . . .52 Table 66: HcDoneHead - Host Controller Done Head register bit allocation . . . . . . . . . . . . . . . . . . . .52 Table 67: HcDoneHead - Host Controller Done Head register bit description . . . . . . . . . . . . . . . . . . .53 Table 68: HcFmInterval - Host Controller Frame Interval register bit allocation . . . . . . . . . . . . . .53 Table 69: HcFmInterval - Host Controller Frame Interval register bit description . . . . . . . . . . . . .54 Table 70: HcFmRemaining - Host Controller Frame Remaining register bit allocation . . . . . . . . . . .54 Table 71: HcFmRemaining - Host Controller Frame Remaining register bit description . . . . . . . . . .55 Table 72: HcFmNumber - Host Controller Frame Number register bit allocation . . . . . . . . . . . . .55 Table 73: HcFmNumber - Host Controller Frame Number register bit description . . . . . . . . . . . .56 Table 74: HcPeriodicStart - Host Controller Periodic Start register bit allocation . . . . . . . . . . . . . . . .56 Table 75: HcPeriodicStart - Host Controller Periodic Start register bit description . . . . . . . . . . . . . . 56 Table 76: HcLSThreshold - Host Controller LS Threshold register bit allocation . . . . . . . . . . . 57 Table 77: HcLSThreshold - Host Controller LS Threshold register bit description . . . . . . . . . . 57 Table 78: HcRhDescriptorA - Host Controller Root Hub Descriptor A register bit allocation . . . . . . 57 Table 79: HcRhDescriptorA - Host Controller Root Hub Descriptor A register bit description . . . . . 58 Table 80: HcRhDescriptorB - Host Controller Root Hub Descriptor B register bit allocation . . . . . . 59 Table 81: HcRhDescriptorB - Host Controller Root Hub Descriptor B register bit description . . . . . 60 Table 82: HcRhStatus - Host Controller Root Hub Status register bit allocation . . . . . . . . . . . . . . 60 Table 83: HcRhStatus - Host Controller Root Hub Status register bit description . . . . . . . . . . . . . 61 Table 84: HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit allocation . . . 62 Table 85: HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit description . . 62 Table 86: Legacy support registers . . . . . . . . . . . . . . . . . 66 Table 87: Emulated registers . . . . . . . . . . . . . . . . . . . . . 66 Table 88: HceControl - Host Controller Emulation Control register bit allocation . . . . . . . . . . . . . . 66 Table 89: HceControl - Host Controller Emulation Control register bit description . . . . . . . . . . . . 67 Table 90: HceInput - Host Controller Emulation Input register bit allocation . . . . . . . . . . . . . . . . . . . . 68 Table 91: HceInput - Host Controller Emulation Input register bit description . . . . . . . . . . . . . . . . . . . 68 Table 92: HceOutput - Host Controller Emulation Output register bit allocation . . . . . . . . . . . . . . 68 Table 93: HceOutput - Host Controller Emulation Output register bit description . . . . . . . . . . . . . 69 Table 94: HceStatus - Host Controller Emulation Status register bit allocation . . . . . . . . . . . . . . 69 Table 95: HceStatus - Host Controller Emulation Status register bit description . . . . . . . . . . . . . 70 Table 96: CAPLENGTH/HCIVERSION - Capability Registers Length/Host Controller Interface Version Number register bit allocation . . . . . . . 70 Table 97: CAPLENGTH/HCIVERSION - Capability Registers Length/Host Controller Interface Version Number register bit description . . . . . 71 Table 98: HCSPARAMS - Host Controller Structural Parameters register bit allocation . . . . . . . . . . 71 Table 99: HCSPARAMS - Host Controller Structural Parameters register bit description . . . . . . . . . 72 Table 100:HCCPARAMS - Host Controller Capability continued >> 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 103 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller Parameters register bit allocation . . . . . . . . . .73 Table 101:HCCPARAMS - Host Controller Capability Parameters register bit description . . . . . . . . .73 Table 102:USBCMD - USB Command register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Table 103:USBCMD - USB Command register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Table 104:USBSTS - USB Status register bit allocation . .77 Table 105:USBSTS - USB Status register bit description 77 Table 106:USBINTR - USB Interrupt Enable register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Table 107:USBINTR - USB Interrupt Enable register bit description . . . . . . . . . . . . . . . . . . . . . . . . .79 Table 108:FRINDEX - Frame Index register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Table 109:FRINDEX - Frame Index register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Table 110:PERIODICLISTBASE - Periodic Frame List Base Address register bit allocation . . . . . . . .81 Table 111:PERIODICLISTBASE - Periodic Frame List Base Address register bit description . . . . . . .82 Table 112:ASYNCLISTADDR - Current Asynchronous List Address register bit allocation . . . . . . . . . .82 Table 113:ASYNCLISTADDR - Current Asynchronous List Address register bit description . . . . . . . . .83 Table 114:CONFIGFLAG - Configure Flag register bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Table 115:CONFIGFLAG - Configure Flag register bit description . . . . . . . . . . . . . . . . . . . . . . . . .83 Table 116:PORTSC 1, 2, 3, 4 - Port Status and Control, 1, 2, 3, 4 register bit allocation . . . . . .84 Table 117:PORTSC 1, 2, 3, 4 - Port Status and Control, 1, 2, 3, 4 register bit description . . . . .84 Table 118:Power consumption when SEL2PORTS is LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Table 119:Power consumption: S1 and S3 . . . . . . . . . . . .88 Table 120:Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .89 Table 121:Recommended operating conditions . . . . . . . .89 Table 122:Static characteristics: I2C-bus interface (SDA and SCL) . . . . . . . . . . . . . . . . . . . . . . . .90 Table 123:Static characteristics: digital pins . . . . . . . . . . .90 Table 124:Static characteristics: PCI interface block . . . .90 Table 125:Static characteristics: USB interface block (pins DM1 to DM4 and DP1 to DP4) . . . . . . . .90 Table 126:Dynamic characteristics: system clock timing .92 Table 127:Dynamic characteristics: I2C-bus interface (SDA and SCL) . . . . . . . . . . . . . . . . . . . . . . . .92 Table 128:Dynamic characteristics: PCI interface block . .92 Table 129:Dynamic characteristics: high-speed source electrical characteristics . . . . . . . . . . . . . . . . .92 Table 130:Dynamic characteristics: full-speed source electrical characteristics . . . . . . . . . . . . . . . . . 93 Table 131:Dynamic characteristics: low-speed source electrical characteristics . . . . . . . . . . . . . . . . . 93 Table 132:PCI clock and I/O timing . . . . . . . . . . . . . . . . . 94 Table 133:Suitability of surface mount IC packages for wave and reflow soldering methods . . . . . . 98 Table 134:Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 135:Revision history . . . . . . . . . . . . . . . . . . . . . . . 100 continued >> 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 104 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 28. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . .5 Power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . .13 Power supply connection. . . . . . . . . . . . . . . . . . .14 EEPROM connection diagram. . . . . . . . . . . . . . .33 Information loading from EEPROM.. . . . . . . . . . .34 PCI clock.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 PCI input timing.. . . . . . . . . . . . . . . . . . . . . . . . . .95 PCI output timing. . . . . . . . . . . . . . . . . . . . . . . . .95 USB source differential data-to-EOP transition skew and EOP width. . . . . . . . . . . . . . . . . . . . . . .95 Fig 11. Package outline SOT420-1 (LQFP128). . . . . . . .96 continued >> 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 105 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 29. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . 12 7.1 OHCI Host Controller . . . . . . . . . . . . . . . . . . . 12 7.2 EHCI Host Controller . . . . . . . . . . . . . . . . . . . 12 7.3 Dynamic port-routing logic . . . . . . . . . . . . . . . 12 7.4 Hi-Speed USB analog transceivers . . . . . . . . 12 7.5 LED indicators for downstream ports . . . . . . . 12 7.6 Power management . . . . . . . . . . . . . . . . . . . . 12 7.7 Legacy support . . . . . . . . . . . . . . . . . . . . . . . . 13 7.8 Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . 13 7.9 Power-On Reset (POR) . . . . . . . . . . . . . . . . . 13 7.10 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1 PCI interface . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.1.1 PCI configuration space . . . . . . . . . . . . . . . . . 15 8.1.2 PCI initiator and target . . . . . . . . . . . . . . . . . . 15 8.2 PCI configuration registers . . . . . . . . . . . . . . . 15 8.2.1 PCI configuration header registers . . . . . . . . . 16 8.2.1.1 Vendor ID register. . . . . . . . . . . . . . . . . . . . . . 17 8.2.1.2 Device ID register . . . . . . . . . . . . . . . . . . . . . . 17 8.2.1.3 Command register . . . . . . . . . . . . . . . . . . . . . 17 8.2.1.4 Status register. . . . . . . . . . . . . . . . . . . . . . . . . 19 8.2.1.5 Revision ID register . . . . . . . . . . . . . . . . . . . . 20 8.2.1.6 Class Code register . . . . . . . . . . . . . . . . . . . . 21 8.2.1.7 CacheLine Size register . . . . . . . . . . . . . . . . . 21 8.2.1.8 Latency Timer register . . . . . . . . . . . . . . . . . . 22 8.2.1.9 Header Type register . . . . . . . . . . . . . . . . . . . 22 8.2.1.10 Base Address register 0 . . . . . . . . . . . . . . . . . 22 8.2.1.11 Subsystem Vendor ID register . . . . . . . . . . . . 23 8.2.1.12 Subsystem ID register . . . . . . . . . . . . . . . . . . 23 8.2.1.13 Capabilities Pointer register . . . . . . . . . . . . . . 23 8.2.1.14 Interrupt Line register . . . . . . . . . . . . . . . . . . . 24 8.2.1.15 Interrupt Pin register . . . . . . . . . . . . . . . . . . . . 24 8.2.1.16 Min_Gnt and Max_Lat registers . . . . . . . . . . . 24 8.2.1.17 TRDY Timeout register . . . . . . . . . . . . . . . . . . 25 8.2.1.18 Retry Timeout register . . . . . . . . . . . . . . . . . . 25 8.2.2 Enhanced Host Controller-specific PCI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.2.2.1 SBRN register. . . . . . . . . . . . . . . . . . . . . . . . . 25 8.2.2.2 FLADJ register . . . . . . . . . . . . . . . . . . . . . . . . 8.2.2.3 PORTWAKECAP register. . . . . . . . . . . . . . . . 8.2.3 Power management registers. . . . . . . . . . . . . 8.2.3.1 Cap_ID register . . . . . . . . . . . . . . . . . . . . . . . 8.2.3.2 Next_Item_Ptr register . . . . . . . . . . . . . . . . . . 8.2.3.3 PMC register . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.3.4 PMCSR register . . . . . . . . . . . . . . . . . . . . . . . 8.2.3.5 PMCSR_BSE register . . . . . . . . . . . . . . . . . . 8.2.3.6 Data register. . . . . . . . . . . . . . . . . . . . . . . . . . 9 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 9.1 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Hardware connections . . . . . . . . . . . . . . . . . . 9.3 Information loading from EEPROM . . . . . . . . 10 Power management. . . . . . . . . . . . . . . . . . . . . 10.1 PCI bus power states . . . . . . . . . . . . . . . . . . . 10.2 USB bus states . . . . . . . . . . . . . . . . . . . . . . . 11 USB Host Controller registers . . . . . . . . . . . . 11.1 OHCI USB Host Controller operational registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1.1 HcRevision register . . . . . . . . . . . . . . . . . . . . 11.1.2 HcControl register . . . . . . . . . . . . . . . . . . . . . 11.1.3 HcCommandStatus register . . . . . . . . . . . . . . 11.1.4 HcInterruptStatus register . . . . . . . . . . . . . . . 11.1.5 HcInterruptEnable register . . . . . . . . . . . . . . . 11.1.6 HcInterruptDisable register . . . . . . . . . . . . . . 11.1.7 HcHCCA register . . . . . . . . . . . . . . . . . . . . . . 11.1.8 HcPeriodCurrentED register. . . . . . . . . . . . . . 11.1.9 HcControlHeadED register. . . . . . . . . . . . . . . 11.1.10 HcControlCurrentED register . . . . . . . . . . . . . 11.1.11 HcBulkHeadED register . . . . . . . . . . . . . . . . . 11.1.12 HcBulkCurrentED register . . . . . . . . . . . . . . . 11.1.13 HcDoneHead register. . . . . . . . . . . . . . . . . . . 11.1.14 HcFmInterval register. . . . . . . . . . . . . . . . . . . 11.1.15 HcFmRemaining register . . . . . . . . . . . . . . . . 11.1.16 HcFmNumber register . . . . . . . . . . . . . . . . . . 11.1.17 HcPeriodicStart register . . . . . . . . . . . . . . . . . 11.1.18 HcLSThreshold register . . . . . . . . . . . . . . . . . 11.1.19 HcRhDescriptorA register . . . . . . . . . . . . . . . 11.1.20 HcRhDescriptorB register . . . . . . . . . . . . . . . 11.1.21 HcRhStatus register . . . . . . . . . . . . . . . . . . . . 11.1.22 HcRhPortStatus[4:1] register . . . . . . . . . . . . . 11.2 USB legacy support registers . . . . . . . . . . . . 11.2.1 HceControl register . . . . . . . . . . . . . . . . . . . . 11.2.2 HceInput register . . . . . . . . . . . . . . . . . . . . . . 11.2.3 HceOutput register . . . . . . . . . . . . . . . . . . . . . 11.2.4 HceStatus register . . . . . . . . . . . . . . . . . . . . . 11.3 EHCI controller capability registers . . . . . . . . 26 26 27 27 27 28 30 31 32 33 33 33 34 34 34 35 35 38 38 39 41 43 45 46 48 48 49 50 51 51 52 53 54 55 56 57 57 59 60 61 66 66 67 68 69 70 continued >> 9397 750 14224 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 14 July 2005 106 of 107 ISP1563 Philips Semiconductors HS USB PCI Host Controller 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.4.6 11.4.7 11.4.8 12 13 14 15 16 16.1 17 18 18.1 18.2 18.3 18.4 18.5 19 20 21 22 23 24 25 26 CAPLENGTH/HCIVERSION register . . . . . . . 70 HCSPARAMS register . . . . . . . . . . . . . . . . . . 71 HCCPARAMS register . . . . . . . . . . . . . . . . . . 73 HCSP-PORTROUTE register . . . . . . . . . . . . . 74 Operational registers of Enhanced USB Host Controller . . . . . . . . . . . . . . . . . . . . . . . . 74 USBCMD register . . . . . . . . . . . . . . . . . . . . . . 74 USBSTS register . . . . . . . . . . . . . . . . . . . . . . 76 USBINTR register . . . . . . . . . . . . . . . . . . . . . . 78 FRINDEX register . . . . . . . . . . . . . . . . . . . . . . 80 PERIODICLISTBASE register . . . . . . . . . . . . 81 ASYNCLISTADDR register . . . . . . . . . . . . . . . 82 CONFIGFLAG register . . . . . . . . . . . . . . . . . . 83 PORTSC registers 1, 2, 3, 4 . . . . . . . . . . . . . . 83 Power consumption. . . . . . . . . . . . . . . . . . . . . 88 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 89 Recommended operating conditions. . . . . . . 89 Static characteristics. . . . . . . . . . . . . . . . . . . . 90 Dynamic characteristics . . . . . . . . . . . . . . . . . 92 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 96 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 97 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 97 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 98 Package related soldering information . . . . . . 98 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 99 References . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Revision history . . . . . . . . . . . . . . . . . . . . . . . 100 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 101 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Contact information . . . . . . . . . . . . . . . . . . . 101 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 14 July 2005 Document number: 9397 750 14224 Published in The Netherlands