NSC PC87351

May 1998
PC87351 PC98 and ACPI Compliant SuperI/O with
System Wake-Up Control
Highlights
General Description
Outstanding Features
The PC87351, a member of National Semiconductor’s SuperI/O family of integrated PC peripherals, is a 128-pin,
PC98 and ACPI compliant SuperI/O that offers a single-chip
solution to the most commonly used ISA peripherals.
The PC87351 incorporates: a Floppy Disk Controller (FDC)
which is available also on the Parallel Port pins as a multiplexed option (PPM), two enhanced Serial Ports, Infrared
Comunication Port (HP-SIR, Sharp-IR, and Consumer
Electronics-IR), a full IEEE 1284 Parallel Port, a Keyboard
and Mouse Controller (KBC), System Wake-Up Control
(SWC), General-Purpose Input/Output (GPIO) Ports with
assert interrupt capability, and Fan Speed Control (FSC).
•
•
Fan Speed Control for two fans
•
System Wake-Up Control powered by VSB, generates
power-up request in response to preprogrammed keyboard or mouse sequence, modem, telephone ring,
and two general-purpose events without an external
clock
•
•
•
Serial or parallel IRQ support
11 General-Purpose I/O Ports, bi-directional, with interrupt assertion capability
Programmable write protect for Floppy Disk Controller
Power-fail recovery support
Block Diagram
Parallel Port/
Floppy Drive
Interface
VSB
VBAT
Serial
Interface
Serial Infrared
Interface Interface
Floppy Drive
Interface
Serial Port 1
Serial Port 2
with IR
Floppy Disk
Controller
System Wake-Up
Control
Wake-Up PWUREQ
Events
ISA
Interface SERIRQ
PPM
IEEE 1284
Parallel Port
Fan Speed Control
General-Purpose
I/O
FANOUT0 FANOUT1
I/O Ports
Host Interface
Keyboard and Mouse
Controller
Keyboard and Mouse Ports
Interface
IBM®, MicroChannel®, PC-AT® and PS/2® are registered trademarks of International Business Machines Corporation.
Microsoft® and Windows® are registered trademarks of Microsoft Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
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PC87351 PC98 and ACPI Compliant SuperI/O with System Wake-Up Control
PRELIMINARY
Highlights (Continued)
•
Features
•
—
—
—
—
—
—
—
Software compatible with the 16550A and the 16450
Shadow register support for write-only bit monitoring
UART data rates up to 1.5 Mbaud
HP-SIR
ASK-IR option of SHARP-IR
DASK-IR option of SHARP-IR
Consumer Remote Control supports RC-5, RC-6,
NEC, RCA and RECS 80
— Non-standard DMA support − 1 or 2 channels
PC98 and ACPI Compliant
— PnP Configuration Register structure
— Flexible resource allocation for all logical devices
❏ Relocatable base address
❏ 9 Parallel IRQ or 15 Serial IRQ routing options
❏ 3 optional 8-bit DMA channels (where applicable)
•
Floppy Disk Controller (FDC)
•
— Software compatible with the PC8477, which contains a superset of the FDC functions in the
µDP8473, the NEC µPD765A and the N82077
— 16-byte FIFO
— Burst and non-burst modes
— High-performance, digital data separator that does
not require any external filter components
— Standard 5.25" and 3.5" Floppy Disk Drive (FDD)
support
— Perpendicular recording drive support
— Three-mode FDD support
— Full support for IBM Tape Drive Register (TDR) implementation of AT and PS/2 drive types
— Programmable write protect
•
Parallel Port
•
•
System Wake-Up Control (SWC)
— Power-up request upon detection of Keyboard,
Mouse, RI1, RI2, RING, PME1 and PME2 activity, as
follows:
❏ Preprogrammed Keyboard or Mouse sequence
❏ External modem ring on serial ports
Parallel Port Multiplexer (PPM)
❏ Ring pulse or pulse train on the RING input
❏ General purpose events, PME1 and PME2
— Optional routing of power-up request on IRQ line
— Powered by VSB
— Battery-backed wake-up setup
— Power-fail recovery support
Serial Port 1
— Software compatible with the 16550A and the 16450
— Shadow register support for write-only bit monitoring
— UART data rates up to 1.5 Mbaud
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11 General-Purpose Bi-Directional I/O (GPIO) Ports
— 11 GPIO pins with interrupt assertion capability
— Programmable drive type for each output pin (opendrain, push-pull or output disable)
— Programmable option for internal pull-up resistor on
each input pin
— Output lock option
— Back-drive protection circuit
— Additional set of FDC signals multiplexed on Parallel
Port pins
— Optional connection of additional, external FDD on
Parallel Port connector
•
Keyboard and Mouse Controller (KBC)
— 8-bit microcontroller
— Software compatible with the 8042AH and PC87911
microcontrollers
— 2 KB custom-designed program ROM
— 256 bytes RAM for data
— Four programmable dedicated open-drain I/O lines
— Asynchronous access to two data registers and one
status register during normal operation
— Support for both interrupt and polling
— 93 instructions
— 8-bit timer/counter
— Support for binary and BCD arithmetic
— Operation at 8 MHz,12 MHz or 16 MHz (programmable option)
— Can be customized by using the PC87323, which includes a RAM-based KBC as a development platform for KBC code
— Software or hardware control
— Enhanced Parallel Port (EPP) compatible with new
version EPP 1.9 and IEEE 1284 compliant
— EPP support for version EPP 1.7 of the Xircom specification
— EPP support as mode 4 of the Extended Capabilities
Port (ECP)
— IEEE 1284 compliant ECP, including level 2
— Selection of internal pull-up or pull-down resistor for
Paper End (PE) pin
— PCI bus utilization reduction by supporting a demand DMA mode mechanism and a DMA fairness
mechanism
— Protection circuit that prevents damage to the parallel port when a printer connected to it powers up or
is operated at high voltages, even if the device is in
power-down
— Output buffers that can sink and source 14 mA
•
Serial Port 2 with Infrared
2
Highlights
•
(Continued)
Fan Speed Control
— Supports different fan types
— Two speed control lines with Pulse Width Modulation
(PWM)
❏ Output signal in the range of 6 Hz to 93.75 KHz
❏ Duty cycle resolution of 1/256
•
Clock Sources
— 48 MHz clock input
— On-chip low frequency clock generator for wake-up
— 33 MHz PCI clock input for Serial IRQ
3
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Datasheet Revision Record
Revision Date
Status
Comments
January 1998
Advanced Information First pass with pin assignment
March 1998
Preliminary
Implemented:
Item 1, Important Notice, pin reassignment
May 1998
Preliminary
Implemented:
Items 2-31 below
Paginated Datasheet Revision Record in datasheet body
Item
Topic
Change/Correction
Location
2
Pin description
Table describing KBCLK, KBDAT, MCLK and MDAT
signals enhanced to identify pin drivers
Section 1.4.7
3
PPM power save mode
All references deleted
Chapter 2
4
Device architecture
9 logical devices
Section 2.1
5
Index 74h, 75h
DMA Channel Select 0, 1
Modified
Section 2.2.3,
Table 2-7
6
VSB Power-Up Reset
Hardware reset explanation modified
Section 2.2.5
7
New section added
REGISTER TYPE ABBREVIATIONS added before
the existing section; all subsequent numbering
changed
Section 2.3
8
SuperI/O Configuration 1 Register
Bit 3
Reserved
Section 2.4.3
9
SuperI/O Configuration 2 Register
Bits
6 5
Function
00
01
10
11
GPIO17
KBRST (default)
P12
PNF (PPM mode enabled)
Bits
2 1 0
Function
00X
011
010
10X
11X
GPIO14 (default)
GPIO14
IRQ9
IRRX2/IRSL0
P17
Section 2.4.4
10
SuperI/O Revision ID Register
Location and Type added
11
Keyboard and Mouse Controller
All references to TEST0 and TEST1 changed to T0 Section 2.11.1
and T1, respectively.
12
Implementation
Ports 1 and 2 description deleted
Section 2.12.2
13
GPIO Configuration Registers’ Access
Drawing modified
Figure 2-6
14
GPIO Pin Configuration Select Register
Bits 5-4
01, 10: Binary value of the port number, 1-2 respectively Section 2.12.4
11: Reserved
15
Fan Speed Control
General Description modified; nomenclature of Fan Section 2.13
Control Duty Cycle and Fan Control Pre-Scale
registers changed; references to Fan Speed Monitor
deleted; configuration parameters (Reset and Type)
modified
16
System events
Number of events changed to seven
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4
Section 2.4.7
Section 3.2
Datasheet Revision Record
Item
(Continued)
Topic
Change/Correction
Location
17
Keyboard Data Shift Register
Description modified
Section 3.4.6
18
Mouse Data Shift Register
Description modified
Section 3.4.7
19
Ports with fewer than 8 bits
Implementation description
Chapter 4
20
Interrupt Assertion and Handling
Bit nomenclature modified
Section 4.3
21
GPIO Pin Configuration Access Register Bit nomenclature and descriptions changed
Section 4.4.1
22
GPIO Data Out Register
Bitmap and Reset values added
Section 4.4.3
23
GPIO Data In Register
Bitmap and Reset values added
Section 4.4.4
24
GPIO Interrupt Enable Register
Bitmap and Reset values added
Section 4.4.5
25
GPIO Status Register
Bitmap and Reset values added
Section 4.4.6
26
Functional Description
Corrected and enhanced
Section 5.2
27
Fan Control Duty Cycle Register
Bits 7-0
00h: PWM output is continuously low
Section 5.3.3
01h-FEh: PWM output is high for [Duty Cycle Value] clock
cycles and low for [256-Duty Cycle Value] clock cycles
FFh: PWM output is continuously high
28
Device Specifications
Timing diagrams drawn more precisely
Chapter 11
29
VBAT Battery Supply Current
Conditions and Max modified
Section 11.1.4
30
Host Interface I/O Cycle Timing
tRDYA, tRDYl and tRWl added to table; footnote 2 added Section 11.2.3
to table; IOCHRDY timing diagram added
31
Serial IRQ Timing
Output timing diagram modified
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5
Section 11.2.6
Contents at a Glance
This datasheet is organized to reflect two major topics: device specific issues (Highlights through Chapter 2), and proprietary functional blocks (Chapters 3 through 10). Chapter 11 summarizes the AC/DC device characteristics.
Highlights ................................................................................................................................................ 1
This chapter provides a description and block diagram of the PC87351 major functional blocks, the features that make this
device outstanding as compared with comparable devices, and the features of each functional block.
Datasheet Revision Record ................................................................................................................... 4
This chapter serves two functions: it provides a record of the datasheet revisions; it documents the major changes of this
revision as compared with the previous one. Each change is cross-referenced and linked to the change location within the
datasheet.
1
Signal/Pin Connection and Description ............................................................................................. 11
This chapter includes four major sections: a connection diagram that shows all pins and their related signals; an alphabetical
directory of all signals/pins linked to a table where more detailed information is provided; a summary of all multiplexed signals
and how to configure them for default and alternate settings, and functionally grouped tables that describe each signal/pin
in detail.
2
Device Architecture and Configuration.............................................................................................. 24
This chapter presents all PC87351 device specific information on the relevant functional blocks, as well as hardware and
software configuration procedures and the related configuration registers.
3
System Wake-Up Control (SWC)......................................................................................................... 51
This chapter describes the system wake-up capabilities of the PC87351, designed to maximize device functionality while
minimizing power consumption.
4
General-Purpose Input/Output (GPIO) Port ....................................................................................... 57
This chapter describes a single 8-bit GPIO port, whose operation is associated with two register sets. Refer to the Device
Architecture and Configuration chapter for the specific implementation in this device.
5
Fan Speed Control................................................................................................................................ 64
This chapter describes the Fan Speed Control, a programmable Pulse Width Modulation (PWM) generator whose output is
used to control the fan’s power voltage. Refer to the Device Architecture and Configuration chapter for the specific implementation in this device.
6-10 Legacy Functional Blocks
Please refer to the PC87307, PC87309 or PC87317 Datasheet for information on the Keyboard and Mouse Controller
(KBC), Serial Port 1, Serial Port 2 with IR, Parallel Port and Floppy Disk Controller (FDC).
11
Device Characteristics ....................................................................................................................................... 72
This chapter provides DC electrical characteristics, both general and of all device pins, as well as AC electrical characteristics.
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6
Table of Contents
Highlights ....................................................................................................................................................... 1
Datasheet Revision Record .................................................................................................................... 4
1.0
2.0
Signal/Pin Connection and Description
1.1
CONNECTION DIAGRAM ......................................................................................................... 11
1.2
SIGNAL/PIN DIRECTORY ........................................................................................................ 12
1.3
PIN MULTIPLEXING ................................................................................................................. 16
1.4
DETAILED SIGNAL/PIN DESCRIPTIONS ................................................................................ 17
1.4.1
Clock ............................................................................................................................ 17
1.4.2
Fan Speed Control ...................................................................................................... 17
1.4.3
FDC (Including PPM) ................................................................................................... 17
1.4.4
General-Purpose Input/Output (GPIO) Ports ............................................................... 19
1.4.5
Host Interface .............................................................................................................. 20
1.4.6
Infrared (IR) ................................................................................................................. 20
1.4.7
Keyboard and Mouse Controller (KBC) ....................................................................... 21
1.4.8
Parallel Port ................................................................................................................. 22
1.4.9
Power and Ground ...................................................................................................... 22
1.4.10 Serial Ports 1 and 2 ..................................................................................................... 23
1.4.11 Strapping ..................................................................................................................... 23
1.4.12 System Wake-Up Control ............................................................................................ 23
Device Architecture and Configuration
2.1
OVERVIEW ............................................................................................................................... 24
2.2
CONFIGURATION STRUCTURE AND ACCESS ..................................................................... 25
2.2.1
The Index-Data Register Pair ...................................................................................... 25
2.2.2
Banked Logical Device Registers ................................................................................ 25
2.2.3
Standard PnP Register Definitions .............................................................................. 26
2.2.4
Overview of PnP Standard Registers .......................................................................... 28
2.2.5
Default Configuration Setup ........................................................................................ 29
2.2.6
Address Decoding ....................................................................................................... 29
2.2.7
The Internal Clocks ...................................................................................................... 29
2.3
REGISTER TYPE ABBREVIATIONS ........................................................................................ 30
2.4
SUPERI/O CONFIGURATION AND CONTROL REGISTERS ................................................. 30
2.4.1
SuperI/O Register Map ................................................................................................ 30
2.4.2
SuperI/O ID Register (SID) .......................................................................................... 30
2.4.3
SuperI/O Configuration 1 Register (SIOCF1) .............................................................. 31
2.4.4
SuperI/O Configuration 2 Register (SIOCF2) .............................................................. 32
2.4.5
SuperI/O Configuration 3 Register (SIOCF3) .............................................................. 33
2.4.6
SuperI/O Configuration 4 Register (SIOCF4) .............................................................. 34
2.4.7
SuperI/O Revision ID Register (SRID) ........................................................................ 34
2.5
PARALLEL PORT MULTIPLEXER (PPM) ................................................................................ 35
2.5.1
PPM Mode ................................................................................................................... 35
2.5.2
TRI-STATE Control of Parallel Port Pins ..................................................................... 36
2.6
FLOPPY DISK CONTROLLER (FDC) - LOGICAL DEVICE 0 ................................................... 37
7
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Table of Contents
2.6.1
2.6.2
2.6.3
2.6.4
3.0
(Continued)
General Description ..................................................................................................... 37
Configuration ............................................................................................................... 37
FDC Configuration Register ........................................................................................ 38
Drive ID Register ......................................................................................................... 38
2.7
PARALLEL PORT - LOGICAL DEVICE 1 ................................................................................. 39
2.7.1
General Description ..................................................................................................... 39
2.7.2
Configuration ............................................................................................................... 39
2.7.3
Parallel Port Configuration Register ............................................................................ 40
2.8
SERIAL PORT 2 - LOGICAL DEVICE 2 .................................................................................... 41
2.8.1
General Description ..................................................................................................... 41
2.8.2
Configuration ............................................................................................................... 41
2.8.3
Serial Port 2 Configuration Register ............................................................................ 41
2.9
SERIAL PORT 1 - LOGICAL DEVICE 3 .................................................................................... 42
2.9.1
Configuration ............................................................................................................... 42
2.9.2
Serial Port 1 Configuration Register ............................................................................ 42
2.10
SYSTEM WAKE-UP CONTROL (SWC) - LOGICAL DEVICE 4 ................................................ 43
2.10.1 Configuration ............................................................................................................... 43
2.11
KEYBOARD AND MOUSE CONTROLLER (KBC) - LOGICAL DEVICES 5 AND 6 .................. 44
2.11.1 General Description ..................................................................................................... 44
2.11.2 Configuration ............................................................................................................... 45
2.11.3 KBC Configuration Register ........................................................................................ 45
2.12
GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS - LOGICAL DEVICE 7 ..................... 46
2.12.1 General Description ..................................................................................................... 46
2.12.2 Implementation ............................................................................................................ 46
2.12.3 Configuration ............................................................................................................... 46
2.12.4 GPIO Pin Configuration Select Register ...................................................................... 47
2.12.5 GPIO Pin Configuration Access Register .................................................................... 48
2.13
FAN SPEED CONTROL - LOGICAL DEVICE 8 ........................................................................ 49
2.13.1 General Description ..................................................................................................... 49
2.13.2 Configuration ............................................................................................................... 49
2.13.3 Fan Speed Control Configuration Register .................................................................. 50
System Wake-Up Control (SWC)
3.1
OVERVIEW ............................................................................................................................... 51
3.2
FUNCTIONAL DESCRIPTION .................................................................................................. 51
3.3
EVENT DETECTION ................................................................................................................. 51
3.3.1
Modem Ring ................................................................................................................ 51
3.3.2
Telephone Ring ........................................................................................................... 51
3.3.3
Keyboard and Mouse Activity ...................................................................................... 51
3.3.4
General-Purpose Events ............................................................................................. 51
3.4
SWC REGISTERS ..................................................................................................................... 52
3.4.1
SWC Register Map ...................................................................................................... 52
3.4.2
Wake-Up Events Control Register (WKCR) ................................................................ 52
3.4.3
Wake-Up Events Status Register (WKSR) .................................................................. 53
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8
Table of Contents
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.5
4.0
5.0
6.0
(Continued)
Wake-Up Configuration Register (WKCFG) ................................................................ 54
PS/2 Protocol Control Register (PS2CTL) ................................................................... 54
Keyboard Data Shift Register (KDSR) ......................................................................... 55
Mouse Data Shift Register (MDSR) ............................................................................. 55
PS/2 Keyboard Key Data Registers (PS2KEY0 - PS2KEY7) ...................................... 56
SWC REGISTER BITMAP ......................................................................................................... 56
General-Purpose Input/Output (GPIO) Port
4.1
OVERVIEW ............................................................................................................................... 57
4.2
BASIC FUNCTIONALITY .......................................................................................................... 58
4.2.1
Configuration Options .................................................................................................. 58
4.2.2
Operation ..................................................................................................................... 58
4.3
INTERRUPT ASSERTION AND HANDLING ............................................................................ 59
4.3.1
Interrupt Configuration ................................................................................................. 59
4.3.2
Interrupt Assertion ....................................................................................................... 59
4.4
GPIO PORT REGISTERS ......................................................................................................... 60
4.4.1
GPIO Pin Configuration Access Register .................................................................... 60
4.4.2
GPIO Port Runtime Register Map ............................................................................... 61
4.4.3
GPIO Data Out Register (GPDO) ................................................................................ 62
4.4.4
GPIO Data In Register (GPDI) .................................................................................... 62
4.4.5
GPIO Interrupt Enable Register (GPIEN) .................................................................... 63
4.4.6
GPIO Status Register (GPST) ..................................................................................... 63
Fan Speed Control
5.1
OVERVIEW ............................................................................................................................... 64
5.2
FUNCTIONAL DESCRIPTION .................................................................................................. 64
5.3
FAN SPEED CONTROL REGISTERS ...................................................................................... 65
5.3.1
Fan Speed Control Register Map ................................................................................ 65
5.3.2
Fan Control Pre-Scale Register (FCPSR) ................................................................... 65
5.3.3
Fan Control Duty Cycle Register (FCDCR) ................................................................. 65
5.4
FAN SPEED CONTROL BITMAP ............................................................................................. 66
Floppy Disk Controller (FDC)
Refer to PC87307, PC87309 or PC87317 datasheet.
7.0
Parallel Port
Refer to PC87307, PC87309 or PC87317 datasheet.
8.0
Serial Port 2 with IR
Refer to PC87307, PC87309 or PC87317 datasheet.
9.0
Serial Port 1
Refer to PC87307, PC87309 or PC87317 datasheet.
10.0
Keyboard and Mouse Controller (KBC)
Refer to PC87307, PC87309 or PC87317 datasheet.
9
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Table of Contents
11.0
(Continued)
Device Characteristics
11.1
DC ELECTRICAL CHARACTERISTICS ................................................................................... 72
11.1.1 Recommended Operating Conditions ......................................................................... 72
11.1.2 Absolute Maximum Ratings ......................................................................................... 72
11.1.3 Capacitance ................................................................................................................. 72
11.1.4 Power Consumption under Recommended Operating Conditions .............................. 73
11.1.5 Input, PCI 5V ............................................................................................................... 73
11.1.6 Strap Pin ...................................................................................................................... 73
11.1.7 Input, TTL Compatible ................................................................................................. 73
11.1.8 Input with TTL Schmitt Trigger .................................................................................... 74
11.1.9 Output, Totem-Pole Buffer ........................................................................................... 74
11.1.10 Output, Open-Drain Buffer ........................................................................................... 74
11.2
AC ELECTRICAL CHARACTERISTICS .................................................................................... 75
11.2.1 AC Test Conditions ...................................................................................................... 75
11.2.2 Clock Timing ................................................................................................................ 75
11.2.3 Host Interface I/O Cycle Timing ................................................................................... 76
11.2.4 Host Interface DMA Cycle Timing ............................................................................... 78
11.2.5 PCICLK Timing Specifications ..................................................................................... 79
11.2.6 Serial IRQ Timing ........................................................................................................ 80
11.2.7 Serial Port, Sharp-IR, SIR and Consumer Remote Control Timing ............................. 81
11.2.8 Modem Control Timing ................................................................................................ 82
11.2.9 FDC Write Data Timing ............................................................................................... 82
11.2.10 FDC Drive Control Timing ........................................................................................... 83
11.2.11 FDC - Read Data Timing ............................................................................................. 83
11.2.12 Standard Parallel Port Timing ...................................................................................... 84
11.2.13 Enhanced Parallel Port Timing .................................................................................... 84
11.2.14 Extended Capabilities Port (ECP) Timing .................................................................... 85
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10
1.0 Signal/Pin Connection and Description
1.0 Signal/Pin Connection and Description
CONNECTION DIAGRAM
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
WGATE
TRK0
WP
RDATA
HDSEL
DSKCHG
NC
IRRX1
IRTX
NC
TC
DACK3
DACK2
VSS
DACK1
DRQ3
DRQ2
DRQ1
MR
CLKIN
NC
GPIO16/IRQ12
GPIO15/IRQ11/P12/P17
GPIO14/IRQ9/IRRX2/P17
GPIO13/IRQ7
GPIO12/IRQ6
1.1
WDATA
STEP
DIR
MTR1
DR0
DR1
MTR0
INDEX
DRATE0
65
66
67
DENSEL
NC
NC
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
PD1/TRK0
ERR/HDSEL
PD0/INDEX
AFD/DSTRB/DENSEL
STB/WRITE
NC
NC
KBRST/GPIO17/P12/PNF
GA20/GPIO20
KBCLK
102
GPIO11/IRQ5
GPIO10/IRQ4
NC
SERIRQ/IRQ3
34
33
32
PCICLK/IRQ1
NC
IOWR
IORD
IOCHRDY
AEN
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
VSS
VDD
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
D3
D2
D1
D0
NC
NC
MDAT
DCD1
DSR1
SIN1
RTS1
SOUT1
CTS1
BADDR/DTR1/BOUT1
RI1
GPIO10/DCD2
GPIO11/DSR2
GPIO12/SIN2
GPIO13/RTS2
VSS
GPIO14/SOUT2
GPIO15/CTS2
GPIO16/DTR2/BOUT2
RI2
NC
VBAT
VSB
PWUREQ
RING/PME1
SUSP/PME2
GPIO21/FANOUT0/P12/PNF
GPIO22/FANOUT1/IRRX2/P17
KBDAT
MCLK
PC87351-xxx/VLA
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
SLCT/WGATE
PE/WDATA
BUSY/WAIT/MTR1
ACK/DR1
PD7/MSEN1
PD6/DRATE0
PD5/MSEN0
PD4/DSKCHG
VSS
VDD
PD3/RDATA
SLIN/ASTRB/STEP
PD2/WP
INIT/DIR
68
69
70
71
72
73
38
37
36
35
Plastic Quad Flatpack (PQFP), JEDEC
Order Number PC87351-xxx/VLA
See NS Package Number VLA128A
xxx = Three character identifier for National data, and keyboard ROM and/or customer identification code
11
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SIGNAL/PIN DIRECTORY
1.0 Signal/Pin Connection and Description
1.2
(Continued)
SIGNAL/PIN DIRECTORY
See Table 1-2 for an alphabetical listing of all signals, cross-referenced to additional information for detailed functional descriptions, electrical DC characteristics, and pin multiplexing. The DC characteristics are denoted by a buffer type symbol,
described briefly in Table 1-1 and in detail in Sections 11.1.6 to 11.1.10. The pin multiplexing information refers to three different types of multiplexing:
•
MUX - Multiplexed functions. Pins are shared between two different functions. Each function is associated with different
board connectivity, and normally, the function selection is determined by the board design and cannot be changed dynamically. The multiplexing options must be configured by the BIOS upon power-up, in order to comply with the board implementation.
•
MM - Multiple Mode. Pins have two or more modes of operation within the same function. These modes are associated
with the same external (board) connectivity. Mode selection may be controlled by the device driver, through the registers
of the functional block, and do not require a special BIOS setup upon power-up. These pins are not considered multiplexed pins from the SuperI/O configuration perspective. The mode selection method (registers and bits) as well as the
signal specification in each mode, are described within the functional description of the relevant functional blocks.
•
PPM - Parallel Port MUX. This special multiplexing of the FDC signals on the Parallel Port pins allows connection of the
external FDC through the Parallel Port connector. This multiplexing is dynamic, controlled by hardware, and does not
require any special BIOS setup except for enabling the PPM function. The PPM functionality and a listing of the pins that
are multiplexed are described in Section 2.5.
Table 1-1. Buffer Types
Name
Description
Section
GND
Ground pin
N/A
INPCI
Input, PCI 5V
11.1.5
INSTRP
Input, Strap pin (min VIH is 0.6VDD) with weak pull-down during strap time
11.1.6
INT
Input, TTL compatible
11.1.7
INTS
Input, TTL compatible with Schmitt trigger
11.1.8
INULR
Input, with serial UL Resistor
N/A
Op/n
Output, Totem-Pole buffer that is capable of sourcing p mA and sinking n mA 11.1.9
ODn
Output, Open-Drain output buffer that is capable of sinking n mA
11.1.10
PWR
Power pin
N/A
Table 1-2. Signal/Pin Directory
Functional Group
Signal
DC Characteristics
Pin/s
Multiplexed
Name
A15-0
28-19, 16-11 Host Interface
ACK
80
AEN
Section
Buffer Type
Section
1.4.5
INT
11.1.7
Parallel Port
1.4.8
INT
11.1.7
29
Host Interface
1.4.5
INT
11.1.7
AFD/DSTRB
94
Parallel Port
1.4.8
OD14, O14/14 11.1.10, 11.1.9
ASTRB
See SLIN/ASTRB
BADDR
110
1.4.11
INSTRP
11.1.6
MUX
BOUT1
See DTR1/BOUT1
BOUT2
See DTR2/BOUT2
BUSY/WAIT
79
Parallel Port
1.4.8
INT
11.1.7
MM/PPM
CLKIN
45
Clock
1.4.1
INT
11.1.7
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Strapping
12
PPM
MM/PPM
(Continued)
Table 1-2. Signal/Pin Directory (Continued)
Functional Group
Signal
DC Characteristics
Pin/s
Multiplexed
Name
Section
Buffer Type
Section
CTS1
109
Serial Port 1
1.4.10
INTS
11.1.8
CTS2
118
Serial Port 2
1.4.10
INTS
11.1.8
D7-0
10-3
Host Interface
1.4.5
INT
O15/24
11.1.7
11.1.9
DACK1-3
50, 52-53
Host Interface
1.4.5
INT
11.1.7
DCD1
104
Serial Port 1
1.4.10
INTS
11.1.8
DCD2
112
Serial Port 2
1.4.10
INTS
11.1.8
FDC
1.4.3
OD24, O4/24
11.1.10, 11.1.9
OD24, O4/24
11.1.10, 11.1.9
74
DENSEL
94
67
DIR
FDC
1.4.3
90
DR0
69
OD24, O4/24
11.1.10, 11.1.9
FDC
1.4.3
OD24, O4/24
11.1.10, 11.1.9
O6/12
11.1.9
73
DRATE0
FDC
1.4.3
82
DRQ1-3
47-49
PPM
PPM
Host Interface
1.4.5
O15/24
11.1.9
FDC
1.4.3
INT
11.1.7
59
DSKCHG
PPM
1.4.3
80
84
MUX
PPM
FDC
70
DR1
MUX
PPM
DSR1
105
Serial Port 1
1.4.10
INTS
11.1.8
DSR2
113
Serial Port 2
1.4.10
INTS
11.1.8
MUX
DSTRB
See AFD/DSTRB
DTR1/BOUT1
110
Serial Port 1
1.4.10
O6/12
11.1.9
MM
DTR2/BOUT2
119
Serial Port 2
1.4.10
O6/12
11.1.9
MM/MUX
ERR
92
Parallel Port
1.4.8
INT
11.1.7
PPM
FANOUT0
127
Fan Speed Control 1.4.2
O2/20
11.1.9
MUX
FANOUT1
128
Fan Speed Control 1.4.2
O2/20
11.1.9
MUX
GPIO17-10
98, 37-43 or
GPIO Port 1
112-5, 117-9
1.4.4
INTS
OD12, O6/12
11.1.8
11.1.10, 11.1.9
MUX
GPIO22-20
127-128, 99
GPIO Port 2
1.4.4
INTS
OD12, O6/12
11.1.8
11.1.10, 11.1.9
MUX
FDC
1.4.3
OD24, O4/24
11.1.10, 11.1.9
INT
11.1.7
60
HDSEL
92
72
INDEX
FDC
1.4.3
93
13
PPM
PPM
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SIGNAL/PIN DIRECTORY
1.0 Signal/Pin Connection and Description
SIGNAL/PIN DIRECTORY
1.0 Signal/Pin Connection and Description
(Continued)
Table 1-2. Signal/Pin Directory (Continued)
Functional Group
Signal
DC Characteristics
Pin/s
Multiplexed
Name
Section
Buffer Type
Section
GA20
99
KBC
1.4.7
OD4
INIT
90
Parallel Port
1.4.8
OD14, O14/14 11.1.10, 11.1.9
IOCHRDY
30
Host Interface
1.4.5
OD24
11.1.10
IORD
31
Host Interface
1.4.5
INT
11.1.7
IOWR
32
Host Interface
1.4.5
INT
11.1.7
IRQ1, 3-7, 9,
11-12
34, 35, 37-43 Host Interface
1.4.5
INT
11.1.7
OD24, O15/24 11.1.10, 11.1.9
IRRX1
57
Infrared
1.4.5
INT
11.1.7
IRRX2/IRSL0
41, 128
Infrared
1.4.5
INT
O6/12
11.1.7
11.1.9
IRRX2
See IRRX2/IRSL0
IRSL0
See IRRX2/IRSL0
IRTX
56
Infrared
1.4.5
O6/12
11.1.9
KBCLK
100
Wake-Up
KBC
1.4.12
1.4.7
INT
OD4
11.1.7
11.1.10
KBDAT
101
Wake-Up
KBC
1.4.12
1.4.7
INT
OD4
11.1.7
11.1.10
KBRST
98
KBC
1.4.7
OD4
11.1.10
MCLK
102
Wake-Up
KBC
1.4.12
1.4.7
INT
OD4
11.1.7
11.1.10
MDAT
103
Wake-Up
KBC
1.4.12
1.4.7
INT
OD4
11.1.7
11.1.10
MR
46
Host Interface
1.4.5
INTS
11.1.8
MSEN0
83
FDC
1.4.3
INT
11.1.7
PPM
MSEN1
81
FDC
1.4.3
INT
11.1.7
PPM
MTR0
71
FDC
1.4.3
OD24, O4/24
11.1.10, 11.1.9
FDC
1.4.3
OD24, O4/24
11.1.10, 11.1.9
68
MTR1
79
11.1.10
MUX
PPM
MUX
MM/MUX
MUX
PPM
P12
42, 98, 127
KBC
1.4.7
OD4
11.1.10
MUX
P17
41, 42, 128
KBC
1.4.7
OD4
11.1.10
MUX
PCICLK
34
Host Interface
1.4.5
INT
11.1.7
MUX
PD7-0
81-84, 87, 89,
Parallel Port
91, 93
1.4.8
INT
11.1.7
OD14, O14/14 11.1.10, 11.1.9
PPM
PE
78
Parallel Port
1.4.8
INT
11.1.7
PPM
PME1
125
Wake-Up
1.4.12
INTS
11.1.8
MUX
PME2
126
Wake-Up
1.4.12
INTS
11.1.8
MUX
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14
(Continued)
Table 1-2. Signal/Pin Directory (Continued)
Functional Group
Signal
DC Characteristics
Pin/s
Multiplexed
Name
Section
Buffer Type
Section
PNF
98, 127
Parallel Port
1.4.8
INT
11.1.7
PWUREQ
124
Wake-Up
1.4.12
OD12
11.1.10
FDC
1.4.3
INT
11.1.7
61
RDATA
87
MUX
PPM
RI1
111
Wake-Up
Serial Port 1
1.4.12
1.4.10
INTS
11.1.8
RI2
120
Wake-Up
Serial Port 2
1.4.12
1.4.10
INTS
11.1.8
RING
125
Wake-Up
1.4.12
INTS
11.1.8
RTS1
107
Serial Port 1
1.4.10
O6/12
11.1.9
RTS2
115
Serial Port 2
1.4.10
O6/12
11.1.9
MUX
SERIRQ
35
Host Interface
1.4.5
INTS
O15/24
11.1.8
11.1.9
MUX
SIN1
106
Serial Port 1
1.4.10
INTS
11.1.8
SIN2
114
Serial Port 2
1.4.10
INTS
11.1.8
MUX
SLCT
77
Parallel Port
1.4.8
INT
11.1.7
PPM
SLIN/ASTRB
88
Parallel Port
1.4.8
OD14, O14/14 11.1.10, 11.1.9
SOUT1
108
Serial Port 1
1.4.10
O6/12
11.1.9
SOUT2
117
Serial Port 2
1.4.10
O6/12
11.1.9
FDC
1.4.3
OD24, O4/24
11.1.10, 11.1.9
66
STEP
88
MUX
MM/PPM
MUX
PPM
STB/WRITE
95
Parallel Port
1.4.8
OD14, O14/14 11.1.10, 11.1.9
MM
SUSP
126
Wake-Up
1.4.12
INTS
11.1.8
MUX
TC
54
Host Interface
1.4.5
INT
11.1.7
FDC
1.4.3
INT
11.1.7
63
TRK0
91
PPM
VBAT
122
Power and Ground 1.4.11
INULR
N/A
VDD
17, 86
Power and Ground 1.4.9
PWR
N/A
VSB
123
Power and Ground 1.4.12
PWR
N/A
VSS
18, 51, 85,
116
Power and Ground 1.4.12
GND
N/A
WAIT
See BUSY/WAIT
OD24, O4/24
11.1.10, 11.1.9
65
WDATA
FDC
1.4.3
78
15
PPM
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SIGNAL/PIN DIRECTORY
1.0 Signal/Pin Connection and Description
PIN MULTIPLEXING
1.0 Signal/Pin Connection and Description
(Continued)
Table 1-2. Signal/Pin Directory (Continued)
Functional Group
Signal
DC Characteristics
Pin/s
Multiplexed
Name
64
Section
FDC
WGATE
1.4.3
77
62
WP
FDC
1.4.3
89
WRITE
1.3
Buffer Type
Section
OD24, O4/24
11.1.10, 11.1.9
INT
11.1.7
PPM
PPM
See STB/WRITE
PIN MULTIPLEXING
There are three categories of pins with multiple names: Multiplexed (MUX), Multiple Mode (MM) and Parallel Port MUX
(PPM). See Section 1.2 for descriptions of these categories. All the multiplexing options in the MUX category and their associated setup configuration are described in Table 1-3. A multiplexing option may be chosen on one pin only per group.
Table 1-3. Pin Multiplexing Configuration
Default
Alternate
Pin
Signal
34 PCICLK
35 SERIRQ
I/O
I
Configuration
Signal
IRQ1
I/O SIOCF2, Bit 0 = 1
I/O SIOCF2, Bit 0 = 0
IRQ3
I/O SIOCF2, Bit 0 = 1
IRQ4
38 GPIO11
IRQ5
I/O SIOCF2, Bit 0 = 0
IRQ6
40 GPIO13
IRQ7
43 GPIO16
IRQ12
41 GPIO14
SIOCF2, Bits 2-1 = 00
I/O
or Bits 2-0 = 011
42 GPIO15
SIOCF2, Bits 4-3 = 00
I/O
or Bits 4-3, 0 = 011
98 KBRST
I/O SIOCF2, Bits 6-5 = 01
99 GA20
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Configuration
SIOCF2, Bit 0 = 0
37 GPIO10
39 GPIO12
I/O
I/O SIOCF2, Bit 7 = 1
16
I/O SIOCF2, Bit 0 = 1
IRQ9
I/O SIOCF2, Bits 2-0 = 010
IRRX2/IRSL0
I/O SIOCF2, Bits 2-1 = 10
P17
I/O SIOCF2, Bits 2-1 = 11
IRQ11
O
P12
I/O SIOCF2, Bits 4-3 = 10
P17
I/O SIOCF2, Bits 4-3 = 11
GPIO17
I/O SIOCF2, Bits 6-5 = 00
P12
I/O SIOCF2, Bits 6-5 = 10
PNF
I/O SIOCF2, Bits 6-5 = 11
GPIO20
I/O SIOCF2, Bit 7 = 0
SIOCF2, Bits 4-3, 0 = 010
DETAILED SIGNAL/PIN DESCRIPTIONS
1.0 Signal/Pin Connection and Description
(Continued)
Table 1-3. Pin Multiplexing Configuration (Continued)
Default
Alternate
Pin
Signal
I/O
Configuration
Signal
112 GPIO10
DCD2
I
113 GPIO11
DSR2
I
114 GPIO12
SIN2
I
RTS2
O
117 GPIO14
SOUT2
O
118 GPIO15
CTS2
I
119 GPIO16
DTR2/BOUT2
O
I/O SIOCF3, Bit 0 = 0
115 GPIO13
Configuration
SIOCF3, Bit 0 = 1
125 RING
I
SIOCF4, Bit 0 = 0
PME1
I
SIOCF4, Bit 0 = 1
126 SUSP
I
SIOCF4, Bit 2 = 0
PME2
I
SIOCF4, Bit 2 = 1
127 GPIO21
I/O SIOCF3, Bits 2-1 = 00
128 GPIO22
I/O SIOCF3, Bits 4-3 = 00
1.4
I/O
FANOUT0
I/O SIOCF3, Bits 2-1 = 01
P12
I/O SIOCF3, Bits 2-1 = 10
PNF
I/O SIOCF3, Bits 2-1 = 11
FANOUT1
I/O SIOCF3, Bits 4-3 = 01
IRRX2/IRSL0
I/O SIOCF3, Bits 4-3 = 10
P17
I/O SIOCF3, Bits 4-3 = 11
DETAILED SIGNAL/PIN DESCRIPTIONS
1.4.1
Clock
Signal
CLKIN
1.4.2
45
I/O
Buffer Type
I
INT
Description
Clock In. A 48MHz clock input.
Fan Speed Control
Signal
FANOUT0
FANOUT1
1.4.3
Pin/s
Pin/s
127,
128
I/O
Buffer Type
Description
O
O2/20
Fan Output 0, 1. Pulse Width Modulation (PWM) signals, that are used to
control the speed of cooling fans by controlling the voltage supplied to the
fan’s motor.
FDC (Including PPM)
The Parallel-Port/FDC MUX (PPM) provides a means to connect an external FDD on the Parallel Port connector, in addition
to the internal FDD on the FDC header. This is done by physically connecting internally each FDC pin to a corresponding
Parallel Port pin while isolating it from the Parallel Port logic. The Parallel Port becomes an additional connecting point to
the FDC interface as long as the PPM is in active mode. The functional descriptions in this table apply to both the FDC pin
and to the corresponding PPM pin. For a detailed description of PPM functionality, see Section 2.5.
17
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DETAILED SIGNAL/PIN DESCRIPTIONS
1.0 Signal/Pin Connection and Description
Signal
DENSEL
Pin/s
74
I/O
Buffer Type
Description
O
O4/24
Density Select. Indicates that a high FDC density data rate (500 Kbps or 1
Mbps) or a low density data rate (250 or 300 Kbps) is selected. DENSEL
polarity is controlled by bit 5 of the FDC Configuration Register.
94
DIR
67
(Continued)
This pin provides an additional density select signal in PPM mode when
PNF = 0.
O
OD24-O4/24
90
Direction. Determines the direction of the Floppy Disk Drive (FDD) head
movement (active = step in, inactive = step out) during a seek operation.
During reads or writes, DIR is inactive.
This pin provides an additional direction signal in PPM mode when
PNF = 0.
DR0
69
O
OD24-O4/24
Drive Select 0. Decoded drive select output signal. DR0 is controlled by
Digital Output Register (DOR) bit 0.
DR1
70
O
OD24-O4/24
Drive Select 1. Decoded drive select output signal. DR1 is controlled by
Digital Output Register (DOR) bit 1.
80
DRATE0
73
This pin provides an additional drive select 1 signal in PPM mode when
PNF = 0.
O
O6/12
82
DSKCHG
59
This pin provides an additional FDC data rate signal in PPM mode, when
PNF = 0.
I
INT
84
HDSEL
60
72
Disk Change. Indicates if the drive door has been opened. The state of this
pin is stored in the Digital Input Register (DIR). This pin can also be
configured as the RGATE data separator diagnostic input signal via the MODE
command.
This pin provides an additional FDC Disk Change signal in PPM Mode
when PNF = 0.
O
OD24, O4/24
92
INDEX
Data Rate 0. Reflects the value of bit 0 of the Configuration Control
Register (CCR) or the Data Rate Select Register (DSR), whichever was
written to last. Output from the pin is totem-pole buffered.
Head Select. Determines which side of the FDD is accessed. Active low
selects side 1, inactive selects side 0.
This pin provides an additional head select signal in PPM mode when
PNF = 0.
I
INT
93
Index. Indicates the beginning of an FDD track.
This pin provides an additional index signal in PPM mode when PNF = 0.
MSEN0,
MSEN1
82,
80
I
INT
Media Sense Signals 0 and 1. Provide media sense signals only in PPM
mode when PNF = 0.
MTR0
71
O
OD24, O4/24
Motor Select 0. Active low, motor enable line for drive 0, controlled by bits
D7-4 of the Digital Output Register (DOR).
This signal is not available on the PPM, assuming that the external FDD is
either drive 1 or 3.
MTR1
68
O
OD24, O4/24
Motor Select 1. Active low, motor enable line for drive 1, controlled by bits
D7-4 of the Digital Output Register (DOR).
79
RDATA
61
87
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This pin provides an additional motor select 1 signal in PPM mode when
PNF = 0. This pin is the motor enable line for drive 1 or drive 0, according
to the TDR Register.
I
INT
Read Data. Raw serial input data stream read from the FDD.
This pin provides an additional read data signal in PPM mode when PNF = 0.
18
Signal
STEP
Pin/s
66
I/O
Buffer Type
Description
O
OD24, O4/24
Step. Issues pulses to the disk drive at a software programmable rate to
move the head during a seek operation.
88
TRK0
63
This pin provides an additional step signal in PPM mode when PNF = 0.
I
INT
91
WDATA
65
64
O
OD24, O4/24
62
O
OD24, O4/24
Write Gate. Enables the write circuitry of the selected disk drive. WGATE
is designed to prevent glitches during power up and power down. This
prevents writing to the disk when power is cycled.
This pin provides an additional WGATE signal in PPM mode when PNF = 0.
I
INT
89
1.4.4
Write Data. Carries out the write pre-compensated serial data that is
written to the selected floppy disk drive. Pre-compensation is software
selectable.
This pin provides an additional WDATA signal in PPM mode when PNF = 0.
77
WP
Track 0. Indicates to the controller that the head of the selected floppy
disk drive is at track 0.
This pin provides an additional Track 0 signal in PPM Mode when PNF = 0.
78
WGATE
(Continued)
Write Protected. Indicates that the disk in the selected drive is write
protected. A software programmable configuration bit (FDC configuration
at Index F0h, Logical Device 0) can force an active write-protect indication
to the FDC regardless of the status of this pin.
This pin provides an additional WP signal in PPM mode when PNF = 0.
General-Purpose Input/Output (GPIO) Ports
Signal
Pin/s
GPIO17
98
GPIO16-10 43-37
I/O
Buffer Type
Description
I/O
INTS/
OD12, O6/12
General-Purpose I/O Port 1, bits 0-7. Each pin is configured independently
as input or I/O, with or without static pull-up, and with either open-drain or totem-pole output type. The port support interrupt assertion and each pin can
be enabled or masked as interrupt source.
GPIO 16-10 119-117,
115-112
GPIO22-20 128,
127, 99
These pins provide alternate GPIO location options.
I/O
INTS/
OD12, O6/12
General-Purpose I/O Port 2, bits 0-2. Same as Port 1.
19
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DETAILED SIGNAL/PIN DESCRIPTIONS
1.0 Signal/Pin Connection and Description
DETAILED SIGNAL/PIN DESCRIPTIONS
1.0 Signal/Pin Connection and Description
1.4.5
(Continued)
Host Interface
Signal
Pin/s
I/O
Buffer Type
Description
A15-A0
11-16,
19-28
I
INT
Address. These address lines of the ISA bus determine which internal
register is accessed. A15-A0 are don’t cares during DMA transfer.
AEN
29
I
INT
Address Enable. This input disables function selection via A15-A0 when it
is high. Access during DMA transfer is NOT affected by this pin.
D7-D0
45
I/O
INT/O15/24
Data. Bi-directional data lines of the ISA bus. D7 is the MSB and D0 is the
LSB.
DACK1-3
50, 52,
53
I
INT
DMA Acknowledge 1, 2 and 3. These active low signals acknowledge a
request for DMA services and enable the IORD and the IOWR input
signals during DMA transfer.
DRQ1-3
47-49
O
O15/24
DMA Request 1, 2, and 3. These active high output signals inform the
DMA controller that a data transfer is needed.
IOCHRDY
30
O
OD24
I/O Channel Ready. This is the I/O channel ready open drain output
signal. When IOCHRDY is driven low, the EPP extends the host cycle.
IORD
31
I
INTS
I/O Read. An active low RD input signal indicates that the microprocessor
has read data.
IOWR
32
I
INTS
I/O Write. WR is an active low input signal that indicates a write operation
from the microprocessor to the controller.
I/O
INT/
OD24, O15/24
Interrupt Request 1, 3-7, 9, 11-12. IRQ polarity and output type selection
is software configurable by the logical device mapped to the IRQ line.
IRQ1,3-7, 9, 34,35,
37-43
11-12
MR
46
I
INTS
Master Reset. An active high MR input signal resets the device with its
default settings.
PCICLK
34
I
INPCI
PCI Clock. Up to 33 MHz.
SERIRQ
35
I/O
INT/O15/24
TC
54
I
INT
DMA Terminal Count. The DMA controller issues TC to indicate the
termination of a DMA transfer. TC is accepted only when a DACK signal is
active.
TC is active high in PC-AT mode, and active low in PS/2 mode.
1.4.6
Infrared (IR)
I/O
Buffer Type
Description
I
INT
Signal
Pin/s
IRRX1
57
IRRX2/
IRSL0
41, 128 I/O
IRTX
56
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O
INT/O6/12
O6/12
Serial IRQ. Encoded interrupts on a serial line.
IR Reception 1. Primary input to receive serial data from the IR
transceiver module.
IRRX2 - IR Reception 2. Auxiliary IR receiver input to support two
transceiver modules.
IRSL0 - IR Control Signals 0. Output to control the IR analog front end.
IR Transmit. IR serial output data.
20
1.4.7
(Continued)
Keyboard and Mouse Controller (KBC)
Signal
Pin/s
I/O
Buffer Type
Description
GA20
99
I/O
INTS/OD4
Gate A20. KBC gate A20 (P21) output.
KBCLK
100
I/O
INTS/OD4
Keyboard Clock. Transfers the keyboard clock between the SuperI/O chip
and the external keyboard using the PS/2 protocol.
This pin is driven by the internal, inverted KBC P26 signal, and is
connected internally to the T0 signal of the KBC. External pull-up resistor
to 5V is required (for PS/2 compliance). The pin is monitored for wake-up
event detection. However, to enable the activity during power off, it must be
pulled up to Keyboard and Mouse standby voltage.
KBDAT
101
I/O
INTS/OD4
Keyboard Data. Transfers the keyboard data between the SuperI/O chip
and the external keyboard using the PS/2 protocol.
This pin is driven by the internal, inverted KBC P27 signal, and is
connected internally to KBC P10. External pull-up resistor to 5V is required
(for PS/2 compliance). The pin is monitored for wake-up event detection.
To enable the activity, it must be pulled up to Keyboard and Mouse standby
voltage.
KBRST
98
I/O
INTS/OD4
KBD Reset. Keyboard Reset (P20) output.
MCLK
102
I/O
INTS/OD4
Mouse Clock. Transfers the mouse clock between the SuperI/O chip and
the external keyboard using the PS/2 protocol.
This pin is driven by the internal, inverted KBC P23 signal, and is
connected internally to KBC’s T1. External pull-up resistor to 5V is
required (for PS/2 compliance). The pin is monitored for wake-up event
detection. To enable the activity, it must be pulled up to Keyboard and
Mouse standby voltage.
MDAT
103
I/O
INTS/OD4
Mouse Data. Transfers the mouse data between the SuperI/O chip and
the external keyboard using the PS/2 protocol.
This pin is driven by the internal, inverted KBC P22 signal, and is
connected internally to KBC’s P11. External pull-up resistor to 5V is
required (for PS/2 compliance). The pin is monitored for wake-up event
detection. To enable the activity, it must be pulled up to Keyboard and
Mouse standby voltage.
P12
42, 98,
127
I/O
INTS/OD4
I/O Port. KBC open-drain signal for general-purpose input and output,
controlled by KBC firmware.
P17
41, 42,
128
I/O
INTS/OD4
I/O Port. KBC open-drain signal for general-purpose input and output,
controlled by KBC firmware.
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DETAILED SIGNAL/PIN DESCRIPTIONS
1.0 Signal/Pin Connection and Description
DETAILED SIGNAL/PIN DESCRIPTIONS
1.0 Signal/Pin Connection and Description
1.4.8
(Continued)
Parallel Port
Signal
Pin/s
I/O
Buffer Type
Description
ACK
80
I
INT
Acknowledge. Pulsed low by the printer to indicate that it has received data
from the Parallel Port.
AFD/
DSTRB
94
O
OD14, O14/14
AFD - Automatic Feed. When low, instructs the printer to automatically
feed a line after printing each line. This pin is in TRI-STATE after a 0 is
loaded into the corresponding control register bit. An external 4.7 KΩ pullup resistor should be attached to this pin.
DSTRB - Data Strobe (EPP). Active low, used in EPP mode as a data
strobe.
BUSY/WAIT 79
I
INT
Busy. Set high by the printer when it cannot accept another character.
Wait. In EPP mode, the Parallel Port device uses this active low signal to
extend its access cycle.
ERR
92
I
INT
Error. Set active low by the printer when it detects an error.
INIT
90
O
OD14-O14/14
Initialize. When low, initializes the printer. This signal is in TRI-STATE
after a 1 is loaded into the corresponding control register bit. Use an
external 4.7 KΩ pull-up resistor.
PD7-0
81-84,
87, 89,
91, 93
I/O
INT/
OD14, O14/14
Parallel Port Data. Transfer data to and from the peripheral data bus and
the appropriate Parallel Port data register. These signals have a high
current drive capability.
PE
78
I
INT
Paper End. Set high by the printer when it is out of paper. This pin has an
internal weak pull-up or pull-down resistor.
PNF
98, 127
I
INT
Printer Not Floppy. This input from the Parallel Port connector is used to
detect that a floppy drive is connected to the Parallel Port, and to activates
the PPM. The PNF pin is driven to 1 when a parallel device is connected,
and to 0 when external FDD is connected. This pin is functional only when
the PPM mode is enabled.
SLCT
77
I
INT
Select. Set active high by the printer when the printer is selected.
SLIN/
ASTRB
88
O
OD14, O14/14
SLIN - Select Input. When low, selects the printer. This signal is in TRISTATE after a 0 is loaded into the corresponding control register bit. Uses
an external 4.7 KΩ pull-up resistor.
ASTRB - Address Strobe (EPP). Active low, used in EPP mode as an
address strobe.
STB/
WRITE
95
O
OD14, O14/14
STB - Data Strobe. Indicates to the printer that valid data is available at
the printer port. This signal is in TRI-STATE after a 0 is loaded into the
corresponding control register bit. An external 4.7 KΩ pull-up resistor
should be employed.
WRITE - Write Strobe. In EPP mode, this active low signal is a write
strobe.
1.4.9
Power and Ground
Signal
Pin/s
Buffer Type
Description
VBAT
122
INULR
Battery Power Supply. Provides battery back-up to the System Wake-Up
Control registers, when VSB is lost (power-fail). The pin is connected to the
internal logic through a series resistor for UL protection.
VDD
17, 86
PWR
Main 5V Power Supply.
VSB
123
PWR
Standby Power Supply. Provides 5V power to the Wake-Up Control circuitry,
while the main power supply is turned off.
VSS
18, 51,
85, 116
GND
Ground.
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22
(Continued)
1.4.10 Serial Ports 1 and 2
Signal
Pin/s
I/O
Buffer Type
Description
CTS1,
CTS2
109,
118
I
INTS
Clear to Send. When low, indicate that the modem or other data transfer
device is ready to exchange data.
DCD1,
DCD1
3,
94
I
INTS
Data Carrier Detected. When low, indicate that the modem or other data
transfer device has detected the data carrier.
DSR1,
DSR2
105,
113
I
INTS
Data Set Ready. When low, indicate that the data transfer device, e.g.,
modem, is ready to establish a communications link.
DTR1/
BOUT1,
DTR2/
BOUT2
110,
O
O6/12
Data Terminal Ready. When low, indicate to the modem or other data
transfer device that the Serial Port is ready to establish a communications
link. After system reset, these pins provides the DTR function, sets these
signals to inactive high, and loopback operation holds them inactive.
Baud Output. Provides the associated serial channel baud rate generator
output signal if test mode is selected, i.e., bit 7 of the EXCR1 Register is
set.
DTR1/BOUT1 is used also as BADDR.
RI1,
RI2
111,
120
I
INTS
Ring Indicators (Modem). When low, indicate that a telephone ring signal
has been received by the modem. These pins may issue wake-up event.
RTS1,
RTS2
107,
115
O
O6/12
Request to Send. When low, indicate to the modem or other data transfer
device that the corresponding Serial Port is ready to exchange data. A
system reset sets these signals to inactive high, and loopback operation
holds them inactive.
SIN1,
SIN2
106,
114
I
INTS
Serial Input. Receive composite serial data from the communications link
(peripheral device, modem or other data transfer device).
SOUT1,
SOUT2
108,
117
O
O6/12
Serial Output. Send composite serial data to the communications link
(peripheral device, modem or other data transfer device). The SOUT2,1
signals are set active high after system reset.
I/O
Buffer Type
Description
I
INSTRP
Base Address Strap. Determines the base address of the Index and Data
registers. It is pulled down by an internal 30 Kohm resistor to get base
address 2Eh for the Index register, and 2Fh for the Data register. If the
respective base addresses are 15Ch and 15Dh, use an external 10 Kohm
pull-up resistor (to VDD).
119
1.4.11 Strapping
Signal
BADDR
Pin/s
110
1.4.12 System Wake-Up Control
Signal
Pin/s
I/O
Buffer Type
Description
PME1,
PME2
125,
126
I
INTS
Power Management Event 1, 2. Detection of an event on PME1 or PME2
may activate the PWUREQ signal (wake-up event).
PWUREQ
124
O
OD6/12
Power Up Request. Low level (active) indicates that wake-up event has
occurred. This may cause the chipset to turn the power supply on, or to
exit its current sleep state. The open-drain output must be pulled up to
VSB, in order to function during power-off.
RING
125
I
INTS
Telephone Line Ring. Detection of a pulse-train on the RING pin, is a
wake-up event that can activate the power-up request (PWUREQ).
SUSP
126
I
INTS
Suspend Power. Power Supply On control signal.
23
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DETAILED SIGNAL/PIN DESCRIPTIONS
1.0 Signal/Pin Connection and Description
The SuperI/O device comprises a collection of generic functional blocks. Each functional block is described in a separate
chapter in this book. However, some parameters in the implementation of each functional block may vary per SuperI/O device. This chapter describes the PC87351 structure and provides all device specific information, including special implementation of generic blocks, host interface and device configuration.
2.1
OVERVIEW
The PC87351 consists of 9 logical devices, a host interface, and a central configuration register set, all built around a central,
internal bus. The internal bus is a replication of an 8-bit ISA bus protocol.
The host interface serves as a bridge between the external ISA interface and the internal bus. It supports 8-bit I/O read, 8bit I/O write and 8-bit DMA transactions, as defined in Personal Computer Bus Standard P996.
PPM
VBAT
VSB
PME1
PME2
SUSP
RING
PWUREQ
System
Wake-Up
Configuration
and Control
Registers
Serial
Port 2
with IR
SIN2
SOUT2
RTS2
DTR2/BOUT2
CTS2
DSR2
DCD2
RI2
IRRX2,1
IRTX
IRSL0
Keyboard
and
Mouse
Controller
P12,P17
GA20, KBRST
KBCLK
KBDAT
MDAT
MCLK
GPIO Ports
BADDR
CLKIN
MR
Host Interface
D7-0
A15-0
AEN
IORD
IOWR
IOCHRDY
PCICLK
SERIRQ
FDC
Figure 2-1. Detailed PC87351 Block Diagram
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Serial
Port 1
SIN1
SOUT1
RTS1
DTR1/BOUT1
CTS1
DSR1
DCD1
RI1
Parallel
Port
Internal Bus
Control Signals
RDATA
WDATA
WGATE
HDSEL
DIR
STEP
TRK0
INDEX
DSKCHG
WP
MTR1,0
DR1,0
DENSEL
DRATE0
Fan Speed
Control
GPIO22-20
STB/WRITE
PD0/INDEX
PD1/TRK0
PD2/WP
PD3/RDATA
PD4/DSKCHG
PD5/MSEN0
PD6/DRATE0
PD7/MSEN1
ACK/DR1
BUSY/MTR1/WAIT
PE/WDATA
SLCT/WGATE
AFD/DENSEL/DSTRB
ERR/HDSEL
INIT/DIR
SLIN/STEP/ASTRB
PNF
FANOUT1
FANOUT0
The central configuration register set supports ACPI compliant PnP configuration. The configuration registers are structured
as a subset of the Plug and Play Standard Registers, defined in Appendix A of the Plug and Play ISA Specification Version
1.0a by Intel and Microsoft. All system resources assigned to the functional blocks (I/O address space, DMA channels and
IRQ lines) are configured in, and managed by, the central configuration register set. In addition, some function-specific parameters are configurable through this unit and distributed to the functional blocks through special control signals.
GPIO17-10
2.0 Device Architecture and Configuration
2.0 Device Architecture and Configuration
24
TC
DACK3-1
DRQ3-1
IRQ9,11-12
IRQ1,3-7
2.2
(Continued)
CONFIGURATION STRUCTURE AND ACCESS
This section describes the structure of the configuration register file, and the method of accessing the configuration registers.
2.2.1
The Index-Data Register Pair
The SuperI/O configuration access is performed via an Index-Data register pair, using only two system I/O byte locations.
The base address of this register pair is determined during reset, according to the state of the hardware strapping option on
the BADDR pin. Table 2-1 shows the selected base addresses as a function of BADDR.
Table 2-1. BADDR Strapping Options
I/O Address
BADDR
Index Register
Data Register
0
002Eh
002Fh
1
015Ch
015Dh
The Index Register is an 8-bit R/W register located at the selected base address (Base+0). It is used as a pointer to the
configuration register file, and holds the index of the configuration register that is currently accessible via the Data Register.
Reading the Index Register returns the last value written to it (or the default of 00h after reset).
The Data Register is an 8-bit virtual register, used as a data path to any configuration register. Accessing the data register
results with physically accessing the configuration register that is currently pointed by the index register.
2.2.2
Banked Logical Device Registers
Each functional block is associated with a Logical Device Number (LDN). The configuration registers are grouped into banks,
where each bank holds the standard PnP configuration registers of the corresponding logical device. Table 2-2 shows the
LDNs of the device functional blocks.
Figure 2-2 shows the structure of the standard PnP configuration register file. The SIO Control and Configuration registers
are not banked and are accessed by the Index-Data register pair only, as described above. However, the device control and
device configuration registers are duplicated over 9 banks for 9 logical devices. Therefore, accessing a specific register in
a specific bank is performed by two dimensional indexing, where the LDN Register selects the bank (or logical device) and
the Index Register selects the register within the bank. Accessing the Data Register while the Index Register holds a value
of 30h or higher results in a physical access to the configuration register currently pointed to by the Index Register, within
the logical device currently selected by the LDN Register.
07h
Logical Device Number Register
20h
2Eh
SuperI/O Configuration Registers
30h
Logical Device Control Register
60h
63h
70h
71h
74h
75h
F0h
F2h
Logical Device Configuration
PnP Standard Registers
Bank Select
Logical Device Configuration
Special (Vendor-defined) Registers
9 Banks - One per
Logical Device
Figure 2-2. Structure of the PnP Standard Registers
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CONFIGURATION STRUCTURE AND ACCESS
2.0 Device Architecture and Configuration
CONFIGURATION STRUCTURE AND ACCESS
2.0 Device Architecture and Configuration
(Continued)
Table 2-2. Logical Device Number (LDN) Assignments
LDN
Functional Block
00h
Floppy Disk Controller (FDC)
01h
Parallel Port
02h
Serial Port 2 with IR
03h
Serial Port 1
04h
System Wake-Up Control (SWC)
05h
Keyboard and Mouse Controller (KBC) - Mouse interface
06h
Keyboard and Mouse Controller (KBC) - Keyboard interface
07h
General-Purpose I/O (GPIO)
08h
Fan Speed Control (FSC)
When accessing unimplemented registers (i.e. accessing the Data Register while the Index Register points to a non-existing
register or the LDN is higher than 08h), write is ignored and read returns 00h on all addresses except for 74h, 75h (PnP DMA
Configuration Registers) which returns 04h (no DMA channel is active). The configuration registers are accessible immediately after reset.
2.2.3
Standard PnP Register Definitions
Tables 2-3 through 2-8 describe the standard PnP registers. For more detailed information on these registers, refer to the
Plug and Play ISA Specification, Version 1.0a, May 5, 1994.
Unless otherwise noted:
•
•
All registers are read/write.
•
Write only registers should not use read-modify-write during updates.
All reserved bits return 0 on reads. To prevent unpredictable results, they must not be modified. Using read-modifywrite is recommended to prevent the values of reserved bits from being changed during write.
Table 2-3. PnP Standard Control Registers
Index
Name
07h
Logical Device
Number
20h - 2Fh
SuperI/O
Configuration
Registers
Description
This register selects the current logical device.
SuperI/O Configuration Registers and ID Registers
Table 2-4. PnP Logical Device Control Registers
Index
Name
30h
Activate
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Description
Bit 0 - Logical Device Activation Control
0: Disabled
1: Enabled
Bits 7-1 - Reserved
26
CONFIGURATION STRUCTURE AND ACCESS
2.0 Device Architecture and Configuration
(Continued)
Table 2-5. PnP I/O Space Configuration Registers
Index
Name
Description
60h
I/O Port Base
Indicates selected I/O lower limit address bits 15-8 for I/O descriptor 0
Address Bits (15-8)
Descriptor 0
61h
I/O Port Base
Indicates selected I/O lower limit address bits 7-0 for I/O descriptor 0
Address Bits (7-0)
Descriptor 0
62h
I/O Port Base
Indicates selected I/O lower limit address bits 15-8 for I/O descriptor 1
Address Bits (15-8)
Descriptor 1
63h
I/O Port Base
Indicates selected I/O lower limit address bits 7-0 for I/O descriptor 1
Address Bits (7-0)
Descriptor 1
Table 2-6. PnP Interrupt Configuration Registers
Index
Name
Description
70h
Interrupt Request Indicates selected interrupt number
Number Select Bits 3-0 select the interrupt number. A value of 1 selects IRQ1, a value of 2 selects
IRQ2, etc. (up to IRQ15). IRQ0 is not a valid interrupt selection.
71h
Interrupt Request Indicates the type and level of the interrupt request number selected in the previous
Type Select
register
Bit 0 - Type of interrupt request selected in previous register
0: Edge
1: Level
Bit 1 - Level of interrupt request selected in previous register
0: Low polarity
1: High polarity
Table 2-7. PnP DMA Configuration Registers
Index
Name
Description
74h
DMA Channel
Select 0
Indicates selected DMA channel for DMA 0
Bits 2-0 select the DMA channel for DMA 0. The valid choices are 1-3, where a
value of 1 selects DMA channel 1, 2 selects DMA channel 2, etc.
A value of 4 indicates that no DMA channel is active.
The values 5-7 are reserved.
75h
DMA Channel
Select 1
Indicates selected DMA channel for DMA 1
Bits 2-0 select the DMA channel for DMA 1. The valid choices are 1-3, where a
value of 1 selects DMA channel 1, 2 selects DMA channel 2, etc.
A value of 4 indicates that no DMA channel is active.
The values 5-7 are reserved.
Table 2-8. PnP Logical Device Configuration Registers
Index
Name
F0h-FEh
Logical Device
Configuration
Description
Vendor-defined
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CONFIGURATION STRUCTURE AND ACCESS
2.0 Device Architecture and Configuration
2.2.4
(Continued)
Overview of PnP Standard Registers
Index
SuperI/O Control and
Configuration Registers
Logical Device Control and
Configuration Registers one per logical device
(some are optional)
Name
07h
Logical Device Number Register
20h
SuperI/O ID Register
21h
SuperI/O Configuration 1 Register
22h
SuperI/O Configuration 2 Register
23h
SuperI/O Configuration 3 Register
24h
SuperI/O Configuration 4 Register
27h
SuperI/O Revision ID Register
2Eh
Reserved exclusively for National use
30h
Logical Device Control Register (Activate)
60h
I/O Base Address Descriptor 0 Bits 15-8
61h
I/O Base Address Descriptor 0 Bits 7-0
62h
I/O Base Address Descriptor 1 Bits 15-8
63h
I/O Base Address Descriptor 1 Bits 7-0
70h
IRQ Number Select
71h
IRQ Type Select
74h
DMA Channel Select 0
75h
DMA Channel Select 1
F0h
Device Specific Logical Device Configuration 1
F1h
Device Specific Logical Device Configuration 2
F2h
Device Specific Logical Device Configuration 3
Figure 2-3. PnP Register Map
SuperI/O Control and Configuration Registers
The only implemented PnP control register in the PC87351 is the Logical Device Number Register at index 07h. All the other
standard PnP control registers are associated with PnP protocol for ISA add-in cards, and are not supported by the PC87351.
The SuperI/O Configuration registers at indexes 20h and 27h are mainly used for part identification, global power management and the selection of pin multiplexing options. For details, see Section 2.5.
Logical Device Control and Configuration Registers
A subset of these registers is implemented for each logical device.
Control
The only implemented logical device control register is the activate register at index 30. Bit 0 of the activate register controls
the activation of the associated function block. Activation of the block enables access to the block’s registers, and attaches
its system resources, which are unused as long as the block is not activated. Other effects may apply, on a function-specific
basis (such as clock enable and active pinout signaling).
Standard Configuration
The standard configuration registers are used to manage the PnP resource allocation to the functional blocks. The I/O port
base address descriptor 0 is a pair of registers at Index 60-61, holding the (first or only) 16-bit base address for the register
set of the functional block. An optional second base-address (descriptor 1) at index 62-63 is used for devices with more than
one continuous register set. IRQ Number Select (index 70h) and IRQ Type Select (index 71h) allocate an IRQ line to the
block and control its type. DMA Channel Select 0 (index 74h) allocates a DMA channel to the block, where applicable. DMA
Channel Select 1 (index 75h) allocates a second DMA channel, where applicable.
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28
(Continued)
Special Configuration
The vendor-defined registers, starting at index F0h are used to control function-specific parameters such as operation
modes, power saving modes, pin TRI-STATE, clock rate selection, and non-standard extensions to generic functions.
2.2.5
Default Configuration Setup
The device has four reset types, described below. See specific register descriptions for bits affected by each register type.
•
Software Reset
This reset is enabled by bit 1 of the SIOCF1 Register, which resets all logical devices. A software reset also resets most
bits in the SuperI/O Configuration and Control Registers.
•
Hardware Reset
This reset is activated by the assertion of the MR input. It resets all logical devices, with the exception of the SWC. It
also resets all SuperI/O Configuration and Control Registers, with the exception of the SIOCF4 Register.
•
VPP Power-Up Reset
This reset is activated when either VSB or VBAT is powered on after both have been off. VPP is an internal voltage which
is a combination of VSB and VBAT. VPP is taken from VSB if VSB is greater than the minimum (Min) value defined in the
Device Characteristics chapter; otherwise, VBAT is used as the VPP source. This reset resets all registers whose values
are retained by VPP.
•
VSB Power-Up Reset
This is an internally generated reset that resets the SWC, excluding those SWC registers whose values are retained by VPP.
The PC87351 wakes up with the default setup, as follows:
•
In the event of a hardware reset:
— The configuration base address is 2Eh or 15Ch, according to the BADDR strap pin value, as shown in Table 2-1.
— The Keyboard Controller (KBC) is active and all other logical devices are disabled, with the exception of the SWC
which remains functional but whose registers cannot be accessed.
— All the multiplexed GPIO pins, except KBRST/GPIO17/P12/PNF and GA20/GPIO20, are configured as GPIO pins
and are in TRI-STATE (default direction is input). KBRST/GPIO17/P12/PNF is configured as KBRST and
GA20/GPIO20 is configured as GA20.
•
In the event of either a hardware or a software reset:
— The legacy devices are assigned with their legacy system resource allocation.
— The National proprietary functions are not assigned with any default resources and the default values of their base
addresses are all 00h.
2.2.6
Address Decoding
A full 16-bit address decoding is applied when accessing the configuration I/O space as well as the registers of the functional
blocks. However, the number of configurable bits in the base address registers vary for each device.
The lower 1, 2, 3 or 4 address bits are decoded within the functional block to determine the offset of the accessed register,
within the device’s I/O range of 2, 4, 8 or 16 bytes, respectively. The rest of the bits are matched with the base address
register to decode the entire I/O range allocated to the device. Therefore the lower bits of the base address register are
forced to 0 (read-only), and the base address is forced to be 2, 4, 8 or 16 byte aligned, according to the size of the IO range.
The base address of the FDC, Serial Port 1, Serial Port 2 and KBC are limited to the I/O address range of 00h to 7FXh only
(bits 11-15 are forced to 0). The Parallel Port base address is limited to the I/O address range of 00h to 3F8h. The addresses
of the non-legacy devices are configurable within the full 16-bit address range (up to FFFXh).
In some special cases, other address bits are used for internal decoding (such as bit 2 in the KBC and bit 10 in the PP). The
KBC has two I/O descriptors with some implied dependency between them. For more details, please see the detailed description of the base address register for each specific logical device.
2.2.7
The Internal Clocks
The source of the device internal clocks is a 48 MHz clock signal, which is routed through the CLKIN pin. Wake-up on KBD,
Mouse and RING pulse train detection operates on internally generated clock.
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CONFIGURATION STRUCTURE AND ACCESS
2.0 Device Architecture and Configuration
REGISTER TYPE ABBREVIATIONS
2.0 Device Architecture and Configuration
2.3
(Continued)
REGISTER TYPE ABBREVIATIONS
The register maps in this chapter use the following abbreviations for Type:
• R/W = Read/Write
•
•
•
•
R = Read from a specific address returns the value of a specific register. Write to the same address is to a different
register.
W = Write
RO = Read Only
R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
2.4
SUPERI/O CONFIGURATION AND CONTROL REGISTERS
This section describes the registers with first level indexes in the range 07h - 2Fh.
2.4.1
SuperI/O Register Map
Index Mnemonic
Name
Type
Section
07h
LDN
Logical Device Number Register
R/W
2.2.2
20h
SID
SuperI/O ID Register
RO
2.4.2
21h
SIOCF1
SuperI/O Configuration 1 Register
R/W
2.4.3
22h
SIOCF2
SuperI/O Configuration 2 Register
R/W
23h
SIOCF3
SuperI/O Configuration 3 Register
R/W
2.4.5
24h
SIOCF4
SuperI/O Configuration 4 Register
R/W
2.4.6
27h
SRID
SuperI/O Revision ID Register
RO
2.4.7
2Eh Reserved exclusively for National use
2.4.2
SuperI/O ID Register (SID)
This register contains the identity number of the chip. The PC87351 is identified by the value E2h.
Location:
Index 20h
Type:
RO
Bit
7
6
5
4
1
1
1
0
Name
Reset
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3
2
1
0
0
0
1
0
Chip ID
30
2.4.3
(Continued)
SuperI/O Configuration 1 Register (SIOCF1)
Location:
Index 21h
Type:
R/W
Bit
7
6
General Purpose
Scratch
Name
Reset
0
5
4
3
2
1
0
Lock
Scratch
PNF Status
Reserved
Pin
Function
Lock
SW Reset
Global
Device
Enable
0
1
0
0
0
1
0
Bit
Description
7-6
General Purpose Scratch. When bit 5 is set to 1, these bits are read only. After reset, these bits can be read
or write. Once changed to read only, the bits can be changed back to read/write only by a hardware reset.
5
Lock Scratch. This bit controls bits 7 and 6 of this register. Once this bit is set to 1 by software, it can be
cleared to 0 only by a hardware reset.
0: Bits 7 and 6 of this register are read/write bits (default).
1: Bits 7 and 6 of this register are read only bits.
4
PNF Status. This read only bit reflects the value of the PNF pin when PPM mode is enabled. If PPM mode is
disabled, this bit is 1. Data written to this bit is ignored.
3
Reserved
2
Pin Function Lock. When this bit is set to 1, all function selection on the associated pins is locked:
•
•
•
All bits of the SIOCF2 Register
Bits 4-0 of the SIOCF3 Register
Bits 3-0 of the SIOCF4 Register.
When this bit is set to 1 by software, it can only be cleared to 0 by MR or power-off.
0: No effect (default)
1: Pin function locked
1
SW Reset. Read always returns 0.
0: Ignored (default)
1: Resets all the devices that are reset by MR (with the exception of the lock bits) and the registers of the SWC
0
Global Device Enable. This bit controls the function enable of all the logical devices in the PC87351, except the
SWC. It allows them to be disabled simultaneously by writing to a single bit.
0: All logical devices in the PC87351 disabled, except SWC
1: Each logical device enabled according to its Activate Register at index 30h (default)
31
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SUPERI/O CONFIGURATION AND CONTROL REGISTERS
2.0 Device Architecture and Configuration
SUPERI/O CONFIGURATION AND CONTROL REGISTERS
2.0 Device Architecture and Configuration
2.4.4
(Continued)
SuperI/O Configuration 2 Register (SIOCF2)
This register controls pin multiplexing of pins: 34, 35, 37-43, 98 and 99.
Location:
Index 22h
Type:
R/W
Bit
7
Pin 99
Function
Select
1
Name
Reset
6
Pin 98 Function Select
0
Bit
Pin 99 Function Select
0: GPIO20
1: GA20 (default).
6-5
Pin 98 Function Select
2-1
0
1
4
3
Pin 42 Function Select
0
0
2
1
Pin 41 Function Select
0
0
Select
Serial IRQ
0
1
Description
7
4-3
5
Bits
6 5
Function
0
0
1
1
GPIO17
KBRST (default)
P12
PNF (PPM mode enabled)
0
1
0
1
Pin 42 Function Select. The setting of bit 0 of this register effects the function selected, as follows:
Bits
4 3 0
Function
0
0
0
1
1
GPIO15 (default)
GPIO15
IRQ11
P12
P17
0
1
1
0
1
X
1
0
X
X
Pin 41 Function Select. The setting of bit 0 of this register effects the function selected, as follows:
Bits
2 1 0
Function
0
0
0
1
1
GPIO14 (default)
GPIO14
IRQ9
IRRX2/IRSL0
P17
0
1
1
0
1
X
1
0
X
X
Select Serial IRQ
0: Pins 34, 35, 37-40 and 43 function as IRQ1, IRQ3-7 and IRQ12, respectively
1: Pins 34 and 35 function as PCICLK and SERIRQ, respectively. Pins 37-40 and 43 function as GPIO (default).
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32
2.4.5
(Continued)
SuperI/O Configuration 3 Register (SIOCF3)
This register controls multiplexing of pins: 112-115, 117-119 and 127-128.
Location:
Index 23h
Type:
R/W
Bit
7
Name
6
Reserved
Reset
0
0
Bit
Reserved
4-3
Pin 128 Function Select
0
0
4
3
2
1
0
Select
Pin 128 Function Select Pin 127 Function Select
Serial Port 2
0
0
0
0
0
Description
7-5
2-1
5
Bits
4 3
Function
0
0
1
1
GPIO22 (default)
FANOUT1
IRRX2/IRSL0
P17
0
1
0
1
Pin 127 Function Select
Bits
2 1
Function
0
0
1
1
GPIO21 (default)
FANOUT0
P12
PNF (PPM mode enabled)
0
1
0
1
Select Serial Port 2
0: Pins 112-115 and 117-119 function as GPIO10-16 (default)
1: Pins 112-115 and 117-119 function as Serial Port 2
33
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SUPERI/O CONFIGURATION AND CONTROL REGISTERS
2.0 Device Architecture and Configuration
SUPERI/O CONFIGURATION AND CONTROL REGISTERS
2.0 Device Architecture and Configuration
2.4.6
(Continued)
SuperI/O Configuration 4 Register (SIOCF4)
This register controls the multiplexing of two pins. Its value is retained by VPP, and is not affected by either hardware or software reset.
Location:
Index 24h
Type:
R/W
Bit
7
Name
SUSP Value
Reset
X
6
5
General Purpose Scratch
0
0
Bit
7
6-4
4
0
3
PME2
Debounce
Enable
1
2
Pin 126
Function
Select
0
1
PME1
Debounce
Enable
1
Description
SUSP Value. Last value of SUSP pin prior to VSB loss (power-fail).
General Purpose Scratch. Battery-backed.
3
PME2 Debounce Enable
0: Debounce disabled
1: 16mS debounce enabled (VPP power-up default)
2
Pin 126 Function Select
0: Pin 126 functions as SUSP (VPP power-up default)
1: Pin 126 functions as PME2
1
PME1 Debounce Enable
0: Debounce disabled
1: 16mS debounce enabled (VPP power-up default)
0
Pin 125 Function Select
0: RING (VPP power-up default)
1: PME1
2.4.7
SuperI/O Revision ID Register (SRID)
This read only register contains the identity number of the chip revision. SRID is incremented on each revision.
Location:
Index 27h
Type:
RO
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34
0
Pin 125
Function
Select
0
2.5
(Continued)
PARALLEL PORT MULTIPLEXER (PPM)
The Parallel Port Multiplexer (PPM) logic allows connection of an external Floppy Disk Drive (FDD) through the Parallel Port
connector (25-pin DIN), instead of, or in addition to, the internal FDD on the normal FDC header. This is done by turning the
Parallel Port pins (normally used by the Parallel Port) into an additional set of FDC pins, while isolating them from the Parallel
Port functionality.
A printer (or any other parallel device) may be exchanged with an external FDD, without turning the system off. The PPM
logic automatically detects whether a parallel device or the FDD is connected, and routes the Parallel Port pins to either the
Parallel Port or the FDC functional blocks, accordingly. See Figure 2-4.
PPM mode is enabled by selecting the PNF pin. When PPM mode is enabled, it is controlled by the PNF input pin, as follows:
•
•
When PNF = 1, PPM is inactive and the Parallel Port pins are assigned Parallel Port functionality.
When PNF = 0, PPM is active and the Parallel Port pins are assigned FDC functionality.
When PPM mode is disabled, the Parallel Port pins are assigned Parallel Port functionality, regardless of the value of PNF.
The internal FDD (on the normal FDC pins) and the external FDD (on the Parallel Port pins) can be assigned as Drive A and
Drive B respectively, or vice versa.
FDC Outputs
FDC Pins
FDC
FDC Inputs
0
1
PPM Active and
Drive 1 or 3 Selected
FDC Outputs
FDC Inputs
PPM Active
Parallel Port Pins
Parallel Port
Outputs
Parallel
Port
Parallel Port Inputs
0
1
Default “Non-Connect”
Parallel Port Input Values
Figure 2-4. PPM Routing
2.5.1
PPM Mode
The Parallel Port pins function as FDD interface for either drive 1 or drive 3. See Figure 2-4 for the internal routing between
the PPM and FDC, and the Parallel Port and FDC pin-sets when PPM mode is active. The FDC output signals are driven
simultaneously both on the normal FDC pins and on the corresponding Parallel Port pins. The FDC inputs are received from
the FDC pins when either drive 0 or drive 2 are selected, and from the corresponding Parallel Port pins when either drive 1
or drive 3 is selected.
The Parallel Port output signals are isolated from the Parallel Port pins. The Parallel Port input signals, as reflected by STR
Register, assume their default values (BUSY = 1, PE = 0, SLCT = 0, ACK = 1), indicating that nothing is connected to the
Parallel Port.
35
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PARALLEL PORT MULTIPLEXER (PPM)
2.0 Device Architecture and Configuration
PARALLEL PORT MULTIPLEXER (PPM)
2.0 Device Architecture and Configuration
2.5.2
(Continued)
TRI-STATE Control of Parallel Port Pins
Normally, the pins of most of the SuperI/O functions can be put in TRI-STATE when the function is disabled. If the TRISTATE control bit of a logical device (normally bit 0 of the Configuration Register at index F0) is set to 1, and its Activate bit
(bit 0 of Activate Register at index 30) is cleared to 0, the output pins of that device are floating. The same is true for the
Parallel Port pins, but TRI-STATE control depends on the current functionality of the pins.
When the PPM is disabled or when a parallel device is connected to the port, then the TRI-STATE of the Parallel Port pins
is controlled by the Parallel Port Activate bit and TRI-STATE control bit. However, when the PPM is enabled and the external
FDD is connected (PNF=0), TRI-STATE is controlled by the corresponding FDC configuration bits.
Table 2-9 shows the standard 25-pin, D-type connector definition for Parallel Port operations in PPM mode.
Table 2-9. Parallel Port Connector Signal Multiplexing
D-Type
Connector Pin
Parallel Port
FDC
PC87351 Pin
Signal
I/O
Signal
I/O
1
95
STB/WRITE
I/O
-
I
2
93
PD0
I/O
INDEX
I
3
91
PD1
I/O
TRK0
I
4
89
PD2
I/O
WP
I
5
87
PD3
I/O
RDATA
I
6
84
PD4
I/O
DSKCHG
I
7
83
PD5
I/O
MSEN0
I
8
82
PD6
I/O
DRATE0
O
PD7
I/O
MSEN1
I
9
81
10
80
ACK
I
DR1
O
11
79
BUSY/WAIT
I
MTR1
O
12
78
PE
I
WDATA
O
13
77
SLCT
I
WGATE
O
14
94
AFD/DSTRB
I/O
DENSEL
O
HDSEL
O
DIR
O
STEP
O
15
92
ERR
I
16
90
INIT
I/O
17
88
SLIN/ASTRB
I/O
18 - 23
24
25
GND
98 or 1271
PNF = Ground
GND
GND
I
PNF = 1
GND
1. The PNF signal is the inverse of pin 24 of the connector (PNF).
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36
I
2.6
(Continued)
FLOPPY DISK CONTROLLER (FDC) - LOGICAL DEVICE 0
2.6.1
General Description
The generic FDC is a standard FDC with a digital data separator, and is DP8473 and N82077 software compatible. The
FDC supports 14 of the 17 standard FDC signals on the normal FDD interface pins, as described in Section 2.4.1. Additionally, the FDC supports another 16 pins, multiplexed on the Parallel Port pins, for external FDD support. See Section 2.5.2
for details on these pins in PPM mode and Section 1.4.3 for signal/pin descriptions.
Table 2-10. FDC Registers
Offset
Mnemonic
00h
SRA
Status Register A
RO
01h
SRB
Status Register B
RO
02h
DOR
Digital Output Register
R/W
03h
TDR
Tape Drive Register
R/W
MSR
Main Status Register
R
04h
05h
Type
DSR
Data Rate Select Register
FIFO
Data (FIFO) Register
N/A
X
DIR
Digital Input Register
R
CCR
Configuration Control Register
W
06h
07h
Name
W
R/W
The FDC is implemented as follows:
•
Automatic media sense is not supported on the standard FDC connector (MSEN0-1 pins are not implemented), but
is supported instead on the Parallel Port pins.
2.6.2
Configuration
Index
Configuration Register or Action
Type
Reset
30h
Activate. See also bit 0 of the SIOCF1 Register.
R/W
00h
60h
Base Address MSB Register. Bits 7-3 (for A15-11) are read only, 00000b.
R/W
03h
61h
Base Address LSB Register. Bits 2 and 0 (for A2 and A0) are read only, 00b.
R/W
F2h
70h
Interrupt Number
R/W
06h
71h
Interrupt Type. Bit 1 is read/write; other bits are read only.
R/W
03h
74h
DMA Channel Select
R/W
02h
75h
Report no second DMA assignment
R
04h
F0h
FDC Configuration Register
R/W
24h
F1h
Drive ID Register
R/W
00h
37
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FLOPPY DISK CONTROLLER (FDC) - LOGICAL DEVICE 0
2.0 Device Architecture and Configuration
FLOPPY DISK CONTROLLER (FDC) - LOGICAL DEVICE 0
2.0 Device Architecture and Configuration
2.6.3
(Continued)
FDC Configuration Register
This register is reset by hardware to 20h.
Location:
Index F0h
Type:
R/W
Bit
7
Four Drive
Control
Name
Reset
Required
0
6
TDR
Register
Mode
0
5
DENSEL
Polarity
Control
1
Bit
4
3
Reserved
Write
Protect
0
0
0
2
1
PC-AT or
PS/2 Drive Reserved
Mode Select
1
0
0
TRI-STATE
Control
0
Description
7
Four Drive Control
0: Two floppy drives directly controlled by DR1-0 and MTR1-0 (default)
1: Four floppy drives controlled with the aid of external logic
6
TDR Register Mode
0: PC-AT compatible drive mode; i.e., bits 7-2 of the TDR are ignored (default)
1: Enhanced drive mode
5
DENSEL Polarity Control
0: Active low for 500 Kbps or 1 Mbps data rates
1: Active high for 500 Kbps or 1 Mbps data rates (default)
4
Reserved. Must be 0.
3
Write Protect. This bit allows forcing of write protect by software. When set, write to the floppy disk drive is
disabled. This effect is identical to WP when it is active.
0: Write protected according to WP signal (default)
1: Write protected regardless of value of WP signal
2
PC-AT or PS/2 Drive Mode Select
0: PS/2 drive mode
1: PC-AT drive mode (default)
1
Reserved
0
TRI-STATE Control. When disabled, this bit controls the TRI-STATE status of the logical device output pins.
0: Disabled (default)
1: Enabled when device inactive
2.6.4
Drive ID Register
This read/write register is reset by hardware to 00h. These bits control bits 5 and 4 of the enhanced TDR Register.
Location:
Index F1h
Type:
R/W
Bit
Name
Reset
7
6
0
0
5
4
3
0
0
0
Reserved
Bit
2
1
0
0
Drive 1 ID
0
Drive 0 ID
0
Description
7-4
Reserved
3-2
Drive 1 ID. These bits are reflected on bits 5 and 4 of the TDR Register, respectively, when drive 1 is accessed.
1-0
Drive 0 ID. These bits are reflected on bits 5 and 4 of the TDR Register, respectively, when drive 0 is accessed.
Usage Hints: Some BIOS implementations support automatic media sense FDD, and bit 5 of the TDR is interpreted as valid
media sense when it is cleared to 0. If drive 0 and/or drive 1 do not support automatic media sense, bits 1 and/or 3 of the
Drive ID Register should be set to 1 respectively, to indicate non-valid media sense, when the corresponding drive is selected and the Drive ID bit is reflected on bit 5 of TDR.
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2.7
2.7.1
(Continued)
PARALLEL PORT - LOGICAL DEVICE 1
General Description
The PC87351 Parallel Port device offers a wide range of operational configurations. It utilizes the most advanced protocols
in current use, while maintaining full backward compatibility to support existing hardware and software. It supports two Standard Parallel Port (SPP) modes of operation for parallel printer ports, two Enhanced Parallel Port (EPP) modes of operation,
and one Extended Capabilities Port (ECP) mode. This versatility is achieved by user software control of the mode in which
the device functions. The following table lists the Parallel Port Registers used in each mode of operation.
Note: The Parallel Port does not support zero wait states.
Table 2-11. Parallel Port Registers Classified by Mode
Offset
SPP
EPP
ECP
00h
DTR
DTR
DATAR (modes 0,1)
AFIFO (mode 3)
01h
STR
STR
DSR
02h
CTR
CTR
DCR
03h
X
ADDR
X
04h
X
DATA0
X
05h
X
DATA1
X
06h
X
DATA2
X
07h
X
DATA3
X
400h
X
X
CFIFO (mode 2)
DFIFO (mode 3)
TFIFO (mode 6)
CNFGA (mode 7)
401h
X
X
CNFGB
402h
X
X
ECR
403h
X
X
EIR1
404h
X
X
EDR1
405h
X
X
EAR1
1. These registers are extended, and not standard 1284 registers.
They are accessible only when enabled by bit 4 of the Parallel Port
Configuration Register (see Section 2.7.3).
2.7.2
Configuration
Index
Configuration Register or Action
Type
Reset
30h Activate. See also bit 0 of the SIOCF1 Register.
R/W
00h
60h Base Address MSB Register. Bits 7-3 (for A15-11) are read only, 00000b.
R/W
02h
61h Base Address LSB Register. Bits 1 and 0 (for A1 and A0) are read only, 00b.
R/W
78h
70h Interrupt Number
R/W
07h
71h Interrupt Type
Bits 7-2 are read only.
Bit 1 is a read/write bit.
Bit 0 is read only. It reflects the interrupt type dictated by the Parallel Port operation
mode and configured by the Parallel Port Configuration Register. This bit is set to 1
(level interrupt) in Extended Mode and cleared (edge interrupt) in all other modes.
R/W
02h
74h DMA Channel Select
R/W
04h
75h Report no second DMA assignment
RO
04h
F0h Parallel Port Configuration Register
R/W
F2h
39
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PARALLEL PORT - LOGICAL DEVICE 1
2.0 Device Architecture and Configuration
PARALLEL PORT - LOGICAL DEVICE 1
2.0 Device Architecture and Configuration
2.7.3
(Continued)
Parallel Port Configuration Register
This register is reset by hardware to F2h.
Note: For normal operation and to maintain compatibility with future chips, do not change bits 7 through 4.
Location:
Index F0h
Type:
R/W
Bit
7
Name
6
Parallel Port Mode Select
Reset
1
1
Bit
7-5
4
3-2
5
1
4
3
Extended
Register
Access
1
2
Reserved
0
1
0
Power
Mode
Control
TRI-STATE
Control
1
0
0
Description
Parallel Port Mode Select. Selection of EPP 1.7 or 1.9 in ECP mode 4 is controlled by bit 4 of the Control2
Configuration Register of the parallel port at offset 02h.
Bits
7 6 5
Mode
0 0 0
SPP Compatible; PD7-0 always output signals
0 0 1
SPP Extended; PD7-0 direction controlled by software
0 1 0
EPP 1.7
0 1 1
EPP 1.9
1 0 0
IEEE1284 (selects IEEE1284 register set), without embedded EPP support
1 0 1
Reserved
1 1 0
Reserved
1 1 1
IEEE1284 (selects IEEE1284 register set), with EPP mode selectable as mode 4 (default)
Extended Register Access
0: Registers at base (address) + 403h, base + 404h and base + 405h are not accessible (reads and writes are ignored).
1: When ECP is selected by bits 7 through 5, the registers at base (address) + 403h, base + 404h and base +
405h are accessible. This option supports run-time configuration within the Parallel Port address space.
Reserved
1
Power Mode Control. When the logical device is active:
0: Parallel port clock disabled
ECP modes and EPP time-out are not functional when the logical device is active. Registers are maintained.
1: Parallel port clock enabled
All operation modes are functional when the logical device is active (default).
0
TRI-STATE Control. This bit controls the TRI-STATE status of the logical device output pins when it is inactive
(disabled).
0: Disabled (default)
1: Enabled when device inactive
Usage Hints: Parallel Port modes determine which address bits are used for register addresses. In SPP mode, 14 bits are
used to decode Parallel Port base addresses. In ECP and EPP modes, 13 address bits are used. Table 2-11 shows which
registers and address bits are used in each mode.
The settings of the CTR Register bits listed below control selection of Parallel Port modes, as follows:
•
•
When changing to ECP mode from any other mode, bit 2 must be set to 1, and bits 3 and 4 must be set to 0.
When changing from SPP to EPP mode, bit 3 must be set to 0.
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40
2.8
SERIAL PORT 2 - LOGICAL DEVICE 2
2.0 Device Architecture and Configuration
(Continued)
SERIAL PORT 2 - LOGICAL DEVICE 2
2.8.1
General Description
Serial Port 2 includes IR functionality as described in the Serial Port 2 with IR chapter.
2.8.2
Configuration
Index
2.8.3
Configuration Register or Action
Type
Reset
30h Activate. See also bit 0 of the SIOCF1 Register.
R/W
00h
60h Base Address MSB Register. Bits 7-3 (for A15-11) are read only, 00000b.
R/W
02h
61h Base Address LSB Register. Bit 2-0 (for A2-0) are read only, 000b.
R/W
F8h
70h Interrupt Number
R/W
03h
71h Interrupt Type. Bit 1 is R/W; other bits are read only.
R/W
03h
74h DMA Channel Select 0 (RX_DMA)
R/W
04h
75h DMA Channel Select 1 (TX_DMA)
R/W
04h
F0h Serial Port 2 Configuration Register
R/W
02h
Serial Port 2 Configuration Register
This register is reset by hardware to 02h.
Location:
Index F0h
Type:
R/W
Bit
7
Name
Bank
Select
Enable
Reset
0
Bit
7
6-3
6
5
4
3
Reserved
0
0
0
0
2
1
0
Busy
Indicator
Power
Mode
Control
TRI-STATE
Control
0
1
0
Description
Bank Select Enable. Enables bank switching for Serial Port 2.
0: All attempts to access the extended registers in Serial Port 2 are ignored (default).
1: Enables bank switching for Serial Port 2.
Reserved
2
Busy Indicator. This read only bit can be used by power management software to decide when to power-down
the Serial Port 2 logical device.
0: No transfer in progress (default).
1: Transfer in progress.
1
Power Mode Control. When the logical device is active in:
0: Low power mode
Serial Port 2 Clock disabled. The output signals are set to their default states. The RI input signal can be
programmed to generate an interrupt. Registers are maintained. (Unlike Active bit in Index 30 that also
prevents access to Serial Port 2 registers.)
1: Normal power mode
Serial Port 2 clock enabled. Serial Port 2 is functional when the logical device is active (default).
0
TRI-STATE Control. This bit controls the TRI-STATE status of the device output pins when it is inactive
(disabled). One exception is the IRTX pin. It is driven to 0 when Serial Port 2 is inactive, and is not affected by
this bit.
0: Disabled (default)
1: Enabled when device inactive
41
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SERIAL PORT 1 - LOGICAL DEVICE 3
2.0 Device Architecture and Configuration
2.9
(Continued)
SERIAL PORT 1 - LOGICAL DEVICE 3
2.9.1
Configuration
Index
Configuration Register or Action
30h Activate. See also bit 0 of the SIOCF1 Register.
2.9.2
Type
Reset
R/W
00h
60h Base Address MSB Register. Bits 7-3 (for A15-11) are read only, 00000b.
R/W
03h
61h Base Address LSB Register. Bit 2-0 (for A2-0) are read only, 000b.
R/W
F8h
70h Interrupt Number
R/W
04h
71h Interrupt Type. Bit 1 is R/W; other bits are read only.
R/W
03h
74h Report no DMA Assignment
R/W
04h
75h Report no DMA Assignment
R/W
04h
F0h Serial Port 1 Configuration Register
R/W
02h
Serial Port 1 Configuration Register
This register is reset by hardware to 02h.
Location:
Index F0h
Type:
R/W
Bit
7
Name
Reset
0
Bit
7
6-3
6
5
Bank
Select
Enable
4
3
Reserved
0
0
0
0
2
1
0
Busy
Indicator
Power
Mode
Control
TRI-STATE
Control
0
1
0
Description
Bank Select Enable. Enables bank switching for Serial Port 1.
0: Disabled (default).
1: Enabled
Reserved
2
Busy Indicator. This read only bit can be used by power management software to decide when to power-down
the Serial Port 1 logical device.
0: No transfer in progress (default).
1: Transfer in progress.
1
Power Mode Control. When the logical device is active in:
0: Low power mode
Serial Port 1 Clock disabled. The output signals are set to their default states. The RI input signal can be
programmed to generate an interrupt. Registers are maintained. (Unlike Active bit in Index 30 that also
prevents access to Serial Port 1 registers.)
1: Normal power mode
Serial Port 1 clock enabled. Serial Port 1 is functional when the logical device is active (default).
0
TRI-STATE Control. This bit controls the TRI-STATE status of the device output pins when it is inactive
(disabled). One exception is the IRTX pin. It is driven to 0 when Serial Port 1 is inactive, and is not affected by
this bit.
0: Disabled (default)
1: Enabled when device inactive
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42
2.10
(Continued)
SYSTEM WAKE-UP CONTROL (SWC) - LOGICAL DEVICE 4
2.10.1 Configuration
Index
Configuration Register or Action
Type
Reset
30h
Activate. When bit 0 is cleared, the registers of this logical device are not
accessible.1
R/W
00h
60h
Base Address MSB Register
R/W
00h
61h
Base Address LSB Register. Bits 3-0 (for A3-0) are read only, 0000b.
R/W
00h
70h
Interrupt Number (For routing the PWUREQ signal).
R/W
00h
71h
Interrupt Type. Bit 1 is read/write. Other bits are read only.
R/W
03h
74h
Report no DMA assignment
RO
04h
75h
Report no DMA assignment
RO
04h
1. The logical device registers are maintained, and all wake-up detection mechanisms are functional.
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SYSTEM WAKE-UP CONTROL (SWC) - LOGICAL DEVICE 4
2.0 Device Architecture and Configuration
KEYBOARD AND MOUSE CONTROLLER (KBC) - LOGICAL DEVICES 5 AND 6
2.0 Device Architecture and Configuration
2.11
(Continued)
KEYBOARD AND MOUSE CONTROLLER (KBC) - LOGICAL DEVICES 5 AND 6
2.11.1 General Description
The KBC is implemented physically as a single hardware module and houses two separate logical devices: a Mouse controller (logical device 5) and a Keyboard controller (logical device 6).
The hardware KBC module is integrated to provide the following pin functions: P12, P17, KBRST (P20), GA20 (P21),
KBDAT, KBCLK, MDAT, and MCLK. P12 and P17 are implemented as quasi bi-directional pins, meaning that they are driven
high by the output buffer for a short period, following a low to high transition of the pins, and then left in TRI-STATE. KBRST
and GA20 are implemented as bi-directional, open-drain pins. The Keyboard and Mouse interfaces are implemented as bidirectional, open-drain pins. Their internal connections are shown in Figure 2-5.
P10, P11, P13-P16, P22-P27 of the KBC core are not available on dedicated pins; neither are T0 and T1. P10, P11, P22,
P23, P26, P27, T0 and T1 are used to implement the Keyboard and Mouse interface.
Internal pull-ups are implemented only on P12 and P17.
The KBC executes a program fetched from an on-chip 2Kbyte ROM. The code programmed in this ROM is user-customizable. The KBC has two interrupt request signals: one for the Keyboard and one for the Mouse. The interrupt requests are
implemented using ports P24 and P25 of the KBC core. The interrupt requests are controlled exclusively by the KBC firmware, except for the type and number, which are affected by configuration registers (see Section 2.11.2).
The interrupt requests are implemented as bi-directional signals. When an I/O port is read, all unused bits return the value
latched in the output registers of the ports.
For KBC firmware that implements interrupt-on-OBF schemes, it is recommended to implement it as follows:
1. Put the data in DBBOUT.
2. Set the appropriate port bit to issue an interrupt request.
KBC
Internal Interface Bus
P12
P12
P17
P17
STATUS
P20
KBRST
DBBIN
P21
GA20
P26
KBCLK
DBBOUT
T0
P27
KBDAT
P10
P23
MCLK
T1
KBD IRQ
Matrix
P22
P24
PnP
Mouse IRQ
P11
P25
Figure 2-5. Keyboard and Mouse Interfaces
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44
MDAT
(Continued)
2.11.2 Configuration
Index
Mouse Configuration Register or Action
Type
Reset
30h
Activate. See also bit 0 of the SIOCF1. When the Mouse of the KBC is inactive, the
IRQ selected by the Mouse Interrupt Number Register (index 70h) is not asserted.
This register has no effect on host KBC commands handling the PS/2 Mouse.
R/W
00h
70h
Mouse Interrupt Number
R/W
0Ch
71h
Mouse Interrupt Type. Bits 1,0 are read/write; other bits are read only.
R/W
02h
74h
Report no DMA assignment
RO
04h
75h
Report no DMA assignment
RO
04h
Type
Reset
Index
Keyboard Configuration Register or Action
30h
Activate. See also bit 0 of the SIOCF1.
R/W
01h
60h
Base Address MSB Register. Bits 7-3 (for A15-11) are read only, 00000b.
R/W
00h
61h
Base Address LSB Register. Bits 2-0 are read only 000b.
R/W
60h
62h
Command Base Address MSB Register. Bits 7-3 (for A15-11) are read only, 00000b.
R/W
00h
63h
Command Base Address LSB. Bits 2-0 are read only 100b.
R/W
64h
70h
KBC Interrupt Number
R/W
01h
71h
KBC Interrupt Type. Bits 1,0 are read/write; others are read only.
R/W
02h
74h
Report no DMA assignment
RO
04h
75h
Report no DMA assignment
RO
04h
F0h
KBC Configuration Register
R/W
40h
2.11.3 KBC Configuration Register
This register is reset by hardware to 40h.
Location:
Index F0h
Type:
R/W
Bit
7
Name
6
4
KBC Clock Source
Reset
Required
0
1
Bit
7-6
5
3
2
1
0
0
0
Reserved
0
0
0
0
TRI-STATE
Control
0
Description
KBC Clock Source. The clock source can be changed only when the KBC is inactive (disabled).
Bits
7 6
Function
0
0
1
1
8 MHz
12 MHz (default)
16 MHz
Reserved
0
1
0
1
5-1
Reserved. Use read-modify-write to change the value of the register. Do not change the value of these bits. Bit
2 must be 0.
0
TRI-STATE Control. If KBC is inactive (disabled) when this bit is set, the KBC pins (KBCLK and KBDAT) are in TRISTATE. If Mouse is inactive (disabled) when this bit is set, the Mouse pins (MCLK and MDAT) are in TRI-STATE.
0: Disabled (default)
1: Enabled when device inactive
Usage Hints: When required to change the clock frequency of the KBC, perform the following:
1. Disable the KBC logical device.
2. Change the frequency setting.
3. Enable the KBC logical device.
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KEYBOARD AND MOUSE CONTROLLER (KBC) - LOGICAL DEVICES 5 AND 6
2.0 Device Architecture and Configuration
GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS - LOGICAL DEVICE 7
2.0 Device Architecture and Configuration
2.12
(Continued)
GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS - LOGICAL DEVICE 7
2.12.1 General Description
The GPIO functional block includes 11 pins, arranged in one 8-bit port and one 3-bit port. Both of these ports are standard.
The eight runtime registers of these ports are arranged in the GPIO address space shown in Table 2-12. The GPIO base
address is 8-byte aligned. Address bits 2-0 are used to indicate the register offset.
Table 2-12. Runtime Registers in GPIO Address Space
Offset
Mnemonic
00h
GPDO1
Name
Reset
GPIO Data Out 1 Register
FFh
Port
Type
R/W
01h
GPDI1
GPIO Data In 1 Register
XXh
02h
GPIEN1
GPIO Interrupt Enable 1 Register
00h
03h
GPST1
GPIO Status 1 Register
00h
R/W1C
04h
GPDO2
GPIO Data Out 2 Register
07h
R/W
05h
GPDI2
GPIO Data In 2 Register
0Xh
06h
GPIEN2
GPIO Interrupt Enable 2 Register
00h
07h
GPST2
GPIO Status 2 Register
00h
1
2
RO
R/W
RO
R/W
R/W1C
2.12.2 Implementation
The standard GPIO port has four runtime registers. Each pin is associated with a configuration register that includes seven
configuration bits.
2.12.3 Configuration
Index
Configuration Register or Action
Type
Reset
R/W
00h
30h
Activate. See also bit 0 of the SIOCF1 Register.
60h
Base Address MSB Register
R/W
00h
61h
Base Address LSB Register. Bits 2-0 (for A2-0) are read only, 000b.
R/W
00h
70h
Interrupt Number (For routing the IRQ from the GPIO).
R/W
00h
71h
Interrupt Type. Bit 1 is read/write. Other bits are read only.
R/W
03h
74h
Report no DMA assignment
R
04h
75h
Report no DMA assignment
R
04h
F0h
GPIO Pin Configuration Select Register
R/W
00h
F1h
GPIO Pin Configuration Access Register
R/W
00h
Figure 2-6 describes the organization of these registers.
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46
(Continued)
Pin Configuration Select Register
Port Select
Pin Select
7
6
5
4
3
2 1
0
Port 1
Configuration
Pin Configuration
Access Register
Port 2
Configuration
Reserved
Figure 2-6. GPIO Configuration Registers’ Access
2.12.4 GPIO Pin Configuration Select Register
This register selects the GPIO pin (port number and bit number) to be configured (i.e., which register is accessed via the
GPIO Pin Configuration Access Register). It is reset by hardware to 00h.
Location:
Index F0h
Type:
R/W
Bit
7
Name
6
5
Reserved
Reset
0
Bit
4
Port Select
0
0
3
Reserved
0
Reserved
5-4
Port Select. These bits select the GPIO port to be configured:
00: Reserved (default)
01, 10: Binary value of the port number, 1-2 respectively
11: Reserved
3
0
1
0
Pin Select
0
0
0
Description
7-6
2-0
2
Reserved
Pin Select. These bits select the GPIO pin to be configured in the selected port:
0-7: Binary value of the pin number, 0-7 respectively (default=0)
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GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS - LOGICAL DEVICE 7
2.0 Device Architecture and Configuration
GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS - LOGICAL DEVICE 7
2.0 Device Architecture and Configuration
(Continued)
2.12.5 GPIO Pin Configuration Access Register
This register reflects, for both read and write, the register currently selected by the GPIO Pin Configuration Select Register.
All the configuration registers that are accessed via this register have a common bit structure, as shown below. This register
is reset by hardware to 44h.
Location:
Index F1h
Type:
R/W
Bit
7
Name
Reserved
Reset
0
6
5
4
IRQ
Debounce IRQ Polarity IRQ Type
Enable
Bit
1
0
0
3
2
1
0
Lock
Pull-Up
Control
Output
Type
Output
Enable
0
1
0
0
Description
7
Reserved
6
IRQ Debounce Enable
0: Disabled
1: Enabled (default)
5
IRQ Polarity. This bit defines the polarity of the signal that issues an interrupt from the corresponding GPIO pin
(falling/low or rising/high).
0: Falling edge or low level input (default)
1: Rising edge or high level input
4
IRQ Type. This bit defines the signal type that issues an interrupt from the corresponding GPIO pin.
0: Edge input (default)
1: Level input
3
Lock. This bit locks the corresponding GPIO pin. Once this bit is set to 1 by software, it can only be cleared to
0 by system reset or power-off. Pin multiplexing is functional until the Multiplexing Lock bit is 1 (bit 7 of SuperI/O
Configuration 3 Register, SIOCF3).
0: No effect (default)
1: Direction, output type, pull-up and output value locked
2
Pull-Up Control. This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin.
It supports open-drain output signals with internal pull-ups and TTL input signals
0: Disabled
1: Enabled (default)
1
Output Type. This bit controls the output buffer type (open-drain or push-pull) of the corresponding GPIO pin.
0: Open-drain (default)
1: Push-pull
0
Output Enable. This bit indicates the GPIO pin output state. It has no effect on input.
0: TRI-STATE (default)
1: Output enabled
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2.13
(Continued)
FAN SPEED CONTROL - LOGICAL DEVICE 8
2.13.1 General Description
This module includes two Fan Speed Controls. The four runtime registers of the two functional blocks are arranged in the
address space shown in Table 2-13. The base address is 8-byte aligned. Address bits 2-0 are used to indicate the register
offset.
Table 2-13. Runtime Registers in Fan Speed Control Address Space
Offset
Mnemonic
Name
Reset
00h
FCPSR0
Fan Control 0 Pre-Scale Register
00h
01h
FCDCR0
Fan Control 0 Duty Cycle Register
FFh
02h
FCPSR1
Fan Control 1 Pre-Scale Register
00h
03h
FCDCR1
Fan Control 1 Duty Cycle Register
FFh
Function
Type
Fan Speed Control 0
Fan Speed Control 1
R/W
R/W
R/W
R/W
04h-07h Reserved
Table 2-14. Fan Speed Control Runtime Register Bitmap
Register
Bits
Offset
Mnemonic
7
00h
FCPSR0
Clock
Select
01h
FCDCR0
02h
FCPSR1
03h
FCDCR1
04h07h
Reserved
6
5
4
3
2
1
0
Pre-Scale Value
Duty Cycle Value
Clock
Select
Pre-Scale Value
Duty Cycle Value
2.13.2 Configuration
Index
Configuration Register or Action
Type
Reset
R/W
00h
30h
Activate. See also bit 0 of the SIOCF1 Register.
60h
Base Address MSB Register
R/W
00h
61h
Base Address LSB Register. Bits 2-0 (for A2-0) are read only, 000b.
R/W
00h
70h
Interrupt Number
RO
00h
71h
Interrupt Type
RO
00h
74h
Report no DMA assignment
RO
04h
75h
Report no DMA assignment
RO
04h
F0h
Fan Speed Control Configuration Register
R/W
00h
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FAN SPEED CONTROL - LOGICAL DEVICE 8
2.0 Device Architecture and Configuration
FAN SPEED CONTROL - LOGICAL DEVICE 8
2.0 Device Architecture and Configuration
(Continued)
2.13.3 Fan Speed Control Configuration Register
This register is reset by hardware to 00h.
Location:
Index F0h
Type:
R/W
Bit
7
6
Name
Inverse
FANOUT1
Inverse
FANOUT0
Reset
0
0
Bit
5
4
3
Fan Speed Fan Speed
Control 1
Control 0
Enable
Enable
0
0
2
1
TRI-STATE
Control
Reserved
0
0
0
0
0
Description
7
Inverse FANOUT1
0: The number in FCDCR1 indicates for how many clocks (of 256) FANOUT1 signal is high (default).
1: The number in FCDCR1 indicates for how many clocks (of 256) FANOUT1 signal is low.
6
Inverse FANOUT0
0: The number in FCDCR0 indicates for how many clocks (of 256) FANOUT0 signal is high (default).
1: The number in FCDCR0 indicates for how many clocks (of 256) FANOUT0 signal is low.
5
Fan Speed Control 1 Enable. When the Fan Speed Interface logical device is active:
0: Clock disabled (stopped). The FSC1 registers are accessible and maintained. FANOUT1 signal is 0 when
Inverse FANOUT1 bit is 0. FANOUT1 signal is 1 when Inverse FANOUT1 is 1 (default).
1: Clock enabled and registers accessible
4
Fan Speed Control 0 Enable. When the Fan Speed Interface logical device is active:
0: Clock disabled (stopped). The FSC0 registers are accessible and maintained. FANOUT0 signal is 0 when
Inverse FANOUT0 bit is 0. FANOUT0 signal is 1 when Inverse FANOUT0 is 1 (default).
1: Clock enabled and registers accessible
3-1
0
Reserved
TRI-STATE Control. This bit controls the TRI-STATE status of the logical device output pins when it is inactive
(disabled).
0: Disabled (default)
1: Enabled when device inactive
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3.1
OVERVIEW
The SWC wakes up the system by asserting the Power-Up Request (PWUREQ) output pin, in response to the following
maskable system events:
• Modem ring (RI1 and RI2 pins)
•
•
•
•
Telephone ring (RING input pin)
Any keyboard activity or specific programmable key sequence
Any mouse activity or specific programmable click/s
Two general-purpose events (PME1 and PME2 input pins).
This chapter describes the general SWC functional block. A device may include a different implementation. For the device
specific implementation, see the Device Architecture chapter.
3.2
FUNCTIONAL DESCRIPTION
The SWC monitors seven system events or activities. Each one of them is fed into a dedicated detector that decides when
this event is active, according to predetermined (either fixed or programmable) criteria. A set of dedicated registers is used
to determine the wake-up criteria, including the Keyboard sequence.
A Wake-Up Events Status Register (WKSR) and a Wake-Up Events Control Register (WKCR) hold a Status bit and Enable
bit respectively, for each one of the events.
Upon detection of any active event, the corresponding Status bit is set to 1. If the event is enabled (the corresponding Enable
bit is set to 1), the PWUREQ output is asserted. In addition, detection of an active wake-up event may be also routed to any
arbitrary IRQ (or SMI over IRQ2 if Serial IRQ is used).
Disabling an event prevents it from issuing PWUREQ, but does not affect the Status bits. The PWUREQ signal is active
when both the Status and Enable bits equal 1 for at least one event.
The SWC logic is powered by VSB.
The SWC configuration registers are battery backed, powered by VPP. The setup of the wake-up events, including programmable sequences, is retained throughout power failures (no VSB) as long as the battery is connected. VPP is taken from VSB
when power is present; otherwise (power-fail), VBAT is used as the VPP source.
System reset does not affect these registers. They are reset only by software reset or power-up of VPP.
3.3
EVENT DETECTION
3.3.1
Modem Ring
High to low transitions on RI1 or RI2 indicate the detection of ring in external modem connected to Serial Port 1 or 2 respectively and can be used as a wake-up event.
3.3.2
Telephone Ring
A telephone ring can be detected by the SWC by processing the raw signal coming directly from the telephone line into the
RING input pin. Detection of a pulse-train with a frequency higher than 16 Hz that lasts at least 0.3 sec is used as a wakeup event.
The RING pulse-train detection is achieved by monitoring the falling edges on RING in time slots of 62.5 msec (a 16 Hz cycle).
A positive detection occurs if falling edges of RING are detected in three consecutive time slots, following a time slot in which
no RING falling edge is detected. This detection method guarantees the detection of a RING pulse-train with frequencies higher
than 16 Hz. It filters out (does not detect) pulses of less than 10 Hz, and may detect pulses between 10 Hz to 16 Hz.
3.3.3
Keyboard and Mouse Activity
The detection of either any activity or a specific predetermined Keyboard or Mouse activity can be used as a wake-up event.
The Keyboard wake-up detection can be programmed to detect:
• Any keystroke
•
•
A specific programmable sequence of up to eight alphanumeric keystrokes
Any programmable sequence of up to 8 bytes of data received from the keyboard.
The Mouse wake-up detection can be programmed to detect either any Mouse click or movement, or a specific programmable click (left or right) or double-clicks.
3.3.4
General-Purpose Events
A general-purpose event is defined as the detection of falling edge, rising edge, low level, or high level on a specific signal.
Each signal’s event is configurable via software. PME1 and PME2 may wake up the system from power-off state, or generate
an interrupt if the system is in power-on state.
A debouncer of 16 ms is enabled (default) on each event. It may be disabled by software.
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3.0 System Wake-Up Control (SWC)
3.0 System Wake-Up Control (SWC)
SWC REGISTERS
3.0 System Wake-Up Control (SWC)
3.4
(Continued)
SWC REGISTERS
SWC register offsets are related to a base address determined by the SWC Base Address Register in the device configuration.
The register maps in this chapter use the following abbreviations for Type:
• R/W = Read/Write
• R = Read from a specific address returns the value of a specific register. Write to the same address is to a different
register.
• W = Write
• RO = Read Only
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
3.4.1
SWC Register Map
Offset Mnemonic
Name
Section
00h
WKCR
Wake-Up Events Control Register
R/W
3.4.2
01h
WKSR
Wake-Up Events Status Register
R/W1C
3.4.3
02h
WKCFG
Wake-Up Configuration Register
R/W
3.4.4
03h
PS2CTL
PS/2 Protocol Control Register
R/W
3.4.5
06h
KDSR
Keyboard Data Shift Register
RO
3.4.6
07h
MDSR
Mouse Data Shift Register
RO
3.4.7
R/W
3.4.8
08h- PS2KEY0PS/2 Keyboard Key Data Registers
0Fh PS2KEY7
3.4.2
Type
Wake-Up Events Control Register (WKCR)
This register is set to 07h on power-up of VPP or software reset. Detected wake-up events that are enabled activate the
PWUREQ signal.
Location:
Offset 00h
Type:
R/W
Bit
7
6
5
4
3
2
1
0
Name
PME2
Event
Enable
PME1
Event
Enable
Reserved
Mouse
Event
Enable
KBD
Event
Enable
RING
Event
Enable
RI2
Event
Enable
RI1
Event
Enable
Reset
0
0
0
0
0
1
1
1
Bit
Description
7
PME2 Event Enable
0: Disabled (default)
1: Enabled
6
PME1 Event Enable
0: Disabled (default)
1: Enabled
5
Reserved
4
Mouse Event Enable
0: Disabled (default)
1: Enabled
3
KBD Event Enable
0: Disabled (default)
1: Enabled
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52
(Continued)
Bit
Description
2
RING Event Enable
0: Disabled
1: Enabled (default)
1
RI2 Event Enable
0: Disabled
1: Enabled (default)
0
RI1 Event Enable
0: Disabled
1: Enabled (default)
3.4.3
SWC REGISTERS
3.0 System Wake-Up Control (SWC)
Wake-Up Events Status Register (WKSR)
This register is set to 00h on power-up of VPP or software reset. It indicates which wake-up events occurred.
Location:
Offset 01h
Type:
R/W1C
Bit
7
6
5
4
3
2
1
0
Name
PME2
Event
Status
PME1
Event
Status
Reserved
Mouse
Event
Status
KBD
Event
Status
RING
Event
Status
RI2
Event
Status
RI1
Event
Status
Reset
0
0
0
0
0
0
0
0
Bit
Description
7
PME2 Event Status
0: Event not detected (default)
1: Event detected
6
PME1 Event Status
0: Event not detected (default)
1: Event detected
5
Reserved
4
Mouse Event Status
0: Event not detected (default)
1: Event detected
3
KBD Event Status
0: Event not detected (default)
1: Event detected
2
RING Event Status
0: Event not detected (default)
1: Event detected
1
RI2 Event Status
0: Event not detected (default)
1: Event detected
0
RI1 Event Status
0: Event not detected (default)
1: Event detected
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SWC REGISTERS
3.0 System Wake-Up Control (SWC)
3.4.4
(Continued)
Wake-Up Configuration Register (WKCFG)
This register is set to 00h on power-up of VPP or software reset.
Location:
Offset 02h
Type:
R/W
Bit
7
6
5
4
3
2
Name
Reserved
PME2 Type
PME2
Polarity
PME1 Type
PME1
Polarity
Swap KBC
Inputs
Reset
0
0
0
0
0
0
Bit
Reserved
6
PME2 Type
0: Edge
1: Level
5
PME2 Polarity
0: Falling edge, low level
1: Rising edge, high level
4
PME1 Type
0: Edge
1: Level
3
PME1 Polarity
0: Falling edge, low level
1: Rising edge, high level
2
Swap KBC Inputs
0: No swapping (default)
1: KBD (KBCLK, KBDAT) and Mouse (MCLK, MDAT) inputs swapped
3.4.5
0
Reserved
0
0
Description
7
1-0
1
Reserved
PS/2 Protocol Control Register (PS2CTL)
This register is set to 00h on power-up of VPP or software reset. It configures the PS/2 Keyboard and Mouse wake-up features.
Location:
Offset 03h
Type:
R/W
Bit
7
Name
Disable
Parity
Check
Reset
0
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6
5
4
3
Mouse Wake-Up Configuration
0
0
0
54
2
1
0
Keyboard Wake-Up Configuration
0
0
0
0
(Continued)
Bit
7
6-4
3-0
Description
Disable Parity Check
Mouse Wake-Up Configuration
Bits
6 5 4
Configuration
0
0
0
0
1
1
1
1
Disable Mouse wake-up detection
Wake-up on any Mouse movement or button click
Wake-up on left button click
Wake-up on left button double-click
Wake-up on right button click
Wake-up on right button double-click
Wake-up on any button single-click (left, right or middle)
Wake-up on any button double-click (left, right or middle)
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Keyboard Wake-Up Configuration
Bits
3 2 1 0
Configuration
0 0 0 0
Disable Keyboard wake-up detection
0 0 0 1
to
0 1 1 1
1 0 0 0
to
1 1 1 1
3.4.6
SWC REGISTERS
3.0 System Wake-Up Control (SWC)
}
}
Special key sequence 2-8 PS/2 scan codes (including scan codes for Shift and Alt keys)
Password enabled with 1-8 keys (excluding scan codes for Shift and Alt keys)
Keyboard Data Shift Register (KDSR)
This register is set to 00h on power-up of VPP or software reset. It stores the Keyboard data shifted in from the Keyboard
during transmission, only when Keyboard wake-up detection is enabled.
Location:
Offset 06h
Type:
RO
Bit
7
6
5
Name
3
2
1
0
0
0
0
Keyboard Data
Reset
3.4.7
4
0
0
0
0
0
Mouse Data Shift Register (MDSR)
This register is set to 00h on power-up of VPP or software reset. It stores the Mouse data shifted in from the Mouse during
transmission, only when Mouse wake-up detection is enabled.
Location:
Offset 07h
Type:
RO
Bit
7
6
Name
Reset
5
4
3
2
Reserved
0
0
0
1
0
Mouse Data
0
55
0
0
0
0
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SWC REGISTER BITMAP
3.0 System Wake-Up Control (SWC)
3.4.8
(Continued)
PS/2 Keyboard Key Data Registers (PS2KEY0 - PS2KEY7)
The following eight registers (PS2KEY0-PS2KEY7) store the scan codes for the password or key sequence of the Keyboard
wake-up feature.
The first register (PS2KEY0) stores the scan code for the first key in the password/key sequence.
The second register (PS2KEY1) stores the scan code for the second key in the password/key sequence.
The third to eighth registers (PS2KEY2 - PS2KEY7) store the scan code for the third to eighth keys in the password/key
sequence.
These registers are set to 00h on power-up of VPP or software reset.
Location:
Offset 08h-0Fh
Type:
R/W
Bit
7
6
5
4
Name
2
1
0
0
0
0
Scan Code of Keys 0-7
Reset
3.5
3
0
0
0
0
0
SWC REGISTER BITMAP
Register
Bits
Offset
Mnemonic
7
6
5
4
3
2
1
0
00h
WKCR
PME2
Event
Enable
PME1
Event
Enable
Reserved
Mouse
Event
Enable
KBD
Event
Enable
RING
Event
Enable
RI2
Event
Enable
RI1
Event
Enable
PME2
Event
Status
PME1
Evemt
Status
Reserved
Mouse
Event
Status
KBD
Event
Status
RING
Event
Status
RI2
Event
Status
RI1
Event
Status
PME2
Type
PME2
Polarity
PME1
Type
PME1
Polarity
Swap KBC
Inputs
01h
WKSR
02h
WKCFG
Reserved
03h
PS2CTL
Disable
Parity
Check
06h
KDSR
07h
MDSR
08-0F
PS2KEY0PS2KEY7
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Mouse Wake-Up Configuration
Reserved
Keyboard Wake-Up Configuration
Keyboard Data
Reserved
Mouse Data
Scan Code of Keys 0-7
56
This chapter describes one 8-bit port. A device may include a combination of several ports with different implementations.
For the device specific implementation, see the Device Architecture and Configuration chapter. If there are fewer than 8 bits
per port in a configuration, only the corresponding lower bits are implemented and the remaining bits are reserved. For instance, if there are 3 bits per port, only bits 0-2 are implemented, and the remaining 5 bits are reserved.
4.1
OVERVIEW
The GPIO port is an 8-bit port which is based on eight pins. It features:
•
•
•
•
Software capability to manipulate and read pin levels
Controllable interrupt assertion based on the pin level or level transition
Ability to capture and manipulate interrupts and their associated status
Back-drive protected pins.
GPIO port operation is associated with two sets of registers:
•
Configuration registers, mapped in the Device Configuration space. These registers are used to statically set up the
logical behavior of each pin. There is one 8-bit register for each GPIO pin.
•
Four 8-bit runtime registers: GPIO Data Out (GPDO), GPIO Data In (GPDI), GPIO Interrupt Enable (GPIEN) and
GPIO Status (GPST). These registers are mapped in the GPIO device IO space (which is determined by the base
address registers in the GPIO Device Configuration). They are used to manipulate and/or read the pin values, and to
control and handle interrupt generation. Each runtime register corresponds to the 8-pin port, such that bit n in each
one of the four registers is associated with GPIOXn pin, where X is the port number.
Each GPIO pin is associated with eight configuration bits and the corresponding bit slice of the four runtime registers, as
shown in Figure 4-1.
The functionality of the GPIO port is divided into basic functionality that includes the manipulation and reading of the GPIO
pins. This functionality is described in Section 4.2. The enhanced functionality which includes the interrupt assertion and
handling is described in Section 4.3.
Bit n
GPDOX
GPIOX Base Address
GPDIX
GPIENX
Runtime
Registers
GPSTX
8 GPIO Configuration
Registers
GPIOXn
Pin
GPIOXn
Port Logic
Pin Configuration
Access Register
GPIOXn CNFG
x8
x8
Pin Select
Pin Configuration
Select Register
Interrupt Pending
Interrupt Request
x8
X = port number;
n = 0 to 7
Figure 4-1. GPIO Port Architecture
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4.0 General-Purpose Input/Output (GPIO) Port
4.0 General-Purpose Input/Output (GPIO) Port
BASIC FUNCTIONALITY
4.0 General-Purpose Input/Output (GPIO) Port
4.2
(Continued)
BASIC FUNCTIONALITY
The basic functionality of each GPIO pin is based on four configuration bits and a bit slice of runtime registers GPDO and
GPDI. The configuration and operation of a single pin GPIOXn (pin n in port X) is shown in Figure 4-2.
GPIO Device
Enable
Read Only
Data In
Static
Pull-Up
Push-Pull=1
Pin
Read/Write
Data Out
Internal
Bus
Pull-Up
Enable
Lock
Bit 3
Pull-Up
Control
Output
Type
Bit 2
Bit 1
GPIO Configuration Register
Output
Enable
Bit 0
Figure 4-2. GPIO Basic Functionality
4.2.1
Configuration Options
The GPIO Configuration Register controls the following basic configuration options:
•
•
Port Direction - Controlled by the Output Enable bit (bit 0)
•
Weak Static Pull-up - May be added to any type of port (input, open-drain or totem pole). It is controlled by Pull-Up Control
(bit 2).
•
Pin Lock - GPIO pin may be locked to prevent any changes in the output value and/or the output characteristics. The
lock is controlled by Lock (bit 3). It disables writes to the GPDO Register bits, and to bits 0-3 of the GPIO Configuration
Register (Including the Lock bit itself). Once locked, it can be released by hardware reset only.
Output Type - Totem pole vs. open-drain. It is controlled by Output Buffer Type (bit 1) by enabling/disabling the pull-up
portion of the output buffer.
4.2.2
Operation
The value that is written to the GPDO Register is driven to the pin, if the output is enabled. Reading from the GPDO Register
returns its contents, regardless of the pin value or the port configuration. The GPDI Register is a read-only register. Reading
from the GPDI Register returns the pin value, regardless of what is driving it (the port itself, configured as an output port, or
the external device when the port is configured as an input port). Writing to this register is ignored.
Activation of the GPIO port is controlled by external device specific configuration bit (or a combination of bits). When the port
is inactive, access to GPDI and GPDO Registers is disabled, and the inputs are blocked. However, there is no change in
the port configuration and in the GPDO value, and hence there is no effect on the outputs of the pins.
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58
4.3
(Continued)
INTERRUPT ASSERTION AND HANDLING
The enhanced GPIO port supports interrupt assertion and handling. This functionality is based on three configuration bits
and a bit slice of runtime registers GPIEN and GPST. The configuration and operation of the interrupt capability is shown in
Figure 4-3.
1
Interrupt
Request
0
Interrupt
Enable
0
Input
Debouncer
Rising
Edge
Detector
1
Status
R/W
R/W 1 to Clear
Interrupt
Requests
from other
GPIO Pins
Pin
Rising Edge or
High Level =1
Level =1
IRQ
Debounce
Enable
IRQ Polarity
IRQ Type
Bit 6
Bit 5
Bit 4
Internal
Bus
GPIO Configuration Register
Figure 4-3. Interrupt Assertion
4.3.1
Interrupt Configuration
Each pin in the GPIO port is a potential interrupt source. The interrupt generator can trigger an interrupt upon predetermined behavior of the source pin. The GPIO Configuration Register determines the interrupt generation trigger type for the interrupt assertion.
IRQ Polarity
Two trigger types of interrupt assertion are supported: edge and level. An edge interrupt may be asserted upon a source pin
transition either from high to low or low to high. A level interrupt may be asserted when the source pin is in active level. The
trigger type is determined by IRQ Type (bit 4 of the GPIO Configuration Register). The direction of the transition (for edge)
or the polarity of the active level (for level) is determined by IRQ Polarity (bit 5 of the GPIO Configuration Register).
IRQ Debounce Enable
The input signal for the interrupt can be debounced for about 15 msec. The signal state should be transferred only after a
debouncing period during which the signal has no transitions, to ensure that the signal is stable. The debouncer adds 15
msec delay to both assertion and de-assertion level interrupts, and to the assertion of edge interrupts. When working with a
level interrupt, it is recommended to disable the debounce if the delay in the interrupt de-assertion is not acceptable.
The debounce is controlled by IRQ Debounce Enable (bit 6 of the GPIO Configuration Register).
4.3.2
Interrupt Assertion
The interrupt assertion for each GPIO pin is controlled by the corresponding bit in the GPIEN Register. Interrupt assertion
by a GPIO pin is enabled if the corresponding bit of this register is set to 1.
The GPST Register is a general-purpose edge detector which may be used to reflect the interrupt source pending status for
edge-triggered interrupts.
The term active edge refers to a change in a GPIO pin level that matches the IRQ Polarity bit (1 for rising edge and 0 for
falling edge). Active level refers to the GPIO pin level that matches the IRQ Polarity bit (1 for high level and 0 for low level).
The corresponding bit of the GPST Register is set by hardware whenever an active edge is detected, regardless of any other
bit settings. Writing 1 to the Status bit clears it to 0. Writing 0 is ignored.
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INTERRUPT ASSERTION AND HANDLING
4.0 General-Purpose Input/Output (GPIO) Port
GPIO PORT REGISTERS
4.0 General-Purpose Input/Output (GPIO) Port
(Continued)
A GPIO pin is in interrupt pending state if the corresponding bit of the GPIEN Register is set and either:
•
•
The IRQ Type is level and the pin is in active level, or
The IRQ Type is edge and the corresponding bit of the GPST Register is set.
The target IRQ line is asserted if at least one GPIO pin is in interrupt pending state. The selection of the target IRQ line is
determined by the IRQ selection procedure of the device configuration. The assertion of the IRQ line is blocked when the
GPIO functional block is deactivated.
If the output is enabled, the IRQ may be initiated by the software when writing to the GPDO Register.
An edge interrupt may be de-asserted by clearing the corresponding GPST bit. However, a level Interrupt source may not
be released by software (except for disabling the source), as long as the pin is in active level. When level interrupt is used,
it is recommended to disable the input debouncer.
Upon de-activation of the GPIO port, the GPST Register is cleared and access to both the GPST and GPIEN Registers is
disabled. The target IRQ line is detached from the GPIO and de-asserted.
Before enabling the interrupts, it is recommended to set the desired interrupt configuration, and then verify that the status
registers are cleared.
4.4
GPIO PORT REGISTERS
The register maps in this chapter use the following abbreviations for Type:
• R/W = Read/Write
• R = Read from a specific address returns the value of a specific register. Write to the same address is to a different
register.
• W = Write
• RO = Read Only
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
4.4.1
GPIO Pin Configuration Access Register
This is a group of eight identical configuration registers, each of which is associated with one GPIO pin. The entire set is
mapped to the PnP configuration space. The mapping scheme is based on the GPIO Pin Configuration Select Register that
functions as an index register, and the specific GPIO Pin Configuration Access Register that reflects the configuration of the
currently selected pin. For details on the GPIO Pin Configuration Select Register, refer to the Device Architecture and Configuration chapter.
Bits 4-6 are applicable only for the enhanced GPIO port with interrupt support. In the basic port. these bits are reserved,
return 0 on read and have no effect on port functionality.
Location:
Device specific
Type:
R/W (bit 3 is set only)
Bit
7
Name
Reserved
Reset
0
6
5
4
IRQ
Debounce IRQ Polarity IRQ Type
Enable
Bit
1
0
0
3
2
1
0
Lock
Pull-Up
Control
Output
Type
Output
Enable
0
1
0
0
Description
7
Reserved
6
IRQ Debounce Enable
0: Disabled
1: Enabled (default)
5
IRQ Polarity. This bit defines the polarity of the signal that issues an interrupt from the corresponding GPIO pin
(falling/low or rising/high).
0: Falling edge or low level input (default)
1: Rising edge or high level input
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60
Bit
(Continued)
Description
4
IRQ Type. This bit defines the signal type that issues an interrupt from the corresponding GPIO pin.
0: Edge input (default)
1: Level input
3
Lock. This bit locks the corresponding GPIO pin. Once this bit is set to 1 by software, it can only be cleared to
0 by system reset or power-off. Pin multiplexing is functional until the Multiplexing Lock bit is 1 (bit 7 of SuperI/O
Configuration 3 Register (SIOCF3).
0: No effect (default)
1: Direction, output type, pull-up and output value locked
2
Pull-Up Control. This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin.
It supports open-drain output signals with internal pull-ups and TTL input signals
0: Disabled
1: Enabled (default)
1
Output Type. This bit controls the output buffer type (open-drain or push-pull) of the corresponding GPIO pin.
0: Open-drain (default)
1: Push-pull
0
Output Enable. This bit indicates the GPIO pin output state. It has no effect on input.
0: TRI-STATE (default)
1: Output enabled
4.4.2
GPIO Port Runtime Register Map
Offset
Mnemonic
Name
Type
Section
Device specific1 GPDO
GPIO Data Out Register
R/W
4.4.3
Device specific1 GPDI
GPIO Data In Register
RO
4.4.4
Device specific1 GPIEN
GPIO Interrupt Enable Register
R/W
4.4.5
Device specific1 GPST
GPIO Status Register
R/W1C
4.4.6
1. The location of this register is defined in the Device Architecture and Configuration
chapter in Section 2.12.1.
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GPIO PORT REGISTERS
4.0 General-Purpose Input/Output (GPIO) Port
GPIO PORT REGISTERS
4.0 General-Purpose Input/Output (GPIO) Port
4.4.3
(Continued)
GPIO Data Out Register (GPDO)
Location:
Device specific
Type:
R/W
Bit
7
6
5
4
Name
3
2
1
0
1
1
1
1
Data Out
Reset
1
1
1
Bit
1
Description
7
6
5
4
3
2
Data Out. Bits 7-0 correspond to pins 7-0 respectively. The value of each bit determines the value driven on the
corresponding GPIO pin when its output buffer is enabled. Writing to the bit latches the written data unless the
bit is locked by the GPIO Configuration Register Lock bit. Reading the bit returns its value, regardless of the pin
value and configuration.
0: Corresponding pin driven to low when output enabled
1: Corresponding pin driven or released to high (according to buffer type and static pull-up selection) when
output enabled
1
0
4.4.4
GPIO Data In Register (GPDI)
Location:
Device specific
Type:
RO
Bit
7
6
5
4
Name
3
2
1
0
X
X
X
X
Data In
Reset
X
Bit
X
X
X
Description
7
6
5
4
3
2
Data In. Bits 7-0 correspond to pins 7-0 respectively. Reading each bit returns the value of the corresponding
GPIO pin, regardless of the pin configuration and the GPDO Register value. Write is ignored.
0: Corresponding pin level low
1: Corresponding pin level high
1
0
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62
4.4.5
(Continued)
GPIO Interrupt Enable Register (GPIEN)
Location:
Device specific
Type:
R/W
Bit
7
6
5
Name
4
3
2
1
0
0
0
0
Interrupt Enable
Reset
0
0
0
Bit
0
0
Description
7
6
5
4
3
2
Interrupt Enable. Bits 7-0 correspond to pins 7-0 respectively. Each bit enables Interrupt generation by the
corresponding GPIO pin. The bit has no effect on the corresponding Status bit in the GPST Register.
0: IRQ generation by corresponding GPIO pin masked
1: IRQ generation by corresponding GPIO pin enabled
1
0
4.4.6
GPIO Status Register (GPST)
Location:
Device specific
Type:
R/W1C
Bit
7
6
5
4
Name
Reset
Bit
3
2
1
0
0
0
0
0
Status
0
0
0
0
Description
7
6
5
4
3
2
Status. Bits 7-0 correspond to pins 7-0 respectively. Each bit is an edge detector that is set to 1 by the hardware
upon detection of an active edge (i.e. edge that matches the IRQ Polarity bit) on the corresponding GPIO pin.
This edge detection is independent of the IRQ Type or the Interrupt Enable bit in the GPIEN Register. However,
the bit may reflect the IRQ status for enabled, edge-trigger IRQ sources. Writing 1 to the Status bit clears it to 0.
0: No active edge detected since last cleared
1: Active edge detected
1
0
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GPIO PORT REGISTERS
4.0 General-Purpose Input/Output (GPIO) Port
5.0 Fan Speed Control
5.0 Fan Speed Control
5.1
OVERVIEW
This chapter describes one Fan Speed Control module. A device may include some modules with different implementations.
For the device specific implementation, see the Device Architecture and Configuration chapter.
The Fan Speed Control is a programmable Pulse Width Modulation (PWM) generator. The PWM output is used to control
the fan’s power voltage, which is correlated to the fan’s speed. Converting a 0 to 100% duty cycle PWM signal to an analog
voltage range is achieved by an external circuit, as shown in Figure 5-1. Some new types of fans accept direct PWM input
without any external circuitry.
Fan
FANOUT
Fan Speed
Control
External
External
Circuitry
Circuitry
Control
Figure 5-1. Fan Speed Control - System Configuration
5.2
FUNCTIONAL DESCRIPTION
The PWM generator operation is based on a PWM counter and two registers: the Fan Speed Control Pre-Scale Register
(FCPSR), used to determine the overall cycle time (or the frequency) of the FANOUT output, and the Fan Speed Control
Duty Cycle Register (FCDCR), used to determine the duty cycle of the FANOUT between 0 to 100%.
The PWM counter is an 8-bit, free-running counter that runs continuously in a cyclic manner, i.e its cycle equals 256 clock
periods. The PWM output is high as long as the count is lower than the FCDCR value, and flips to low as the counter exceeds
that value. The duty cycle (expressed as a percentage) is therefore (FCDCR/256)*100. In particular, the PWM output is continuously low when FCDCR=0 and continuously high when FCDCR=FFh. The FANOUT output may be inverted by an external configuration bit, in which case the FANOUT duty cycle is ([256-FCDCR]/256)*100.
The PWM counter clock is generated by dividing the input clock, either 24 MHz or 200 KHz (according to Clock Select, bit
7 of the FCPSR Register) using a clock divider. The division factor, which must be between 1 and 124, is defined as PreScale Value+1, where Pre-Scale is the binary value stored in bits 6 to 0 of the FCPSR Register. The resulting PWM output
frequency is therefore (24 MHz or 200 kHz/([Pre-Scale Value+1]*256). The default selection of 24 MHz input clock allows a
programmable FANOUT frequency in the range of 756 Hz to 93.75 KHz. For lower frequencies, selecting the 200 KHz input
clock allows a frequency range of 6 Hz to 781 Hz. See Figure 5-2.
The FANOUT frequency must be pre-selected according to the fan type specific requirements prior to enabling the Fan
Speed Control. The only run-time change that is required to dynamically control the fan speed is the value of the FCDCR
Register. The contents of the FCPSR Register must not be changed when the Fan Speed Control is enabled.
24 MHz
0
200 KHz 1
Clock
Divider
(1-124)
PWM
Counter
Invert
FANOUT
PWM Output -
Comparator
Bit 7
FCDCR > Counter
Bits 6-0
O
FCPSR Register
FCDCR Register
Figure 5-2. PWM Generator (FANOUT)
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0
64
1
FANOUT
5.3
(Continued)
FAN SPEED CONTROL REGISTERS
The register maps in this chapter use the following abbreviations for Type:
• R/W = Read/Write
• R = Read from a specific address returns the value of a specific register. Write to the same address is to a different
register.
• W = Write
• RO = Read Only
• R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
5.3.1
Fan Speed Control Register Map
Offset
Mnemonic
Device specific1
FCPSR
Device specific1
FCDCR
Name
Type
Section
Fan Speed Control Pre-Scale Register
R/W
5.3.2
Fan Speed Control Duty Cycle Register
R/W
5.3.3
1. The location of this register is defined in the Device Architecture and Configuration chapter in
Section 2.13.1.
5.3.2
Fan Control Pre-Scale Register (FCPSR)
Location:
Device specific
Type:
R/W
Bit
7
Name
Clock
Select
Reset
0
6
5
6-0
5.3.3
1
0
0
0
0
0
0
0
0
Clock Select. This bit selects the input clock for the clock divider.
0: 24 MHz
1: 200 KHz
Pre-Scale Value. The clock divider for the input clock (24 MHz or 200 KHz) is Pre-Scale Value + 1. Writing 0
transfers the input clock directly to the counter. The maximum clock divider is 124 (7Bh +1). These bits must not
be programmed with the values 7Ch, 7Dh, 7Eh and 7Fh as this may produce unpredictable results.
The contents of this register should not be changed when the corresponding Fan Speed Control Enable bit of
the Fan Speed Control Configuration Register is 1 (See Device Architecture and Configuration chapter).
Otherwise, there may be unpredictable results.
Fan Control Duty Cycle Register (FCDCR)
Device specific
Type:
R/W
7
6
5
Name
Reset
2
Description
Location:
Bit
3
Pre-Scale Value
Bit
7
4
4
3
2
1
0
1
1
1
Duty Cycle Value
1
1
1
1
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FAN SPEED CONTROL REGISTERS
5.0 Fan Speed Control
FAN SPEED CONTROL BITMAP
5.0 Fan Speed Control
(Continued)
Bit
Description
7-0
Duty Cycle. The binary value of this 8-bit field determines the number of clock cycles, out of a 256-cycle period,
during which the PWM output is high (while FANOUT is either equal to or the inverse of the PWM output,
depending on the Inverse FANOUT configuration bit).
00h: PWM output is continuously low
01h - FEh: PWM output is high for [Duty Cycle Value] clock cycles and low for [256-Duty Cycle Value] clock
cycles
FFh: PWM output is continuously high
5.4
FAN SPEED CONTROL BITMAP
Register
Bits
Offset
Mnemonic
7
Device
specific1
FCPSR
Clock
Select
Device
specific1
FCDCR
6
5
4
3
2
Pre-Scale Value
Duty Cycle Value
1. The location of this register is defined in the Device Architecture and Configuration chapter.
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66
1
0
6.0 Floppy Disk Controller (FDC)
6.0 Floppy Disk Controller (FDC)
Refer to PC87307, PC87309 or PC87317 datasheet.
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7.0 Parallel Port
7.0 Parallel Port
Refer to PC87307, PC87309 or PC87317 datasheet.
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8.0 Serial Port 2 with IR
8.0 Serial Port 2 with IR
Refer to PC87307, PC87309 or PC87317 datasheet.
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9.0 Serial Port 1
9.0 Serial Port 1
Refer to PC87307, PC87309 or PC87317 datasheet.
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10.0 Keyboard and Mouse Controller (KBC)
10.0 Keyboard and Mouse Controller (KBC)
Refer to PC87307, PC87309 or PC87317 datasheet.
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11.0 Device Characteristics
11.0 Device Characteristics
11.1 DC ELECTRICAL CHARACTERISTICS
Sections 11.1.6 to 11.1.10 summarize the DC characteristics of all device pins described in the Signal/Pin Connection and
Description chapter. The characteristics describe the general I/O buffer type. For the exception, refer to the notes at the end
of this section.
11.1.1 Recommended Operating Conditions
Symbol Parameter
Min
Typ
Max
Unit
VDD
Supply Voltage
4.5
5.0
5.5
V
VSB
Standby Supply Voltage
4.5
5.0
5.5
V
VBAT
Battery Supply Voltage
2.4
3.0
3.6
V
TA
Operating Temperature
0
+70
°C
11.1.2 Absolute Maximum Ratings
Absolute maximum ratings are values beyond which damage to the device may occur. Unless otherwise specified, all voltages are relative to ground.
Symbol Parameter
Min
Max
Unit
Supply Voltage
−0.5
TBD
V
VI
Input Voltage
−0.5
VDD + 0.5
V
VO
Output Voltage
−0.5
VDD + 0.5
V
Storage Temperature
−65
+165
°C
1
W
+260
°C
VDD
TSTG
Conditions
PD
Power Dissipation
TL
Lead Temperature Soldering (10 sec)
CZAP = 100 pF
ESD Tolerance
2000
RZAP = 1.5 KΩ1
V
1. Value based on test complying with RAI-5-048-RA human body model ESD testing.
11.1.3 Capacitance
Symbol Parameter
Min
Max
Unit
5
7
pF
8
12
pF
CIN
Input Pin Capacitance
CIN1
Clock Input Capacitance
CIO
I/O Pin Capacitance
10
12
pF
CO
Output Pin Capacitance
6
8
pF
5
TA = 25°C, f = 1 MHz
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Typ
72
DC ELECTRICAL CHARACTERISTICS
11.0 Device Characteristics
(Continued)
11.1.4 Power Consumption under Recommended Operating Conditions
Symbol
Parameter
VDD Average Main Supply Current
ICC
ICCLP
VDD Quiescent Main Supply Current
in Low Power Mode
Conditions
Typ
Max
Unit
VIL = 0.5 V, VIH = 2.4 V
No Load
32
50
mA
VIL = VSS, VIH = VDD
No Load
1.3
1.7
mA
VSB Average Main Supply Current
VIL = 0.5 V, VIH = 2.4 V
No Load
15
mA
ISBLP
VSB Quiescent Main Supply Current
in Low Power Mode
VIL = VSS, VIH = VSB V
No Load
3
mA
IBAT
VBAT Battery Supply Current
VDD, VSB = 0 V,
VBAT = 3 V
250
nA
ISB
11.1.5 Input, PCI 5V
Symbol: INPCI
Symbol Parameter
Conditions
Min
Max
Unit
VIH
Input High Voltage
2.0
VDD + 0.5
V
VIL
Input Low Voltage
-0.5
0.8
V
lIL1
Input Leakage Current
-/+10
µA
0 < Vin < VDD
1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with TRI-STATE outputs.
11.1.6 Strap Pin
Symbol: INSTRP
Symbol Parameter
VIH
Input High Voltage
IIL
Input Leakage Current
Conditions
Min
Max
Unit
0.6VDD 1
VDD 1
V
During Reset: VIN = VDD
250
µA
VIN = VSS
−10
µA
1. Not tested. Guaranteed by design.
11.1.7 Input, TTL Compatible
Symbol: INT
Symbol Parameter
Conditions
Min
Max
Unit
VIH
Input High Voltage
2.0
VDD1
V
VIL
Input Low Voltage
−0.51
0.8
V
µA
Input Leakage Current
VIN = VDD
10
IIL
VIN = VSS
−10
µA
1. Not tested. Guaranteed by design.
73
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DC ELECTRICAL CHARACTERISTICS
11.0 Device Characteristics
(Continued)
11.1.8 Input with TTL Schmitt Trigger
Symbol: INTS
Symbol Parameter
Conditions
Min
Max
Unit
VIH
Input High Voltage
2.0
VDD1
V
VIL
Input Low Voltage
−0.5 1
0.8
V
µA
Input Leakage Current
VIN = VDD
10
IIL
VIN = VSS
−10
µA
VH
Input Hysteresis
250
mV
1. Not tested. Guaranteed by design.
11.1.9 Output, Totem-Pole Buffer
Symbol: Op/n
Output, Totem-Pole buffer that is capable of sourcing p mA and sinking n mA
Symbol Parameter
Conditions
Min
2.4
VOH
Output High Voltage
IOH = −p mA
VOL
Output Low Voltage
IOL = n mA
Max
Unit
V
0.4
V
11.1.10 Output, Open-Drain Buffer
Symbol: ODn
Output, Open-Drain output buffer that is capable of sinking n mA. Output from these signals is open-drain and cannot be
forced high.
Symbol Parameter
VOL
Conditions
IOL = n mA
Output Low Voltage
Min
Max
Unit
0.4
V
Notes:
1. All pins are back-drive protected.
2. The following pins have a static pull-up resistor and therefore may have input leakage current (when VIN = VSS) of about
-250µA: TBD
3. The following pins have a static pull-down resistor and therefore may have input leakage current (when VIN = VDD) of
about 200µA: TBD
4. Output from SLCT, BUSY/WAIT (and PE if bit 2 of PP Confg0 Register is “0”) is open-drain in all SPP modes, except in
SPP Compatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is 1.
Otherwise, output from these signals is level 2. External 4.7 KW pull-up resistors should be used.
5. Output from ACK, ERR (and PE if bit 2 of PP Confg0 Register is “1”) is open-drain in all SPP modes, except in SPP
Compatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel port register is 1. Otherwise, output from these signals is level 2. External 4.7 KW pull-up resistors should be used.
6. IOH on pins P12 and P17 are driven for 10 nsec after the low-to-high transition.
7. Output from STB, AFD, INIT, SLIN is open-drain in all SPP modes, except in SPP Compatible mode when the setup
mode is ECP-based (FIFO). Otherwise, output from these signals is Level 2. External 4.7 KΩ pull-up resistors should be
used.
8. Output from PD7-0 is open-drain in all SPP modes, except in SPP Compatible mode when the setup mode is ECP-based
(FIFO) and bit 4 of the Control2 parallel port register is 1. Otherwise, output from these signals is Level 2. External 4.7
KΩ pull-up resistors should be used.
9. IOH is valid for a GPIO signals only when it is not configured as open-drain.
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74
(Continued)
11.2 AC ELECTRICAL CHARACTERISTICS
11.2.1 AC Test Conditions
Load Circuit (Notes 1, 2, 3)
AC Testing Input, Output Waveform
VDD
S1
2.4
0.1 µf
2.0
0.8
0.4
Test Points
2.0
0.8
RL
Device
Under
Test
Input
Output
CL
Figure 11-1. AC Test Conditions, TA = 0 °C to 70 °C, VDD = 5.0 V ±10%
Notes:
1. CL = 100 pF, includes jig and scope capacitance.
2. S1 = Open for push-pull output pins.
S1 = VDD for high impedance to active low and active low to high impedance measurements.
S1 = GND for high impedance to active high and active high to high impedance measurements.
RL = 1.0KΩ for µP interface pins.
For the FDC open-drive interface pins, S1 = VDD and RL = 150Ω
11.2.2 Clock Timing
48MHz
Symbol
Parameter
Min
Max
Unit
tCH
Clock High Pulse Width1
8.4
nsec
tCL
Clock Low Pulse Width1
8.4
nsec
tCP
Clock Period 1
20
21.5
nsec
1. Not tested. Guaranteed by design.
.
tCP
tCH
CLKIN
tCL
75
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AC ELECTRICAL CHARACTERISTICS
11.0 Device Characteristics
AC ELECTRICAL CHARACTERISTICS
11.0 Device Characteristics
(Continued)
11.2.3 Host Interface I/O Cycle Timing
Symbol
Parameter
Min
tAR
Valid Address to Read Active
18
nsec
tAW
Valid Address to Write Active
18
nsec
tDH
Data Hold
0
nsec
tDS
Data Setup
18
nsec
tHZ
Read to Floating Data Bus1
13
tRA
Address Hold from Inactive Read
0
nsec
tRCU
Read Cycle Update1
45
nsec
tRD
Read Strobe Width
60
nsec
tRDH
Read Data Hold
10
nsec
tRI
Read Strobe to Clear IRQ
55
nsec
tRVD
Active Read to Valid Data
55
nsec
tWA
Address Hold from Inactive Write
0
nsec
tWCU
Write Cycle Update1
45
nsec
tWI
Write Strobe to Clear IRQ
tWR
Write Strobe Width
60
nsec
RC
Read Cycle = tAR + tRD + tRCU1
123
nsec
WC
Write Cycle = tAW + tWR + tWC1
123
nsec
tWRR
RD low after WR high1
80
nsec
tRDYA
RD/WR active to IOCHRDY active2
0
tRDYI
WAIT inactive to IOCHRDY inactive2
tRWI
IOCHRDY inactive to RD/WR inactive2
25
55
1. Not tested. Guaranteed by design.
2. Applicable for EPP mode only.
www.national.com
Max
76
10
Unit
nsec
nsec
24
nsec
40
nsec
nsec
(Continued)
Read
AEN
Valid
A15-0
Valid
RC
tAR
tRD
tRCU
RD
tRA
OR
tRVD
WR
Valid Data
D7-0
tRDH
tHZ
IRQ
tRI
Write
AEN
Valid
A15-0
tAW
Valid
WC
tWR
tWCU
WR
tWA
tWRR
RD
Valid Data
D7-0
tDS
tDH
tWI
IRQ
IOCHRDY
RD/WR
WAIT
tRWI
IOCHRDY
tRDYA
tRDYI
77
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AC ELECTRICAL CHARACTERISTICS
11.0 Device Characteristics
AC ELECTRICAL CHARACTERISTICS
11.0 Device Characteristics
(Continued)
11.2.4 Host Interface DMA Cycle Timing
Symbol
Parameter
tACH
Min
Max
AEN Hold from RD, WR Inactive
0
nsec
tACS
AEN Signal Setup
15
nsec
tDCH
DACK Hold from RD, WR Inactive
0
nsec
tDCS
DACK Signal Setup
15
nsec
tDSW
RD, WR Pulse Width
60
tRQS
DRQ Inactive from RD, WR Active
tTCH
TC Hold from RD, WR Inactive
0
nsec
tTCS
TC Signal Setup
40
nsec
nsec
60
DRQ
AEN
tACH
tDCH
tDCS
DACK
tDSW
RD, WR
tACS
tRQ
tTCS
TC
www.national.com
Unit
78
tTCH
nsec
AC ELECTRICAL CHARACTERISTICS
11.0 Device Characteristics
(Continued)
11.2.5 PCICLK Timing Specifications
Symbol
Parameter
Min
Max
Units
∞
ns
tCYC1
PCICLK Cycle Time
30
tHIGH
PCICLK High Time
11
ns
tLOW
PCCLK Low Time
11
ns
PCICLK Slew Rate2
1
-
4
V/ns
1. The PCI may have any clock frequency between nominal DC and 33 MHz.
Device operational parameters at frequencies under 16 MHz may be guaranteed by design rather than by testing. The clock frequency may be
changed at any time during the operation of the system as long as the clock
edges remain “clean” (monotonic) and the minimum cycle and high and low
times are not violated. The clock may only be stopped in a low state.
2. Rise and fall times are specified in terms of the edge rate measured in V/ns.
This slew rate must be met across the minimum peak-to-peak portion of
the clock wavering as shown below.
tLOW
tHIGH
2.4 V
2.0 V
2.0 V, p-to-p
(minimum)
1.5 V
0.8 V
0.4 V
tCYC
79
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AC ELECTRICAL CHARACTERISTICS
11.0 Device Characteristics
(Continued)
11.2.6 Serial IRQ Timing
Symbol
Description
Reference Conditions
tVAL
Output Valid Delay
After RE PCICLK
tON
Float to Active Delay
After RE PCICLK
tOFF
Active to Float Delay
After RE PCICLK
tSU
Input Setup Time
Before RE PCICLK
7
tHI
Input Hold Time
After RE PCICLK
0
Output
PCICLK
tVAL
tON
SERIRQ
tOFF
Input
PCICLK
tSU
SERIRQ
www.national.com
Min
(ns)
Input
Valid
80
tHI
Max
(ns)
11
2
28
(Continued)
11.2.7 Serial Port, Sharp-IR, SIR and Consumer Remote Control Timing
Symbol Parameter
tBT
Single Bit Time in Serial Port and Sharp-IR
tCMW
Modulation Signal Pulse Width in Sharp-IR
and Consumer Remote Control
tCMP
Modulation Signal Period in Sharp-IR and
Consumer Remote Control
tSPW
SIR Signal Pulse Width
Conditions
Min
Max
Unit
Transmitter
tBTN − 25
1
tBTN + 25
nsec
Receiver
tBTN − 2%
tBTN + 2%
nsec
Transmitter
tCWN − 252
tCWN + 25
nsec
Receiver
500
Transmitter
tCPN − 253
tCPN + 25
nsec
Receiver
tMMIN4
tMMAX4
nsec
Transmitter,
Variable
(3/16) x tBTN − 151
(3/16) x tBTN + 151
nsec
Transmitter,
Fixed
1.48
1.78
µsec
Receiver
1.00
nsec
µsec
SDRT
SIR Data Rate Tolerance.
% of Nominal Data Rate.
Transmitter
± 0.87%
Receiver
± 2.0%
tSJT
SIR Leading Edge Jitter
% of Nominal Bit Duration.
Transmitter
± 2.5%
Receiver
± 6.5%
1. tBTN is the nominal bit time in Serial Port, Sharp-IR, SIR and Consumer Remote Control modes. It is determined by the setting of the Baud Generator Divisor registers
2. tCWN is the nominal pulse width of the modulation signal for Sharp-IR and Consumer Remote Control modes. It
is determined by the MCPW field (bits 7-5) of the IRTXMC register and the TXHSC bit (bit 2) of the RCCFG
register.
3. tCPN is the nominal period of the modulation signal for Sharp-IR and Consumer Remote Control modes. It is determined by the MCFR field (bits 4-0) of the IRTXMC register and the TXHSC bit (bit 2) of the RCCFG register.
4. tMMIN and tMMAX define the time range within which the period of the incoming subcarrier signal has to fall in
order for the signal to be accepted by the receiver. These time values are determined by the contents of register IRRXDC and the setting of the RXHSC bit (bit 5) of the RCCFG register
tBT
Serial Port
tCMP
tCMW
Sharp-IR
Consumer Remote Control
tSPW
SIR
81
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AC ELECTRICAL CHARACTERISTICS
11.0 Device Characteristics
AC ELECTRICAL CHARACTERISTICS
11.0 Device Characteristics
(Continued)
11.2.8 Modem Control Timing
Symbol
Parameter
tHL
RI2,1 High to Low Transition
10
nsec
tLH
RI2,1 Low to High Transition
10
nsec
tSIM
Delay to Set IRQ from Modem Input
CTS, DSR, DCD
Min
tSIM
Max
40
Unit
nsec
tSIM
INTERRUPT
tSIM
(Read MSR)
(Read MSR)
RI
tHL
tLH
11.2.9 FDC Write Data Timing
Symbol
Parameter
Min
Max
tHDH
HDSEL Hold from WGATE Inactive1
750
µsec
tHDS
HDSEL Setup to WGATE Active1
100
µsec
tWDW
Write Data Pulse Width
See tDRP, tICP and tWDW values in table below
1. Not tested. Guaranteed by design.
HDSEL
WGATE
tHDS
tHDH
tWDW
WDATA
tDRP tICP tWDW Values
Data Rate
tDRP
tICP
tICP Nominal
tWDW
tWDW Minimum
Unit
1 Mbps
1000
6 x tCP1
125
2 x tICP
250
nsec
500 Kbps
2000
6 x tCP1
125
2 x tICP
250
nsec
300 Kbps
3333
10 x tCP1
208
2 x tICP
375
nsec
250 Kbps
4000
12 x tCP1
250
2 x tICP
500
nsec
1. tCP is the clock period defined in Section 11.2.2.
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82
Unit
AC ELECTRICAL CHARACTERISTICS
11.0 Device Characteristics
(Continued)
11.2.10 FDC Drive Control Timing
Symbol
Parameter
Min
Max
Unit
6
µsec
Index Pulse Width
100
nsec
tSTD
DIR Hold from STEP Inactive
tSTR
msec
tSTP
STEP Active High Pulse Width1
8
µsec
tSTR
STEP Rate Time1
1
msec
tDST
DIR Setup to STEP Active
tIW
1
1. Not tested. Guaranteed by design.
DIR
tSTD
tDST
STEP
tSTP
tSTR
INDEX
tIW
11.2.11 FDC - Read Data Timing
RDATA
Symbol
Parameter
Min
tRDW
Read Data Pulse Width
50
Max
Unit
nsec
tRDW
83
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AC ELECTRICAL CHARACTERISTICS
11.0 Device Characteristics
(Continued)
11.2.12 Standard Parallel Port Timing
Symbol Parameter
Conditions
Typ
Max
Unit
tPDH
Port Data Hold
These times are system dependent
and are therefore not tested.
500
nsec
tPDS
Port Data Setup
These times are system dependent
and are therefore not tested.
500
nsec
tSW
Strobe Width
These times are system dependent
and are therefore not tested.
500
nsec
Typical Data Exchange
BUSY
ACK
tPDH
tPDS
PD7-0
tSW
STB
11.2.13 Enhanced Parallel Port Timing
Symbol
Parameter
Min
Max
EPP 1.7 EPP 1.9
tWW19a
WRITE Active from WAIT Low
45
✔
nsec
tWW19ia
WRITE Inactive from WAIT Low
45
✔
nsec
tWST19a
DSTRB or ASTRB Active from WAIT Low
65
✔
nsec
tWEST
DSTRB or ASTRB Active after WRITE Active
10
✔
✔
nsec
tWPDH
PD7-0 Hold after WRITE Inactive
0
✔
✔
nsec
tWPDS
PD7-0 Valid after WRITE Active
✔
✔
nsec
tEPDW
PD7-0 Valid Width
80
✔
✔
nsec
tEPDH
PD7-0 Hold after DSTRB or ASTRB Inactive
0
✔
✔
nsec
15
Unit
tWW19a
WRITE
DSTRB
or
ASTRB
tWST19a
tWEST
tWPDH
PD7-0
tWPDS
tWW19ia
WAIT
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84
tWST19a
tEPDH
Valid
tEPDW
AC ELECTRICAL CHARACTERISTICS
11.0 Device Characteristics
(Continued)
11.2.14 Extended Capabilities Port (ECP) Timing
Forward Mode
Symbol
Parameter
Min
Max
Unit
tECDSF
Data Setup before STB Active
0
nsec
tECDHF
Data Hold after BUSY Inactive
0
nsec
tECLHF
BUSY Active after STB Active
75
nsec
tECHHF
STB Inactive after BUSY Active
0
1
sec
tECHLF
BUSY Inactive after STB Active
0
35
msec
tECLLF
STB Active after BUSY Inactive
0
nsec
tECDHF
PD7-0
AFD
tECDSF
tECLLF
STB
tECHLF
tECLHF
BUSY
tECHHF
Reverse Mode
Symbol
Parameter
Min
Max
Unit
tECDSR
Data Setup before ACK Active
0
nsec
tECDHR
Data Hold after AFD Active
0
nsec
tECLHR
AFD Inactive after ACK Active
75
nsec
tECHHR
ACK Inactive after AFD Inactive
0
35
msec
tECHLR
AFD Active after ACK Inactive
0
1
sec
tECLLR
ACK Active after AFD Active
0
nsec
tECDHB
PD7-0
BUSY
tECDSB
ACK
tECLLB
tECLHB
AFD
tECHLB
tECHHB
85
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PC87351 PC98 and ACPI Compliant SuperI/O with System Wake-Up Control
Physical Dimensions
All dimensions are in millimeters
Plastic Quad Flatpack (PQFP), JEDEC
Order Number PC87351-xxx/VLA
NS Package Number VLA128A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
National Semiconductor
Corporation
Fax: 1-800-737-7018
Email: [email protected]
Tel: 1-800-272-9959
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.