IP4853CX24 SD, MMC and microSD memory card integrated level shifter with PSU, EMI filter and ESD protection Rev. 02 — 15 June 2009 Product data sheet 1. Product profile 1.1 General description The IP4853CX24 is a device that fully integrates a bidirectional level shifter or voltage translator, EMI filter and ESD protection diodes. It is specifically designed to be used for memory card interfaces such as SD, microSD and MultiMediaCard (MMC) memory cards. The integrated power supply unit supplies memory cards with 2.9 V directly from the battery. This enables a 1.8 V operating host-side device (e.g. a processor interface) to communicate with a 2.9 V compliant memory card using its integrated level shifter. Radiation from digital signals in the higher harmonics, close to typical mobile phone frequencies, is suppressed by the EMI filter. The IP4853CX24 is fabricated using monolithic silicon technology in a Wafer Level Chip-Scale Package (WLCSP) with 0.4 mm pitch. 1.2 Features n n n n n n Dark Green compliant. Pb-free, RoHS compliant Integrated EMI filters Feedback channel for clock synchronization Integrated ESD protection according to IEC 61000-4-2, level 4 WLCSP with 0.4 mm pitch 1.3 Applications n SD memory card, microSD memory card and MMC interfaces in latest electronic appliances such as: u Mobile phone or smart phone u Digital camera u Card reader in (laptop) computer n Appliances requiring one or several of the following features: u Level shifting and voltage translation from 1.8 V to 2.9 V and from 2.9 V to 1.8 V u ESD protection according to IEC 61000-4-2, level 4 u Power supply regulation from battery to 2.9 V card memory voltage u EMI filtering u Integration of interface-specific biasing resistor network IP4853CX24 NXP Semiconductors SD, MMC and microSD memory card integrated level shifter 2. Pinning information 2.1 Pinning bump A1 index area IP4853CX24 1 2 3 4 5 A B C D E 001aah951 Transparent top view Fig 1. Pin configuration for WLCSP24 package Table 1. Pin allocation table Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol A1 DATA2_H A2 DIR_CMD A3 DIR_0 A4 VBAT A5 DATA2_SD B1 DATA3_H B2 n.c. B3 VCC B4 VSD B5 DATA3_SD C1 CLK_IN C2 ENABLE C3 GND C4 GND C5 CLK_SD D1 DATA0_H D2 CMD_H D3 CD D4 CMD_SD D5 DATA0_SD E1 DATA1_H E2 CLK_FB E3 DIR_1_3 E4 WP E5 DATA1_SD 2.2 Pin description Table 2. Pin description Symbol[1] Pin Type[2] Description DATA2_H A1 I/O data 2 input or output on host-side DIR_CMD A2 I direction control input for command DIR_0 A3 I direction control input for data 0 VBAT A4 S supply voltage from battery for regulator DATA2_SD A5 I/O data 2 input or output on memory card-side DATA3_H B1 I/O data 3 input or output on host-side n.c. B2 - not connected VCC B3 S supply voltage for host-side circuits VSD B4 O output supply voltage for memory card DATA3_SD B5 I/O data 3 input or output on memory card-side CLK_IN C1 I clock signal input IP4853CX24_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 15 June 2009 2 of 19 IP4853CX24 NXP Semiconductors SD, MMC and microSD memory card integrated level shifter Table 2. Pin description …continued Symbol[1] Pin Type[2] Description ENABLE C2 I device enable input GND C3 S supply ground GND C4 S supply ground CLK_SD C5 O clock signal output on memory card-side DATA0_H D1 I/O data 0 input or output on host-side CMD_H D2 I/O command input or output on host-side CD D3 O card detect switch biasing output CMD_SD D4 I/O command input or output on memory card-side DATA0_SD D5 I/O data 0 input or output on memory card-side DATA1_H E1 I/O data 1 input or output on host-side CLK_FB E2 O clock feedback output to host DIR_1_3 E3 I direction control input for data 1, data 2 and data 3 WP E4 O write protect switch biasing output DATA1_SD E5 I/O data 1 input or output on memory card-side [1] The pin names relate particularly to SD memory cards, but also apply to microSD and MMC memory cards. [2] I = input, O = output, I/O = input and output, S = power supply. 3. Ordering information Table 3. Ordering information Type number Package Name IP4853CX24 Description WLCSP24 wafer level chip-size package; 24 bumps; 2.01 × 2.01 × 0.61 mm IP4853CX24_2 Product data sheet Version IP4853CX24 © NXP B.V. 2009. All rights reserved. Rev. 02 — 15 June 2009 3 of 19 IP4853CX24 NXP Semiconductors SD, MMC and microSD memory card integrated level shifter 4. Block diagram host side VBAT CLK_IN CLK_FB DIR_CMD SD card side A4 B4 VOLTAGE REGULATOR R1 C1 C5 DIR_0 A2 R10 D4 DIR_1_3 A3 R11 D5 DATA0_SD D1 E3 R12 R4 DATA1_H CMD_SD D2 R3 DATA0_H CLK_SD E2 R2 CMD_H VSD E5 DATA1_SD E1 R13 R5 DATA2_H A5 R6 DATA3_H VCC ENABLE DATA2_SD A1 B5 DATA3_SD B1 R7 B3 C3, C4 C2 R14 GND R15 E4 D3 WP CD IP4853CX24 001aah980 Fig 2. Block diagram IP4853CX24_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 15 June 2009 4 of 19 IP4853CX24 NXP Semiconductors SD, MMC and microSD memory card integrated level shifter 5. Functional description 5.1 Logic control signals Table 4. Control signal truth table VBAT ≥ 2.7 V. Control Host-side Level[1] Pin Pin Memory card-side Function Pin Function Pin ENABLE = HIGH and VCC ≥ 1.62 V DIR_CMD DIR_0 DIR_1_3 - H CMD_H input CMD_SD output L CMD_H output CMD_SD input H DATA0_H input DATA0_SD output L DATA0_H output DATA0_SD input H DATA1_H, DATA2_H, DATA3_H input DATA1_SD, DATA2_SD, DATA3_SD output L DATA1_H, DATA2_H, DATA3_H output DATA1_SD, DATA2_SD, DATA3_SD input - CLK_FB output CLK_SD output Pin ENABLE = LOW or VCC ≤ 0.8 V DIR_CMD X CMD_H high-Z CMD_SD high-Z DIR_0 X DATA0_H high-Z DATA0_SD high-Z DIR_1_3 X DATA1_H, DATA2_H, DATA3_H high-Z DATA1_SD, DATA2_SD, DATA3_SD high-Z - - CLK_FB high-Z CLK_SD high-Z [1] H = HIGH; L = LOW and X = don’t care. IP4853CX24_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 15 June 2009 5 of 19 IP4853CX24 NXP Semiconductors SD, MMC and microSD memory card integrated level shifter 6. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VBAT battery supply voltage input voltage VI Conditions Min Max Unit −0.5 +3.5 V 4 ms transient −0.5 +5.5 V operating −0.5 +5.0 V −0.5 +5.5 V at I/O pins 4 ms transient −0.5 +5.0 V - 550 mW storage temperature −55 +150 °C Tamb ambient temperature −30 +85 °C VESD electrostatic discharge voltage contact - ±8000 V air discharge - ±15000 V - ±2000 V Min Max Unit operating Ptot total power dissipation Tstg Tamb = −30 °C to +70 °C pin VBAT and all memory card-side pins to ground; according to IEC 61000-4-2, level 4 all other pins to ground; according to IEC 61340-3-1, human body model 7. Recommended operating conditions Table 6. Operating conditions Symbol Parameter VCC supply voltage 1.62 2.1 V VBAT battery supply voltage 2.7[1] 5.0 V VI input voltage output voltage VO Conditions host-side 0 2.1 V memory card-side; VBAT ≥ 3.2 V 0 2.9 V 0 VCC V active mode; pin ENABLE = HIGH host-side 0 VO(reg) V host-side; between 0.2VCC and 0.7VCC - 2 ns/V memory card-side; between 0.2VO(reg) and 0.7VO(reg) - 2 ns/V memory card-side ∆t/∆V [1] time difference over voltage change The device is still fully functional, but the voltage on pin VSD might drop below the recommended memory card supply voltage. IP4853CX24_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 15 June 2009 6 of 19 IP4853CX24 NXP Semiconductors SD, MMC and microSD memory card integrated level shifter 8. Static characteristics Table 7. Static characteristics At recommended operating conditions; Tamb = −30 °C to +85 °C; voltages are referenced to GND (ground = 0 V); unless otherwise specified. Symbol Parameter Min Typ[1] Max Unit IO(reg) = 0 A - 2.9 2.987 V IO(reg) = 200 mA; VBAT ≥ 2.9 V 2.75 - - V - - 150 mV Conditions Voltage regulator output: pin VSD VO(reg) regulator output voltage ∆Vdo(reg) regulator dropout voltage variation CL = 1 µF IO(reg) = 200 mA IO(reg) regulator output current - 200 - mA IO(sc) short-circuit output current - - 500 mA Iq(reg) regulator quiescent current pin ENABLE = HIGH (active mode) external capacitance Cext - - 200 µA pin ENABLE = LOW (not active mode) - - 2 µA recommended capacitor at pin VSD - 1.0 - µF 0.65 × VCC - - V - - 0.3 V - - 20 pF 0.65 × VO(reg) - - V - - 0.3 V - - 20 pF Control and data inputs Host-side: pins ENABLE, DIR_0, DIR_1_3, DIR_CMD, CLK_IN and DATA0_H to DATA3_H VIH HIGH-level input voltage VIL LOW-level input voltage channel capacitance Cch VI = 0 V; fi = 1 MHz [2] Memory card-side: pins CMD_SD and DATA0_SD to DATA3_SD VIH HIGH-level input voltage VIL LOW-level input voltage channel capacitance Cch VI = 0 V; fi = 1 MHz [2] Control and data outputs Host-side: pins CLK_FB, CMD_H and DATA0_H to DATA3_H VOH HIGH-level output voltage IO = −3 mA; VI = VIH VCC − 0.45 - - V VOL LOW-level output voltage IO = 3 mA; VI = VIL - - 0.45 V Memory card-side: pins CLK_SD, CMD_SD and DATA0_SD to DATA3_SD, CD and WP VOH HIGH-level output voltage IO = −6 mA; VI = VIH VO(reg) − 0.45 - - V VOL LOW-level output voltage IO = 6 mA; VI = VIL - - 0.45 V ILRzd Zener diode reverse leakage current VI = 3 V - - 100 nA Rs series resistance R1 to R6; tolerance ±20 % 32 40 48 Ω Rpd pull-down resistance R7; tolerance ±30 % 329 470 611 kΩ Rpu pull-up resistance R10; tolerance ±30 % 10.5 15 19.5 kΩ R11 to R13; tolerance ±30 % 49 70 91 kΩ R14 and R15; tolerance ±30 % 70 100 130 kΩ [1] Typical values are measured at Tamb = 25 °C. [2] EMI filter line capacitance per data channel from I/O pin to driver; Cch is guaranteed by design. IP4853CX24_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 15 June 2009 7 of 19 IP4853CX24 NXP Semiconductors SD, MMC and microSD memory card integrated level shifter 9. Dynamic characteristics Table 8. Voltage regulator Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit fripple = 1 kHz 40 - - dB fripple = 10 kHz 30 - - dB - - 200 µs Min Typ Max Unit 9 - - dB Voltage regulator output: pin VSD PSRR power supply rejection ratio tstartup(reg) regulator start-up time VBAT = 3.0 V; Vripple(p-p) = 223.6 mV (0 dBm); Rsource = 50 Ω VCC = 1.8 V; VBAT = 3.0 V; IO(reg) = 200 mA; CL = 1 µF; see Figure 3 VI 50 % ENABLE GND tstartup(reg) VO(reg) 97 % regulator output 0V 001aah981 Measuring points: ENABLE signal at 0.5VCC and regulator output signal at 0.97VO(reg). Fig 3. Regulator start-up time Table 9. Frequency response of integrated EMI filters Tamb = 25 °C; unless otherwise specified. Symbol Parameter Conditions Clock, command and data channels[1] αil insertion loss Rsource = 50 Ω; CL = 10 pF; RL = 50 Ω fi = 401 MHz to 800 MHz [1] fi = 801 MHz to 1.4 GHz - 17 - dB fi = 1.4 GHz to 6.0 GHz - 32 - dB Guaranteed by design. IP4853CX24_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 15 June 2009 8 of 19 IP4853CX24 NXP Semiconductors SD, MMC and microSD memory card integrated level shifter Table 10. Output rise and fall times VBAT = 3.5 V; VO(reg) = 2.9 V; unless otherwise specified; transition time is the same as output rise time and output fall time; see Figure 4 for timing diagram and Figure 5 for test circuit. Symbol Parameter Conditions Min Typ Max Unit Tamb = +25 °C; VCC = 1.8 V - 1.5 2.5 ns Tamb = −30 °C; VCC = 1.9 V - 1.5 2.5 ns Tamb = +70 °C; VCC = 1.62 V - 1.8 2.8 ns Tamb = +25 °C; VCC = 1.8 V - 2.7 3.6 ns Tamb = −30 °C; VCC = 1.9 V - 2.7 3.6 ns Tamb = +70 °C; VCC = 1.62 V - 2.9 3.8 ns Tamb = +25 °C; VCC = 1.8 V - 3.0 4.2 ns Tamb = −30 °C; VCC = 1.9 V - 2.9 4.1 ns Tamb = +70 °C; VCC = 1.62 V - 3.7 4.9 ns Tamb = +25 °C; VCC = 1.8 V - 1.5 2.4 ns Tamb = −30 °C; VCC = 1.9 V - 1.3 2.3 ns Tamb = +70 °C; VCC = 1.62 V - 1.6 2.5 ns Tamb = +25 °C; VCC = 1.8 V - 1.7 2.9 ns Tamb = −30 °C; VCC = 1.9 V - 1.4 2.5 ns Tamb = +70 °C; VCC = 1.62 V - 1.8 3.0 ns Memory card-side outputs: pins CLK_SD, CMD_SD and DATA0_SD to DATA3_SD Reference points at 70 % and 20 % tt transition time CL = 20 pF; RL = 100 kΩ CL = 40 pF; RL = 100 kΩ Reference points at 90 % and 10 % tt transition time CL = 20 pF; RL = 100 kΩ Host-side outputs: pins CLK_FB, CMD_H and DATA0_H to DATA3_H Reference points at 70 % and 20 % tt transition time CL = 5 pF; RL = 100 kΩ CL = 20 pF; RL = 100 kΩ Reference points at 90 % and 10 % tt transition time CL = 5 pF; RL = 100 kΩ Tamb = +25 °C; VCC = 1.8 V - 2.4 3.1 ns Tamb = −30 °C; VCC = 1.9 V - 2.3 3.0 ns Tamb = +70 °C; VCC = 1.62 V - 2.5 3.2 ns IP4853CX24_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 15 June 2009 9 of 19 IP4853CX24 NXP Semiconductors SD, MMC and microSD memory card integrated level shifter Table 11. Propagation delay of time domain response driver part VBAT = 3.5 V; VO(reg) = 2.9 V; Rsource = 50 Ω; propagation delay measurements include PCB delays and connectors; see Figure 4 for timing diagram and Figure 5 for test circuit. Symbol Parameter Conditions Min Typ Max Unit CL = 20 pF 6.2 7.0 7.8 ns CL = 40 pF 7.3 8.2 9.1 ns CL = 20 pF 5.7 6.5 7.3 ns CL = 40 pF 6.5 7.5 8.5 ns CL = 20 pF 6.7 7.8 8.9 ns CL = 40 pF 7.5 8.8 10.1 ns CL = 5 pF 4.2 6.0 7.8 ns CL = 20 pF 6.3 7.2 8.1 ns Host-side inputs to memory card-side outputs propagation delay tPD nominal case; Tamb = +27 °C; VCC = 1.8 V [1] best case; Tamb = −30 °C; VCC = 1.9 V worst case; Tamb = +70 °C; VCC = 1.62 V Memory card-side inputs to host-side outputs propagation delay tPD nominal case; Tamb = +27 °C; VCC = 1.8 V [1] best case; Tamb = −30 °C; VCC = 1.9 V CL = 5 pF 4 5.9 6.9 ns CL = 20 pF 5.1 6.7 8.5 ns CL = 5 pF 5.4 6.5 7.7 ns CL = 20 pF 6.7 8.0 9.2 ns CL = 5 pF 7.6 9.2 10.7 ns CL = 20 pF 8.2 9.9 11.6 ns CL = 5 pF 6.7 8.1 9.5 ns CL = 20 pF 7.6 8.8 10.5 ns CL = 5 pF 8.5 10.7 12.9 ns CL = 20 pF 9.1 11.4 13.9 ns worst case; Tamb = +70 °C; VCC = 1.62 V Host-side pins CLK_IN to CLK_FB propagation delay tPD nominal case; Tamb = +27 °C; VCC = 1.8 V [1] best case; Tamb = −30 °C; VCC = 1.9 V worst case; Tamb = +70 °C; VCC = 1.62 V [1] tPD is the same as HIGH-to-LOW propagation delay (tPHL) and LOW-to-HIGH propagation delay (tPLH). IP4853CX24_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 15 June 2009 10 of 19 IP4853CX24 NXP Semiconductors SD, MMC and microSD memory card integrated level shifter VI VM A, B input GND tPLH tPHL VOH B, A output VM 001aae967 VOL Measuring points: host-side at 0.5VCC and memory card-side at 0.5VO(reg). VOL and VOH are typical output voltage levels that occur with the output load. Fig 4. Output rise and fall times and data input to output propagation delay times (host-side to card-side or card-side to host-side) Table 12. Power dissipation per channel VCC = 1.8 V; VBAT = 4 V; all values are typical; memory card-side CL = 20 pF and host-side CL = 5 pF. Frequency (MHz) IBAT (mA) ICC (mA) P (mW)[1] Host-side input to memory card-side output Data channel 1.0 0.79 0.002 3.16 10.0 3.30 0.020 13.3 20.0 5.79 0.037 23.2 50.0 12.3 0.090 49.4 1.0 0.44 0.05 1.85 10.0 3.1 0.59 13.5 20.0 5.4 0.97 23.4 50.0 12.2 2.36 53.1 Clock channel Memory card-side input to host-side output Data channel 1.0 0.18 0.1 0.9 10.0 0.42 0.96 3.41 20.0 0.66 1.91 6.1 50.0 1.4 4.5 13.7 [1] Power consumption is largely dependent on capacitive load connected to a driver output: P = VCC × ICC + VBAT × IBAT. IP4853CX24_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 15 June 2009 11 of 19 IP4853CX24 NXP Semiconductors SD, MMC and microSD memory card integrated level shifter 10. Test information tW VI 70 % negative input 50 % 0V tf tr tr tf VI 70 % positive input 0V 50 % 20 % 50 % 50 % 20 % tW VBAT VCC PULSE GENERATOR tr = tf = 1.8 ns Rsource VI VO DUT 50 Ω Rterm CL RL 001aah982 Definitions test circuit: Rsource = source resistance of pulse generator. Rterm = termination resistance should be equal to output impedance Z0 of the pulse generator. CL = load capacitance including jig and probe capacitance. RL = load resistance. Fig 5. Load circuitry for measuring switching time 11. Marking bump A1 indicator LASER MARKING AREA 001aah952 top view Fig 6. Marking of IP4853CX24 IP4853CX24_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 15 June 2009 12 of 19 IP4853CX24 NXP Semiconductors SD, MMC and microSD memory card integrated level shifter 12. Package outline WLCSP24: wafer level chip-size package; 24 bumps; 2.01 x 2.01 x 0.61 mm IP4853CX24 D bump A1 index area A2 E A A1 detail X e1 e b E e D e2 C B A 1 2 3 4 5 X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A A1 A2 b D E e e1 e2 0.66 0.61 0.56 0.22 0.20 0.18 0.44 0.41 0.38 0.29 0.26 0.23 2.06 2.01 1.96 2.06 2.01 1.96 0.4 1.6 1.6 OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 08-04-14 09-06-11 IP4853CX24 Fig 7. EUROPEAN PROJECTION Package outline IP4853CX24 (WLCSP24) IP4853CX24_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 15 June 2009 13 of 19 IP4853CX24 NXP Semiconductors SD, MMC and microSD memory card integrated level shifter 13. Packing information 3° to 8° K B-B θ A0 A D1 P K0 5° max G W1 B0 W B B F E P2 A D0 0.05 / 40 T1 P0 T A-A direction of feed Fig 8. 001aai051 Tape and reel information Table 13. Tape dimensions Description Item Overall dimensions Sprocket holes[1] Symbol Dimension Tolerance tape width W 8.00 ±0.1 thickness K 1.20 max. distance G 0.75 min. diameter D0 1.50 +0.1 distance E 1.75 ±0.1 pitch P0 4.00 ±0.1 Distance between center lines length direction P2 2.00 ±0.05 width direction F 3.50 ±0.05 Compartments length A0 2.20 ±0.05 width B0 2.20 ±0.05 depth K0 0.80 ±0.05 hole diameter D1 0.50 +0.1 pitch P 4.00 ±0.1 rotation θ 20° max. Device Carrier tape antistatic[2] Cover tape[3] Bending radius film thickness T 0.25 ±0.07 width W1 5.75 max. film thickness T1 0.1 max. in winding direction R 30 min. IP4853CX24_2 Product data sheet Specification (mm) © NXP B.V. 2009. All rights reserved. Rev. 02 — 15 June 2009 14 of 19 IP4853CX24 NXP Semiconductors SD, MMC and microSD memory card integrated level shifter [1] Cumulated pitch error: ±0.2 mm per 10 pitches. [2] Carbon loaded polystyrene 100 % recyclable. [3] The cover tape shall not overlap the sprocket holes. 14. Design and assembly recommendations 14.1 PCB design guidelines To achieve optimum performance it is recommended to use a Non-Solder Mask Design (NSMD) PCB design, also known as a copper defined design, incorporating laser-drilled micro-vias connecting the ground pads to a buried ground-plane layer. This results in the lowest possible ground inductance and provides the best high frequency and ESD performance. Refer to Table 14 for the recommended PCB design parameters. Table 14. Recommended PCB design parameters PCB pad size 225 µm diameter Micro-via diameter 100 µm Solder mask opening 335 µm diameter Copper thickness 20 µm to 40 µm Copper finish OSP PCB material FR4 14.2 PCB assembly guidelines for Pb-free soldering Table 15. Assemble recommendations Solder screen aperture size 255 µm diameter Solder screen thickness 100 µm (0.004") Solder paste: Pb-free SnAg[1]Cu[2] Solder/flux ratio 50 : 50 Solder reflow profile see Figure 9 [1] 3 to 4. [2] 0.5 to 0.9. IP4853CX24_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 15 June 2009 15 of 19 IP4853CX24 NXP Semiconductors SD, MMC and microSD memory card integrated level shifter T (°C) Treflow(peak) 250 230 cooling rate 217 pre-heat t1 t (s) t3 t2 t4 t5 001aai161 The device is capable of withstanding at least three reflows of this profile. Fig 9. Table 16. Symbol Pb-free solder reflow profile Characteristics Parameter Treflow(peak) peak reflow temperature Conditions Min Typ Max Unit ∆T = 0 °C to +5 °C 230 - 255 °C t1 time 1 soak time 60 - 180 s t2 time 2 time from T = 25 °C to Treflow(peak) 240 - 300 s t3 time 3 time during T ≥ 250 °C - - 30 s t4 time 4 time during T ≥ 230 °C 10 - 50 s t5 time 5 time during T > 217 °C 30 - 150 s dT/dt rate of change of temperature cooling rate - - −6 °C/s pre-heat 2.5 - 4.0 °C/s 15. Abbreviations Table 17. Abbreviations Acronym Description DUT Device Under Test EMI ElectroMagnetic Interference ESD ElectroStatic Discharge FR4 Flame Retard 4 MMC MultiMediaCard NSMD Non-Solder Mask Design OSP Organic Solderability Preservation PCB Printed-Circuit Board PSU Power Supply Unit IP4853CX24_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 15 June 2009 16 of 19 IP4853CX24 NXP Semiconductors SD, MMC and microSD memory card integrated level shifter Table 17. Abbreviations …continued Acronym Description RoHS Restriction of Hazardous Substances SD Secure Digital WLCSP Wafer Level Chip-Scale Package 16. Revision history Table 18. Revision history Document ID Release date Data sheet status Change notice Supersedes IP4853CX24_2 20090615 Product data sheet - IP4853CX24_1 Modifications: IP4853CX24_1 • • • • Table 11: Added minimum values and values for ‘host-side pins CLK_IN to CLK_FB’. Table 7: Changed maximum value for regulator quiescent current (not active mode). Table 8: Moved values from maximum to minimum for power supply rejection ratio. Removed /LF from all instances of type number IP4853CX24. 20080722 Product data sheet IP4853CX24_2 Product data sheet - - © NXP B.V. 2009. All rights reserved. Rev. 02 — 15 June 2009 17 of 19 IP4853CX24 NXP Semiconductors SD, MMC and microSD memory card integrated level shifter 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] IP4853CX24_2 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 02 — 15 June 2009 18 of 19 IP4853CX24 NXP Semiconductors SD, MMC and microSD memory card integrated level shifter 19. Contents 1 1.1 1.2 1.3 2 2.1 2.2 3 4 5 5.1 6 7 8 9 10 11 12 13 14 14.1 14.2 15 16 17 17.1 17.2 17.3 17.4 18 19 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Logic control signals . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Test information . . . . . . . . . . . . . . . . . . . . . . . . 12 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Packing information. . . . . . . . . . . . . . . . . . . . . 14 Design and assembly recommendations . . . 15 PCB design guidelines . . . . . . . . . . . . . . . . . . 15 PCB assembly guidelines for Pb-free soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 15 June 2009 Document identifier: IP4853CX24_2