AN86272 PRoC - CS Hardware Design Guidelines.pdf

AN86272
PRoC™-CS Hardware Design Guidelines
Author: Selvakumar Manickam
Associated Project: N/A
Associated Part Family: CYRF89435
Software Version: N/A
If you have a question, or need help with this application note, contact the author at
[email protected]
AN86272 describes the recommended hardware design guidelines for PRoC-CS (Programmable Radio on Chip ®
CapSense ). This includes schematics and layout design guidelines for creating designs with CapSense and Wireless
capabilities. PRoC-CS is part of the PRoC-UI (Programmable Radio on Chip - User Interface) product family. It is a
single-chip solution that combines Cypress’s CapSense capacitive touch technologies with 2.4 GHz GFSK-modulated
1-Mbps wireless transceiver to offer a complete solution for capacitive human interface and wireless communication.
Contents
Introduction
Introduction.................................................................................. 1
Typical PRoC-CS Hardware Design ............................................ 2
CapSense User Interface ....................................................... 2
2.4-GHz Wireless Capability................................................... 2
Mechanical buttons, LEDs, and Other Peripherals ................. 2
Power Supply ......................................................................... 2
Programming (ISSP) and Debugging (I2C)............................. 2
PRoC-CS versus PRoC-LP/PRoC-LPStar ................................... 3
Schematics Design ...................................................................... 3
PRoC-CS Pinout .................................................................... 3
Power Supply ......................................................................... 3
Clock ...................................................................................... 6
2.4-GHz RF ............................................................................ 7
CapSense Buttons and Sliders ............................................... 8
Peripherals ........................................................................... 11
Programming (ISSP) and Debugging (I2C)........................... 12
Layout Design ........................................................................... 13
Layer Stack up ..................................................................... 13
PRoC-CS Device Package Dimensions ............................... 13
Power Supply ....................................................................... 13
Clock .................................................................................... 13
2.4 GHz RF Design .............................................................. 14
CapSense Button Design ..................................................... 15
CapSense Slider Design ...................................................... 15
CapSense Sensor Placement and Vias ................................ 16
Trace Length, Width, and Routing ........................................ 16
Antenna Recommendations ................................................. 17
PIFA Antenna Dimension ..................................................... 18
CapSense Layout Guidelines: Quick Reference ........................ 19
Schematics and Layout Review Checklist .................................. 20
Reference Documents ............................................................... 21
Development Kit ........................................................................ 21
Worldwide Sales and Design Support ........................................ 23
PRoC-CS is a 2.4-GHz RF solution integrated with
Cypress’ capacitive touch sensing 8-bit MCU. The PRoCCS is a complete solution featuring 32-KB flash, with
support for CapSense button, slider, proximity sensors,
and a GFSK radio modem which can support data rate up
to 1 Mbps. Some of the key applications you can create
using PRoC-CS are:
www.cypress.com



Keyboard with capacitive buttons
Mouse with capacitive scroll-wheel
Remote controller with capacitive buttons
This application note explains how to create the
schematics and layout for a PRoC-CS-based application.
It also includes a checklist that you can use as a quick
reference to check conformance to the recommended
hardware design guidelines.
A reference schematic to illustrate the design of a wireless
keyboard with CapSense buttons and a slider is attached
with this document.
Document No. 001-86272 Rev. **
1
PRoC™-CS Hardware Design Guidelines
Typical PRoC-CS Hardware Design
Figure 1. Typical PRoC-CS-based Design
Figure 1 illustrates a typical PRoC-CS-based hardware
design. You can use such designs with PRoC-USB based
USB dongle design which acts as a bridge with your PC to
transmit data from PRoC-CS-based devices.
The following sections briefly describe each of the subsystems that make up the design. Detailed schematics
and layout guidelines are discussed in later sections of
this application note.
For more information about the capabilities of PRoC-CS
product refer to the PRoC-CS datasheet listed in the
Reference Documents section on page 21.
CapSense User Interface
Capacitive sensing buttons, sliders, and proximity sensors
are the three types of user interfaces that you can create
using PRoC-CS. Each of the touch buttons requires a
GPIO. A slider is a continuous strip of sensors which you
can use to implement controls requiring gradual
adjustments, such as brightness control, volume control,
and so on. The number of GPIOs needed to form a slider
depends on the resolution required, and a minimum of five
GPIOs are required to form a slider. You can implement a
proximity sensor using a GPIO in the form of a button,
wire, or PCB trace.
www.cypress.com
2.4-GHz Wireless Capability
PRoC-CS provides wireless capability using an in-built
2.4-GHz RF transceiver. An antenna, along with matching
network, needs to be connected to PRoC-CS to implement
wireless functionality.
Mechanical buttons, LEDs, and Other
Peripherals
You can connect mechanical buttons and LEDs over
GPIOs. Other peripherals, such as mouse sensors, can be
connected to a PRoC-CS device over GPIOs or SPI.
Power Supply
Power supply consists of a power source such as AA/AAA
batteries and an optional DC-DC regulator.
Programming (ISSP) and Debugging (I2C)
In-System Serial Programming (ISSP) Interface is required
to program the firmware onto a PRoC-CS device. PRoCCS supports I2C slave and it is used to tune and debug
the CapSense functionality by measuring sensor
capacitance. You can access both these interfaces using
the Miniprog3 kit. For more information, refer to the
development kit listed in the Reference Documents
section on page 21.
Document No. 001-86272 Rev. **
2
PRoC™-CS Hardware Design Guidelines
PRoC-CS versus PRoC-LP/PRoCLPStar
Figure 3. 68-QFN PRoC-CS Pinout
The following table lists the differences between PRoC-CS
and other PRoC devices (PRoC-LP and PRoC-LPStar)
Table 1. PRoC-CS versus PRoC-LP/PRoC-LPStar
PRoC-CS
PRoC-LP/PRoCLPStar
Radio
2.4 GHz with
GSFK modulation
2.4GHz with GFSK or
DSSS modulation
Radio Tx
Power
+1 dBm
+ 4 dBm
Max Tx Power
consumption
22.5 mA
45 mA
CapSense
capabilities
Button, slider, and
proximity sensor
None
Parameter
To summarize, PRoC-CS provides additional CapSense
capabilities with the next generation low-power 2.4-GHz
transceiver.
CYRF8943568LTXC
Schematics Design
The schematics and layout design details explained in this
application note are based on the 68-QFN package variant
of PRoC-CS. All these design details are also applicable
to the 40-QFN package of PRoC-CS, unless stated
otherwise.
PRoC-CS Pinout
Power Supply
PRoC-CS is available in 40-QFN and 68-QFN variants.
The 68-QFN variant provides more GPIOs compared to
the 40-QFN variant. Figure 2 and Figure 3 show the pinout
details for these variants.
Figure 2. 40-QFN PRoC-CS Pinout
Power Supply Design
PRoC-CS can operate in the voltage range of 1.9 V to
3.6 V. Cypress recommends that you use an external DCDC regulator for the following types of applications:


Applications powered by a single AA/AAA battery
Applications with parts that require a constant supply
voltage, such as mouse optical sensors
Figure 4 shows a reference power supply design for
PRoC-CS using an external DC-DC regulator.
CYRF8943540LTXC
Figure 4. Reference Power Supply Design Schematics
VCC
U3
3
2
GND1
VBat
2
3
IN
FB
EN
6
5
4
C15
22uF
C19
100uF
SPDT
BT1
BT2
Low ESR
7
1
OUT
Low ESR
TP9
SW4
LX
TPAD
1
L2
4.7uH
SC120ULTRT
+
C17
22uF
BATTERY
www.cypress.com
Document No. 001-86272 Rev. **
3
C16
0.10uF
PRoC™-CS Hardware Design Guidelines
The output voltage range is 1.9 V to 3.6 V.
The output noise at the 50-kHz component must be
less than 50 mV pk-pk.
Reference DC-DC Regulator Parts
The recommended DC-DC regulator parts that you can
use in PRoC-CS-based hardware designs are:
SC120ULTRT: SC120ULTRT by Semtech Corporation is
a high efficiency, low noise, synchronous step-up DC-DC
converter that provides boosted voltage levels in lowvoltage handheld applications.
LT1763CS8-3.3: LT1763 series LDO by Linear
Technology is a low noise, low dropout regulator capable
of supplying 500 mA of output current with a dropout
voltage of 300 mV. LT1763 parts are available in an 8-pin
package. Because these parts can support input voltage
range of 3.7 V to 20 V, you can use them in designs where
an AC-DC adapter or Lithium Ion batteries are used as a
power source.
If the regulator does not support this feature, add a
mechanism to detect low battery condition in the firmware,
so that you can shut down the device. This is also
applicable for designs that do not use a DC-DC regulator.
Figure 5 describes a schematic to detect the battery
voltage level using the in-built ADC of PRoC-CS.
Figure 5. Detecting Battery Level
U5
51
50
VBat
R8 1%
5.62K
SC120ULTRT
Step-up
(Semtech Corporation)
DC-DC
Regulator
LT1763CS8-3.3
(Linear Technology)
www.cypress.com
LDO
Regulator
Vin
(Volt)
0.7-3.8
48
LVD
LVD
Type
Vout
(Volt)
3.3
49
ADC_EN
Table 2. Reference DC-DC Regulator Parts
Regulator Part Number
and Manufacturer
P10
47
46
45
R9 1%
3.32K
44
43
42
ADC_EN
41
3.7 to
20
52


Handling Low Battery Condition
The power supply design should ensure that battery
leakage does not occur under low battery condition. If you
are using a DC-DC regulator, check whether the regulator
has an in-built feature (undervolt lockout) to auto
shutdown when it detects low battery condition.
XRES
DC-DC Regulator Part Selection Criteria
The DC-DC regulator part must meet the following criteria:
3.3
40
39
Document No. 001-86272 Rev. **
P1_6
VDD
P1_4
P1_2
P1_0
TEST1
NC
XTALI
XTALO
VDD
GND
P1_1
VOUT
4
PRoC™-CS Hardware Design Guidelines
P o w e r S u p p l y C o n n e c t i vi t y
PRoC-CS has 3 VIN pins. VIN supports the operating voltage that can vary between 1.9 V to 3.6 V. PRoC-CS has an in-built
LDO providing a constant output of1.8 V (VOUT), which powers seven VDD pins as shown in Figure 6.
The following schematics describe the connectivity among VIN, VOUT, and VDD pins.
Figure 6. PRoC-CS Power Supply Connectivity
C11
0.10uF
69
Epad
68
P0_2
67
P0_0
66
65
P2_6
P2_4
64
P2_2
63
62
VDD
P2_0
61
ANT
P4_2
60
59
P4_0
58
ANTB
P3_6
57
56
55
P3_4
P3_2
54
P3_0
VDD
P0_7
GND
P0_5
P1_1
P0_3
VOUT
FIFO
P1_3
P0_1
VIN
VIN
1
C24
0.10uF
2
C21
3
4
0.10uF
5
6
C22
7
8
0.10uF
9
10
11
12
13
14
VCC
15
16
C23
0.10uF
P2_5
17
18
P2_3
19
P2_1
20
P4_1
21
22
23
34
+1.8V
P3_7
P2_7
SPI_SS
CCLK
P3_5
OCDOE
VDD
HCLK
24
35
C6
0.10uF
OCDE
P3_3
36
XTALO
25
37
OCDO
PROC CS
PKT
38
XTALI
26
VCC
39
VDD
P3_1
+1.8V
NC
27
40
VIN
CLK
C25
0.10uF
TEST1
28
41
P0_6
MOSI
42
P1_0
29
43
P0_4
MISO
44
P1_2
30
45
VDD
P1_7
46
Test3
P1_4
31
47
VDD
RST_N
48
VCC
Test2
32
49
C27
0.10uF
P1_6
P1_5
50
33
51
VDD
XRES
U5
53
52
C26
0.10uF
VCC
+
C12
4.7uF
R41 10K
www.cypress.com
TP18
Document No. 001-86272 Rev. **
5
PRoC™-CS Hardware Design Guidelines
Clock
Clock Circuit Design
PRoC-CS requires an external crystal. Figure 7 shows the
reference schematic for the clock circuit.
61
60
ANT
P4_2
59
58
P4_0
57
ANTB
P3_6
56
55
P3_4
54
P3_2
53
P3_0
52
P1_3
10 pF
7M-12.000MEEQ-T
TXC Corp
10 PPM
10 pF
NXK12.000AE12FKAB5
JenJaan
Quartek
20 PPM
12 pF
34
P3_3
PKT
CCLK
XTALI
XTALO
Fundamental mode, parallel resonant 12.000 MHz
Frequency tolerance of +/- 40 ppm. This tolerance
must be calculated by using the RSS (Root Square
Sum) approach involving the following four types of
errors represented in ppm:

Base, or initial error, measured at room
temperature (Ippm)

Drift due to temperature changes within the
o
o
operating temperature range of 0 C to 70 C
(Tppm)

Drift attributed to aging (Appm)
Uncertainty caused by load capacitance error
(Lppm)
Apply the following formula to calculate the total frequency
tolerance using RSS approach:
Equation 1


10 PPM
HCLK
C r ys t a l P a r t S e l e c t i o n C r i t e r i a
The crystal used on a PRoC-CS-based design must meet
the following criteria:


TXC Corp
Figure 8. Crystal Circuit
VIN
VDD
35
7B-12.000MEEQ-T
25
36
VOUT
P3_1
37
26
38
P1_1
27
39
GND
CLK
40
VDD
MOSI
2.2k
PROC CS
XTALO
28
41
C7
15pF
XTALI
MISO
42
43
NC
29
R25
TEST1
P1_7
44
P1_0
30
R24
680k
Stability
Calculating Load Capacitance Values
Load capacitors play a critical role in providing accurate
clock source to PRoC-CS, which is very important for
PRoC-CS to generate accurate RF signals. These
capacitors must be chosen carefully based on the load
capacitance value of the crystal. The following section
explains the procedure to choose the correct load
capacitor values.
P1_2
RST_N
Y1
Load
Cap.
Manufacturer
P1_4
31
45
46
VDD
32
47
Quartz xtal 12MHz
48
C8
15pF
P1_6
P1_5
49
VDD
XRES
50
33
51
Table 3. Reference Crystal Parts
MPN
Figure 7. Clock Circuit Design
U5
R e f e r e n c e C r ys t a l P a r t s
The recommended list of crystals is:
Figure 8 illustrates the crystal circuit. To provide the most
accurate clock source, crystal manufacturers specify the
optimum load capacitance value that must be supported
on the circuit. The two capacitors (C1 and C2) determine
the load capacitance, and the net load capacitance is
calculated using the following equation:
Equation 2
Cs is the stray capacitance of the printed circuit board
whose typical value is 2.5 pF. Hence, values of C1 and C2
must be chosen in such a way that they match the
crystal’s specification. For a crystal with 10-pF load
capacitance, the load capacitance value will be 15 pF for
both C1 and C2.
Maximum ESR value of 80 ohm
10-pF load capacitance is preferred
www.cypress.com
Document No. 001-86272 Rev. **
6
PRoC™-CS Hardware Design Guidelines
Figure 10. MCU and RF Connectivity
HCLK
MCU and RF Connectivity
The in-built MCU and WUSB-NL blocks must be
connected over SPI externally. All PRoC-CS-based
hardware designs must implement this connectivity
externally, by following these steps:




Connect MOSI to P1.1

Connect RESET_n to a GPIO with a pull-up resistor.
The WUSB-NL block must be reset using this GPIO
Connect MISO to P1.5
Connect CLK to P1.3
SPI_SS can be connected to any GPIO (preferably
P1.7)
P3_7
P3_5
SPI_SS
22
23
P3_3
PKT
SPI_ss
24
25
P3_1
26
27
28
SPI_clk
RESET_n
29
SPI_mosi
CLK
MOSI
MISO
30
34
PRoC-CS has an in-built WUSB-NL RF transceiver that
can provide up to 1-Mbps data throughput. PRoC-CS
supports differential RF input/out using ANT and ANTb
pins. These pins must be connected to a two-element
matching network to provide 50-ohm impedance matching
for PRoC-CS.
P1_7
CCLK
VDD
35
VIN
SPI_miso
36
PRoC CS
P1_3
RST_N
37
VOUT
31
38
SPI_ss
SPI_clk
P1_5
Figure 9. PRoC-CS RF Design Overview
P1_1
32
39
RESET_n
SPI_mosi 40
33
2 . 4 - G H z R F D e s i g n O ve r vi e w
SPI_miso
2.4-GHz RF
+Vin
R41 10K
TP12
TP16
TP18
TP14
TP15
Matching Circuit Design
A shunt capacitor (0.5 pF) and a series inductor (2.2 nH)
form the matching network and they match the impedance
between PRoC-CS and the antenna. The values shown
below must not be modified. When you select these
components, choose parts that have low loss at RF. The
chosen parts should exhibit a minimum Q of approximately
20 or better, at 2.4 GHz. The reference part numbers for
the matching network are:
Table 4, Matching Network Passives
See Figure 10 to understand the connectivity between the
MCU and WUSB-NL blocks. Make sure to add test points
on the previously mentioned signal lines to enable
debugging during firmware development.
www.cypress.com
Type
MPN
Manufacturer
0.5-pF Capacitor
500R14N0R5CV4T
Johanson Dielectric
2.2-nH Inductor
MLG1608B2N2S
TDK
The differential antenna input/output (ANTb) pin should
have a resistance to ground of 51 Ω ± 20%, to match its
50-Ω impedance. In addition, the ANT pin requires a DC
path to ground. A resistor of 20 kΩ ± 20% to ground must
be placed on the antenna-side end of the matching
network, as shown in Figure 11.
Document No. 001-86272 Rev. **
7
PRoC™-CS Hardware Design Guidelines
Figure 11. Matching Network Design
R11
51
C10
R40
0.5pF
20K
L1
2.2nH
1
2
3
4
J3
1
2
3
4
50 Ohm
2.4 GHz
Antenna
Antenna
The sensor capacitance measured by PRoC-CS is called
Cx. When a finger is not on the sensor, Cx is equal to the
parasitic capacitance of the system (Cp). When a finger is
placed, Cx increases to Cp+Cf, where Cf is the finger
capacitance. This increase in capacitance is used to
detect TOUCH or NO TOUCH state for the sensor.
CapSense Buttons and Sliders
69
EPAD
68
P0_2
66
67
P0_0
P2_6
65
P2_4
64
P2_2
62
63
P2_0
VDD7
61
P4_2
60
ANT
59
P4_0
58
P3_6
57
ANT_B
P3_4
56
Figure 14. CapSense Buttons
PROC-CS
CapSense Buttons and Sliders
Construction of CapSense Sensor
You can use a CapSense button to implement the
functionality of a mechanical button. It is realized by
connecting a copper sensor pad to a PRoC-CS controller’s
GPIO using a trace and by attaching a non conductive
overlay material on top of the cooper sensor pad.
Figure 12. Construction of a CapSense Sensor
Figure 15. CapSense Slider
PRoC-CS
CapSense technology works by measuring the change in
the capacitance due to finger presence on each I/O pin
that is designated as a sensor. A sensor is implemented
using copper pads etched on the surface of the PCB and
by connecting it to a GPIO of the PRoC-CS controller. A
non conductive overlay serves as the touch surface for the
button.
Figure 13. CapSense Equivalent Model
A CapSense slider can be used for controls that require
gradual adjustments, for example, a lighting control
(dimmer), volume control, graphic equalizer, and speed
control. A slider is built using an array of capacitive
sensors called segments that are placed adjacent to one
another.
For more information, refer to the CapSense-related
documents listed in the Reference Documents section on
page 21.
www.cypress.com
Document No. 001-86272 Rev. **
8
PRoC™-CS Hardware Design Guidelines
40-QFN
13
7
6
68-QFN
35
9
26
P2_3
P2_1
P4_1
P3_7
SPI_SS
16
17
B1
Button1
1
Button2
1
R45 560R
Button3
CapSense Button 9mm Round
B3
1 Sensor
Shield
R46 560R
Button4
R47 560R
Button5
R48 560R
Sensor
Shield
CapSense Button 9mm Round
P2_5
18
GPIOs available
for CapSense
19
Reserved
GPIOs
P2_7
20
Total
GPIOs
OCDOE
21
PRoC-CS
Variant
Figure 16. CapSense Button Design
22
Table 5. Available GPIOs for CapSense Features
Figure 16 illustrates a design of five CapSense buttons
using PRoC-CS.
23
CapSense Button & Slider Design
The available number of GPIOs determines the number of
CapSense buttons and sliders which can be implemented
on a hardware design. Table 5 lists the total number of
GPIOs available on the 40-QFN and 68-QFN variants of
PRoC-CS.
R44 560R
B2
Sensor
Shield
CapSense Button 9mm Round
1
B4
Sensor
Shield
CapSense Button 9mm Round
The following tables provide more details about the
reserved GPIOs and their usage:
1
B5
Sensor
Shield
CSSH2
CapSense Button 9mm Round
Table 6. Reserved GPIOs of 40-QFN PRoC-CS Variant
1
HATCHED GND
#
GPIO
Purpose
1
P1[0]
Programming Interface (ISSP SDATA)
2
P1[1]
Programming Interface (ISSP SCLK ) and
SPI MOSI for WUSB-NL block
3
P1[3]
SPI CLCK for WUSB-NL block
4
P1[5]
SPI MISO for WUSB-NL block
5
P1[7]
SPI SS for WUSB-NL block
6
P0[4]
RESET for WUSB-NL block
7
P0[1]/ P0[3]
To connect CMOD CAP
Note that each CapSense button must be allocated a
dedicated GPIO pin.
Table 7. Reserved GPIOs of 68-QFN PRoC-CS Variant
#
GPIO
Purpose
1
P1[0]
Programming Interface (ISSP SDATA)
2
P1[1]
Programming Interface (ISSP SCLK ) and
SPI MOSI for WUSB-NL block
3
P1[3]
SPI CLCK for WUSB-NL block
4
P1[5]
SPI MISO for WUSB-NL block
5
P0[1]/P0[3]
To connect CMOD CAP
6
P4[0]
RESET for WUSB-NL block
7
P4[2]
SPI SS for WUSB-NL block
8
P3[6]
For non-CapSense usage
9
P3[4]
For non-CapSense usage
www.cypress.com
Document No. 001-86272 Rev. **
9
PRoC™-CS Hardware Design Guidelines
CapSense Slider Design
Figure 17 illustrates a design of a slider made up of eight sensors.
Figure 17. CapSense Slider Design
VDD
P0_4
P0_6
VIN
VDD
OCDO
OCDE
P0_7
P0_5
P0_3
FIFO
P0_1
VIN
OCDOE
CSS1
5
R51
1
560R
6
2
7
SLD8
SLD7
3
SLD6
4
SLD5
5
SLD4
6
SLD3
7
SLD2
8
8
9
10
R50
560R
11
R49
560R
12
CMOD
13
TP11
C3
2.2nF
14
SLD1
9
10
15
16
17
R48
CapSense Linear Slider 8 Seg
BRING SHIELD
AROUND SLIDER
ELEMENTS.
560R
P2_5
P2_3
P2_1
P4_1
P3_7
4
18
19
20
21
22
23
SPI_SS
P2_7
3
R44
560R
R45
560R
R46
560R
R47
560R
Note that the minimum number of sensors needed to
create a slider is five, with each sensor requiring a GPIO.

On a slider when any segment is scanned, the
adjacent segments are grounded. To maintain
uniformity, the two segments on both ends of a slider
should also be grounded. Therefore, for a design with
a slider of ‘n’ segments, there must be n+2 segments.

In a typical application, a slider with five segments can
resolve at least 100 physical finger positions on the
slider which can meet the requirement of most
applications. Add more slider segments if higher
number of finger positions need to be resolved.
Consider the following important points while designing
buttons and sliders:

Use series resistor 560 ohms for all I/Os used as
sensors.

Connect an integration capacitor, called as ‘CMOD’ of
value 2.2 nF, to implement CapSense functionality. It
must be connected to either pin P0.3 or P0.1.

Do not use GPIO P1.0 or P1.1 as CapSense sensors
because they must be reserved for Programming
(ISSP) and Debug (I2C) interfaces.

Do not use the two pins adjacent to ANT and the two
pins adjacent to ANTb on the 68-QFN package for
CapSense buttons and sliders.
www.cypress.com
For more information about advanced topics, such as
radial sliders, proximity sensors, and matrix buttons, refer
to the CapSense-related documents listed in the
Reference Documents section on page 21.
Document No. 001-86272 Rev. **
10
PRoC™-CS Hardware Design Guidelines
Peripherals
I n t e g r a t i n g P e r i p h e r a l s O ve r G P I O
PRoC-CS GPIO lines can be used to interface with LEDs, mechanical buttons, and peripherals, such as a mouse optical
sensor. Figure 18 shows how to use these GPIOs to connect an optical sensor.
Figure 18. Interfacing Mouse Optical Sensor Over GPIO
VCC
2
J6 for sensor current measurement.
1
J6
2.54mm
U6
R20
36K 1%
P3_3
1
2
P3_4
3
P3_5
4
RST/QB/PD
C15
1uF
VDDA
MOTSWK
VDD
SDIO
VSS
SCLK
LED
8
7
6
C16
C17
10uF
0.1uF
5
D7
LED
R28 22R
PAW3204UL
Caps for pins7, 8 must have trace length of less than 5mm from the sensor
When you connect LEDs, use the negative terminal of the LED to GPIO, and the positive terminal to VCC, given that the sink
current for ProC-UI is more than the source current.
www.cypress.com
Document No. 001-86272 Rev. **
11
PRoC™-CS Hardware Design Guidelines
I n t e g r a t i n g P e r i p h e r a l s O ve r S P I
41
SPI_mosi
NC
39
SPI_clk
C20
3.3uF/16V
C21
100nF
C19
100nF
40
38
37
C14
3.3uF/16V
36
P2_6
P2_4
64
63
P2_2
VDD
P2_0
62
61
60
ANT
P4_2
59
58
P4_0
ANTB
P3_6
57
56
55
P3_4
54
P3_2
53
P1_1
VOUT
P1_3
VIN
HCLK
CCLK
SPI_miso
34
VDD
35
GND
P4_1
O_MOTION
10
21
SPI_mosi
7
66
O_NCS
6
VDD
P3_7
MOSI
MOTION
PRoC CS
XTALO
SPI_SS
42
22
SCLK
XTALI
23
43
P3_5
SPI_clk
24
5
NC
P3_3
SPI_miso
44
MISO
VDD3
4
TEST1
PKT
GND
O_NCS
25
9
REFB
3
26
11
REFA
45
NCS
P3_1
12
DGND
LASER_NEN
CLK
VCC
VDDIO
P1_0
27
13
XY LASER
46
2
P1_2
28
14
47
VCSEL-VE
MOSI
15
VCSEL+VE
P1_4
29
8
48
MISO
16
U4
P1_7
1
30
C4
470pF
VDD
31
ADNS7350
P1_6
RST_N
49
P1_5
50
32
51
NTA4151P
Q1
VDD
C13
0.10uF
33
10nF
XRES
C5
P3_0
U5
52
C24
100nF
65
VCC
VCC
C23
3.3uF/16V
O_MOTION
Figure 19. Interfacing Mouse Optical Sensor Over SPI
You can connect SPI-based peripherals to PRoC-CS in multi-slave mode. The previous figures show adding an SPI-based
Mouse Optical Sensor over an SPI interface to PRoC-CS. This forms a two-slave SPI network, because the in-built WUSB-NL
also acts as another SPI slave.
Programming (ISSP) and Debugging (I2C)
Figure 20. Programming and Debugging Interface
VCC
1
2
3
RESET
SPI_mosi 4
5
P10
1
2
3
4
5
J2
XRES
SCLK
SDATA
I2C_SCL
SPI_mosi
I2C_SDA
P10
5 PIN 2.54mm Pitch HDR
ISSP interface is used to download firmware onto the flash of PRoC-CS. I2C interface is used to debug and fine tune sensor
capacitance. ISSP and I2C share common lines, as shown in Figure 20.
www.cypress.com
Document No. 001-86272 Rev. **
12
PRoC™-CS Hardware Design Guidelines
Layout Design
PRoC-CS Device Package Dimensions
The following sections list the layout guidelines for
creating PRoC-CS based hardware designs:
The 40-pin and 68-pin variants are packaged in a QFN
(Quad Flat No-leads) package. The following table lists the
package size and recommended pad size for both
variants:
Layer Stack up
PRoC-CS-based hardware can be designed on a twolayer or on a four-layer PCB design. Out of these two, a
four-layer design enables compact design, while meeting
the layout guidelines. Hence, a four-layer design approach
is preferred. If you use a two-layer design, ensure that all
the layout guidelines are met.
Figure 21 and Figure 22 illustrate the layer stack up for
two- and four-layer designs.
Figure 21. Two-Layer Stack Up
Table 8. PRoC-CS Package Details
40-QFN
68-QFN
Package Size
6 mm x 6 mm
8 mm x 8 mm
Recommended
Pad Size
0.25 mm
0.2 mm
Power Supply
Power Supply Design

Decoupling capacitors must be placed as close as
possible to PRoC-CS.

Do not gang the decoupling capacitors. Instead,
connect them individually to the corresponding power
terminals.
Clock
Clock Circuit Design
Figure 22. Four-Layer Stack up

Do not route any trace beneath the crystal pads. The
layer beneath the crystal pads must have solid
ground.

Place the crystal as close as possible to PRoC-CS.
Figure 23. Crystal Layout Design
FR4-based PCB designs perform well with board
thicknesses ranging from 0.020 inches (0.5 mm) to
0.063 inches (1.6 mm).
Refer to the section CapSense Layout Guidelines: Quick
on page 19 for the complete list of recommended values
for various layout parameters.
www.cypress.com
Document No. 001-86272 Rev. **
13
PRoC™-CS Hardware Design Guidelines
Figure 25. Ground Below E-pad and Antenna Feed Line
2.4 GHz RF Design

PRoC-CS supports different types of antenna designs.
Refer to the section Antenna Recommendations on
page 17 for the list of antenna designs. This
application note also provides the dimension details of
PIFA Antenna Dimension. Pick an antenna design
that suits your application. The guidelines provided in
this document are based on PIFA antenna, and these
guidelines are applicable for other antenna types too.

Place the Antenna Matching Network Passives as
shown in Figure 24.
Figure 24. Antenna Matching Network

Use vias to implement ground stitching between the
top and bottom layers.

Maximize ground in complete design. Note that
hatched ground must be used in areas where
CapSense buttons and sliders are located. The rest of
the area can use solid ground.

The layer beneath the PRoC-CS e-pad must be solid
ground, and it must be extended until the antenna
feed line, as shown in Figure 25. Note that the ground
regions are marked in blue.

The top layer on which PRoC-CS is mounted must
have solid ground pad which aligns with the PRoC-CS
e-pad, and this pad must be soldered to e-pad. In
addition, this ground pad on the top layer must be
connected to the ground pad located in the layer
beneath using thermal vias.

Neighboring I/Os near ANTb and ANT must not be
routed in parallel to ANT and ANTb lines

All grounds on the hardware must be connected
together.

The antenna must be isolated from other layers and
no signal traces or ground must be added in any of
the layers, as shown in Figure 26.
Figure 26. Isolation of Antenna

www.cypress.com
During PCB manufacturing, do not place metal
content such as PCB vendor logo, Pb-free symbol, or
manufacturing lot number under the antenna, because
any metal under the antenna can affect the RF radio
range. You must ensure that this is mentioned
explicitly in the fabrication notes of layout design files.
Document No. 001-86272 Rev. **
14
PRoC™-CS Hardware Design Guidelines
Figure 29. Recommended Button Shapes
CapSense Button Design
The recommended shape for sensing a finger press is a
solid round pattern as shown in Figure 27.
Figure 27. CapSense Button Shape
CapSense Slider Design
The diameter of the button can range from 5 mm to
15 mm, with 10 mm being suitable for the majority of
applications. A larger diameter helps with thicker overlays.
The annular gap size must be equal to the overlay
thickness, but no smaller than 0.5 mm, and no larger than
2 mm. For example, a PCB layout for a system with a
1-mm overlay must have a 1-mm annular gap, while a
3-mm overlay design must have a 2-mm annular gap. The
spacing between the two adjacent buttons should be large
enough that if one button is pressed, a finger should not
reach the annular gap of the other button.
Ground fill is added to both the top and bottom of the
sensing board on both two-layer and four-layer designs.
Typical hatching for the ground fill is 25 percent on the top
layer (7 mil line, 45 mil spacing) and 17 percent on the
bottom layer (7 mil line, 70 mil spacing). Ground on each
layer should be connected to each other with as many vias
as possible.
Figure 28. Ground fill for Touch Sensor
The layout for a slider involves placing a group of sensors
in a saw tooth pattern (double chevron), as shown in
Figure 30.
Figure 30. Slider Layout
The key attributes in designing a slider are:



Width of the Segment (A)
Clearance between Segments (B)
Height of the segment (C)
Table 9 lists the minimum, maximum, and recommended
values for these attributes.
Table 9. Slider Layout Details
Attribute
A square or rectangular button with a curved edge works if
the layout does not support a round shape. Buttons should
not be triangular or include other pointed features with
angles less than 90 degrees.
www.cypress.com
Min
Value
Max
value
Recommendation
Width of the
Segment (A)
1.5 mm
4 mm
Equal to overlay
thickness, but within
the min/max limits.
Clearance
between
segments (B)
0.5 mm
2 mm
Equal to overlay
thickness, but within
the min/max limits
Height of the
segment ( C )
7 mm
15 mm
12 mm
Document No. 001-86272 Rev. **
15
PRoC™-CS Hardware Design Guidelines
CapSense Sensor Placement and Vias
Trace Length, Width, and Routing

Minimize the trace length from PRoC-CS pins to the
sensor pad to optimize signal strength.


Mount series resistors within 10 mm of PRoC-CS pins
to reduce RF interference and provide ESD
protection.
Minimize the parasitic capacitance of the traces and
sensor pad. Trace capacitance is minimized when
they are short and narrow.

The maximum recommended trace length is 12 inches
(300 mm).

Isolate switching signals, such as PWM, I2C
communication lines, and LEDs, from the sensor and
the sensor PCB traces. Do this by placing them at
least 4 mm apart and fill a hatched ground between
CapSense traces and non CapSense traces to avoid
crosstalk.

Trace width must not be greater than 7 mil (0.18 mm).
CapSense traces must be surrounded by hatched
ground with trace-to-ground clearance of 10 mil to
20 mil (0.25 mm to 0.51 mm).

Route sensor traces on the bottom layer of the PCB,
so that the only user interaction with the CapSense
sensors is with the active sensing area. Do not route
traces directly under any sensor pad, unless the trace
is connected to that sensor.

Do not run capacitive sensing traces in close proximity
to communication lines, such as I2C or SPI masters. If
it is necessary to cross communication lines with
sensor pins, make sure the intersection is at right
angles.

Avoid connectors between the sensor and PRoC-CS
pins, because connectors increase parasitic
capacitance and decrease noise immunity.

Use the minimum number of vias to route CapSense
inputs to minimize parasitic capacitance. The vias
must be placed to minimize the trace length, which is
usually on the edge of the sensor pad, instead of
placing it at the center of the sensor pad.
For more information, refer to the CapSense design
guides listed in the section Reference Documents on page
21.
www.cypress.com
Document No. 001-86272 Rev. **
16
PRoC™-CS Hardware Design Guidelines
Antenna Recommendations
The antenna is usually the biggest factor in achieving a successful RF performance. A rigorous antenna tutorial is beyond the
scope of this application note, but some simple antenna recommendations that you can easily apply to PRoC-CS-based
applications are introduced.
You can use virtually any type of good quality 50-ohm, 2.4-GHz antenna with the PRoC-CS. Table 10 lists several available
choices.
Table 10. Antenna Choices
Antenna type
Picture or Drawing
DC Grounded?
Wiggle antenna
Yes
Description/Notes
Described in the Cypress application note AN48610 Design and Layout Guidelines for Matching Network
and Antenna for WirelessUSB™ LP Family.
Cost: Almost free of cost when added to the existing
PCB.
Custom
printed-trace
antenna
This is a specialized antenna,
customized to each application.
Chip antenna
Depends on
the design
No
Cost: Almost free of cost when added to the existing
PCB.
Easy to use.
You must read the datasheet and follow all the
manufacturer instructions. Manufacturer’s
specifications for mounting and layout must be exactly
followed.
Model 2450AT18B100E,
Johanson Technology Inc.
Cost: Can be expensive.
PIFA
Yes
The Printed Inverted-F Antenna (PIFA).
Cost: Almost free of cost when added to the existing
PCB.
1/2 wave end-fed
dipole
No
Delivers ‘textbook’ 0 dBd performance.
Easy removal and replacement.
Accommodates EMC compliance and end applications.
Requires RF connect on the board.
Cost: Relatively expensive.
Illustrated: Model W1010, by Pulse.
www.cypress.com
Document No. 001-86272 Rev. **
17
PRoC™-CS Hardware Design Guidelines
PIFA Antenna Dimension
Figure 31 shows a detailed dimension of PIFA antenna for use in PRoC-CS designs.
Figure 31. PIFA Antenna Dimensions
www.cypress.com
Document No. 001-86272 Rev. **
18
PRoC™-CS Hardware Design Guidelines
CapSense Layout Guidelines: Quick Reference
Table 11. CapSense Button and Slider Layout Guidelines
Sl.
Category
Min
Max
Recommendations/Remarks
1
Button Shape
2
Button Size
5 mm
3
Button-Button spacing
1 mm
4
Button Ground Clearance
0.5 mm
5
Ground Flood – Top Layer
Hatched ground 7 mil trace and 45 mil grid
6
Ground Flood – Bottom Layer
Hatched ground 7 mill trace and 70 mil grid
7
Slider Segment Pattern
8
No of Slider Segments
5
9
Slider Segment Size
2 mm
5 mm
2 mm
10
Slider Segment Spacing
0.5 mm
2 mm
Slider Segment Spacing = Overlay thickness
11
Trace length from Sensor to
PRoC-CS (Buttons)
300 mm
< 100 mm. Trace length should be as minimum as possible. For long trace,
length design requires large sensing pads and a thin overlay to maximize
the signal from the sensor.
12
Trace length from Sensor to
PRoC-CS (Slider)
230 mm
< 100 mm
13
Trace Width
0.20 mm
0.17 mm (7 mil)
14
Trace Routing
Traces should be routed on the non sensor side. If any non CapSense trace
crosses CapSense trace, ensure that intersection is orthogonal.
15
Via position for the sensors
Via should be placed near the edge of the button/slider to reduce trace
length, thereby increasing sensitivity.
16
Via Hole Size for sensor traces
10 mil
17
No. of via on sensor trace
18
CapSense and LED resistor
placement
19
Distance between any
CapSense trace to Ground
flood
20
PRoC-CS placement
PRoC-CS can be placed on top or bottom layer, depending on the board
size. Minimize the distance between PRoC-CS and the sensors. Antenna
and PRoC-CS must be placed on the same layer.
21
Placement of components in 2
layer PCB
Top Layer – Sensor Pads, PRoC-CS and antenna. Bottom Layer – other
components and traces.
22
Placement of components in 4
layer PCB
Top layer – Sensor Pads
Layer 2 – Traces
Layer 3 – Ground
Bottom layer – PRoC-CS, Antenna and other components
23
Overlay Thickness – Buttons
0 mm
5 mm
2 mm
24
Overlay Thickness – Slider
0 mm
2 mm
1 mm
25
Overlay Material
Needs to be non-conductive material. Glass, ABS plastic, Formica.
26
Overlay Adhesives
Adhesive should be non conductive and dielectrically homogenous. Use
467MP and 468MP adhesives made by 3M.
27
Board Thickness
www.cypress.com
Solid round pattern or rectangle with curved edges.
15 mm
10 mm
8 mm (adjacent buttons to be ground if spacing is less)
4 mm
Button ground clearance = Overlay Thickness
Saw Tooth pattern
0.17 mm
1
Max – depends on available I/O pins of PRoC-CS
2
1
Place CapSense and LED resistors close to PRoC-CS for noise
suppression. CapSense resistors have highest priority. Place them first.
10 mil
0.5 mm
20 mil
1.6mm
20 mil
Standard Board Thickness for PRoC-CS FR4 based designs is 1.6 mm.
Document No. 001-86272 Rev. **
19
PRoC™-CS Hardware Design Guidelines
Schematics and Layout Review Checklist
Table 12 lists all the important guidelines as a checklist. Assign an answer to each checklist item to find out the extent to which
your hardware design meets these guidelines.
Table 12. Schematics and Layout Review Checklist
Sl.
Checklist Item
1
Are correct Load Cap values used based on the load capacitance value of the crystal?
2
Are all seven VDD pins connected to VOUT?
3
Is connectivity between MCU and WUSB-NL blocks established over SPI?
4
Are test points added on the SPI lines connecting MCU and WUSB-NL blocks?
5
Are all the sensors attached with a 560-ohm series resistor?
6
Is the value of the CMOD capacitor used 2.2 nF?
7
For sliders, are two additional segments added on both ends of the slider and connected to ground?
8
Are ISSP SDATA and ISSP SCLK connected to P1[0] and P1[1] respectively?
9
Does the power supply design ensure that battery leakage does not occur under low battery condition?
10
Is the Antenna laid out exactly according to the dimension?
11
Is it ensured that there is no ground/trace running below the PIFA antenna?
12
Is adequate solid ground added below the ANT, ANTb pins, and antenna feed line?
13
Are de-coupling capacitors placed close to power pins?
14
Is it ensured that the adjacent pins of ANT and ANTb are not used for CapSense buttons or sliders (applicable
only in 68-QFN package)?
15
Is it ensured that GPIO P1.0 or P1.1 is not used for CapSense sensors?
16
Is solid ground added below the crystal pads?
17
Is hatched ground added around CapSense buttons and sliders?
18
Is hatched ground added below CapSense buttons and sliders?
19
Are all the grounds connected together?
20
Are CapSense buttons and sliders laid out according to the section CapSense Layout Guidelines: Quick
Reference on page 16?
21
Are the mounting pads laid out according to spec (0.25 mm for 40-QFN package and 0.2 mm for 68-QFN
package)?
22
Are the ground on each layer interconnected using as many vias as possible?
23
Are series resistors placed within 10 mm of PRoC-CS pins?
www.cypress.com
Document No. 001-86272 Rev. **
Answer
(Yes / No/ NA)
20
PRoC™-CS Hardware Design Guidelines
Reference Documents
For more information, refer to the following documentation available at www.cypress.com:






Getting Started with CapSense
CapSense Design Guide
AN72428 - Schematic Review Checklist for WirelessUSB™ NL
AN64285 - WirelessUSB™ NL Low Power Radio Recommended Usage and PCB Layout
AN48610 - Design and Layout Guidelines for Matching Network and Antenna for WirelessUSB™ LP Family
PRoC-CS Datasheet
Development Kit

®
CY8CKIT-002 PSoC MiniProg3 Program and Debug Kit
www.cypress.com
Document No. 001-86272 Rev. **
21
PRoC™-CS Hardware Design Guidelines
Document History
Document Title: PRoC™-CS Hardware Design Guidelines
Document Number: 001-86272
Revision
ECN
Orig. of
Change
Submission
Date
**
3958542
SELV
04/08/2013
www.cypress.com
Description of Change
New Spec.
Document No. 001-86272 Rev. **
22
PRoC™-CS Hardware Design Guidelines
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find
the office closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
cypress.com/go/automotive
psoc.cypress.com/solutions
Clocks & Buffers
cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 5LP
Interface
cypress.com/go/interface
Lighting & Power Control
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
cypress.com/go/usb
Wireless/RF
cypress.com/go/wireless
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
PSoC and CapSense are registered trademarks and PRoC is a trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are the property of their respective owners.
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone
Fax
Website
: 408-943-2600
: 408-943-4730
: www.cypress.com
© Cypress Semiconductor Corporation, 2013. The information contained herein is subject to change without notice. Cypress Semiconductor
Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any
license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or
safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The
inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies
Cypress against all charges.
This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide
patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a
personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative
works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source
Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the
right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or
use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a
malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
www.cypress.com
Document No. 001-86272 Rev. **
23