MPC5500 Family Detailed MPC5500 Family Memory Map MPC5533 MPC5534 MPC5553 MPC5554 MPC5561 MPC5565 MPC5566 MPC5567 MPC557x √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ MPC5500 Family Address Rangea Allocated Size Used Size Use 0x0000_0000–0x000B_FFFF 768 Kb 768 Kb Flash Array 0x000C_0000–0x000F_FFFF 256 Kb 256 Kb Flash Array 0x0010_0000–0x0017_FFFF 512 Kb 512 Kb Flash Array 0x0018_0000–0x001F_FFFF 512 Kb 512 Kb Flash Array 0x0020_0000–0x002F_FFFF 1 Mb 1 Mb Flash Array 0x0030_0000–0x00FF_FBFF ~13 Mb N/A Reserved 0x00FF_FC00–0x00FF_FFFF 1024 bytes 1024 bytes Flash Shadow Block √ √ √ √ √ √ √ √ MPC500 Family 0x0100_0000–0x1FFF_FFFF 496 Mb 2 Mb Emulation Mapping of Flash Array √ √ √ √ √ √ √ √ MPC555 0x2000_0000–0x3FFF_FFFF 512 Mb N/A External Memory √ √ √ √ √ √ √ √ 0x4000_0000–0x4000_7FFF 32 Kb 32 Kb SRAM Array, Standby Powered √ √ √ √ √ √ √ √ MPC5566 Performance/Integration √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ SRAM Array √ √ 64 Kb SRAM Array √ (<1.5 Gb) N/A Reserved 0xA000_0000–0xAFFF_FFFF 256 Mb 256 Mb Parallel Digital Interface 0xA000_0000–0xBFFF_FFFF 256 Mb 256 Mb Reserved 16 Kb 16 Kb SRAM Array 0x4000_C000–0x4000_FFFF 16 Kb 16 Kb SRAM Array 0x4001_0000–0x4001_3FFF 16 Kb 16 Kb SRAM Array 0x4001_4000–0x4001_FFFF 48 Kb 48 Kb 0x4002_0000–0x4002_FFFF 64 Kb 0x4003_0000–0x9FFF_FFFF MPC5561 MPC5534 MPC5533 MPC565 √ MPC561 1999 • • • • • • • e200z Core 1.5V Regulator Control √ Signal Processing Engine 64-bit General Purpose Registers Core Timers Unit (FIT, TB, DEC) Integer Execution Unit Special Purpose Registers Exception Handler Multiply Unit Instruction Unit Variable Length Encoded Instruction JTAG Branch Prediction Unit Unified 8-32 Kb Cache Nexus Load/Store Unit Memory Management Unit FMPLL √ √ √ FMPLL √ √ √ √ √ √ √ √ External Bus Interface (EBI) Configuration √ √ √ √ √ √ √ √ 28 Flash Configuration 0xC3F8_C000–0xC3F8_FFFF 16 Kb N/A Reserved 0xC3F9_0000–0xC3F9_3FFF 16 Kb 2.5 Kb System Integration Unit (SIU) 0xC3F9_4000–0xC3F9_FFFF 48 Kb N/A Reserved 0xC3FA_0000–0xC3FA_3FFF 16 Kb 1056 Modular Timer System (eMIOS) 0xC3FA_4000–0xC3FA_7FFF 16 Kb 1056 Modular Timer System (eMIOS_B)c 0xC3FA_8000–0xC3FB_FFFF 96 Kb N/A Reserved 0xC3FC_0000–0xC3FC_3FFF 16 Kb 3 Kb Enhanced Time Processing Unit (eTPU) Registers 0xC3FC_4000–0xC3FC_7FFF 16 Kb N/A Reserved 0xC3FC_8000–0xC3FC_09FF 16 Kb 2.5 Kb eTPU Shared Data Memory (Parameter RAM) 0xC3FC_8A00–0xC3FC_8BFF √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ Master √ √ √ √ √ √ √ √ √ √ √ √ √ eTPU (32 Ch) √ 3 Kb eTPU Shared Data Memory (Parameter RAM) mirror √ √ √ √ √ √ √ 0xC3FD_0000–0xC3FD_2FFF 20 Kb 12 Kb eTPU Shared Code RAM (12K,16K, or 20K) √ √ √ √ √ √ √ 0xC3FD_3000–0xC3FD_3FFF 4 Kb 0xC3FD_4000–0xC3FD_4FFF 4 Kb 140 Kb N/A Reserved 0xC3FF_8000–0xC3FF_BFFF 16 Kb N/A Reserved 0xC3FF_C000–0xC3FF_FFFF 16 Kb N/A Reserved 0xC400_0000–0xDFFF_FFFF (448 Mb) N/A Reserved √ √ Bridge B Peripherals 0xE000_0000–0xFBFF_FFFF (448 Mb) N/A Reserved 0xFC00_0000–0xFFEF_FFFF 63 Mb N/A Reserved 16 Kb 16 Kb N/A N/A 2 3 4 5 6 7 8 9 10 11 12 13 14 15 AN37 AN11 VDDA1 AN16 AN1 AN5 VRH AN23 AN27 AN28 AN35 VSSA0 AN15 ETRIG ETPUB ETPUB ETPUB ETPUB 1 18 20 24 27 B VDD VSS AN36 AN39 AN19 AN20 AN0 AN4 REF BYPC AN22 AN26 AN31 AN32 VSSA0 AN14 ETRIG ETPUB ETPUB ETPUB ETPUB MDO10 MDO7 0 21 25 28 31 VDD VSS AN8 AN17 VSSA1 AN21 AN3 AN7 VRL AN25 AN30 AN33 VDDA0 AN13 ETPUB ETPUB ETPUB ETPUB MDO9 19 22 26 30 MDO6 AN29 AN34 VDDEH AN12 9 ETPUB ETPUB ETPUB ETPUB MDO5 16 17 23 29 MDO2 VDDEH 8 √ √ Crossbar (XBAR) √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ 0xFFF4_4000–0xFFF4_7FFF 16 Kb N/A DMA Controller 2 (eDMA) √ √ √ √ √ √ √ √ 0xFFF4_8000–0xFFF4_BFFF 16 Kb N/A Interrupt Controller (INTC) √ √ √ √ √ √ √ √ 192 Kb N/A Reserved 0xFFF8_0000–0xFFF8_3FFF 16 Kb 164 Enhanced Queued Analog-to-Digital Converter (eQADC) 0xFFF8_4000–0xFFF8_7FFF 16 Kb 164 Enhanced Queued Analog-to-Digital Converter (eQADC_B)c VDD 16 Kb N/A Reserved 0xFFF8_C000–0xFFF8_FFFF 16 Kb N/A Reserved 0xFFF9_0000–0xFFF9_3FFF 16 Kb 200 Deserial Serial Peripheral Interface (DSPI_A) 200 √ √ √ √ √ √ √ 0xFFF9_8000–0xFFF9_BFFF 16 Kb 200 Deserial Serial Peripheral Interface (DSPI_C) √ √ √ √ 0xFFF9_C000–0xFFF9_FFFF 16 Kb 200 Deserial Serial Peripheral Interface (DSPI_D) √ √ √ √ c 16 Kb 200 Deserial Serial Peripheral Interface (DSPI_E) 0xFFFA_4000–0xFFFA_7FFF 16 Kb 200 Deserial Serial Peripheral Interface (DSPI_F)c 0xFFFA_8000–0xFFFA_FFFF 32 Kb N/A Reserved 16 Kb 44 Serial Communications Interface (SCI_A) 0xFFFB_4000–0xFFFB_7FFF 16 Kb 44 Serial Communications Interface (SCI_B) 0xFFFB_8000–0xFFFB_BFFF 16 Kb 44 Serial Communications Interface (SCI_C) 16 Kb 44 1152 Controller Area Network (FlexCAN_A) 16 Kb 1152 Controller Area Network (FlexCAN_B) 0xFFFC_8000–0xFFFC_BFFF 16 Kb 1152 Controller Area Network (FlexCAN_C) 1152 0xFFFD_0000–0xFFFD_3FFF 16 Kb 1152 Controller Area Network (FlexCAN_E) 0xFFFD_4000–0xFFFD_FFFF 48 Kb N/A Reserved 16 Kb 2k FlexRay 0xFFFE_4000–0xFFFE_7FFF 16 Kb N/A Reserved 32 Parallel Digital Interface 0xFFFE_C000–0xFFFF_BFFF 64 Kb N/A Reserved Boot Assist Module (BAM) √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ √ VSS AN38 AN9 AN10 AN18 AN2 AN6 AN24 Version 1.3p – 29 May 2004 MDO0 VSS MDO1 VSS VDDE7 VSS VDDE7 VDDE7 TMS EVTI EVTO F GPIO 204 ETPUB G 15 RDY GPIO 203 A VDDE7 B VDD C TCK TDI D TDO TEST E ETPUB ETPUB H 14 13 VDDEH ETPUB ETPUB ETPUB J 6/10* 12 11 9 K ETPUA ETPUA ETPUA ETPUA 12 11 10 9 VSS VSS VSS VSS ETPUA ETPUA ETPUA ETPUA L 8 7 6 5 VSS VSS VSS VSS VSS VSS VSS VDDE7 ETPUB ETPUB ETPUB ETPUB L 6 4 3 2 VDDE2 VDDE2 VSS VSS VSS VSS VSS VDDE7 TCRCLK ETPUB ETPUB B 1 0 ETPUB ETPUB ETPUB ETPUB K 10 8 7 5 VDDE7 VDDE7 VDDE7 VDDE7 M ETPUA ETPUA ETPUA ETPUA 4 3 2 1 N BDIP TEA ETPUA TCRCLK 0 A VDDE2 VDDE2 VSS VSS VSS VSS VSS VDDE7 SOUTB PCSB3 PCSB0 PCSB1 N P CS3 CS2 CS1 CS0 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS PCSA3 PCSB4 SCKB PCSB2 P R WE3 WE2 WE1 WE0 VDDE2 VDDE2 VSS VSS VSS VSS VSS VSS PCSB5 SOUTA U ADDR 16 TSIZ1 V ADDR 18 ADDR W 20 Y AA TA VDD33 VDDE2 ADDR 17 TS ADDR 8 ADDR 19 ADDR 9 ADDR 10 ADDR 22 ADDR 21 ADDR VDDE2 11 ADDR 24 ADDR 23 ADDR 13 ADDR 12 AB VDDE2 ADDR 25 ADDR 15 ADDR 14 ADDR AC 26 ADDR 27 ADDR 31 VSS AD ADDR 28 ADDR 30 VSS AE ADDR 29 VSS VSS 1 AF VSS VSS SINA SINB M SCKA R VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS PCSA1 PCSA0 PCSA2 VDDE2 VDDE2 VDDE2 VDDE2 VDDE2 VSS VSS PCSA4 TXDA PCSA5 VFLASH U CNTXC RXDA RSTOUT VPP RST CFG T V RXDB CNRXC TXDB RESET W Note: NC PLL CFG2 WKP CFG No connect. AC22 & AD23 reserved VDDEH PLL 6 CFG1 1. Ball Y25 is PLLCFG2 on the MPC5567. VRC VSS1 VSS SYN Y BOOT EXTAL AA CFG0 VDD VRC CTL PLL CFG0 XTAL AB VSS VDD VRC33 VDD SYN AC NC VSS VDD VDDE2 DATA 31 DATA 8 DATA 10 VDDE2 DATA 12 DATA 27 DATA 29 VDD33 GPIO 207 DATA 9 DATA 11 DATA 13 DATA 15 DATA 21 DATA 23 DATA 0 DATA 2 DATA 4 DATA 6 OE BR BG EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS 1 5 9 13 16 19 23 VDD AE VDDE2 DATA 20 DATA 22 GPIO 206 DATA 1 DATA 3 VDDE2 DATA 5 DATA 7 BB EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 0 4 7 11 14 18 20 ENG CLK VSS AF 4 5 6 7 8 9 10 11 12 13 14 25 26 1 2 3 4 5 VSS VDD VSTBY AN37 AN11 VSS VDD AN36 AN39 AN19 VSS VDD AN8 VSS VDD VDD DATA 28 VDD DATA 24 DATA 25 VDD DATA 17 DATA 19 VDD DATA 16 DATA 18 2 3 DATA 14 BOOT CFG1 DATA 30 DATA 26 √ √ √ √ √ √ √ B VDD33 C E √ ETPUA ETPUA ETPUA ETPUA F 18 23 22 17 √ G ETPUA ETPUA ETPUA ETPUA 20 19 14 13 H ETPUA ETPUA ETPUA VDDEH 16 15 10 1 √ √ √ √ √ √ √ √ √ √ K √ √ √ √ √ √ √ √ √ ETPUA ETPUA 30 31 ETPUA ETPUA ETPUA D 26 28 29 √ √ √ √ √ If allocated size > used size, then the base address for the module is the lowest address of the listed address range, unless noted otherwise. The Fast Ethernet controller (FEC) uses different pins on the MPC5553/MPC5566 than the MPC5567. Reserved for future compatibility. No device is currently defined that uses these regions. BAM address range is configured so that 4k BAM occupies 0xFFFF_F000-0xFFFF_FFFF. √ 8K 32K 8K 32K 32K 8K 0K 0K Cache Size MDO4 ETPUA ETPUA ETPUA ETPUA 14 13 16 15 EMIOS EMIOS EMIOS EMIOS VDDEH VDDE5 2 8 12 21 4 NC EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 3 6 10 15 17 22 15 16 17 18 19 20 21 22 23 24 6 7 8 9 10 11 12 13 14 15 16 AN1 AN5 VRH VRL AN27 AN28 AN35 VSSA0 AN12 MDO11 MDO10 MDO8 AN16 AN0 AN4 REF BYPC AN23 AN26 AN31 AN32 VSSA0 AN13 MDO9 MDO7 MDO4 AN17 AN20 AN21 AN3 AN7 AN22 AN25 AN30 AN33 VDDA0 AN14 MDO5 MDO2 AN38 AN9 AN10 AN18 AN2 AN6 AN24 AN29 AN34 VDDEH AN15 9 MDO6 MDO3 VDDA1 VSSA1 17 18 ETPUA ETPUA ETPUA ETPUA 21 24 27 25 19 20 21 22 VDD VDD33 VSS MDO0 VSS VDD33 AD MDO1 VSS VDDE7 VDD C VSS VDDE7 TCK TDI D VDDE7 TMS TDO TEST E EVTI EVTO F VDDE7 JCOMP RDY Version 2.2p – 13 July 2004 A VDDE7 B MCKO MSEO0 MSEO1 G VDDEH GPIO 10 203 GPIO 204 SINB H ETPUA ETPUA ETPUA ETPUA J 12 11 9 6 VSS VSS VSS VSS VSS VDDE7 SOUTB PCSB3 PCSB0 PCSB1 J ETPUA ETPUA ETPUA ETPUA 8 7 2 5 VSS VSS VSS VSS VSS VSS PCSA3 PCSB4 SCKB PCSB2 K ETPUA ETPUA ETPUA ETPUA L 4 3 0 1 VSS VSS VSS VSS VSS VSS PCSB5 SOUTA M TCRCLK BDIP A CS1 CS0 N CS3 WE1 WE0 P ADDR 16 ADDR R 18 CS2 ADDR VDDE2 19 ADDR 21 ADDR 12 TS ADDR 23 ADDR 13 ADDR 14 V ADDR 24 ADDR 25 ADDR 15 ADDR 31 W ADDR ADDR VDDE2 26 30 ADDR 27 NC PLL CFG2 VSS VSS VSS VSS PCSA1 PCSA0 PCSA2 VDDE2 VSS VSS VSS PCSA4 TXDA PCSA5 VFLASH N VSS VSS VDDE2 VSS VSS VSS CNTXC RXDA RSTOUT RST CFG No connect. Reserved (W18 & Y19 are shorted to each other) 1. Ball Y25 is PLLCFG2 on the MPC5561 and the MPC5567. DATA 11 DATA 12 DATA 14 EMIOS EMIOS VDDEH EMIOS EMIOS VDDE5 21 8 2 4 12 DATA 10 GPIO 207 DATA 13 DATA 15 EMIOS EMIOS EMIOS EMIOS EMIOS CNTXA VDDE5 6 10 15 17 22 VDDE2 VDD33 VDDE2 VSS VDD DATA 8 DATA 9 SCKA L VSS WKP CFG Note: SINA VSS TA ADDR U 22 ADDR Y 28 VDDE2 VDDE2 ADDR RD_WR VDD33 17 ADDR 20 T 16 Kb 16 Kb √ √ 0xFFFE_8000–0xFFFE_BFFF 16 Kb √ √ Controller Area Network (FlexCAN_D) 0xFFFE_0000–0xFFFE_3FFF √ √ √ 26 VSS MPC5554/MPC5566 416 PBGA Ball Map Diagram Serial Communications Interface (SCI_D) 0xFFFC_4000–0xFFFC_7FFF 16 Kb √ 25 VDD33 J A 0xFFFB_0000–0xFFFB_3FFF 16 Kb √ √ Deserial Serial Peripheral Interface (DSPI_B) 0xFFFA_0000–0xFFFA_3FFF √ MDO3 VDD T VDDE2 TSIZ0 RD_WR VDDE2 0xFFF8_8000–0xFFF8_BFFF 16 Kb √ Reserved 0xFFF5_0000–0xFFF7_FFFF 24 VDD MSEO1 MCKO √ N/A 23 ETPUA ETPUA ETPUA ETPUA 23 22 25 21 √ 15 Kb 22 MDO11 MDO8 MSEO0 JCOMP √ √ 21 GPIO 205 ETPUA ETPUA ETPUA VDDEH 24 27 26 1 ECSM √ 20 F N/A Fast Ethernet Controller (FEC) 19 √ 16 Kb N/A 18 ETPUA ETPUA VDDEH 28 29 1 0xFFF4_0000–0xFFF4_3FFF 1 Kb 17 E Reserved b 16 √ N/A 09 October 2006rd v 1.5 ADC AMUX ETPUA ETPUA D 30 31 192 Kb a. b. c. d. ADCi ADC Not available on all devices. VSTBY 0xFFF1_0000–0xFFF3_FFFF 0xFFFF_C000–0xFFFF_FFFF eQADC – Decrementer – Fixed interval timer – Time base – Watchdog timer 1 C VDD33 Bridge B Registers – Controller area network (FlexCAN) – Deserial/serial peripheral interface – Enhanced direct memory access – Enhanced modular I/O system – Enhanced queued analog/digital converter – Enhanced serial communications interface – Enhanced time processing units – Fast EtherNet Controller – Frequency modulated phase-locked loop – Static RAM VSS ETPUA ETPUA ETPUA ETPUA H 20 19 18 17 d 12-20 Kb Code RAM A G 0xFFFC_C000–0xFFFC_FFFF eMIOS (24 Ch) eTPU (32 Ch) DEC FIT TB WDT Reserved 0xFFFC_0000–0xFFFC_3FFF 2.5-4 Kb Data RAM Peripheral Bridge B (PBRIDGE_B) e200z Core Component Acronyms N/A 0xFFFB_C000–0xFFFC_FFFF Boot Assist Module SRAM 48-192 Kb CAN DSPI eDMA eMIOS eQADC eSCI eTPU FEC FMPLL SRAM 32 Kb 0xFFF9_4000–0xFFF9_7FFF Slave MPC5500 Device Module Acronyms 0xFFF0_8000–0xFFF0_FFFF 0xFFF4_C400–0xFFF4_FFFF Interface Digital Parallel System/Bus Integration Slave Slave LEGEND √ 0xC3FD_5000–0xC3FF_FFFF 0xFFF4_C000–0xFFF4_C3FF Slave Slave eTPU Parameter RAM Reserved 16 Kb 0xFFF0_4000–0xFFF0_7FFF Master √ 0xC3FC_C000–0xC3FC_FFFF 0xFFF0_0000–0xFFF0_3FFF Master Master Peripheral Bridge A (PBRIDGE_A) 1 Kb 0xC3FC_9000–0xC3FC_BFFF √ Master External Bus Interface Crossbar Switch (XBAR) Flash 768Kb-3Mb 0.5 Kb 0xC3FC_8C00–0xC3FC_8FFF Master Slave √ External Master Interface FlexRay FlexCAN 16 Kb Fast Ethernet Controller eDMA 32-64 Channels FlexCAN 0xC3F8_8000–0xC3F8_BFFF Calibration Bus FlexCAN 48 Reserved FlexCAN N/A FlexCAN 16 Kb √ FlexCAN 0xC3F8_4000–0xC3F8_7FFF √ eSCI 16 Kb √ eSCI 0xC3F8_0000–0xC3F8_3FFF √ MPC5500 Family Interrupt Controller DSPI 496 K √ Nexus Interface DSPI 0xC3F0_4000–0xC3F7_FFFF Reserved Bridge A Registers • • • • • • • DSPI 16k 2006 DSPI 0xC3F0_0000–0xC3F0_3FFF N/A 2005 Availability Bridge A Peripherals 63 M MPC5565 MPC5553 MPC563 0x4000_8000–0x4000_BFFF 0xC000_0000–0xC3EF_FFFF MPC5567 MPC5554 VSS VDD VDDE2 AA ADDR 29 VSS VDD VDDE2 DATA 1 VDDE2 GPIO 206 DATA 5 DATA 7 AB VSS VDD VDDE2 DATA 0 DATA 2 DATA 3 DATA 4 DATA 6 OE 1 2 3 4 5 6 7 8 9 NC VPP M P CNRXC TXDB RESET R BOOT CFG1 VRC VSS1 VDDEH PLL 6 CFG1 BOOT CFG0 VDD VRC CTL PLL CFG0 XTAL V VSS VDD VRC33 VDD SYN W NC VSS VDD RXDB VSS SYN T EXTAL U VDD33 Y VDDE2 EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNRXA VDDE5 CLKOUT VSS 3 5 9 13 16 19 23 VDD AA EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS EMIOS CNTXB CNRXB VDDE5 0 1 4 7 11 14 18 20 ENG CLK VSS AB 21 22 10 11 12 13 14 15 16 17 18 19 20 MPC5533/MPC5534/MPC5553/MPC5565 324 PBGA Ball Map Diagram For more information on the MPC5500 Family, go to http://www.freescale.com/MPC55xx. © 2006 Freescale Semiconductor