DC Motor - 2 outputs version - XOR version TPU Function Set

Freescale Semiconductor, Inc.
Application Note
AN2526/D
Rev.0, 5/2003
DC Motor – 2 outputs version
– XOR version TPU Function
Set (DCm2Xor)
Freescale Semiconductor, Inc...
By Milan Brejl, Ph.D.
Functional Overview
The DC Motor – 2 outputs version – XOR version (DCm2Xor) TPU function is
a version of the DC Motor – 2 output version (DCm2) function that uses two
TPU channels to generate one PWM output channel. The TPU channel outputs
are connected to an XOR gate whos output is the required PWM signal. See
Figure 1. An advantage of this solution is that the full range (0% to 100%) of
PWM duty-cycle ratios is available. There is no MPW (minimum pulse width)
parameter to limit the edge duty-cycle ratios in this version, as opposed to the
DCm2. A disadvantage is that the number of assigned TPU channels is
doubled.
50% PWM
SW1_1
XOR
SW1
XOR
SW3
PWM period
PWM period
center-time
center-time
SW1_2
SW3_1
SW3_2
motor
voltage
Figure 1. Functionality of XOR version – illustation
The DCm2Xor TPU functions, unlike the DCmXor, generates only the top
channel signal of each PWM pair. The bottom channel signal can be derived
from the top channel signal by external hardware.
The function set consists of 5 TPU functions:
© Freescale Semiconductor, Inc., 2004. All rights reserved.
For More Information On This Product,
Go to: www.freescale.com
© Motorola, Inc., 2003
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
AN2526/D
•
DC Motor – 2 outputs version – XOR version – C channels
(DCm2Xor_C)
•
DC Motor – 2 outputs version – XOR version – T channels (DCm2Xor_T)
•
Synchronization Signal for DC Motor – 2 outputs version – XOR version
(DCm2Xor_sync)
•
Resolver Reference Signal for DC Motor – 2 outputs version – XOR
version (DCm2Xor_res)
•
Fault Input for DC Motor – 2 outputs version – XOR version
(DCm2Xor_fault)
The DCm2Xor TPU function set drives a DC Motor, independently of the CPU.
The CPU is only required to set a duty-cycle (dc) parameter in the range (–1,1),
which determines both the speed and the direction. The function generates
unipolar-switched center-aligned PWM signals.
The DCm2Xor_C and DCm2Xor_T TPU functions work together to generate 2
pairs of XOR gate inputs. The XOR gate outputs then produce a 2-channel 2phase center-aligned PWM signal. The Synchronization Signal for the
DCm2Xor function can be used to generate one or more adjustable signals for
a wide range of uses. These signals are synchronized to the PWM, and track
changes in the PWM period. The Resolver Reference Signal for the DCm2Xor
function can be used to generate one or more 50% duty-cycle adjustable
signals that are also synchronized to the PWM.The Fault Input for the
DCm2Xor function is a TPU input function that sets all PWM outputs low when
the input signal goes low.
Function Set Configuration
None of the TPU functions in the DC Motor – 2 outputs version – XOR version
TPU function set can be used separately. The DCm2Xor_C and DCm2Xor_T
functions have to be used together. The DCm2Xor_C runs on pins SW1_1 and
SW3_1 – see Figure 1. The DCm2Xor_T runs on the other pins. One or more
channels running Synchronization Signal for DCm2Xor as well as Resolver
Reference Signals for DCm2Xor functions can be added. They can run with
different settings on each channel. The function Fault Input for DCm2Xor can
also be added. It is recommended to use it on channel 15, and to set the
hardware option that disables all TPU output pins when the channel 15 input
signal is low (DTPU bit = 1). This ensures that the hardware reacts quickly to a
pin fault state. Note that it is not only the PWM channels, but all TPU output
channels, including the synchronization signals, that are disabled in this
configuration.
Table 1 shows the configuration options and restrictions.
2
DC Motor – 2 outputs version – XOR version TPU Function Set (DCm2Xor)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
AN2526/D
Function Set Configuration
Table 1. DCm2Xor TPU function set configuration options and
restrictions
DCm2Xor_C
DCm2Xor_T
DCm2Xor_sync
DCm2Xor_res
Optional/
Mandatory
mandatory
mandatory
optional
optional
How many
channels
2
2
1 or more
1 or more
DCm2Xor_fault
optional
1
Freescale Semiconductor, Inc...
TPU function
Assignable channels
any 2 channels
any 2 channels
any channels
any channels
any, recommended is 15 and DTPU bit
set
Table 2 shows an example of configuration.
Table 2. Example of configuration
Channel
0
1
2
3
10
11
15
TPU function
DCm2Xor_C
DCm2Xor_T
DCm2Xor_C
DCm2Xor_T
DCm2Xor_sync
DCm2Xor_res
DCm2Xor_fault
Priority
high
high
high
high
low
low
high
Table 3 shows the TPU function code sizes.
Table 3. TPU function code sizes
TPU function
DCm2Xor_C
DCm2Xor_T
DCm2Xor_sync
DCm2Xor_res
DCm2Xor_fault
Configuration Order
Code size
78 µ instructions + 8 entries = 68 long words
3 µ instructions + 8 entries = 11 long words
26 µ instructions + 8 entries = 34 long words
38 µ instructions + 8 entries = 46 long words
9 µ instructions + 8 entries = 17 long words
The CPU configures the TPU as follows.
1. Disables the channels by clearing the two channel priority bits on each
channel used (not necessary after reset).
2. Selects the channel functions on all used channels by writing the
function numbers to the channel function select bits.
DC Motor – 2 outputs version – XOR version TPU Function Set (DCm2Xor)
For More Information On This Product,
Go to: www.freescale.com
3
Freescale Semiconductor, Inc.
AN2526/D
3. Initializes function parameters. The parameters T and sync_presc_addr
must be set before initialization. If a DCm2Xor_sync channel or a
DCm2Xor_res channel is used, then its parameters must also be set
before initialization.
Freescale Semiconductor, Inc...
4. Issues an HSR (Host Service Request) type %10 to one of the
DCm2Xor_C channels to initialize all DCm2Xor_C and DCm2Xor_T
channels. Issues an HSR type %10 to the DCm2Xor_sync channels,
DCm2Xor_res channels and DCm2Xor_fault channel, if used.
5. Enables servicing by assigning high, middle or low priority to the channel
priority bits. All DCm2Xor_C and DCm2Xor_T channels must be
assigned the same priority to ensure correct operation. The CPU must
ensure that the DCm2Xor_sync or DCm2Xor_res function is initialized
after the initialization of DCm2Xor:
–
–
–
NOTE:
assign a priority to the DCm2Xor_C and DCm2Xor_T channels to
enable their initialization
if a Synchronization Signal or a Resolver Reference Signal channel
is used, wait until the HSR bits are cleared to indicate that
initialization of the DCm2Xor_C and DCm2Xor_T channels has
completed and
assign a priority to the DCm2Xor_sync or DCm2Xor_res channel to
enable its initialization
A CPU routine that configures the TPU can be generated automatically using
the MPC500_Quick_Start Graphical Configuration Tool.
Detailed Function Description
DC Motor – 2
outputs version –
XOR version – C
channels
(DCm2Xor_C) and
DC Motor – 2
outputs version –
XOR version – T
channels
(DCm2Xor_T)
The DCm2Xor_C and DCm2Xor_T TPU functions work together to generate 2
pairs of XOR gate inputs. The XOR gate outputs then produce a 2-channel 2phase center-aligned PWM signal. Unlike the DCmXor, the generated signals
are not top-bottom complementary pairs with dead-times but only top-like
signals without dead-times. In order to charge the bootstrap transistors, the
PWM signals start to run 1.6ms after their initialization (at 20MHz TCR1 clock).
The functions generate signals corresponding to a value 0 in duty-cycle ratio dc
until the first dc value is processed, or for at least for one PWM period.
The CPU controls the PWM output by setting the TPU parameters. The dutycycle ratio dc and PWM period T can be adjusted during run time. The dutycycle ratio dc can gain a value in the range (–1, 1). The sign controls the motion
system direction, while the absolute value controls the amplitude of the applied
voltage.
The following figures show the input dc value and corresponding XOR gate
outputs:
4
DC Motor – 2 outputs version – XOR version TPU Function Set (DCm2Xor)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
AN2526/D
Detailed Function Description
dc = - 0.5
dc = 0
dc = 0.5
PWM period
PWM period
PWM period
center-time
center-time
center-time
SW1
SW3
Freescale Semiconductor, Inc...
motor
voltage
Figure 2. Unipolar switching
The following equations describe how the PWM signal transition times
SW1_1T, SW1_2T, SW3_1T and SW3_2T are calculated:
Tdc = T ⋅ dc
T + Tdc
4
T − Tdc
Y =
4
X =
SW1_1 T = center _ time − X
SW1_2T = center _ time + X
SW3_1 T = center _ time − Y
SW3_2 T = center _ time + Y
Host Interface
Written By CPU
Written by both CPU and TPU
Written By TPU
Not Used
Table 4. DCm2Xor_C Control Bits
Name
3
2
1
0
Channel Function Select
Options
DCm2Xor_C function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
DC Motor – 2 outputs version – XOR version TPU Function Set (DCm2Xor)
For More Information On This Product,
Go to: www.freescale.com
5
Freescale Semiconductor, Inc.
AN2526/D
Table 4. DCm2Xor_C Control Bits
Name
1
0
Channel Priority
1
0
Host Service Bits (HSR)
Freescale Semiconductor, Inc...
1
Options
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
00 – No Host Service Request
01 – Not used
10 – Initialization
11 – Stop
0
Host Sequence Bits (HSQ)
xx – Not used
Channel Interrupt Enable
x – Not used
Channel Interrupt Status
x – Not used
0
0
Table 5. DCm2Xor_T Control Bits
Name
3
2
1
0
Channel Function Select
1
0
Channel Priority
1
0
Host Service Bits (HSR)
1
Options
DCm2Xor_T function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
00 – No Host Service Request
01 – Not used
10 – Not used
11 – Not used
0
Host Sequence Bits (HSQ)
xx – Not used
Channel Interrupt Enable
x – Not used
Channel Interrupt Status
x – Not used
0
0
6
DC Motor – 2 outputs version – XOR version TPU Function Set (DCm2Xor)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
AN2526/D
Detailed Function Description
Table 6. DCm2Xor_C and DCm2Xor_T Parameter RAM
SW3_2
SW3_1
SW1_2
Freescale Semiconductor, Inc...
SW1_1
Channel
Parameter 15 14 13 12 11 10 9 8 7 6 5
0
XY_X
SW13_2_ch_SW1
1
2
3
other_ch_SW1
dc
4
T
5
6
7
fault_pinstate
0
Ttime_SW1_2
T_copy
1
2
3
center_time
4
5
CPU14
6
7
0
XY_Y
1
SW13_2_ch_SW3
2
3
other_ch_SW3
4
5
sync_presc_addr
6
7
0
Ttime_SW3_2
1
2
3
4
5
6
7
4
3
2
1
0
Table 7. DCm2Xor_C and DCm2Xor_T parameter description
Parameter
dc
T
Format
Description
Parameters written by CPU
duty-cycle ratio in the range
16-bit fractional
<–1,1)
PWM period in number of TCR1
16-bit unsigned integer
TPU cycles
DC Motor – 2 outputs version – XOR version TPU Function Set (DCm2Xor)
For More Information On This Product,
Go to: www.freescale.com
7
Freescale Semiconductor, Inc.
AN2526/D
Table 7. DCm2Xor_C and DCm2Xor_T parameter description
Freescale Semiconductor, Inc...
Parameter
Format
Description
Time of 14 IMB clocks in TCR1
CPU14
16-bit unsigned integer
clocks.
address of synchronization
channel prescaler parameter:
$X4,
sync_presc_addr 8-bit unsigned integer
where X is synchronization
channel number.
$0 if no synchronization channel
is used.
Parameters written by TPU
If fault channel is used, state of
fault pin:
fault_pinstate
0 or 1
0 ... low
1 ... high
Other parameters are just for TPU function inner use.
Performance
Table 8. DCm2Xor_T State Statistics
State
ST
SF
Max IMB Clock Cycles
2
2
RAM Accesses by TPU
1
0
Table 9. DCm2Xor_C State Statistics
State
INIT
STOP
C1
C2
Max IMB Clock Cycles
50
52
68
10
RAM Accesses by TPU
10
1
12
4
Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
8
DC Motor – 2 outputs version – XOR version TPU Function Set (DCm2Xor)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
AN2526/D
Detailed Function Description
dc > 0%
SW1_1
C1
T
T
center-time
center-time
C2
C2
ST
SF
SW1_2
SF
C2
SW3_1
C1
SF
SW3_2
Freescale Semiconductor, Inc...
dc < 0%
ST
C2
ST
SF
ST
flag0 = 1
link
Figure 3. DCm2Xor_C and DCm2Xor_T timing
SF
SF
ST
ST
ST
SF
ST
flag0 = 1
link
Figure 4. DCm2Xor_T state diagram and 3 cases of timing
NOTE:
The timing of the link determines which case accurs.
DC Motor – 2 outputs version – XOR version TPU Function Set (DCm2Xor)
For More Information On This Product,
Go to: www.freescale.com
9
Freescale Semiconductor, Inc.
AN2526/D
INIT
C1
STOP
HSR = 10
HSR = 11
Freescale Semiconductor, Inc...
C2
Figure 5. DCm2Xor_C state diagram
Synchronization
signal for DC Motor
– 2 outputs version –
XOR version
(DCm2Xor_sync)
The DCm2Xor_sync TPU function uses information obtained from
DCm2Xor_C and DCm2Xor_T functions, the actual PWM center times and the
PWM periods. This allows a signal to be generated, that tracks the changes in
the PWM period and is always synchronized with the PWM. The
synchronization signal is a positive pulse generated repeatedly after the
prescaler or presc_copy PWM periods (see next paragraph). The low to high
transition of the pulse can be adjusted by a parameter, either negative or
positive, to go before or after the PWM period center time of a number of TCR1
TPU cycles. The pulse width pw is another synchronization signal parameter.
move > 0
prescaler = 1
pw
|move|
center_time
center_time
T
T
move < 0
prescaler = 2
pw
|move|
center_time
center_time
center_time
T
T
T
Figure 6. Synchronization signal adjustment examples
10
DC Motor – 2 outputs version – XOR version TPU Function Set (DCm2Xor)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
AN2526/D
Detailed Function Description
Synchronized Change
of PWM Prescaler
And Synchronization
Signal Prescaler
The DCm2Xor_sync TPU function actually uses the presc_copy parameter
instead of the prescaler parameter. The prescaler parameter holds the
prescaler value that is copied to the presc_copy by the DCm2Xor_bottom
function at the time of the PWM parameters reload. This ensures that new
prescaler values for the PWM signals, as well as the synchronization signal, are
applied at the same time. Write the synchronization signals prescaler
parameter address to the sync_presc_addr parameter to enable this
mechanism. Write 0 to disable it, and remember to set the synchronization
signal presc_copy parameter instead of the prescaler parameter in this case.
Freescale Semiconductor, Inc...
Host Interface
Written By CPU
Written by both CPU and TPU
Written By TPU
Not Used
Table 10. DCm2Xor_sync Control Bits
Name
3
2
1
0
Channel Function Select
1
0
Channel Priority
1
0
Host Service Bits (HSR)
1
Options
DCm2Xor_sync function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
00 – No Host Service Request
01 – Not used
10 – Initialization
11 – Not used
0
Host Sequence Bits (HSQ)
xx – Not used
Channel Interrupt Enable
0 – Channel Interrupt Disabled
1 – Channel Interrupt Enabled
Channel Interrupt Status
0 – Interrupt Not Asserted
1 – Interrupt Asserted
0
0
TPU function DCm2Xor_sync generates an interrupt after each low to high
transition.
DC Motor – 2 outputs version – XOR version TPU Function Set (DCm2Xor)
For More Information On This Product,
Go to: www.freescale.com
11
Freescale Semiconductor, Inc.
AN2526/D
Table 11. DCm2Xor_sync Parameter RAM
Freescale Semiconductor, Inc...
Synchronization channel
Channel
Parameter 15 14 13 12 11 10 9 8 7 6
0
move
pw
1
prescaler
2
3
presc_copy
time
4
dec
5
6
T_copy
5
4
3
2
1
0
7
Table 12. DCm2Xor_sync parameter description
Parameter
Format
Description
Parameters written by CPU
The number of TCR1 TPU cycles to
forego (negative) or come after
move
16-bit signed integer
(positive) the PWM period center
time
Synchronization pulse width in
pw
16-bit unsigned integer
number of TCR1 TPU cycles.
The number of PWM periods per
synchronization pulse
prescaler
16-bit unsigned integer
– use in case of synchronized
prescalers change
The number of PWM periods per
synchronization pulse
presc_copy
16-bit unsigned integer
– use in case of asynchronized
prescalers change
Parameters written by TPU
Other parameters are just for TPU function inner use.
Performance
There is one limitation. The absolute value of parameter move has to be less
then a quarter of the PWM period T.
move <
12
T
4
DC Motor – 2 outputs version – XOR version TPU Function Set (DCm2Xor)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
AN2526/D
Detailed Function Description
Table 13. DCm2Xor_sync State Statistics
State
INIT
S1
S2
S3
Freescale Semiconductor, Inc...
NOTE:
RAM Accesses by TPU
5
6
3
7
Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
S2
S1
Max IMB Clock Cycles
12
12
8
16
S3
S1
center_time
center_time
center_time
T
T
T
S2
Figure 7. DCm2Xor_sync timing
HSR = 10
INIT
S1
S2
S3
Figure 8. DCm2Xor_sync state diagram
Resolver Reference
Signal for DC Motor
– 2 outputs version –
XOR version
(DCm2Xor_res)
The DCm2Xor_res TPU function uses information read from the DCm2Xor_C
and DCm2Xor_T functions, the actual PWM center times and the PWM
periods. This allows a signal to be generated, which tracks the changes of the
PWM period and is always synchronized with the PWM. The resolver reference
signal is a 50% duty-cycle signal with a period equal to prescaler or
DC Motor – 2 outputs version – XOR version TPU Function Set (DCm2Xor)
For More Information On This Product,
Go to: www.freescale.com
13
Freescale Semiconductor, Inc.
AN2526/D
synchronization channel presc_copy PWM periods (see next paragraph). The
low to high transition of the pulse can be adjusted by a parameter, either
negative or positive, to go before or after the PWM period center time of a
number of TCR1 TPU cycles.
move > 0
prescaler = 1
Freescale Semiconductor, Inc...
|move|
center_time
center_time
T
T
center_time
center_time
center_time
T
T
T
move < 0
prescaler = 2
|move|
Figure 9. Resolver reference signal adjustment examples
Synchronized Change
of PWM Prescaler
And Resolver
Reference Signals
Prescaler
The DCm2Xor_res TPU function can inherit the Synchronization Signal
prescaler that is synchronously changed with PWM prescaler. Write the
synchronization signals presc_copy parameter address to the presc_addr
parameter to enable this mechanism. Write 0 to disable it, and in this case set
prescaler parameter to directly specify prescaler value.
Host Interface
Written By CPU
Written by both CPU and TPU
Written By TPU
Not Used
Table 14. DCm2Xor_res Control Bits
Name
3
2
1
0
Channel Function Select
1
0
Channel Priority
14
Options
DCm2Xor_res function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
DC Motor – 2 outputs version – XOR version TPU Function Set (DCm2Xor)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
AN2526/D
Detailed Function Description
Table 14. DCm2Xor_res Control Bits
Name
1
0
Host Service Bits (HSR)
1
Options
00 – No Host Service Request
01 – Not used
10 – Initialization
11 – Not used
0
Host Sequence Bits (HSQ)
xx – Not used
Channel Interrupt Enable
x – Not used
Channel Interrupt Status
x – Not used
0
Table 15. DCm2Xor_res Parameter RAM
Channel
Resolver
Freescale Semiconductor, Inc...
0
Parameter 15 14 13 12 11 10 9 8 7 6
0
move
1
2
presc_addr
prescaler
3
4
time
dec
5
T_copy
6
7
5
4
3
2
1
0
Table 16. DCm2Xor_res parameter description
Parameter
move
presc_addr
Format
Description
Parameters written by CPU
The number of TCR1 TPU cycles to
forego (negative) or come after
16-bit signed integer
(positive) the PWM period center
time
$00X6, where X is a number of
Synchronization Signal channel, to
inherit Sync. channel prescaler
or
16-bit unsigned integer
$0000 to enable direct specification
of prescaler value in prescaler
parameter
DC Motor – 2 outputs version – XOR version TPU Function Set (DCm2Xor)
For More Information On This Product,
Go to: www.freescale.com
15
Freescale Semiconductor, Inc.
AN2526/D
Table 16. DCm2Xor_res parameter description
Parameter
Description
The number of PWM periods per
prescaler
1, 2, 4, 6, 8, 10, 12, 14, ...
synchronization pulse
– use when apresc_addr = 0
Parameters written by TPU
Other parameters are just for TPU function inner use.
Performance
Format
There is one limitation. The absolute value of parameter move has to be less
than a quarter of the PWM period T.
Freescale Semiconductor, Inc...
move <
T
4
Table 17. DCm2Xor_res State Statistics
State
INIT
S1
S3
NOTE:
S1
Max IMB Clock Cycles
12
26
16
RAM Accesses by TPU
5
9
7
Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
S3
S1
center_time
center_time
center_time
T
T
T
Figure 10. DCm2Xor_res timing
16
DC Motor – 2 outputs version – XOR version TPU Function Set (DCm2Xor)
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
AN2526/D
Detailed Function Description
HSR = 10
Freescale Semiconductor, Inc...
INIT
S1
S3
Figure 11. DCm2Xor_res state diagram
Fault Input for DC
Motor – 2 outputs
version – XOR
version
(DCm2Xor_fault)
The DCm2Xor_fault is an input TPU function that monitors the pin, and if a high
to low transition occurs, immediately sets all PWM channels low and cancels
all further transitions on them. The PWM channels, as well as the
synchronization and resolver reference signal channels (if used), have to be
initialized again to start them running.
The function returns the actual pinstate as a value of 0 (low) or 1 (high) in the
parameter fault_pinstate. The parameter is placed on the SW1_1 channel to
keep the fault channel parameter space free.
Host Interface
Written By CPU
Written by both CPU and TPU
Written By TPU
Not Used
Table 18. DCm2Xor_fault Control Bits
3
2
1
Name
0 Channel Function Select
1
0 Channel Priority
Options
DCm2Xor_fault function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
DC Motor – 2 outputs version – XOR version TPU Function Set (DCm2Xor)
For More Information On This Product,
Go to: www.freescale.com
17
Freescale Semiconductor, Inc.
AN2526/D
Freescale Semiconductor, Inc...
Table 18. DCm2Xor_fault Control Bits
1
Name
0 Host Service Bits (HSR)
1
0 Host Sequence Bits (HSQ)
Options
00 – No Host Service Request
01 – Not used
10 – Initialization
11 – Not used
xx – Not used
0 Channel Interrupt Enable
0 – Channel Interrupt Disabled
1 – Channel Interrupt Enabled
0 Channel Interrupt Status
0 – Interrupt Not Asserted
1 – Interrupt Asserted
TPU function DCm2Xor_fault generates an interrupt when a high to low
transition appears.
Table 19. DCm2Xor_fault Parameter RAM
Fault input
Channel
Parameter 15 14 13 12 11 10 9
0
1
2
3
4
5
6
7
8
7
6
5
4
3
Table 20. DCm2Xor_fault parameter description
Parameter
fault_pinstate
18
Format
Description
Parameters written by TPU
State of fault pin:
0 or 1
0 ... low
1 ... high
DC Motor – 2 outputs version – XOR version TPU Function Set (DCm2Xor)
For More Information On This Product,
Go to: www.freescale.com
2
1
0
Freescale Semiconductor, Inc.
AN2526/D
Detailed Function Description
Performance
Table 21. DCm2Xor_fault State Statistics
State
INIT
FAULT
NO_FAULT
Freescale Semiconductor, Inc...
NOTE:
Max IMB Clock Cycles
8
58
4
RAM Accesses by TPU
2
2
1
Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
NO_FAULT
FAULT
Figure 12. DCm2Xor_fault timing
HSR = 10
INIT
FAULT
NO_FAULT
Figure 13. DCm2Xor_fault state diagram
DC Motor – 2 outputs version – XOR version TPU Function Set (DCm2Xor)
For More Information On This Product,
Go to: www.freescale.com
19
Freescale Semiconductor, Inc.
How to Reach Us:
Home Page:
www.freescale.com
Freescale Semiconductor, Inc...
E-mail:
support@freescale.com
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130
support@freescale.com
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
support@freescale.com
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 2666 8080
support.asia@freescale.com
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
AN2526/D
Rev.0
5/2003
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be
provided in Freescale Semiconductor data sheets and/or specifications can and do
vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.
For More Information On This Product,
Go to: www.freescale.com