3Sin with Dead-Time Correction - XOR version TPU Function Set

Freescale Semiconductor, Inc.
Application Note
AN2519/D
Rev. 0, 5/2003
3Sin with Dead-Time
Correction – XOR version
TPU Function Set (3SinDtXor)
Freescale Semiconductor, Inc...
By Milan Brejl, Ph.D.
Functional Overview
The 3-Phase Sine Wave Generator with Dead-Time Correction – XOR version
(3SinDtXor) is a version of the 3-Phase Sine Wave Generator with Dead-Time
Correction (3SinDt) function that uses two TPU channels to generate one PWM
output channel. The TPU channel outputs are to be connected to a XOR gate
whose output is the required PWM signal. See Figure 1. An advantage of this
solution is that it provides the full range 0% to 100% of PWM duty-cycle ratios.
There is no MPW (minimum pulse width) parameter to limit the edge duty-cycle
ratios in this version, unlike in the 3SinDt. A disadvantage is that the number of
assigned TPU channels is doubled.
AT1
XOR
Phase A - top
XOR
Phase A - bottom
XOR
Phase B - top
XOR
Phase B - bottom
XOR
Phase C - top
XOR
Phase C - bottom
AT2
AB1
AB2
BT1
BT2
BB1
BB2
CT1
CT2
CB1
CB2
Figure 1. Functionality of XOR version – illustration
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The dead-time correction technique requires knowledge of the instantaneous
direction of phase currents. In the case of positive phase current the top
channel high-time is equal to the calculated high-time, and the bottom channel
has to control the dead-time. In case of negative phase current the bottom
channel low-time is equal to the calculated high-time, and the top channel has
to control the dead-time. See Figure 2.
calculated
high-time
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In case of positive current:
top channel
bottom channel
DT
DT
In case of negative current:
top channel
bottom channel
DT
DT
Figure 2. Dead-Time Correction Technique
The function set consists of 5 TPU functions:
•
3-Phase Sine Wave Generator with Dead-Time Correction – XOR
version – R channels (3SinDtXor_R)
•
3-Phase Sine Wave Generator with Dead-Time Correction – XOR
version – T channels (3SinDtXor_T)
•
Synchronization Signal for 3-Phase Sine Wave Generator with DeadTime Correction – XOR version (3SinDtXor_sync)
•
Resolver Reference Signal for 3-Phase Sine Wave Generator with
Dead-Time Correction – XOR version (3SinDtXor_res)
•
Fault Input for 3-Phase Sine Wave Generator with Dead-Time
Correction – XOR version (3SinDtXor_fault)
The 3SinDtXor_R and 3SinDtXor_T TPU functions work together to generate
6 pairs of XOR gate inputs. The XOR gate outputs then produce a 6-channel
3-phase center-aligned PWM signal with dead-time between the top and
bottom channels. The Synchronization Signal for the 3SinDtXor function can be
used to generate one adjustable signal for a wide range of uses, which is
synchronized to the PWM, and tracks changes in the PWM period. The
2
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Function Set Configuration
Resolver Reference Signal for the 3SinDtXor function can be used to generate
one 50% duty-cycle adjustable signal, which is also synchronized to the PWM.
The Fault Input for the 3SinDtXor function is a TPU input function that sets all
XOR gate outputs low when the input signal goes low.
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Function Set Configuration
None of the TPU functions in the 3-Phase Sine Wave Generator with DeadTime Correction – XOR version TPU function set can be used separately. The
3SinDtXor_R and 3SinDtXor_T functions have to be used together. The
3SinDtXor_R runs on pins AB1, BB1, CB1 – see Figure 1. 3SinDtXor_T runs
on the other pins. The 3SinDtXor_R and 3SinDtXor_T functions use a table of
32 cosine function values. The table is placed in the parameter space of four
consecutive channels. One channel running Synchronization Signal for
3SinDtXor and one channel running Resolver Reference Signal for 3SinDtXor
functions can be added to the 3SinDtXor_R and 3SinDtXor_T functions. They
can run on one of the channels where the cosine table values are placed,
because the 3SinDtXor_sync and 3SinDtXor_res parameters are placed on
two 3SinDtXor_T channels. The function Fault Input for 3SinDtXor can also be
added to the 3SinDtXor_R and 3SinDtXor_T functions. It is recommended to
use it on channel 15, and to set the hardware option that disables all TPU
output pins when the channel 15 input signal is low (DTPU bit = 1). This
ensures that the hardware reacts quickly to a pin fault state. Note that it is not
only the PWM channels, but all TPU output channels, including the
synchronization and resolver reference signals, that are disabled in this
configuration. The function 3SinDtXor_fault can run on one of the four channels
where the table of cosine function values is placed, because the
3SinDtXor_fault function does not have any parameters.
Table 1 shows the configuration options and restrictions.
Table 1. 3SinDtXor TPU function set configuration options and
restrictions
TPU function
3SinDtXor_R
3SinDtXor_T
Cosine table
3SinDtXor_sync
3SinDtXor_res
3SinDtXor_fault
Optional/ How many
Mandatory channels
mandatory
3
mandatory
9
mandatory
4
optional
1
optional
1
optional
1
Assignable channels
any 3 channels
any 9 channels
any 4 consecutive channels
one of Cosine Table channels
one of Cosine Table channels
one of Cosine Table channels,
recommended is 15 and DTPU bit set
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Table 2 shows an example of configuration.
Table 2. Example of configuration
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Channel
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TPU function
3SinDtXor_T
3SinDtXor_T
3SinDtXor_R
3SinDtXor_T
3SinDtXor_T
3SinDtXor_T
3SinDtXor_R
3SinDtXor_T
3SinDtXor_T
3SinDtXor_T
3SinDtXor_R
3SinDtXor_T
Cosine table 1
3SinDtXor_sync, Cosine table 2
3SinDtXor_res, Cosine table 3
3SinDtXor_fault, Cosine table 4
Priority
middle
middle
middle
middle
middle
middle
middle
middle
middle
middle
middle
middle
none
low
low
high
Table 3 shows the TPU function code sizes.
Table 3. TPU function code sizes
TPU function
3SinDtXor_R
3SinDtXor_T
3SinDtXor_sync
3SinDtXor_res
3SinDtXor_fault
Configuration Order
Code size
317 µ instructions + 8 entries = 325 long words
3 µ instructions + 8 entries = 11 long words
30 µ instructions + 8 entries = 38 long words
41 µ instructions + 8 entries = 49 long words
9 µ instructions + 8 entries = 17 long words
The CPU configures the TPU as follows.
1. Disables the channels by clearing the two channel priority bits on each
channel used (not necessary after reset).
2. Selects the channel functions on all used channels by writing the
function numbers to the channel function select bits.
3. Initializes function parameters. The parameters T, prescaler, DT,
Theta_H, Theta_L and sync_presc_addr must be set before
initialization. 32 cosine table values must be set. If an 3SinDt_sync
channel or an 3SinDt_res channel is used, then its parameters must also
be set before initialization.
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Detailed Function Description
4. Issues an HSR (Host Service Request) type %10 to one of the
3SinDtXor_R channels to initialize all 3SinDtXor_R and 3SinDtXor_T
channels. Issues an HSR type %10 to the 3SinDtXor_sync channel,
3SinDtXor_res channel and 3SinDtXor_fault channel, if used.
5. Enables servicing by assigning a high, middle or low priority to the
channel priority bits. All 3SinDtXor_R and 3SinDtXor_T channels must
be assigned the same priority to ensure correct operation. The CPU
must ensure that the 3SinDtXor_sync or 3SinDtXor_res channels are
initialized after the initialization of 3SinDtXor_R and 3SinDtXor_T
channels:
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–
–
–
NOTE:
assign a priority to the 3SinDtXor_R and 3SinDtXor_T channels to
enable their initialization
if a Synchronization Signal or a Resolver Reference Signal channel
is used, wait until the HSR bits are cleared to indicate that
initialization of the 3SinDtXor_R and 3SinDtXor_T channels has
completed and
assign a priority to the 3SinDtXor_sync or 3SinDtXor_res channels
to enable their initialization
A CPU routine that configures the TPU can be generated automatically using
the MPC500_Quick_Start Graphical Configuration Tool.
Detailed Function Description
3-Phase Sine Wave
Generator with
Dead-Time
Correction – XOR
version – R channels
(3SinDtXor_R)
and 3-Phase Sine
Wave Generator with
Dead-Time
Correction – XOR
version – T channels
(3SinDtXor_T)
The 3SinDtXor_R and 3SinDtXor_T TPU functions work together to generate
6 pairs of XOR gate inputs. The XOR gate outputs then produce a 6-channel
3-phase center-aligned PWM signal with dead-time between the top and
bottom channels. In order to charge the bootstrap transistors, the PWM signals
start to run 1.6ms after their initialization (at 20MHz TCR1 clock). The functions
generate signals corresponding to Reference Voltage Vector Amplitude of 0
(50% duty-cycle) until the first reloaded values are processed.
The CPU controls the PWM output by setting the TPU parameters. The Stator
Reference Voltage Vector Amplitude Ampl, the Stator Reference Voltage
Vector angle Theta (32-bit) and the angle increment dTheta (32-bit), can be
adjusted during run time. The PWM period T and the prescaler – the number of
PWM periods per reload of new values – are also read at each reload, so these
parameters can be changed during run time. Conversely, the dead-time (DT) is
not supposed to be changed during run time. The phase currents currentA,
currentB and currentC are read by the TPU asynchronously to the PWM
parameters reload. They are read in the last part of the edge-time calculation
to reflect the latest state of the phase currents. The CPU notifies the TPU that
the new reload values are prepared by setting the LD_OK parameter. The TPU
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notifies the CPU that the reload values have been read and new values can be
written by clearing the LD_OK parameter.
The TPU function rotates the Stator Reference Voltage Vector by dTheta angle
each period so that the TPU can drive the motor with constant amplitude and
constant speed independently of the CPU. The CPU can adjust the Ampl
parameter to change the Stator Reference Voltage Vector amplitude, the
dTheta parameter to change the rotation speed. The CPU can also set the
absolute value of Stator Reference Voltage Vector angle Theta. To notify the
TPU that the Theta parameter should be loaded instead of using the buffered
value, the CPU must set LD_OK = $8001 instead of $0001.
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The following equations describe how the 3-phase sine wave PWM signal hightimes htA, htB, htC and transition times ttrans of each channel are calculated:
Theta = Theta + dTheta
s A = cos (Theta )
s B = cos (Theta − 120 ° )
s C = − (s A + s B )
The function cos is calculated using a table of 32 values from the first quadrant
of one cosine wave period. The function parameter is mirrored in the first
quadrant. The function value is obtained by linear interpolation between the two
closest table values. Figure 3 shows the error of the cosine function value
calculation. The maximum error is 7 in the amplitude range <–32768, 32767>,
that is 0.021%.
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Detailed Function Description
8
6
function error
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4
2
0
-2
-4
-6
-8
0
10
20
30
40
50
60
70
80
90
angle [deg]
Figure 3. Cosine function value error
Ampl ⋅ s A + 1
2
Ampl ⋅ sB + 1
ht B = T ⋅
2
Ampl ⋅ s C + 1
ht C = T ⋅
2
ht A = T ⋅
positive current
ht A
htA
AT1
XOR
top channel
XOR
bottom channel
AT2
AB1
AB2
DT
center_time
DT
T
DT
DT
center_time
T
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negative current
ht A
ht A
AT1
XOR
top channel
XOR
bottom channel
AT2
AB1
AB2
DT
center_time
DT
DT
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T
T
Phase A:
Positive current
Negative current
– T1 channel
– T1 channel
t trans
ht
= center_time − A
2
ht
= center_time + A
2
ht A
+ DT
2
t trans = center_time +
ht A
− DT
2
– B1 channel
– B1 channel
ttrans = center_time −
– B2 channel
ttrans
t trans = center_time −
– T2 channel
– T2 channel
t trans
DT
center_time
htA
− DT
2
ht
= center_time + A + DT
2
t trans = center_time −
ht A
2
– B2 channel
t trans = center_time +
ht A
2
Phase B and Phase C similarly with htB and htC substituted to htA.
Host Interface
Written By CPU
Written by both CPU and TPU
Written By TPU
Not Used
Table 4. 3SinDtXor_T Control Bits
Name
3
2
1
0
Channel Function Select
1
0
Channel Priority
8
Options
3SinDtXor_T function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
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Detailed Function Description
Table 4. 3SinDtXor_T Control Bits
Name
1
0
Host Service Bits (HSR)
1
Options
00 – No Host Service Request
01 – Not used
10 – Not used
11 – Not used
0
Host Sequence Bits (HSQ)
xx – Not used
Channel Interrupt Enable
x – Not used
Channel Interrupt Status
x – Not used
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0
0
Table 5. 3SinDtXor_R Control Bits
Name
3
2
1
0
Channel Function Select
1
0
Channel Priority
1
0
Host Service Bits (HSR)
1
Options
3SinDtXor_R function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
00 – No Host Service Request
01 – Not used
10 – Initialization
11 – Stop
0
Host Sequence Bits (HSQ)
xx – Not used
Channel Interrupt Enable
0 – Channel Interrupt Disabled
1 – Channel Interrupt Enabled
Channel Interrupt Status
0 – Interrupt Not Asserted
1 – Interrupt Asserted
0
0
TPU function 3SinDtXor_R generates an interrupt when the current values of
Ampl, dTheta (optionaly also Theta), T and prescaler have been read by the TPU
and indicates to the CPU that it can write new variables. The CPU program can
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either wait for this interrupt to occur, or poll the LD_OK parameter to check it
has cleared. The interrupt is generated at each reload by one of the R
channels. The T channels do not generate any interrupts.
Table 6. 3SinDtXor_T and 3SinDtXor_R Parameter RAM
Phase A
B2 channel
Phase A
B1 channel
Phase A
T2 channel
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Phase A
T1 channel
Channel
10
Parameter 15 14 13 12 11 10 9 8 7 6 5
0
Ttime_AT1
state
1
2
3
prsc_copy
4
LD_OK
prescaler
5
6
7
fault_pinstate
0
Ttime_AT2
1
2
max_ht
dec
3
Theta_H
4
5
Theta_L
6
7
0
htA
B2_chan_A
1
T1_chan_A
2
3
T2_chan_A
B1a_chan_A
4
B1b_chan_A
5
6
currentA
7
0
Ttime_AB2
1
2
center_time
TA_buf
3
4
Theta_buf_H
Theta_buf_L
5
6
7
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3
2
1
0
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Detailed Function Description
Table 6. 3SinDtXor_T and 3SinDtXor_R Parameter RAM
Phase B
T2 channel
Phase B
B1 channel
Phase B
B2 channel
Phase C
T1 channel
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Phase B
T1 channel
Channel
Parameter 15 14 13 12 11 10 9 8 7 6 5
0
Ttime_BT1
1
2
F_chan
T_copy
3
Ampl
4
5
T
6
7
0
Ttime_BT2
1
2
dTheta_buf_H
dTheta_buf_L
3
dTheta_H
4
5
dTheta_L
6
7
0
htB
B2_chan_B
1
T1_chan_B
2
3
T2_chan_B
B1a_chan_B
4
B1b_chan_B
5
6
currentB
7
0
Ttime_BB2
1
2
3
4
CPU14
5
6
7
0
Ttime_CT1
1
2
3
4
DT
5
6
7
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3
2
1
0
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Table 6. 3SinDtXor_T and 3SinDtXor_R Parameter RAM
Phase C
B2 channel
Phase C
B1 channel
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Phase C
T2 channel
Channel
Parameter 15 14 13 12 11 10 9 8 7 6 5
0
Ttime_CT2
move_res
1
2
3
presc_addr_res
prescaler_res
4
5
time_res
dec_res
6
T_copy_res
7
0
htC
B2_chan_C
1
2
T1_chan_C
T2_chan_C
3
B1a_chan_C
4
5
B1b_chan_C
currentC
6
7
0
Ttime_CB2
move_sync
1
pw_sync
2
3
prescaler_sync
presc_copy_sync
4
time_sync
5
6
dec_sync
T_copy_sync
7
4
3
2
1
0
Table 7. 3SinDtXor_T and 3SinDtXor_R parameter description
Parameter
Format
Description
Parameters written by CPU
12
Ampl
16-bit fractional
Stator Reference Voltage Vector
amplitude,
positive values only!
currentA
0 or 1
0 ... positive current on phase A
1 ... negative current on phaseA
currentB
0 or 1
0 ... positive current on phase B
1 ... negative current on phaseB
currentC
0 or 1
0 ... positive current on phase C
1 ... negative current on phaseC
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Detailed Function Description
Table 7. 3SinDtXor_T and 3SinDtXor_R parameter description
Parameter
Description
32-bit fractional
Stator Ref. Voltage Vector angle
range <–1, 1) corresponds to
<–180°, 180°)
dTheta
32-bit fractional
Stator Reference Voltage Vector
angle increment
range <–1, 1) corresponds to
<–180°, 180°)
T
16-bit unsigned integer
PWM period in number of TCR1
TPU cycles
prescaler
16-bit unsigned integer
The number of PWM periods
per reload of new values
DT
16-bit unsigned integer
Dead-time in number of TCR1
TPU cycles
CPU14
16-bit unsigned integer
Time of 14 IMB clocks in TCR1
clocks.
Theta
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Format
Parameters written by both TPU and CPU
LD_OK
16-bit unsigned integer
0 ...... CPU can update
variables
<>0 .. TPU can read variables:
$0001 ... load Ampl, dTheta, T
and prescaler only
$8001 ... load also Theta
CPU sets $0001 or $8001, TPU
sets 0
Parameters written by TPU
fault_pinstate
Theta_buf
0 or 1
If fault channel is used, state of
fault pin:
0 ... low
1 ... high
32-bit fractional
Actual Stator Reference Voltage
Vector angle
range <–1, 1) corresponds to
<–180°, 180°)
Other parameters are just for TPU function inner use.
Performance
The maximum PWM frequency is 38kHz (PWM period T = 525). This can be
achieved when only 3SinDtXor_R and 3SinDtXor_T run on the TPU and the
IMB clock is 40MHz. When other functions run on the same TPU the minimum
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PWM period T has to be greater. Get all the other running function states that
can be served during one PWM period. Get their lengths (number of IMB clock
cycles) and add a time slot transition of 10 IMB clock cycles to each one. Sum
all the states lengths including the time slot transition. Convert the result from
IMB clock cycles to TCR1 clock cycles according to TCR1 prescaler settings.
The result indicates how much greater than the minimum value of 525 T has to
be for that particular case.
Table 8. 3SinDtXor_T State Statistics
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State
ST
SF
Max IMB Clock Cycles
2
2
RAM Accesses by TPU
1
0
Table 9. 3SinDtXor_R State Statistics
State
INIT
STOP
SFR0
SFR
C7
SFC0
SFC1
SFC2
SFC3
SFC4
SFC5
SFC6
NOTE:
14
Max IMB Clock Cycles
154
166
6
64
44
6
58
96
88
68
68
80
RAM Accesses by TPU
37
4
1
24
15
1
7
12
7
8
8
9
Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
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Detailed Function Description
SF
AT1
ST
SF
AT2
SF
ST
ST
SF
ST
Phase A
SFR0
AB1
C7
SF
AB2
SF
BT1
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SFR0
ST
SF
ST
SF
BT2
C7
SF
ST
ST
ST
SF
ST
Phase B
SFR0
BB1
SFR0
C7
SF
BB2
SF
CT1
ST
SF
ST
SF
SF
CT2
C7
ST
ST
ST
SF
ST
Phase C
CB1
SFR SFC SFC SFC SFC
SFR SFC SFC SFC SFC SFC
C7
C7
flag1 = 1
SF
CB2
flag0 = 1
ST
SF
center_time
not a reload period
center_time
a reload period
T
T
ST
link service request
Figure 4. 3SinDtXor_T and 3SinDtXor_R timing
NOTE:
The R channel with the momentary earliest transition within the PWM period is
marked by a flag1 and runs the SFR and SFC states.
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SF
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SF
ST
ST
ST
SF
ST
flag0 = 1
link
Figure 5. 3SinDtXor_T state diagram and 3 cases of timing
NOTE:
16
The case that happens is determined by the time when the link comes.
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Detailed Function Description
SFR
SFC
6th-time
C7
5-times
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INIT
STOP
HSR = 10
HSR = 11
SFC0
C7
SFR0
flag1 = 0
flag1 = 1 – channel with momentary longest high-time
Figure 6. 3SinDtXor_R state diagram
Synchronization
signal for 3-Phase
Sine Wave
Generator with
Dead-Time
Correction – XOR
version
(3SinDtXor_sync)
The 3SinDtXor_sync TPU function uses information obtained from
3SinDtXor_R and 3SinDtXor_T functions, the actual PWM center times and the
PWM periods. This allows a signal to be generated, which tracks the changes
in the PWM period and is always synchronized with the PWM. The
synchronization signal is a positive pulse generated repeatedly after the
prescaler PWM periods. The low to high transition of the pulse can be adjusted
by a parameter, either negative or positive, to go a number of TCR1 TPU cycles
before or after the PWM period center time. The pulse width pw is another
synchronization signal parameter.
The 3SinDtXor_sync parameters are placed on the CB2 channel to keep the
channel parameter space free, available for the table of cosine values.
3Sin with Dead-Time Correction – XOR version TPU Function Set (3SinDtXor)
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move > 0
prescaler = 1
pw
|move|
center_time
center_time
T
T
move < 0
prescaler = 2
Freescale Semiconductor, Inc...
pw
|move|
center_time
center_time
center_time
T
T
T
Figure 7. Synchronization signal adjustment examples
Synchronized Change
of PWM Prescaler
And Synchronization
Signal Prescaler
The 3SinDtXor_sync TPU function actually uses the presc_copy parameter
instead of the prescaler parameter. The prescaler parameter holds the
prescaler value that is copied to the presc_copy by the 3SinDtXor_R function
at the time the PWM parameters are reloaded. This ensures that new prescaler
values for the PWM signals, as well as the synchronization signal, are applied
at the same time.
Host Interface
Written By CPU
Written by both CPU and TPU
Written By TPU
Not Used
Table 10. 3SinDtXor_sync Control Bits
Name
3
2
1
0
Channel Function Select
1
0
Channel Priority
1
0
Host Service Bits (HSR)
18
Options
3SinDtXor_sync function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
00 – No Host Service Request
01 – Not used
10 – Initialization
11 – Not used
3Sin with Dead-Time Correction – XOR version TPU Function Set (3SinDtXor)
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Detailed Function Description
Table 10. 3SinDtXor_sync Control Bits
Name
1
Options
0
Host Sequence Bits (HSQ)
xx – Not used
Channel Interrupt Enable
0 – Channel Interrupt Disabled
1 – Channel Interrupt Enabled
Channel Interrupt Status
0 – Interrupt Not Asserted
1 – Interrupt Asserted
0
TPU function 3SinDtXor_sync generates an interrupt after each low to high
transition.
Table 11. 3SinDtXor_sync Parameter RAM
Channel
Synchronization channel
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0
Parameter 15 14 13 12 11 10 9
0
1
2
3
4
5
6
8
7
6
5
4
3
2
1
0
7
Table 12. 3SinDtXor_sync parameter description
Parameter
Format
Description
Parameters written by CPU
move
16-bit signed integer
The number of TCR1 TPU cycles
to forego (negative) or come after
(positive) the PWM period center
time
pw
16-bit unsigned integer
Synchronization pulse width in
number of TCR1 TPU cycles.
prescaler
16-bit unsigned integer
The number of PWM periods per
synchronization pulse
Parameters written by TPU
3Sin with Dead-Time Correction – XOR version TPU Function Set (3SinDtXor)
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Table 12. 3SinDtXor_sync parameter description
Parameter
Format
Description
Other parameters are just for TPU function inner use.
Performance
There is one limitation. The absolute value of parameter move has to be less
than a quarter of the PWM period T.
Freescale Semiconductor, Inc...
move <
T
4
Table 13. 3SinDtXor_sync State Statistics
State
INIT
S1
S2
S3
NOTE:
S1
Max IMB Clock Cycles
14
14
10
18
RAM Accesses by TPU
5
6
3
7
Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
S2
S3
S1
center_time
center_time
center_time
T
T
T
Figure 8. 3SinDtXor_sync timing
20
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S2
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Detailed Function Description
HSR = 10
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INIT
S1
S2
S3
Figure 9. 3SinDtXor_sync state diagram
Resolver Reference
Signal for 3-Phase
Sine Wave
Generator with
Dead-Time
Correction – XOR
version
(3SinDtXor_res)
The 3SinDtXor_res TPU function uses information read from the 3SinDtXor_R
and 3SinDtXor_T functions, the actual PWM center times and the PWM
periods. This allows a signal to be generated, which tracks the changes of the
PWM period and is always synchronized with the PWM. The resolver reference
signal is a 50% duty-cycle signal with a period equal to prescaler or
synchronization channel presc_copy PWM periods (see next paragraph). The
low to high transition of the pulse can be adjusted by a parameter, either
negative or positive, to go a number of TCR1 TPU cycles before or after the
PWM period center time.
The 3SinDtXor_res parameters are placed on the CT2 channel to keep the
channel parameter space free, available for the table of cosine values.
3Sin with Dead-Time Correction – XOR version TPU Function Set (3SinDtXor)
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move > 0
prescaler = 1
|move|
center_time
center_time
T
T
center_time
center_time
center_time
T
T
T
Freescale Semiconductor, Inc...
move < 0
prescaler = 2
|move|
Figure 10. Resolver reference signal adjustment examples
Synchronized Change
of PWM Prescaler
And Resolver
Reference Signal
Prescaler
The 3SinDtXor_res TPU function can inherit the Synchronization Signal
prescaler that is synchronously changed with the PWM prescaler. Write the
synchronization signals presc_copy parameter address to the presc_addr
parameter to enable this mechanism. Write 0 to disable it, and in this case set
the prescaler parameter to directly specify prescaler value.
Host Interface
Written By CPU
Written by both CPU and TPU
Written By TPU
Not Used
Table 14. 3SinDtXor_res Control Bits
Name
3
2
1
0
Channel Function Select
1
0
Channel Priority
1
0
Host Service Bits (HSR)
22
Options
3SinDtXor_res function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
00 – No Host Service Request
01 – Not used
10 – Initialization
11 – Not used
3Sin with Dead-Time Correction – XOR version TPU Function Set (3SinDtXor)
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Detailed Function Description
Table 14. 3SinDtXor_res Control Bits
Name
1
Options
0
Host Sequence Bits (HSQ)
xx – Not used
Channel Interrupt Enable
x – Not used
Channel Interrupt Status
x – Not used
0
Table 15. 3SinDtXor_res Parameter RAM
Channel
Resolver
Freescale Semiconductor, Inc...
0
Parameter 15 14 13 12 11 10 9
0
1
2
3
4
5
6
7
8
7
6
5
4
3
2
1
0
Table 16. 3SinDtXor_res parameter description
Parameter
Format
Description
Parameters written by CPU
move
presc_addr
16-bit signed integer
The number of TCR1 TPU cycles
to forego (negative) or come after
(positive) the PWM period center
time
16-bit unsigned integer
$00X8, where X is a number of
CB2 channel, to inherit Sync.
channel prescaler
or
$0000 to enable direct specification
of prescaler value in prescaler
parameter
3Sin with Dead-Time Correction – XOR version TPU Function Set (3SinDtXor)
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Table 16. 3SinDtXor_res parameter description
Parameter
prescaler
Format
Description
The number of PWM periods per
synchronization pulse
– use when presc_addr = 0
1, 2, 4, 6, 8, 10, 12, 14, ...
Parameters written by TPU
Freescale Semiconductor, Inc...
Other parameters are just for TPU function inner use.
Performance
There is one limitation. The absolute value of parameter move has to be less
than a quarter of the PWM period T.
move <
T
4
Table 17. 3SinDtXor_res State Statistics
State
INIT
S1
S3
NOTE:
S1
Max IMB Clock Cycles
14
28
20
RAM Accesses by TPU
5
9
7
Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
S3
S1
center_time
center_time
center_time
T
T
T
Figure 11. 3SinDtXor_res timing
24
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Detailed Function Description
HSR = 10
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INIT
S1
S3
Figure 12. 3SinDtXor_res state diagram
Fault Input for 3Phase Sine Wave
Generator with
Dead-Time
Correction – XOR
version
(3SinDtXor_fault)
The 3SinDtXor_fault is an input TPU function that monitors the pin, and if a high
to low transition occurs, immediately sets all PWM channels low and cancels
all further transitions on them. The PWM channels, as well as the
synchronization and resolver reference signal channels (if used), have to be
initialized again to start them running.
The function returns the actual pinstate as a value of 0 (low) or 1 (high) in the
parameter fault_pinstate. The parameter is placed on the AT1 channel to keep
the fault channel parameter space free.
Host Interface
Written By CPU
Written by both CPU and TPU
Written By TPU
Not Used
Table 18. 3SinDtXor_fault Control Bits
3
2
1
Name
0 Channel Function Select
1
0 Channel Priority
Options
3SinDtXor_fault function number
(Assigned during assembly the
DPTRAM code from library TPU
functions)
00 – Channel Disabled
01 – Low Priority
10 – Middle Priority
11 – High Priority
3Sin with Dead-Time Correction – XOR version TPU Function Set (3SinDtXor)
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Table 18. 3SinDtXor_fault Control Bits
1
Name
0 Host Service Bits (HSR)
1
0 Host Sequence Bits (HSQ)
Options
00 – No Host Service Request
01 – Not used
10 – Initialization
11 – Not used
xx – Not used
0 Channel Interrupt Enable
0 – Channel Interrupt Disabled
1 – Channel Interrupt Enabled
0 Channel Interrupt Status
0 – Interrupt Not Asserted
1 – Interrupt Asserted
TPU function 3SinDtXor_fault generates an interrupt when a high to low
transition appears.
Table 19. 3SinDtXor_fault Parameter RAM
Fault input
Channel
Parameter 15 14 13 12 11 10 9
0
1
2
3
4
5
6
7
8
7
6
5
4
3
Table 20. 3SinDtXor_fault parameter description
Parameter
Format
Description
Parameters written by TPU
fault_pinstate
26
0 or 1
State of fault pin:
0 ... low
1 ... high
3Sin with Dead-Time Correction – XOR version TPU Function Set (3SinDtXor)
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1
0
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Detailed Function Description
Performance
Table 21. 3SinDtXor_fault State Statistics
State
INIT
FAULT
NO_FAULT
Freescale Semiconductor, Inc...
NOTE:
Max IMB Clock Cycles
8
172
4
RAM Accesses by TPU
2
5
1
Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
NO_FAULT
FAULT
Figure 13. 3SinDtXor_fault timing
HSR = 10
INIT
FAULT
NO_FAULT
Figure 14. 3SinDtXor_fault state diagram
3Sin with Dead-Time Correction – XOR version TPU Function Set (3SinDtXor)
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AN2519/D
Rev. 0
5/2003
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