Low Voltage, 1.15 V to 5.5 V, 8-Channel Bidirectional Logic Level Translators ADG3308/ADG3308-1 FEATURES FUNCTIONAL BLOCK DIAGRAM VCCA Bidirectional logic level translation Operates from 1.15 V to 5.5 V Low quiescent current < 1 μA No direction pin VCCY A1 Y1 APPLICATIONS A2 Y2 Low voltage ASIC level translation Smart card readers Cell phones and cell phone cradles Portable communication devices Telecommunications equipment Network switches and routers Storage systems (SAN/NAS) Computing/server applications GPS Portable POS systems Low cost serial interfaces A3 Y3 A4 Y4 A5 Y5 A6 Y6 A7 Y7 A8 Y8 EN GND 04865-001 ADG3308/ADG3308-1/ ADG3308-2 Figure 1. GENERAL DESCRIPTION The ADG3308/ADG3308-1/ADG3308-2 are bidirectional level translators containing eight bidirectional channels. They can be used in multivoltage digital system applications, such as a data transfer between a low voltage DSP controller and a higher voltage device. The internal architecture allows the device to perform bidirectional level translation without an additional signal to set the direction in which the translation takes place. The voltage applied to VCCA sets the logic levels on the A side of the device, and VCCY sets the levels on the Y side. For proper operation, VCCA must always be less than VCCY. The VCCA compatible logic signals applied to the A side of the device appear as VCCY compatible levels on the Y side. Similarly, VCCY compatible logic levels applied to the Y side of the device appear as VCCA compatible logic levels on the A side. The enable pin (EN) provides three-state operation on both the A side and the Y side pins. When the EN pin is pulled low, the terminals on both sides of the device are in the high impedance state. For normal operation, EN should be driven high. The ADG3308 is available in a compact 20-lead TSSOP and a 20-lead LFCSP, the ADG3308-1 is available in a 20-ball WLCSP, and the ADG3308-2 is available in a backside-coated 20-ball WLCSP. The EN pin is referred to the VCCY supply voltage for the ADG3308 and to the VCCA supply voltage for the ADG3308-1 and ADG3308-2. The ADG3308/ADG3308-1/ADG3308-2 are guaranteed to operate over the 1.15 V to 5.5 V supply voltage range and the extended −40°C to +85°C temperature range. PRODUCT HIGHLIGHTS 1. Bidirectional logic level translation. 2. Fully guaranteed over the 1.15 V to 5.5 V supply range. 3. No direction pin. 4. Packages: 20-lead TSSOP and 20-lead LFCSP (ADG3308), 20-ball WLCSP (ADG3308-1), and backside-coated 20-ball WLCSP (ADG3308-2). Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved. ADG3308/ADG3308-1 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 16 Applications....................................................................................... 1 Level Translator Architecture ................................................... 16 Functional Block Diagram .............................................................. 1 Input Driving Requirements..................................................... 16 General Description ......................................................................... 1 Output Load Requirements ...................................................... 16 Product Highlights ........................................................................... 1 Enable Operation ....................................................................... 16 Revision History ............................................................................... 2 Power Supplies............................................................................ 16 Specifications..................................................................................... 3 Data Rate ..................................................................................... 17 Absolute Maximum Ratings............................................................ 6 Applications..................................................................................... 18 ESD Caution.................................................................................. 6 Layout Guidelines....................................................................... 18 Pin Configurations and Function Descriptions ........................... 7 Outline Dimensions ....................................................................... 19 Typical Performance Characteristics ............................................. 8 Ordering Guide .......................................................................... 20 Test Circuits..................................................................................... 12 Terminology .................................................................................... 15 REVISION HISTORY 9/07—Rev. B to Rev. C Updated Outline Dimensions ....................................................... 19 7/07—Rev. A to Rev. B Added Backside-Coated WLCSP Package ......................Universal Changes to Input Driving Requirements Section ...................... 16 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 7/06—Rev. 0 to Rev. A Added WLCSP Package…………………………..……Universal Added Figure 4………………………………………………......7 Updated Outline Dimensions……………………………….…19 Changes to Ordering Guide………………………………....…19 1/05—Revision 0: Initial Version Rev. C | Page 2 of 20 ADG3308/ADG3308-1 SPECIFICATIONS VCCY = 1.65 V to 5.5 V, VCCA = 1.15 V to VCCY, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted. 1 Table 1. Parameter LOGIC INPUTS/OUTPUTS A Side Input High Voltage 3 Input Low Voltage3 Output High Voltage Output Low Voltage Capacitance3 Leakage Current Y Side Input High Voltage3 Input Low Voltage3 Output High Voltage Output Low Voltage Capacitance3 Leakage Current Enable (EN) Input High Voltage3 ADG3308 (TSSOP, LFCSP) ADG3308-1/ADG3308-2 (WLCSP) Input Low Voltage3 ADG3308 (TSSOP, LFCSP) ADG3308-1/ADG3308-2 (WLCSP) Leakage Current Capacitance3 Enable Time3 SWITCHING CHARACTERISTICS3 3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V A→Y Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y→A Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Symbol Conditions Min VIHA VIHA VILA VOHA VOLA CA ILA, HIGH-Z VCCA = 1.15 V VCCA = 1.2 V to 5.5 V VCCA − 0.3 0.65 × VCCA VY = VCCY, IOH = 20 μA, see Figure 29 VY = 0 V, IOL = 20 μA, see Figure 29 f = 1 MHz, EN = 0, see Figure 34 VA = 0 V or VCCA, EN = 0, see Figure 31 VCCA − 0.4 VIHY VILY VOHY VOLY CY ILY, HIGH-Z Typ 2 Max 0.35 × VCCA 0.4 10 ±1 0.65 × VCCY 0.35 × VCCY VA = VCCA, IOH = 20 μA, see Figure 30 VA = 0 V, IOL = 20 μA, see Figure 30 f = 1 MHz, EN = 0, see Figure 35 VY = 0 V or VCCY, EN = 0, see Figure 32 VCCY − 0.4 0.4 6.8 ±1 Unit V V V V V pF μA V V V V pF μA VIHEN VCCA = 1.15 V VCCA = 1.2 V to 5.5 V 0.65 × VCCY VCCA − 0.3 0.65 × VCCA V V V VILEN ILEN CEN tEN 0.35 × VCCY 0.35 × VCCA ±1 VEN = 0 V or VCCY, VA = 0 V, see Figure 33 RS = RT = 50 Ω, VA = 0 V or VCCA (A→Y), VY = 0 V or VCCY (Y→A), see Figure 36 V V μA pF μs 4.5 1 1.8 6 2 2 10 3.5 3.5 2 4 3 ns ns ns Mbps ns ns 4 1 7 3 ns ns 3 7 2 3.5 2 ns Mbps ns ns RS = RT = 50 Ω, CL = 50 pF, see Figure 37 tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tSKEW, A→Y tPPSKEW, A→Y 50 RS = RT = 50 Ω, CL = 15 pF, see Figure 38 tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tSKEW, Y→A tPPSKEW, Y→A 50 Rev. C | Page 3 of 20 ADG3308/ADG3308-1 Parameter 1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A→Y Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y→A Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew 1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A→Y Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y→A Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew 1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 1.8 V ± 0.3 V A→Y Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y→A Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Symbol Conditions Min Typ 2 Max Unit 8 2 2 11 5 5 2 4 4 ns ns ns Mbps ns ns 5 2 2 8 3.5 3.5 2 3 3 9 3 2 18 5 5 2 5 10 5 2 2 9 4 4 2 4 4 12 7 3 25 12 5 2 5 15 14 5 2.5 35 16 6.5 3 6.5 23.5 RS = RT = 50 Ω, CL = 50 pF, see Figure 37 tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tSKEW, A→Y tPPSKEW, A→Y 50 RS = RT = 50 Ω, CL = 15 pF, see Figure 38 tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tSKEW, Y→A 50 tPPSKEW, Y→A ns ns ns Mbps ns ns RS = RT = 50 Ω, CL = 50 pF, see Figure 37 tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tSKEW, A→Y tPPSKEW, A→Y 40 ns ns ns Mbps ns ns RS = RT = 50 Ω, CL = 15 pF, see Figure 38 tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tSKEW, Y→A tPPSKEW, Y→A 40 ns ns ns Mbps ns ns RS = RT = 50 Ω, CL = 50 pF, see Figure 37 tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tSKEW, A→Y tPPSKEW, A→Y 25 ns ns ns Mbps ns ns RS = RT = 50 Ω, CL = 15 pF, see Figure 38 tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tSKEW, Y→A tPPSKEW, Y→A 25 Rev. C | Page 4 of 20 ns ns ns Mbps ns ns ADG3308/ADG3308-1 Parameter 2.5 V ± 0.2 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A→Y Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew Y→A Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Channel-to-Channel Skew Part-to-Part Skew POWER REQUIREMENTS Power Supply Voltages Quiescent Power Supply Current Symbol Min Typ 2 Max Unit 7 2.5 2 10 4 5 1.5 2 4 ns ns ns Mbps ns ns 5 1 3 8 4 5 2 3 3 ns ns ns Mbps ns ns 0.17 5.5 5.5 1 V V μA 0.27 1 μA 0.1 0.1 1 1 μA μA RS = RT = 50 Ω, CL = 50 pF, see Figure 37 tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tSKEW, A→Y tPPSKEW, A→Y 60 RS = RT = 50 Ω, CL = 15 pF, see Figure 38 tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tSKEW, Y→A 60 tPPSKEW, Y→A VCCA VCCY ICCA ICCY Three-State Mode Power Supply Current Conditions IHIGH-ZA IHIGH-ZY VCCA ≤ VCCY VA = 0 V or VCCA, VY = 0 V or VCCY, VCCA = VCCY = 5.5 V, EN = VCCY VA = 0 V or VCCA, VY = 0 V or VCCY, VCCA = VCCY = 5.5 V, EN = VCCY VCCA = VCCY = 5.5 V, EN = 0 VCCA = VCCY = 5.5 V, EN = 0 1 Temperature range is −40°C to +85°C (B Version) for the TSSOP, the LFCSP, the WLCSP, and the backside-coated WLCSP. All typical values are at TA = 25°C, unless otherwise noted. 3 Guaranteed by design; not subject to production test. 2 Rev. C | Page 5 of 20 1.15 1.65 ADG3308/ADG3308-1 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2. Parameter VCCA to GND VCCY to GND Digital Inputs (A) Digital Inputs (Y) EN to GND Operating Temperature Range Extended Industrial Range (B Version) Storage Temperature Range Junction Temperature θJA Thermal Impedance 20-Lead TSSOP 20-Lead LFCSP 20-Ball WLCSP 20-Ball Backside-Coated WLCSP Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature (<20 sec) Rating −0.3 V to +7 V VCCA to +7 V −0.3 V to (VCCA + 0.3 V) −0.3 V to (VCCY + 0.3 V) −0.3 V to +7 V −40°C to +85°C −65°C to +150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. ESD CAUTION 78°C/W 30.4°C/W 100°C/W 100°C/W 300°C 260°C (+0°C/−5°C) Rev. C | Page 6 of 20 ADG3308/ADG3308-1 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADG3308 17 Y3 A4 5 TOP VIEW (Not to Scale) 16 Y4 A5 6 15 Y5 A6 7 14 Y6 A7 8 13 Y7 A8 9 12 Y8 EN 10 11 GND A2 A3 A4 A5 A6 1 2 3 4 5 ADG3308 TOP VIEW (Not to Scale) 15 14 13 12 11 Y3 Y4 Y5 Y6 Y7 2 3 4 a VCCY Y1 A1 VCCA b Y2 Y3 A3 A2 c Y4 Y5 A5 A4 d Y6 Y7 A7 A6 e Y8 GND EN A8 THE EXPOSED PAD CAN BE TIED TO GND OR IT CAN BE LEFT FLOATING. DO NOT TIE IT TO VCCA OR VCCY . ADG3308-1/ ADG3308-2 TOP VIEW (Not to Scale) (BALLS AT THE BOTTOM) Figure 2. 20-Lead TSSOP Figure 3. 20-Lead LFCSP Figure 4. 20-Ball WLCSP Table 3. Pin Function Descriptions TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin/Ball No. LFCSP WLCSP 19 a4 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 a3 b4 b3 c4 c3 d4 d3 e4 e3 e2 e1 d2 d1 c2 c1 b2 b1 a2 a1 Mnemonic VCCA A1 A2 A3 A4 A5 A6 A7 A8 EN GND Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 VCCY Description Power Supply. Power supply voltage input for the A1 I/O pin to the A8 I/O pin (1.15 V ≤ VCCA < VCCY). Input/Output A1. Referenced to VCCA. Input/Output A2. Referenced to VCCA. Input/Output A3. Referenced to VCCA. Input/Output A4. Referenced to VCCA. Input/Output A5. Referenced to VCCA. Input/Output A6. Referenced to VCCA. Input/Output A7. Referenced to VCCA. Input/Output A8. Referenced to VCCA. Active High Enable Input. Ground. Input/Output Y8. Referenced to VCCY. Input/Output Y7. Referenced to VCCY. Input/Output Y6. Referenced to VCCY. Input/Output Y5. Referenced to VCCY. Input/Output Y4. Referenced to VCCY. Input/Output Y3. Referenced to VCCY. Input/Output Y2. Referenced to VCCY. Input/Output Y1. Referenced to VCCY. Power Supply. Power supply voltage input for the Y1 I/O pin to the Y8 I/O pin (1.65 V ≤ VCCY ≤ 5.5 V). Rev. C | Page 7 of 20 04865-057 A3 4 PIN 1 INDICATOR 04865-003 18 Y2 1 6 7 8 9 10 19 Y1 A2 3 A7 A8 EN GND Y8 A1 2 20 19 18 17 16 20 VCCY 1 04865-002 VCCA A1 VCCA VCCY Y1 Y2 BALL a1 INDICATOR ADG3308/ADG3308-1 TYPICAL PERFORMANCE CHARACTERISTICS 3.0 1.0 TA = 25°C 1 CHANNEL 0.9 CL = 50pF 2.5 0.8 VCCA = 3.3V, VCCY = 5V 0.7 2.0 0.6 ICCY (mA) ICCA (mA) TA = 25°C 1 CHANNEL CL = 15pF 0.5 0.4 VCCA = 1.8V, VCCY = 3.3V 0.3 VCCA = 3.3V, VCCY = 5V 1.5 1.0 VCCA = 1.8V, VCCY = 3.3V 0.2 0.5 0.1 5 10 15 20 25 30 35 DATA RATE (Mbps) 40 45 0 04865-004 0 50 VCCA = 1.2V, VCCY = 1.8V 0 1.6 VCCA = 3.3V, VCCY = 5V 6 ICCY (mA) 30 35 40 45 50 20Mbps 5 4 0.8 10Mbps 0.6 VCCA = 1.8V, VCCY = 3.3V 3 1.0 0.4 2 VCCA = 1.2V, VCCY = 1.8V 1 5Mbps 0.2 10 15 20 25 30 35 DATA RATE (Mbps) 40 45 50 0 13 1.0 0.8 VCCA = 3.3V, VCCY = 5V ICCA (mA) 1.5 1.0 0.6 20Mbps 0.4 10Mbps 0.2 VCCA = 1.2V, VCCY = 1.8V 10 15 20 25 30 35 40 5Mbps 0.1 45 DATA RATE (Mbps) 50 04865-006 5 73 0.5 0.3 VCCA = 1.8V, VCCY = 3.3V 0 63 0.7 2.0 0 53 TA = 25°C 1 CHANNEL VCCA = 1.2V VCCY = 1.8V 0.9 0.5 43 Figure 9. ICCY vs. Capacitive Load at Pin Y for A→Y (1.2 V→1.8 V) Level Translation TA = 25°C 1 CHANNEL CL = 15pF 2.5 33 CAPACITIVE LOAD (pF) Figure 6. ICCY vs. Data Rate (A→Y Level Translation) 3.0 23 04865-012 5 04865-005 1Mbps 0 0 1Mbps 13 23 33 43 CAPACITIVE LOAD (pF) Figure 10. ICCA vs. Capacitive Load at Pin A for Y→A (1.8 V→1.2 V) Level Translation Figure 7. ICCA vs. Data Rate (Y→A Level Translation) Rev. C | Page 8 of 20 53 04865-013 ICCY (mA) 25 1.2 7 ICCA (mA) 20 TA = 25°C 1 CHANNEL VCCA = 1.2V VCCY = 1.8V 1.4 8 0 15 Figure 8. ICCY vs. Data Rate (Y→A Level Translation) TA = 25°C 1 CHANNEL CL = 50pF 9 10 DATA RATE (Mbps) Figure 5. ICCA vs. Data Rate (A→Y Level Translation) 10 5 04865-007 VCCA = 1.2V, VCCY = 1.8V 0 ADG3308/ADG3308-1 9 7 TA = 25°C 1 CHANNEL VCCA = 1.8V VCCY = 3.3V 8 7 TA = 25°C 1 CHANNEL 6 VCCA = 3.3V VCCY = 5V 50Mbps 50Mbps 5 ICCA (mA) ICCY (mA) 6 5 30Mbps 4 3 4 30Mbps 3 20Mbps 20Mbps 2 10Mbps 10Mbps 1 1 5Mbps 23 33 43 53 CAPACITIVE LOAD (pF) 63 73 0 04865-016 13 Figure 11. ICCY vs. Capacitive Load at Pin Y for A→Y (1.8 V→3.3 V) Level Translation 5.0 4.5 4.0 33 43 CAPACITIVE LOAD (pF) 53 Figure 14. ICCA vs. Capacitive Load at Pin A for Y→A (5 V→3.3 V) Level Translation 10 TA = 25°C 9 1 CHANNEL DATA RATE = 50kbps 8 TA = 25°C 1 CHANNEL VCCA = 1.8V VCCY = 3.3V 3.5 VCCA = 1.2V, VCCY = 1.8V 7 50Mbps 3.0 RISE TIME (ns) ICCA (mA) 23 2.5 2.0 30Mbps 1.5 6 5 4 VCCA = 1.8V, VCCY = 3.3V 3 20Mbps 1.0 2 VCCA = 3.3V, VCCY = 5V 10Mbps 0.5 1 5Mbps 23 33 43 CAPACITIVE LOAD (pF) 53 0 13 04865-017 0 13 Figure 12. ICCA vs. Capacitive Load at Pin A for Y→A (3.3 V→1.8 V) Level Translation 33 43 53 CAPACITIVE LOAD (pF) 63 73 Figure 15. Rise Time vs. Capacitive Load at Pin Y (A→Y Level Translation) 4.0 12 TA = 25°C 1 CHANNEL VCCA = 3.3V 10 V CCY = 5V 23 04865-023 0 13 5Mbps 04865-021 2 50Mbps 3.5 TA = 25°C 1 CHANNEL DATA RATE = 50kbps VCCA = 1.2V, VCCY = 1.8V 3.0 FALL TIME (ns) 30Mbps 6 20Mbps 4 2 VCCA = 1.8V, VCCY = 3.3V 2.0 1.5 VCCA = 3.3V, VCCY = 5V 0.5 5Mbps 23 33 43 53 CAPACITIVE LOAD (pF) 63 Figure 13. ICCY vs. Capacitive Load at Pin Y for A→Y (3.3 V→5 V) Level Translation 73 0 13 23 33 43 53 CAPACITIVE LOAD (pF) 63 73 04865-024 0 13 2.5 1.0 10Mbps 04865-020 ICCY (mA) 8 Figure 16. Fall Time vs. Capacitive Load at Pin Y (A→Y Level Translation) Rev. C | Page 9 of 20 ADG3308/ADG3308-1 12 10 TA = 25°C 9 1 CHANNEL DATA RATE = 50kbps 8 10 PROPAGATION DELAY (ns) VCCA = 1.2V, VCCY = 1.8V 6 5 4 VCCA = 1.8V, VCCY = 3.3V 3 2 8 6 VCCA = 1.8V, VCCY = 3.3V 4 2 1 28 33 38 43 48 53 0 13 33 43 53 63 73 CAPACITIVE LOAD (pF) Figure 20. Propagation Delay (tPHL) vs. Capacitive Load at Pin Y (A→Y Level Translation) Figure 17. Rise Time vs. Capacitive Load at Pin A (Y→A Level Translation) 9 4.0 TA = 25°C 8 1 CHANNEL DATA RATE = 50kbps PROPAGATION DELAY (ns) 3.0 2.5 VCCA = 1.2V, VCCY = 1.8V 2.0 VCCA = 1.8V, VCCY = 3.3V 1.5 VCCA = 3.3V, VCCY = 5V 1.0 0.5 7 VCCA = 1.2V, VCCY = 1.8V 6 5 4 3 VCCA = 1.8V, VCCY = 3.3V 2 VCCA = 3.3V, VCCY = 5V 1 18 23 28 33 38 43 CAPACITIVE LOAD (pF) 48 53 0 13 04865-026 13 23 28 33 38 43 48 53 CAPACITIVE LOAD (pF) Figure 21. Propagation Delay (tPLH) vs. Capacitive Load at Pin A (Y→A Level Translation) Figure 18. Fall Time vs. Capacitive Load at Pin A (Y→A Level Translation) 9 14 TA = 25°C 1 CHANNEL 8 DATA RATE = 50kbps TA = 25°C 1 CHANNEL 12 DATA RATE = 50kbps PROPAGATION DELAY (ns) VCCA = 1.2V, VCCY = 1.8V 10 8 6 18 04865-029 TA = 25°C 1 CHANNEL 3.5 DATA RATE = 50kbps FALL TIME (ns) 23 04865-028 23 04865-025 18 CAPACITIVE LOAD (pF) VCCA = 1.8V, VCCY = 3.3V 4 VCCA = 3.3V, VCCY = 5V 2 VCCA = 1.2V, VCCY = 1.8V 7 6 5 4 VCCA = 1.8V, VCCY = 3.3V 3 VCCA = 3.3V, VCCY = 5V 2 1 0 13 23 33 43 53 CAPACITIVE LOAD (pF) 63 73 0 04865-027 PROPAGATION DELAY (ns) VCCA = 3.3V, VCCY = 5V VCCA = 3.3V, VCCY = 5V 0 13 0 VCCA = 1.2V, VCCY = 1.8V Figure 19. Propagation Delay (tPLH) vs. Capacitive Load at Pin Y (A→Y Level Translation) 13 18 23 28 33 38 43 CAPACITIVE LOAD (pF) 48 53 Figure 22. Propagation Delay (tPHL) vs. Capacitive Load at Pin A (Y→A Level Translation) Rev. C | Page 10 of 20 04865-030 RISE TIME (ns) 7 TA = 25°C 1 CHANNEL DATA RATE = 50kbps ADG3308/ADG3308-1 TA = 25°C DATA RATE = 25Mbps CL = 50pF 1 CHANNEL 400mV/DIV Figure 23. Eye Diagram at Y Output (1.2 V→1.8 V Level Translation, 25 Mbps) CL = 50pF 1 CHANNEL 5ns/DIV TA = 25°C DATA RATE = 50Mbps CL = 50pF 1 CHANNEL 1V/DIV Figure 24. Eye Diagram at A Output (1.8 V→1.2 V Level Translation, 25 Mbps) 500mV/DIV Figure 27. Eye Diagram at Y Output (3.3 V→5 V Level Translation, 50 Mbps) TA = 25°C DATA RATE = 50Mbps CL = 15pF 1 CHANNEL CL = 50pF 1 CHANNEL 3ns/DIV 04865-039 TA = 25°C DATA RATE = 50Mbps 3ns/DIV 04865-041 200mV/DIV Figure 26. Eye Diagram at A Output (3.3 V→1.8 V Level Translation, 50 Mbps) 04865-038 TA = 25°C DATA RATE = 25Mbps 3ns/DIV 800mV/DIV Figure 25. Eye Diagram at Y Output (1.8 V→3.3 V Level Translation, 50 Mbps) 3ns/DIV Figure 28. Eye Diagram at A Output (5 V→3.3 V Level Translation, 50 Mbps) Rev. C | Page 11 of 20 04865-042 5ns/DIV 04865-040 04865-037 400mV/DIV TA = 25°C DATA RATE = 50Mbps CL = 15pF 1 CHANNEL ADG3308/ADG3308-1 TEST CIRCUITS EN ADG3308/ ADG3308-1 / ADG3308-2 VCCA 0.1µF VCCY VCCA 0.1µF 0.1µF Ax ADG3308/ ADG3308-1 / ADG3308-2 VCCY 0.1µF Yx K2 Yx Ax K1 GND EN IOH K A 04865-047 GND 04865-043 IOL Figure 29. VOH/VOL Voltages at Pin A ADG3308/ ADG3308-1 / ADG3308-2 VCCA 0.1µF K2 Ax Figure 33. EN Pin Leakage Current EN VCCY VCCA 0.1µF ADG3308/ ADG3308-1 / ADG3308-2 EN VCCY Yx Ax Yx K1 GND CAPACITANCE METER GND 04865-048 IOH 04865-044 IOL Figure 30. VOH/VOL Voltages at Pin Y VCCA 0.1µF EN ADG3308/ ADG3308-1 / ADG3308-2 VCCA VCCY ADG3308/ ADG3308-1 / ADG3308-2 EN VCCY 0.1µF Ax A Figure 34. Capacitance at Pin A Yx Ax Yx K Figure 31. Three-State Leakage Current at Pin A VCCA 0.1µF ADG3308/ ADG3308-1 / ADG3308-2 Figure 35. Capacitance at Pin Y EN VCCY 0.1µF Yx A GND K 04865-046 Ax GND Figure 32. Three-State Leakage Current at Pin Y Rev. C | Page 12 of 20 CAPACITANCE METER 04865-049 04865-045 GND ADG3308/ADG3308-1 A→Y DIRECTION VCCA 0.1µF + 10µF ADG3308/ ADG3308-1 / ADG3308-2 VCCY + 10µF 0.1µF 1MΩ Ax VA K1 Yx VY K2 50pF 1MΩ SIGNAL SOURCE EN Z0 = 50Ω RS GND VEN RT 50Ω 50Ω Y→A DIRECTION VCCA 0.1µF + 10µF VCCY ADG3308/ ADG3308-1 / ADG3308-2 + 10µF 0.1µF 1MΩ K1 Ax VA Yx VY K2 15pF SIGNAL SOURCE 1MΩ EN Z0 = 50Ω RS GND VEN RT 50Ω 50Ω VEN tEN1 VCCY 0V VCCA /VCCY VA/VY 0V VCCY /VCCA 90% VY/VA tEN2 0V VA/VY VCCA /VCCY 0V VCCY /VCCA VY/VA 10% 0V NOTES 1. tEN IS WHICHEVER IS LARGER BETWEEN tEN1 AND tEN2 IN BOTH A→Y AND Y→A DIRECTIONS. Figure 36. Enable Time Rev. C | Page 13 of 20 04865-050 VEN 0V VCCY ADG3308/ADG3308-1 SIGNAL SOURCE RS + 10µF 0.1µF Z0 = 50Ω V A EN ADG3308/ ADG3308-1 / ADG3308-2 VCCA VCCY Ax Yx VY RT 50Ω 50Ω + 10µF 0.1µF 50pF GND VA 50% tF, A→Y 04865-051 90% 50% 10% tP, A→Y tP, A→Y VY tR, A→Y Figure 37. Switching Characteristics (A→Y Level Translation) VCCA + 0.1µF VA 10µF ADG3308/ ADG3308-1 / ADG3308-2 EN VCCY + 10µF 0.1µF Ax Yx VY Z0 = 50Ω RS 50Ω RT 50Ω 15pF SIGNAL SOURCE GND VY 50% tP, Y→A tF, Y→A tP, Y→A tR, Y→A Figure 38. Switching Characteristics (Y→A Level Translation) Rev. C | Page 14 of 20 04865-052 90% 50% 10% VA ADG3308/ADG3308-1 TERMINOLOGY DMAX, A→Y Guaranteed data rate when translating logic levels in the A→Y direction under the driving and loading conditions specified in Table 1. VIHA Logic input high voltage at Pin A1 to Pin A8. VILA Logic input low voltage at Pin A1 to Pin A8. tSKEW, A→Y Difference between propagation delays on any two channels when translating logic levels in the A→Y direction. VOHA Logic output high voltage at Pin A1 to Pin A8. VOLA Logic output low voltage at Pin A1 to Pin A8. CA Capacitance measured at Pin A1 to Pin A8 (EN = 0). tPPSKEW, A→Y Difference in propagation delay between any one channel and the same channel on a different part (under same driving/ loading conditions) when translating in the A→Y direction. ILA, HIGH-Z Leakage current at Pin A1 to Pin A8 when EN = 0 (high impedance state at Pin A1 to Pin A8). tP, Y→A Propagation delay when translating logic levels in the Y→A direction. VIHY Logic input high voltage at Pin Y1 to Pin Y8. tR, Y→A Rise time when translating logic levels in the Y→A direction. VILY Logic input low voltage at Pin Y1 to Pin Y8. tF, Y→A Fall time when translating logic levels in the Y→A direction. VOHY Logic output high voltage at Pin Y1 to Pin Y8. DMAX, Y→A Guaranteed data rate when translating logic levels in the Y→A direction under the driving and loading conditions specified in Table 1. VOLY Logic output low voltage at Pin Y1 to Pin Y8. CY Capacitance measured at Pin Y1 to Pin Y8 (EN = 0). tSKEW, Y→A Difference between propagation delays on any two channels when translating logic levels in the Y→A direction. ILY, HIGH-Z Leakage current at Pin Y1 to Pin Y8 when EN = 0 (high impedance state at Pin Y1 to Pin Y8). VIHEN Logic input high voltage at the EN pin. tPPSKEW, Y→A Difference in propagation delay between any one channel and the same channel on a different part (under same driving/ loading conditions) when translating in the Y→A direction. VILEN Logic input low voltage at the EN pin. VCCA VCCA supply voltage. CEN Capacitance measured at EN pin. VCCY VCCY supply voltage. ILEN Enable (EN) pin leakage current. ICCA VCCA supply current. tEN Three-state enable time for Pin A1 to Pin A8/Pin Y1 to Pin Y8. ICCY VCCY supply current. tP, A→Y Propagation delay when translating logic levels in the A→Y direction. IHIGH-ZA VCCA supply current during three-state mode (EN = 0). tR, A→Y Rise time when translating logic levels in the A→Y direction. IHIGH-ZY VCCY supply current during three-state mode (EN = 0). tF, A→Y Fall time when translating logic levels in the A→Y direction. Rev. C | Page 15 of 20 ADG3308/ADG3308-1 THEORY OF OPERATION The ADG3308/ADG3308-1/ADG3308-2 level translators allow the level shifting necessary for data transfer in a system where multiple supply voltages are used. The device requires two supplies, VCCA and VCCY (VCCA ≤ VCCY). These supplies set the logic levels on each side of the device. When driving the A pins, the device translates the VCCA compatible logic levels to VCCY compatible logic levels available at the Y pins. Similarly, because the device is capable of bidirectional translation, when driving the Y pins the VCCY compatible logic levels are translated to the VCCA compatible logic levels available at the A pins. When EN = 0, the A1 pin to the A8 pin and the Y1 pin to the Y8 pin are three-stated. When EN is driven high, the ADG3308/ ADG3308-1/ADG3308-2 go into normal operation mode and perform level translation. LEVEL TRANSLATOR ARCHITECTURE The ADG3308/ADG3308-1/ADG3308-2 consist of eight bidirectional channels. Each channel can translate logic levels in either the A→Y or the Y→A direction. They use a one-shot accelerator architecture, ensuring excellent switching characteristics. Figure 39 shows a simplified block diagram of a bidirectional channel. VCCA VCCY INPUT DRIVING REQUIREMENTS To ensure correct operation of the ADG3308/ADG3308-1/ ADG3308-2, the circuit that drives the input of the device should be able to ensure rise/fall times of less than 3 ns when driving a load consisting of a 6 kΩ resistor in parallel with the input capacitance of the ADG3308/ADG3308-1/ADG3308-2 channel. OUTPUT LOAD REQUIREMENTS The ADG3308/ADG3308-1/ADG3308-2 level translators are designed to drive CMOS-compatible loads. If current-driving capability is required, it is recommended to use buffers between the ADG3308/ADG3308-1/ADG3308-2 outputs and the load. ENABLE OPERATION The ADG3308/ADG3308-1/ADG3308-2 provide three-state operation at the A I/O pins and the Y I/O pins by using the enable (EN) pin, as shown in Table 4. Table 4. Truth Table EN 0 1 1 2 T1 T2 6kΩ T4 U2 ONE-SHOT GENERATOR U4 Y N U3 T3 High impedance state. In normal operation, the ADG3308/ADG3308-1/ADG3308-2 perform level translation. POWER SUPPLIES 04865-053 P A A I/O Pins High-Z1 Normal operation2 When EN = 0, the ADG3308/ADG3308-1/ADG3308-2 enter into three-state mode. In this mode, the current consumption from both the VCCA and VCCY supplies is reduced, allowing the user to save power, which is critical, especially in batteryoperated systems. The EN input pin can only be driven with VCCY compatible logic levels for the ADG3308, whereas the ADG3308-1/ADG3308-2 can be driven with either VCCA- or VCCY compatible logic levels. 6kΩ U1 Y I/O Pins High-Z1 Normal operation2 Figure 39. Simplified Block Diagram of an ADG3308/ADG3308-1/ADG3308-2 Channel The logic level translation in the A→Y direction is performed using a level translator (U1) and an inverter (U2), whereas the translation in the Y→A direction is performed using the U3 inverter and U4 inverter. The one-shot generator detects a rising or falling edge present on either the A side or the Y side of the channel. It sends a short pulse that turns on the PMOS transistors (T1 and T2) for a rising edge, or the NMOS transistors (T3 and T4) for a falling edge. This charges/discharges the capacitive load faster, resulting in fast rise and fall times. For proper operation of the device, the voltage applied to the VCCA must always be less than or equal to the voltage applied to VCCY. To meet this condition, the recommended power-up sequence is VCCY first and then VCCA. The ADG3308/ADG3308-1/ ADG3308-2 operate properly only after both supply voltages reach their nominal values. It is not recommended to use the part in a system where, during power-up, VCCA may be greater than VCCY due to a significant increase in the current taken from the VCCA supply. For optimum performance, the VCCA and VCCY pins should be decoupled to GND as close as possible to the device. The inputs of the unused channels (A or Y) should be tied to their corresponding VCC rail (VCCA or VCCY) or to GND. Rev. C | Page 16 of 20 ADG3308/ADG3308-1 DATA RATE The maximum data rate at which the device is guaranteed to operate is a function of the VCCA and VCCY supply voltage combination and the load capacitance. It represents the maximum frequency of a square wave that can be applied to the I/O pins, ensuring that the device operates within the data sheet specifications in terms of output voltage (VOL and VOH) and power dissipation (the junction temperature does not exceed the value specified under the Absolute Maximum Ratings section). Table 5 shows the guaranteed data rates at which the ADG3308/ ADG3308-1/ADG3308-2 can operate in both directions (A→Y level translation or Y→A level translation) for various VCCA and VCCY supply combinations. Table 5. Guaranteed Data Rates 1 VCCA 1.2 V (1.15 V to 1.3 V) 1.8 V (1.65 V to 1.95 V) 2.5 V (2.3 V to 2.7 V) 3.3 V (3.0 V to 3.6 V) 5 V (4.5 V to 5.5 V) 1 1.8 V (1.65 V to 1.95 V) 25 Mbps 2.5 V (2.3 V to 2.7 V) 30 Mbps 45 Mbps VCCY 3.3 V (3.0 V to 3.6 V) 40 Mbps 50 Mbps 60 Mbps The load capacitance used is 50 pF when translating in the A→Y direction and 15 pF when translating in the Y→A direction. Rev. C | Page 17 of 20 5 V (4.5 V to 5.5 V) 40 Mbps 50 Mbps 50 Mbps 50 Mbps ADG3308/ADG3308-1 APPLICATIONS The ADG3308/ADG3308-1/ADG3308-2 are designed for digital circuits that operate at different supply voltages; therefore, logic level translation is required. The lower voltage logic signals are connected to the A pins, and the higher voltage logic signals to the Y pins. The ADG3308/ADG3308-1/ADG3308-2 can provide level translation in both directions (A→Y or Y→A) on all eight channels, eliminating the need for a level translator IC for each direction. The internal architecture allows the ADG3308/ ADG3308-1/ADG3308-2 to perform bidirectional level translation without an additional signal to set the direction in which the translation is made. It also allows simultaneous data flow in both directions on the same part, for example, when two channels translate in the A→Y direction while the other two translate in the Y→A direction. This simplifies the design by eliminating the timing requirements for the direction signal and reduces the number of ICs used for level translation. 100nF ADG3308/ ADG3308-1 / ADG3308-2 VCCY GND Y1 A1 1.8V I/OL1 I/OH2 Y2 A2 I/OL2 I/OH3 Y3 A3 I/OL3 I/OH4 Y4 A4 I/OL4 I/OH5 Y5 A5 I/OL5 I/OH6 Y6 A6 I/OL6 I/OH7 Y7 A7 I/OL7 I/OH8 Y8 A8 I/OL8 CS EN GND GND 100nF Y1 ADG3308/ ADG3308-1 / ADG3308-2 VCCY 100nF VCCA A1 I/OL1 1.8V 1.8V A1 I/OL1 Y2 A2 I/OL2 Y3 A3 I/OL3 Y4 A4 I/OL4 Y5 A5 I/OL5 Y6 A6 I/OL6 Y7 A7 I/OL7 I/OH2 Y2 A2 I/OL2 Y8 A8 I/OL8 I/OH3 Y3 A3 I/OL3 EN GND GND I/OH4 Y4 A4 I/OL4 I/OH5 Y5 A5 I/OL5 I/OH6 Y6 A6 I/OL6 I/OH7 Y7 A7 I/OL7 I/OH8 Y8 A8 I/OL8 EN GND GND Figure 41. 1.8 V to 3.3 V Level Translation Circuit Using the Three-State Feature LAYOUT GUIDELINES 04865-056 GND PERIPHERAL DEVICE MICROPROCESSOR/ MICROCONTROLLER/ DSP ADG3308/ ADG3308-1 / ADG3308-2 VCCA Y1 04865-055 3.3V I/OH1 100nF PERIPHERAL DEVICE 2 VCCY VCCA I/OH1 PERIPHERAL DEVICE 1 MICROPROCESSOR/ MICROCONTROLLER/ DSP 3.3V Figure 40 shows an application where a 3.3 V microprocessor can read or write data to and from a 1.8 V peripheral device using an 8-bit bus. 100nF 100nF Figure 40. 1.8 V to 3.3 V 8-Bit Level Translation Circuit When the application requires level translation between a microprocessor and multiple peripheral devices, the ADG3308/ADG3308-1/ADG3308-2 I/O pins can be threestated by setting EN = 0. This feature allows the ADG3308/ ADG3308-1/ADG3308-2 to share the data buses with other devices without causing contention issues. Figure 41 shows an application where a 3.3 V microprocessor is connected to 1.8 V peripheral devices using the three-state feature. As with any high speed digital IC, the printed circuit board layout is important in the overall performance of the circuit. Care should be taken to ensure proper power supply bypass and return paths for the high speed signals. Each VCC pin (VCCA and VCCY) should be bypassed using low effective series resistance (ESR) and effective series inductance (ESI) capacitors placed as close as possible to the VCCA and VCCY pins. The parasitic inductance of the high speed signal track can cause significant overshoot. This effect can be reduced by keeping the length of the tracks as short as possible. A solid copper plane for the return path (GND) is also recommended. Rev. C | Page 18 of 20 ADG3308/ADG3308-1 OUTLINE DIMENSIONS 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 42. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 0.60 MAX 4.00 BSC SQ 0.60 MAX 15 PIN 1 INDICATOR 20 16 1 PIN 1 INDICATOR 3.75 BCS SQ 0.50 BSC 2.25 2.10 SQ 1.95 EXPOSED PAD (BOTTOM VIEW) 5 TOP VIEW SEATING PLANE 12° MAX 10 6 0.25 MIN 0.80 MAX 0.65 TYP 0.30 0.23 0.18 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 Figure 43. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-20-1) Dimensions shown in millimeters Rev. C | Page 19 of 20 082207-B 1.00 0.85 0.80 0.75 0.60 0.50 11 ADG3308/ADG3308-1 0.65 0.59 0.53 2.06 2.00 1.94 3 4 2 1 A A1 BALL IDENTIFIER 2.56 2.50 2.44 B 0.50 BSC PITCH C D 0.36 0.32 0.28 E 0.28 0.24 0.20 BOTTOM VIEW (BALL SIDE UP) 070606- A TOP VIEW (BALL SIDE DOWN) Figure 44. 20-Ball Wafer Level Chip Scale Package [WLCSP] (CB-20-2) Dimensions shown in millimeters 2.06 2.00 1.94 0.042 0.040 0.037 0.645 0.585 0.525 4 3 2 1 A 2.56 2.50 2.44 B 0.50 BSC PITCH C D 0.36 0.32 0.28 0.28 0.24 0.20 TOP VIEW (BALL SIDE DOWN) E BOTTOM VIEW (BALL SIDE UP) 081707-B A1 BALL IDENTIFIER Figure 45. Backside-Coated 20-Ball Wafer Level Chip Scale Package [WLCSP] (CB-20-3) Dimensions shown in millimeters ORDERING GUIDE Model ADG3308BRUZ 1 ADG3308BRUZ-REEL1 ADG3308BRUZ-REEL71 ADG3308BCPZ-REEL1 ADG3308BCPZ-REEL71 ADG3308BCBZ-1-RL71 ADG3308BCBZ-1-REEL1 ADG3308BCBZ-2-RL71 ADG3308BCBZ-2-REEL1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Ball Wafer Level Chip Scale Package [WLCSP] 20-Ball Wafer Level Chip Scale Package [WLCSP] Backside-Coated 20-Ball Wafer Level Chip Scale Package [WLCSP] Backside-Coated 20-Ball Wafer Level Chip Scale Package [WLCSP] Package Option RU-20 RU-20 RU-20 CP-20-1 CP-20-1 CB-20-2 CB-20-2 CB-20-3 CB-20-3 Z = RoHS Compliant Part. ©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04865-0-9/07(C) T T Rev. C | Page 20 of 20