INTEGRATED CIRCUITS DATA SHEET SAA2505H Digital multi-channel audio IC (DUET) Preliminary specification File under Integrated Circuits, IC01 1998 Mar 10 Philips Semiconductors Preliminary specification Digital multi-channel audio IC (DUET) SAA2505H FEATURES Hardware features • Two 40 MIPS 20-bit DSP cores • All input and output buffer RAM is on-chip • Program ROM on-chip for all decoding modes • Two I2S-bus inputs with normal, double and quad speed mode (slave only) APPLICATIONS The SAA2505H is intended for all markets where a multi-channel audio decoder for Dolby AC-3 and MPEG 2 is required. • Second serial input usable for ADC (Karaoke input) • Three normal and double speed I2S-bus outputs (slave and master from 256 and 384fs) Primary markets are for DVD video players, TV sets and audio/video amplifiers. • One normal, double, quad speed I2S-bus output (slave and master from 256 and 384fs) • Japanese EIAJ serial input and output formats GENERAL • Sony Philips Digital Interface (SPDIF) output The SAA2505H decodes multi-channel audio up to MPEG 7.1, AC-3 5.1 and pro-logic on a dual DSP core. • I2C-bus control (up to 400 kHz) • 3.3 V supply with 5 V TTL compatible inputs/outputs The device contains all of the RAM and ROM necessary for operation. This minimises the need for external components and no microcode download is required. • Boundary scan for printed-circuit board testing. Software features The device is primarily intended for audio/video surround sound amplifiers where the amplifier is connected to the data source by means of SPDIF (IEC 60958). The input interface is, therefore, made for SPDIF (IEC 60958) and formatted for the I2S-bus. • AC-3 up to 5.1 channels • MPEG 2 L2 up to 7.1 channels • MPEG 1 L2 (Video-CD) 2 channels at 44.1 kHz • Dolby pro-logic decoding at 32, 44.1 and 48 kHz The primary device output is PCM, sent via four I2S-bus ports. There is also a SPDIF (IEC 60958) formatted output. • Output configuration for 7, 5, 4, 3, 2 and 1 channels with or without Low Frequency Enhancement (LFE) • Bass redirection for small satellite loudspeakers plus subwoofer User control is achieved via an I2C-bus. However, the SAA2505H is capable of stand-alone operation. • Karaoke voice mix • Dynamic range compression (AC-3 and MPEG) • Adjustable delay up to 15 ms for surround channels (1.5 kbyte words) • Adjustable delay up to 5 ms for centre channel (250 words) • Rounding to DAC word length • Mute by pin and I2C-bus command • AC-3 and MPEG bitstream information available via the I2C-bus • Concealment of CRC errors • SPDIF coded output • Fully programmable SPDIF channel status information. 1998 Mar 10 2 Philips Semiconductors Preliminary specification Digital multi-channel audio IC (DUET) SAA2505H QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDDD digital supply voltage 3.0 3.3 3.6 V IDDD digital supply current − 160 − mA VDDA analog supply voltage 3.0 3.3 3.6 V IDDA analog supply current − tbf − mA fxtal crystal frequency − 35 − MHz Tamb operating ambient temperature 0 − 70 °C VESD electrostatic discharge sensitivity for all pins note 1 −2000 − +2000 V note 2 −300 − +300 V Notes 1. Human body model: equivalent to discharging a 100 pF capacitor through a 1500 Ω resistor. 2. Machine model: equivalent to discharging a 200 pF capacitor through a 0 Ω resistor. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA2505H QFP64 1998 Mar 10 DESCRIPTION plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 × 14 × 2.7 mm 3 VERSION SOT393-1 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... IIS0 bitstream e.g. from microphone IIS1 IEC 1397 PARSER L 8 channels R audio clock 256 or 384fs C LFE MPEG2 OR LS AC-3 DECODER RS LT, RT L, R, C, S PRO LOGIC DOWNMIXING channels AND 1 to 8 VOLUME CONTROL LC RC 4 channels PCM 1 to 8 AND DOWNSAMPLING SWITCH 8 channels NOISE GENERATOR I2S-BUS OUTPUTS Philips Semiconductors bitstream DELAY Digital multi-channel audio IC (DUET) BLOCK DIAGRAM ok, full pagewidth 1998 Mar 10 I2S-bus interface microphone DOWNMIXING bitstream L, R SPDIF MGL324 Preliminary specification SAA2505H Fig.1 Simplified block diagram. Philips Semiconductors Preliminary specification Digital multi-channel audio IC (DUET) SAA2505H PINNING SYMBOL PIN DRIVE/ LOAD(1) STANDALONE 1 A I select stand-alone mode input EFO1 2 F O output flag FO1; from DSP2 EFO2 3 F O output flag FO2; from DSP2 EFO3 4 F O output flag FO3; from DSP2 EFO4 5 F O output flag FO4; from DSP1 EFO5 6 F O output flag FO5; from DSP1 EFO6 7 F O output flag FO6; from DSP1 VSSDI 8 − S digital ground for internal logic and memories; note 2 VDDDI 9 − S digital supply voltage for internal logic and memories (+3.3 V); note 3 EFI1 10 A I input flag FI1; to DSP2 TYPE DESCRIPTION EFI2 11 A I input flag FI2; to DSP1 EFI3 12 A I input flag FI3; to DSP1 VDDDE 13 − S digital supply voltage for I/O cells (+3.3 V); note 4 WSO 14 G I/O word select input/output for ports 0 to 2; also used for output port 3 when not in quad mode (I2S-bus) SCK 15 G I/O serial clock input/output for ports 0 to 2; also used for output port 3 when not in quad mode (I2S-bus) VSSDE 16 − S digital ground for I/O cells; note 5 SDO0 17 F O serial data output for port 0 (I2S-bus) SDO1 18 F O serial data output for port 1 (I2S-bus) VDDDE 19 − S digital supply voltage for I/O cells (+3.3 V); note 4 VSSDI 20 − S digital ground for internal logic and memories; note 2 VDDDI 21 − S digital supply voltage for internal logic and memories (+3.3 V); note 3 VSSDI 22 − S digital ground for internal logic and memories; note 2 VDDDI 23 − S digital supply voltage for internal logic and memories (+3.3 V); note 3 VDDDI 24 − S digital supply voltage for internal logic and memories (+3.3 V); note 3 VSSDI 25 − S digital ground for internal logic and memories; note 2 VDDDE 26 − S digital supply voltage for I/O cells (+3.3 V); note 4 SDO2 27 F O serial data output for port 2 (I2S-bus) SDO3 28 F O serial data output for port 3 (I2S-bus) VSSDE 29 − S digital ground for I/O cells; note 5 WSO3 30 F O word select output for port 3; used in quad mode (I2S-bus) SCKO3 31 F O serial clock output for port 3; used in quad mode (I2S-bus) VDDDE 32 − S digital supply voltage for I/O cells (+3.3 V); note 4 SDB 33 F O serial data begin output for port 3; used in quad mode (I2S-bus) SPDIF 34 F O SPDIF output VSSDE 35 − S digital ground for I/O cells; note 5 VSSDI 36 − S digital ground for internal logic and memories; note 2 VDDDI 37 − S digital supply voltage for internal logic and memories (+3.3 V); note 3 1998 Mar 10 5 Philips Semiconductors Preliminary specification Digital multi-channel audio IC (DUET) SAA2505H PIN DRIVE/ LOAD(1) TYPE VSSDE 38 − S digital ground for I/O cells; note 5 SYSCLK 39 E O programmable system clock output VDDDE 40 − S digital supply voltage for I/O cells (+3.3 V); note 4 VDDA 41 − S analog supply voltage for crystal oscillator (+3.3 V) CLKI 42 H I oscillator input CLKO 43 H O oscillator output VSSDA 44 − S digital ground for crystal oscillator ACLK 45 A I audio clock input for master mode SYMBOL DESCRIPTION VSSDE 46 − S digital ground for I/O cells; note 5 TDI 47 B I boundary scan test data input (this pin should be pulled HIGH for normal operation) TMS 48 B I boundary scan test mode select input (this pin should be pulled HIGH for normal operation) TCK 49 B I boundary scan test clock input TRST 50 B I boundary scan test reset input (this pin should be pulled LOW for normal operation) TDO 51 B O boundary scan test data output VDDDI 52 − S digital supply voltage for internal logic and memories (+3.3 V); note 3 VSSDI 53 − S digital ground for internal logic and memories; note 2 WSI 54 A I word select input for ports 0 and 1 (I2S-bus) SDBI 55 A I serial data begin input for port 0 (I2S-bus) SDI0 56 A I serial data input for port 0 (I2S-bus) SDI1 57 A I serial data input for port 1 (I2S-bus) SCKI 58 A I serial clock input for ports 0 and 1 (I2S-bus) VSSDI 59 − S digital ground for internal logic and memories; note 2 VDDDI 60 − S digital supply voltage for internal logic and memories (+3.3 V); note 3 RESET 61 C I hardware reset ADDR 62 A I select address input (I2C-bus) SCL 63 C I serial clock input; external pull-up to +5 V (I2C-bus) SDA 64 D I/O serial data input/output; external pull-up to +5 V (I2C-bus) Notes 1. See Table 1. 2. All VSSDI pins are internally connected. 3. All VDDDI pins are internally connected. 4. All VDDDE pins are internally connected. 5. All VSSDE pins are internally connected. 1998 Mar 10 6 Philips Semiconductors Preliminary specification Digital multi-channel audio IC (DUET) Pin drive and load descriptions DRIVE/LOAD DESCRIPTION G +5 V tolerant bidirectional 3-state pin; with 3 mA output drive and slew rate limiting; TTL level input; without pull-up or pull-down resistor H crystal pins 56 SDI0 63 SCL 64 SDA handbook, full pagewidth 49 TCK TTL characterised +5 V tolerant 3-state slew rate limited output with 3 mA drive capability 50 TRST F 51 TDO TTL characterised +5 V tolerant 3-state output with 3 mA drive capability 52 VDDDI E 53 VSSDI +5 V tolerant 400 kHz (I2C-bus) 54 WSI D 57 SDI1 +5 V tolerant input; TTL Schmitt-trigger characterized 58 SCKI C 59 VSSDI +5 V tolerant input; TTL characterized with internal pull-up resistor 60 VDDDI B 61 RESET +5 V tolerant input; TTL characterized with internal pull-down resistor 62 ADDR A 55 SDBI Table 1 SAA2505H STANDALONE 1 48 TMS EFO1 2 47 TDI EFO2 3 46 VSSDE EFO3 4 45 ACLK EFO4 5 44 VSSDA EFO5 6 43 CLKO EFO6 7 42 CLKI VSSDI 8 41 VDDA SAA2505H VDDDI 9 40 VDDDE EFI1 10 39 SYSCLK EFI2 11 38 VSSDE EFI3 12 37 VDDDI VDDDE 13 36 VSSDI WSO 14 35 VSSDE SCK 15 34 SPDIF VSSDE 16 Fig.2 Pin configuration. 1998 Mar 10 7 VDDDE 32 SCKO3 31 WSO3 30 VSSDE 29 SDO3 28 SDO2 27 VDDDE 26 VSSDI 25 VDDDI 24 VDDDI 23 VSSDI 22 VDDDI 21 VSSDI 20 VDDDE 19 SDO1 18 SDO0 17 33 SDB MGL323 Philips Semiconductors Preliminary specification Digital multi-channel audio IC (DUET) SAA2505H In the I2S-bus slave mode the output data is clocked to pin 15. This can either be the serial clock input at pin 58 (SCKI) or a suitable external clock. When in slave mode the signal at pin 15 is replicated at pin 31. CLOCK BUILD-UP Up to four clocks provide the timing information for the SAA2505H. These are as follows: 1. Data source clock 2. Data processing clock FUNCTIONAL DESCRIPTION 3. I2C-bus data/control clock Data sinks 4. Data sink clock. Coded audio data or PCM audio data can be input to both DSPs from two slave-only serial interfaces capable of receiving data in either I2S-bus or EIAJ formats. Both serial interfaces use the same serial clock (pin 58) and word select input (pin 54). The serial clock must be at least 32fs. Data source clock Clocking of the input data is derived from the serial clock input at pin 58 and is compliant with the I2S-bus and EIAJ transfer formats. The ports are capable of operating at normal, double and quad speed. Serial data is applied to pins 56 and 57 (SDI0 and SDI1). These pins are mode shared between the I2S-bus and EIAJ formatted serial data. Port mode selection is achieved via the I2C-bus interface, see Table 3. Data processing clock This clock is used for data processing and internal data transfer. The clock can either be provided by an external clock generator having a duty cycle between 40 and 60% or by using the internal crystal clock generator and an external crystal. The external clock should be connected between pins 42 (CLKI) and 43 (CLKO) (see Fig.11). I2S-BUS FORMATTED SPDIF INFORMATION In the I2S-bus mode ‘big-endian’ data is received, MSB justified to 1 clock period after a falling edge of the word select output. The data stream should be formatted according to “IEC 60958 - SPDIF” including the extensions for non-PCM encoded audio data (“IEC 61937”). To use the internal clock a 35 MHz crystal operating on the 3rd harmonic must be connected between pins 42 and 43 (CLKI and CLKO). AC-3 and MPEG coded data is formatted in 16-bit words. These words are expected at a sample rate (fs) of 48 kHz and thus a minimum serial clock of 1.536 MHz; two 16-bit words per word select period. If the transmission word length is in excess of 16 bits all additional bits are discarded. A buffered version of this clock is available at pin 39 (SYSCLK). This can be optionally disabled or, a divided version (4, 2 and 1) of the clock input at pin 42 (CLKI) can be made available. PCM sample lengths of up to 20-bit words are supported with sample rates of 44.1 and 48 kHz. This mode is used to transfer PCM and PCM with Dolby pro-logic encoded data. Word select LOW corresponds to transmission of data for the left channel, word select HIGH corresponds to transmission of data for the right channel. I2C-bus data/control clock The I2C-bus control logic supports I2C-bus clock speeds up to 400 kHz. This is supplied to pin 63 (SCL). If the SAA2505H is in the stand-alone mode (pin 1 HIGH) no I2C-bus clock needs to be supplied. Pin 55 (SDBI) is reserved for a multi-channel extension to the I2S-bus and is currently not supported. Data sink clock The data sink clock source is dependant on the mode of operation of the I2S-bus output ports. In the master mode the I2S-bus clock is derived form an external 256 or 384fs source connected to pin 45 (ACLK). This is internally divided and used to drive the serial clock at pins 15 and 31 (SCK and SCKO3). To ensure that the digital outputs poses good timing qualities (jitter and wander) pin 45 should be a connected to a high quality timing source. 1998 Mar 10 8 Philips Semiconductors Preliminary specification Digital multi-channel audio IC (DUET) handbook, full pagewidth write SAA2505H read SCK SD MSB MSB − 1 LSB + 1 LSB first WS write read SCK SD MSB MSB − 1 second WS MGL327 Fig.3 I2S-bus format (MSB fixed). EIAJ FORMATTED INPUTS In EIAJ mode ‘big-endian’ data is received LSB justified to the rising edge of word select output. Formatting of the data is identical to that used in the I2S-bus mode. handbook, full pagewidth write read SCK LSB + 1 SD WS first first write read SCK SD WS LSB + 1 LSB second MGL328 Fig.4 EIAJ format (LSB justified). 1998 Mar 10 LSB 9 Philips Semiconductors Preliminary specification Digital multi-channel audio IC (DUET) SAA2505H Data sources SPDIF FORMATTED OUTPUT I2S-BUS AND EIAJ FORMATTED OUTPUTS The SPDIF output can transmit either coded data, as received from the serial data input at pin 56 (SDI0), or down-mixed 20-bit PCM stereo. The down-mixed stereo may be Pro-logic encoded. The device has four I2S-bus/EIAJ mode select outputs. These outputs are capable of outputting data in EIAJ 20, 18 or 16-bit and I2S-bus modes. The EIAJ outputs are capable of operating in single or double speed, the I2S-bus output is capable of operating in single, double and quad speed. Together with the PCM samples additional control bits are transmitted. These are the channel status, user data and validity bits. The first five bytes of the channel status bits are user programmable, all following bytes are zeroed automatically. Transmission is LSB first. The output ports can either be in the slave or master mode. In the slave mode they can either be slaved to the I2S-bus serial clock input (pin 15) or to an external clock. In the master mode an audio clock is applied to pin 45 that is 256 or 384fs. The master clocking scheme allows the support of a 96 kHz sample rate DAC by use of the double speed output option. The quad speed output option is intended to allow multiple SAA2505H devices to be connected together. The user data can carry message lengths of 129 bytes. These are transmitted over the SPDIF port at a rate of 2 bits per stereo sample. The message buffer of 129 bytes is loaded via the I2C-bus, if no message is written the SAA2505H outputs all zeros for the user data. In order to obtain a high quality digital output in the master mode the audio clock should be of high quality, having low jitter and an even mark space ration. Table 2 Output port timing information AUDIO CLOCK SAMPLING FREQUENCY WORD SELECT SAMPLING FREQUENCY SERIAL CLOCK SAMPLING FREQUENCY SERIAL DATA BEGIN SAMPLING FREQUENCY Single 256 or 384fs 1fs 64fs − Double 256 or 384fs 2fs 128fs − Quad 256fs 4fs 256fs 1fs Quad 384fs 4fs 192fs 1fs MODE When pin 1 is LOW a reset defaults the outputs to quiet, however when pin 1 is HIGH a reset defaults the I2S-bus output to active and the SPDIF output to mute. When pin 1 is HIGH some of the I2C-bus registers cannot be accessed see Table 3. Control Inputs The SAA2505H can be operated in two stand-alone modes or can be managed by the I2C-bus. STAND-ALONE MODES I2C-BUS REGISTER CONTROL Two stand-alone modes exist to allow the device to be used in systems without a microcontroller. These two modes are STANDALONE (pin 1) held HIGH and STANDALONE connected to RESET (pin 61). 1998 Mar 10 The I2C-bus port supports 5 V, 400 kHz operation. The details of the registers are given in Table 3. 10 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... SECTION General REGISTER NAME SOFT_RESET MEMORY ADDRESS $8 000-b0 DEFAULT VALUE 1(1) 0 2(2) 0 DESCRIPTION 3(3) 0 0: operation 1: reset General SYSCLCKEN $8 000-b1 0 note 4 1 0: enable SYSCLK output 1: disable SYSCLK output General SYSCLKDIV $8 000-b3 and b2 00 note 4 10 00: SYSCLK = 1⁄4CLK 01: SYSCLK = 1⁄2CLK 10: SYSCLK = CLK 11: reserved General EN_INP_INT_DSP1 $8 000-b4 0 note 4 1 0: disable input interrupts on DSP1 1: enable input interrupts on DSP1 General EN_OUTP_INT_DSP1 $8 000-b5 0 note 4 0 General EN_INP_INT_DSP1 0 note 4 1 0: disable output interrupts on DSP1 1: enable output interrupts on DSP1 $8 000-b6 0: disable input interrupts on DSP2 11 1: enable input interrupts on DSP2 General EN_OUTP_INT_DSP1 $8 000-b7 0 note 4 0 General ACLKSEL 0 note 4 0 Philips Semiconductors I2C-bus control register Digital multi-channel audio IC (DUET) 1998 Mar 10 Table 3 0: disable output interrupts on DSP2 1: enable output interrupts on DSP2 $8 000-b8 0: ACLK = 256fs 1: ACLK = 384fs General MEMCONFIG $8 000-b9 0 note 4 0 0: program memory on DSP1 = 12 kbytes 0: program memory on DSP2 = 8 kbytes 1: program memory on DSP1 = 8 kbytes 1: program memory on DSP2 = 12 kbytes I2SCONTROL IISMODE $8 001-b1 and b0 00 note 4 00 00: I2S-bus/EIAJ input format 11: reserved I2SCONTROL IISINP $8 001-b2 0 note 4 0 $8 001-b3 0 note 4 0 0: I2S-bus input format 1: EIAJ 16-bit input format I2SCONTROL IISI_SDB_EN 0: SDBI is DSP1 Input flag 1: SDBI is aligned to WS to allow multi-channel I2S-bus input SAA2505H 10: reserved Preliminary specification 01: reserved This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... MEMORY ADDRESS DEFAULT VALUE 1(1) 2(2) DESCRIPTION 3(3) I2SCONTROL reserved $8 001-b4 0 note 4 0 reserved I2SCONTROL IISOUTMOD $8 001-b6 and b5 00 note 4 00 00: I2S-bus format data output 01: EIAJ 16-bit format data output 10: EIAJ 18-bit format data output 11: EIAJ 20-bit format data output I2SCONTROL IISOUTMST $8 001-b7 0 note 4 0 0: I2S-bus outputs are slaves 1: I2S-bus outputs are masters I2SCONTROL IISOUTSPD $8 001-b8 0 note 4 0 0: I2S-bus outputs 0 to 2 operate at normal speed 1: I2S-bus outputs 0 to 2 operate at double speed I2SCONTROL IIS3OUTSPD $8 001-b10 and b9 00 note 4 00 00: I2S-bus output 3 operates at normal speed 01: I2S-bus output 3 operates at double speed 10: I2S-bus output 3 operates at quad speed 11: I2S-bus output 3 operates at normal speed I2SCONTROL IISO0EN $8 001-b11 0 note 4 1 0: SDO0 output 3-stated 12 1: SDO0 output enabled I2SCONTROL IISO1EN $8 001-b12 0 note 4 1 I2SCONTROL IISO2EN $8 001-b13 0 note 4 1 Philips Semiconductors REGISTER NAME Digital multi-channel audio IC (DUET) 1998 Mar 10 SECTION 0: SDO1 output 3-stated 1: SDO1 output enabled 0: SDO2 output 3-stated 1: SDO2 output enabled I2SCONTROL IISO3EN $8 001-b14 0 note 4 1 0: SDO3 output 3-stated 1: SDO3 output enabled I2SCONTROL IIS3CLKEN $8 001-b15 0 note 4 0 SPDIF1 $8 002-b0 0 0 0 0: SCKO3, WSO3 and SDB outputs 3-stated 1: SCKO3, WSO3 and SDB outputs enabled SPDIFVAL 0: SPDIF validity bit = 0 SPDIFBYP $8 002-b1 0 0 0 0: output PCM data from DSP1 1: output I2S-bus data from I2S-bus input SPDIF1 IISUBIT $8 002-b2 0 0 0 SPDIF1 SPDIFEN $8 002-b3 0 0 0 reserved 0: 3-state SPDIF output and reset SPDIF block 1: enable SPDIF output SAA2505H SPDIF1 Preliminary specification 1: SPDIF transmitting valid PCM This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... DEFAULT VALUE 1(1) 2(2) DESCRIPTION 3(3) Normal usage SPDIF1 CSBYTE0 $8 002-b15 to b8 0000 0000 b8: consumer mode b9: LPCM b10: copy protection b11 to b13: pre-emphasis b14 to b15: mode SPDIF2 CSBYTE1 $8 003-b7 to b0 0000 0000 b0 to b7: category code SPDIF2 CSBYTE2 $8 003-b15 to b8 0000 0000 b8 to b11: source b12 to b15: channel number SPDIF3 CSBYTE3 $8 003-b7 to b0 0000 0000 b0 to b3: source b4 to b6: clock accuracy SPDIF3 CSBYTE4 $8 003-b15 to b8 Notes 13 1. STANDALONE held LOW. 0000 0000 b0 to b3: word length Philips Semiconductors MEMORY ADDRESS REGISTER NAME Digital multi-channel audio IC (DUET) 1998 Mar 10 SECTION 2. STANDALONE held HIGH. 3. STANDALONE connected to RESET. 4. Controlled by DSP; no I2C-bus access. All unused bits return a value of 0. Preliminary specification SAA2505H Philips Semiconductors Preliminary specification Digital multi-channel audio IC (DUET) SAA2505H I2C-bus control and commands (pins 63 and 64) START AND STOP CONDITIONS INTRODUCTION Both data and clock line will remain HIGH when the bus in not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as a STOP condition (P) (see Fig.6). A general description of “The I2C-bus and how to use it” can be obtained from Philips sales offices using ordering number 9398 393 40011. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as a START condition (S) (see Fig.6). For the external control of the SAA2505H a fast I2C-bus is implemented. This is a 400 kHz bus which is downward compatible with the standard 100 kHz bus. There are two different types of control instructions: DATA TRANSFER A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Fig.7). • Instructions to control the DSP program; programming the coefficient RAM and reading the values of parameters • Instructions controlling source selection and programmable parts; through the control registers as detailed in Table 3. ACKNOWLEDGE The number of data bits transferred between the START and STOP conditions from the transmitter to the receiver is not limited. Each byte of 8 bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level left on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull-down the SDA line, left HIGH by the transmitter, during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Set-up and hold times must be taken into account. A master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition (see Fig.8). The detailed description of the I2C-bus and commands is given in the following sections. CHARACTERISTICS OF THE I2C-BUS The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are the serial data line (SDA) and the serial clock line (SCL). Both lines must be connected to the supply rail via a pull-up resistor when connected to the output stages of a microcontroller. For a 400 kHz I2C-bus, the recommendation from Philips Semiconductors must be followed (e.g. up to loads of 200 pF on the bus a pull-up resistor can be used, between 200 and 400 pF a current source or switched resistor must be used). Data transfer can only be initiated when the bus is not busy. BIT TRANSFER One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. The maximum clock frequency is 400 kHz. To be able to run at this high frequency all of the Inputs and outputs connected to the bus must be designed for this high speed I2C-bus according the Philips specification (see Fig.5). 1998 Mar 10 STATE OF THE I2C-BUS INTERFACE DURING AND AFTER POWER-ON RESET During power-on reset the internal SDA line is kept HIGH and the SDA pin is therefore high impedance. The SDA line remains HIGH until a master pulls it down to initiate communication. 14 Philips Semiconductors Preliminary specification Digital multi-channel audio IC (DUET) SAA2505H handbook, full pagewidth SDA SCL data line stable; data valid change of data allowed MBC621 Fig.5 Bit transfer on the I2C-bus. handbook, full pagewidth SDA SDA SCL SCL S P START condition STOP condition Fig.6 START and STOP conditions. 1998 Mar 10 15 MBC622 Philips Semiconductors Preliminary specification Digital multi-channel audio IC (DUET) SAA2505H handbook, full pagewidth SDA MSB acknowledgement signal from receiver acknowledgement signal from receiver byte complete, interrupt within receiver clock line held low while interrupts are serviced SCL 1 S 2 7 8 9 1 2 3-8 ACK 9 P ACK START CONDITION MBC601 Fig.7 Data transfer on the I2C-bus. handbook, full pagewidth DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START condition MBC602 Fig.8 Acknowledge on the I2C-bus. 1998 Mar 10 16 STOP CONDITION Philips Semiconductors Preliminary specification Digital multi-channel audio IC (DUET) I2C-bus format Table 5 I2C-bus write sequence I2C-BUS MASTER ADDRESSING I2C-bus, Before any data is transmitted on the the device which should respond is addressed first. The addressing is always done with the first byte transmitted after the start procedure. SLAVE ADDRESS SELECTION (PIN 62) The SAA2505H acts as slave receiver or a slave transmitter. Therefore the clock signal (SCL) is only an input signal. The data signal (SDA) is a bidirectional line. The SAA2505H slave addresses are shown in Table 4. Table 4 SAA2505H I2C-bus address SAA2505H START − I2C-bus address of SAA2505H − Write − − acknowledge Address high part − − acknowledge Address low part − − acknowledge Data high part − − acknowledge I2C-BUS LEVEL I2C-BUS ADDRESS Data medium part − 1 59H − acknowledge 0 58H Data low part − − acknowledge Data high part − − acknowledge Data medium part − − acknowledge Data low part − − acknowledge The subaddress bit A0 corresponds to the hardware address at pin 52 which allows the device to have 2 different addresses. This allows control of two DUET ICs via the same I2C-bus. WRITE AND READ CYCLES The I2C-bus configuration for a write cycle is shown in Table 5. The write cycle is used to write the bytes to memory and control registers. Continued exchanges STOP Condition The I2C-bus configuration for a read cycle is shown in Table 6. The read cycle is used to read bytes from memory and control registers. 1998 Mar 10 17 − Philips Semiconductors Preliminary specification Digital multi-channel audio IC (DUET) Table 6 I2C-bus read sequence I2C-BUS MASTER SAA2505H Table 7 SAA2505H SAA2505H I2C-bus address ranges START STOP MEMORY BLOCK START − $0 $1FFF DSP1 X memory I2C-bus address of SAA2505H − $2000 $3FFF DSP1 Y memory $4000 $5FFF DSP2 X memory Write − $6000 $7FFF DSP2 Y memory − acknowledge $8000 $9FFF control registers Address high part − − acknowledge Power supply connections and EMC Address low part − − acknowledge START − I2C-bus address of SAA2505H − Read − − acknowledge − data high part − acknowledge The digital part of the chip has in total 13 positive supply line connections and 13 ground connections. To minimise radiation the device should be put on a double layer PCB with, on one side, a large ground plane. The ground supply lines should have a short connection to this ground plane. The supply line connections should have minimum inter-pin PCB track impedances. A low reactance (Q) ferrite bead/capacitor network in the positive supply line can be used as a high frequency filter. Special attention should be paid to the analog supply lines (VDDA and VSSA). − data medium part − acknowledge − data low part − acknowledge − data high part − acknowledge − data medium part − acknowledge − data low part − acknowledge Boundary scan test interface The SAA2505H has a 5 pin boundary scan test interface which implements the three required commands of the IEEE1149; BYPASS, SAMPLE and EXTEST. The boundary scan test interface uses the following pins TDI (pin 47), TMS (pin 48), TCK (pin 49), TRST (pin 50) and TDO (pin 51). Naming and use of the pins is as per IEEE recommendations. Though TRST, TMS and TDI have internal pull-up resistors there should also be system level pull-up resistors. Continued Exchanges STOP Condition − All RAM and peripheral registers are mapped into a common 16-bit address range. The data words are all MSB padded to 24-bit, however, the on-chip RAM is 20-bit and therefore the 4 MSBs are padded with zeros. 1998 Mar 10 18 Philips Semiconductors Preliminary specification Digital multi-channel audio IC (DUET) SAA2505H LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDDD digital supply voltage −0.3 +3.3 V ∆VDDD voltage difference between two supply voltage pins − 330 mV IIK DC input clamp diode current VI < −0.3 V or VI > VDDD + 0.3 V − ±10 mA IOK DC output clamp diode current output type 4 mA; VO < −0.3 V or VO > VDDD + 0.3 V − ±10 mA IO DC output source or sink current output type 4 mA; −0.3 V < VO < VDDD + 0.3 V − ±10 mA IDDD ISSD DC current per supply pin (VDDD or VSSD) − ±500 mA Tamb operating ambient temperature 0 70 °C Tstg storage temperature range −55 +125 °C LTCH latch-up protection 100 − mA VESD electrostatic discharge sensitivity note 1 for all pins note 2 CIC specification/test method −2000 +2000 V −300 +300 V Notes 1. Human body model: equivalent to discharging a 100 pF capacitor through a 1500 Ω resistor. 2. Machine model: equivalent to discharging a 200 pF capacitor through a 0 Ω resistor. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER VALUE UNIT 45 K/W thermal resistance from junction to ambient in free air CHARACTERISTICS Digital I/O at Tamb = 0 to 70 °C; VDDD = 3.0 to 3.6 V; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDDD digital supply voltage 3 3.3 3.6 V VDDA analog supply voltage for the crystal oscillator 3 3.3 3.6 V IDDD digital supply current fxtal = 41 MHz; maximum activity of the DSP − tbf tbf mA IDD(xtal) supply current for the crystal oscillator fxtal = 41 MHz; functional mode − tbf tbf mA Ptot total power dissipation fxtal = 41 MHz; maximum activity of the DSP − tbf tbf W Vhys schmitt trigger hysteresis pin type SCHMITCD 0.4 − 0.7 V VIH HIGH-level input voltage Io = −3 mA; pin types A, B and C 2.0 − − V VIL LOW-level input voltage VDDD = 3.0 V; Io = 3 mA; pin types A, B and C − − 0.8 V 1998 Mar 10 19 Philips Semiconductors Preliminary specification Digital multi-channel audio IC (DUET) SYMBOL PARAMETER SAA2505H CONDITIONS MIN. TYP. MAX. UNIT VOH HIGH-level digital output voltage Io = −3 mA; pin types A, B and C 2.4 − − V VOL LOW-level digital output voltage VDDD = 3.0 V; Io = 3 mA; pin types A, B and C − − 0.4 V VOL(I2C) LOW-level digital output voltage and I2C-bus data output Io = 8 mA; pin type D − − 0.4 V ILO(Z) output leakage current, 3-state outputs Vo = 0 or VDDD; pin types A, B and C − − ±5 µA Rpu(int) internal pull-up resistor to VDDDX pin type B − 76 − kΩ Rpd(int) internal pull-down resistor to VSSDX pin type A − 76 − kΩ ti(r) input rise time VDDD = 3.6 V − tbf 3.6 ns ti(f) input fall time VDDD = 3.6 V − tbf 3.6 ns to(r) output rise time pin types E, F and G; VDDD = 3.3 V; Tamb = 25 °C; process = 0 σ; CL = 20 pF − − 3.0 ns to(f) output fall time pin types E, F and G; VDDD = 3.3 V; Tamb = 25 °C; process = 0 σ; CL = 20 pF − − 3.5 ns Oscillator input/output fxtal crystal frequency 40 40.5 − MHz Vxtal voltage across the crystal 3.0 3.3 3.6 V gm transconductance CL(CLK) at start-up 10.5 19 32 mS in operating range 3.6 − 38 mS − 500 1000 fF − 1000 − cycles capacitive load of clock output Tcy(STRTU) number of cycles in start-up time depends on quality of the external crystal 1998 Mar 10 20 Philips Semiconductors Preliminary specification Digital multi-channel audio IC (DUET) SAA2505H TIMING CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Serial digital inputs and outputs; (see Fig.9) tr rise time Tcy = 50 ns − 7.5 ns tf fall time Tcy = 50 ns − 7.5 ns Tcy bit clock cycle time 70 − ns tBCK(H) bit clock time HIGH Tcy = 50 ns 17.5 − ns tBCK(L) bit clock time LOW Tcy = 50 ns 17.5 − ns ts;DAT data set-up time host Tcy = 50 ns ts;DAT data set-up time I2S-bus input th;DAT data hold time host th;DAT data hold time I2S-bus Tcy = 50 ns input − ns − ns 50 − ns 10 − ns 100 − ns 100 − ns data delay time host − 20 ns word select delay time host − 15 ns I2S-bus ts;WS word select set-up time th;WS word select hold time I2S-bus input td;DAT td;WS I2C-bus 320 10 input Tcy = 50 ns Tcy = 50 ns timing; (see Fig.10) fSCL SCL clock frequency 0 400 kHz tBUF bus free between a STOP and START condition 1.3 − µs tHD;STA hold time (repeated) start condition; after this period the first clock pulse is generated 0.6 − µs tLOW LOW period of the SCL clock 1.3 − µs tHIGH HIGH period of the SCL clock 0.6 − µs tSU;STA set-up time for a repeated start condition 0.6 − µs tHD;DAT data hold time 0 0.9 µs − ns I2C-bus tSU;DAT data set-up time for standard mode system tSU;DAT > 250 ns 100 tr rise time of both SDA and SCL signals fSCL = 400 kHz 20 + 0.1Cbus(1) 300 ns fSCL = 100 kHz 0.1Cbus(1) 0.1Cbus(1) 1000 ns 300 ns 20 + tf fall time of both SDA and SCL signals tSU;STO set-up time for STOP condition 0.6 − µs CL(bus) capacitive load for each bus line − 400 pF tSP pulse width of spikes which must be suppressed by the input filter 0 50 ns 20 + fSCL = 400 kHz Note 1. Cbus = bus line capacitance in pF. 1998 Mar 10 21 Philips Semiconductors Preliminary specification Digital multi-channel audio IC (DUET) SAA2505H handbook, full pagewidth WS OUTPUT LEFT WS INPUT RIGHT tBCK(H) tr th;WS td;DAT tBCK(L) tf ts;WS td;WS BCK ts;DAT Tcy DATA INPUT LSB th;DAT MSB DATA OUTPUT MGL326 Fig.9 Timing definitions of the serial digital data inputs and outputs. 1998 Mar 10 22 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... t BUF t LOW tr tf t HD;STA t SP SCL 23 S t HD;DAT t HIGH t SU;DAT t SU;STA MBC611 P Preliminary specification Fig.10 Timing definition of the I2C-bus. t SU;STO Sr SAA2505H handbook, full pagewidth t HD;STA P Philips Semiconductors Digital multi-channel audio IC (DUET) 1998 Mar 10 SDA This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... WS WS SD SD DAC L/R SYSCLK SCK DAC WS EFO1 to EFO6 SYSCLK SCK ADC WS SD EFI1 to EFI3 TDI TDO TMS SD TCK 24 SCKI ACLK WSI SCKO SDI0 WSO SDI1 SDO0 SDBI SDO1 SCL SDO2 SAA2505H SDA SCK WS SD DAC C/LFE SCKO3 ADDR WSO3 SYSCLK STANDALONE SDO3 SCK SDBO3 WS SPDIF SD SYSCLK SCK VSSD VDDD RESET VDDDA VSSDA TRST CLKI DAC LC/RC SDB CLKO 40.5 MHz 47 nF SCL I2C-bus from SDA microcontroller SYSCLK LS/RS Philips Semiconductors SCK Digital multi-channel audio IC (DUET) SPDIF SYSCLK SCK APPLICATION INFORMATION handbook, full pagewidth 1998 Mar 10 SYSCLK 3:1 47 µF 4.7 kΩ 15 pF 15 pF SPDIF 0.1 µF 3.3 µH 10 nF MGL325 Fig.11 Application diagram for SAA2505H. SAA2505H 0.1 µF +3.3 V Preliminary specification 1 µF 75 Ω Philips Semiconductors Preliminary specification Digital multi-channel audio IC (DUET) SAA2505H PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm SOT393-1 c y X A 48 33 49 32 ZE e E HE A A2 (A 3) A1 θ wM Lp bp pin 1 index L 17 64 detail X 16 1 w M bp e v M A ZD D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 3.00 0.25 0.10 2.75 2.55 0.25 0.45 0.30 0.23 0.13 14.1 13.9 14.1 13.9 0.8 HD HE L 17.45 17.45 1.60 16.95 16.95 Lp v w y 1.03 0.73 0.16 0.16 0.10 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ o 7 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT393-1 1998 Mar 10 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 96-05-21 97-08-04 MS-022 25 Philips Semiconductors Preliminary specification Digital multi-channel audio IC (DUET) If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Reflow soldering Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9397 750 00192). A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm. 1998 Mar 10 SAA2505H 26 Philips Semiconductors Preliminary specification Digital multi-channel audio IC (DUET) SAA2505H DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1998 Mar 10 27 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1998 SCA57 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545102/1200/01/pp28 Date of release: 1998 Mar 10 Document order number: 9397 750 02979