Philips Semiconductors FAST Products Preliminary specification 16 × 4 Synchronous FIFO (3-State) FEATURES 74F224 However, an external gating is required (see Figure 1). For longer words using 74F224, the IR signals of the first-rank packages and OR signals of the last-rank packages must be ANDed for proper synchronization.The 3-State outputs controlled by a single input (OE) make bus connection and multiplexing easy. DESCRIPTION • Independent synchronous inputs and This 64-bit active element First-In-First-Out (FIFO) is a monolithic Schottky-clamped transistor-transistor logic (STLL) array organized as 16 words of 4-bits each. A memory system using the 74F224 can be easily expanded in multiples of 15m+1 words or of 4n bits, or both (where n is the number of packages in the horizontal array). outputs • Organized as 16 words of 4 bits • DC to 50MHz data rate • 3-State outputs • Cascadable in word–width and depth direction TYPE TYPICAL fmax TYPICAL SUPPLY CURRENT (TOTAL) 50MHz 90mA 74F224 ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE DRAWING NUMBER VCC = 5V ±10%, Tamb = 0°C to +70°C 16-pin plastic Dual In-line Package N74F224N 0406C 16-pin plastic Small Outline Large N74F224D 0171B INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS DESCRIPTION LDCP D0 – D3 OE UNCP 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Load clock input 1.0/1.0 20µA/0.6mA Data inputs 1.0/1.0 20µA/0.6mA Output enable input (active high) 1.0/1.0 20µA/0.6mA Unload clock input 1.0/1.0 20µA/0.6mA MR Master reset input (active low) 1.0/1.0 20µA/0.6mA IR Input ready output 50/33 1.0mA/20mA Data outputs 50/33 1.0mA/20mA 50/33 1.0mA/20mA Q0 – Q3 OR Output ready output NOTE TO INPUT AND OUTPUT LOADING AND FAN OUT TABLE 1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. PIN CONFIGURATION LOGIC SYMBOL 4 OE 1 16 IED/IEEE SYMBOL 5 6 7 FIFO 16 X 4 1 9 VCC D0 D1 D2 D3 2 15 UNCP LDCP 3 14 OR 1 13 OE UNCP 3 3 9 LDCP MR 15 IR D0 4 13 Q0 D1 5 12 Q1 D2 D3 6 7 11 10 13 12 11 10 2 14 GND 8 9 MR VCC = Pin 16 GND = Pin 8 September 7, 1990 1 +/C1 & & – CT=0 2 Z3 4 1D Q3 CTR Z2 CT>0 Q0 Q1 Q2 Q3 IR OR Q2 EN5 CT=0 CT<0 2 2 3 14 & V4 4,5 13 5 12 6 13 7 10