IMAGE SENSORS FTF3020-M Full Frame CCD Image Sensor Product specification File under Image Sensors Philips Semiconductors 1999 November 22 Philips Semiconductors Product specification Full Frame CCD Image Sensor FTF3020-M • 35mm film compatible image format (36 x 24 mm2) • 6M active pixels (3072H x 2048V) • Progressive scan • Excellent anti-blooming • Variable electronic shuttering • Square pixel structure • H and V binning • 100% optical fill factor • High linear dynamic range (>72dB) • High sensitivity • Low dark current and fixed-pattern noise • Low read-out noise • Data rate up to 36 MHz • Mirrored, split and four quadrant read-out • Perfectly matched to visual spectrum Description The FTF3020-M is a full frame CCD monochrome image sensor designed for professional digital photography applications, with very low dark current and a linear dynamic range of over 12 true bits at room temperature. The four low-noise output amplifiers, one at each corner of the chip, make the FTF3020-M suitable for a wide range of high-end visual light applications. With one output amplifier, a progressively scanned image can be read out at 5 frames per second. By using multiple outputs the frame rate increases accordingly. The device structure is shown in figure 1. Device structure 6 black lines Z Optical size: Chip size: Pixel size: Active pixels: Total no. of pixels: Optical black pixels: Timing pixels: Dummy register cells: Optical black lines: 36.864 mm (H) x 24.576 mm (V) 39.148 mm (H) x 26.508 mm (V) 12 µm x 12 µm 3072 (H) x 2048 (V) 3120 (H) x 2060 (V) Left: 20 Right: 20 Left: 4 Right: 4 Left: 7 Right: 7 Bottom: 6 Top: 6 Image Area 2048 2060 active lines lines 20 4 X 6 black lines 7 Output amplifier 3120 cells Output register 3134 cells Figure 1 - Device structure 2 4 20 3072 active pixels W 1999 November Y 7 Philips Semiconductors Product specification Full Frame CCD Image Sensor FTF3020-M Architecture of the FTF3020-M The optical centres of all pixels in the image section form a square grid. The charge is generated and integrated in this section. Output registers are located below and above the image section for readout. After the integration time, the image charge is shifted one line at the time to either the upper or lower register or to both simultaneously, depending on the read-out mode. The left and the right half of each register can be controlled independently. This enables either single or multiple read-out. During vertical transport, the C3 gates separate the pixels in the register. The central C3 gates of the lower and upper registers are part of the left half of the sensor (W and Z quadrants respectively). Each register can be used for vertical binning. Each register contains a summing gate at both ends that can be used for horizontal binning (see figure 2). IMAGE SECTION Image diagonal (active video only) Aspect ratio Active image width x height Pixel width x height Geometric fill factor Image clock pins Capacity of each clock phase Number of active lines Number of black reference lines Number of dummy black lines Total number of lines Number of active pixels per line Number of overscan (timing) pixels per line Number of black reference pixels per line Total number of pixels per line 44.30 mm 3:2 36.864 x 24.576 mm2 12x12 µm2 100% 16 pins (A1..A4) 7.5nF per pin 2048 4 (=2x2) 8 (=2x4) 2060 3072 8 (2x4) 40 (2x20) 3120 OUTPUT REGISTERS Output buffers on each corner Number of registers Number of dummy cells per register Number of register cells per register Output register horizontal transport clock pins Capacity of each C-clock phase Overlap capacity between neighbouring C-clocks Output register Summing Gates Capacity of each SG Reset Gate clock phases Capacity of each RG 1999 November Three-stage source follower 2 14 (2x7) 3134 (3120+14) 6 pins per register (C1..C3) 200 pF per pin 40pF 4 pins (SG) 15pF 4 pins (RG) 15pF 3 Philips Semiconductors Product specification Full Frame CCD Image Sensor 7 dummy pixels 3K image pixels 20 black &4 timing columns RD RG OG SG C2 C1 C3 FTF3020-M C2 C1 C3 OUT_Z C2 C1 C3 C3 C2 C1 C3 C2 C1 C3 C2 C1 C3 20 black & 4 timing columns C2 C1 C3 C2 C1 C3 C2 C1 C3 A1 A2 A3 A3 A2 A3 A4 A1 A2 A2 A3 A3 A4 A3 2K active images lines 3K x 2K FF CCD A1 A1 A2 A3 A4 A1 A1 A2 A2 A3 A3 A4 OUT_W OG SG C2 C1 C3 A4 IMAGE A4 A1 A1 A4 6 black lines A1 A1 A2 A2 A3 A3 A4 A4 A1 C2 C1 C3 C2 C1 C3 OUT_Y A2 A1 A2 C2 C1 SG OG A1 A1 A4 A1 A1 C2 C1 C3 A4 6 black lines A3 summing gate output gate reset gate reset drain RG A2 A1 A1 SG: OG: RG: RD: RD C2 C1 C3 A1 A4 One Pixel 7 dummy pixels OUT_X A1 C2 C1 C3 C2 C1 C3 C3 C2 C1 C3 C2 C1 C3 C2 C1 C3 C2 C1 C3 C2 C1 C3 C2 C1 C3 C2 C1 SG OG RG RG RD RD column 1 column 24 + 3K column 24 + 1 A1, A2, A3, A4: clocks of image section C1, C2, C3: clocks of horizontal registers Figure 2 - Detailed internal structure 1999 November column 24 +3K +24 4 Philips Semiconductors Product specification Full Frame CCD Image Sensor FTF3020-M Specifications ABSOLUTE MAXIMUM RATINGS1 MIN. MAX. UNIT GENERAL: storage temperature ambient temperature during operation voltage between any two gates DC current through any clock phase (absolute value) OUT current (no short circuit protection) -55 -40 -20 -0.2 0 +80 +60 +20 +2.0 10 °C °C V µA mA VOLTAGES IN RELATION TO VPS: VNS, SFD, RD VCS, SFS all other pins -0.5 -8 -5 +30 +5 +25 V V V VOLTAGES IN RELATION TO VNS: SFD, RD VCS, SFS, VPS all other pins -15 -30 -30 +0.5 +0.5 +0.5 V V V DC CONDITIONS2 VNS3 VPS SFD SFS VCS OG RD MIN. [V] N substrate P substrate Source Follower Drain Source Follower Source Current Source Output Gate Reset Drain 18 1 16 0 -5 4 13 AC CLOCK LEVEL CONDITIONS2 8 10 -5 OUTPUT REGISTER CLOCKS: C-clock amplitude (duty cycle during hor. transport = 3/6) C-clock low level Summing Gate (SG) amplitude Summing Gate (SG) low level OTHER CLOCKS: Reset Gate (RG) amplitude Reset Gate (RG) low level Charge Reset (CR) pulse on Nsub 24 3 20 0 0 6.5 15.5 MIN. IMAGE CLOCKS: A-clock amplitude during integration and hold A-clock amplitude during vertical transport (duty cycle=5/8) 4 A-clock low level Charge Reset (CR) level on A-clock 5 4.75 2 5 5 0 1 TYPICAL [V] MAX. [V] 28 7 24 0 3 8 18 TYPICAL MAX. [mA] 15 15 4.5 1 - MAX. 10 14 0 -5 UNIT V V V V 5 3.5 10 3.5 5.25 10 3 10 10 10 10 V V V V V V V During Charge Reset it is allowed to exceed maximum rating levels (see note 5). All voltages in relation to SFS. 3 To set the VNS voltage for optimal Vertical Anti-Blooming (VAB), it should be adjustable between minimum and maximum values. 4 Three-level clock is preferred for maximum charge; the swing during vertical transport should be 4V higher than the voltage during integration. A two level clock (typically 10V) can be used if a lower maximum charge handling capacity is allowed. 5 Charge Reset can be achieved in two ways: • The typical A-clock low level is applied to all image clocks; for proper CR, an additional Charge Reset pulse on VNS is required (preferred). • The typical CR level is applied to all image clocks simultaneously. 2 1999 November 5 Philips Semiconductors Product specification Full Frame CCD Image Sensor FTF3020-M Timing diagrams (for default operation) AC CHARACTERISTICS Horizontal frequency (1/Tp) 1 Vertical frequency Charge Reset (CR) time Rise and fall times: image clocks (A) register clocks (C) 2 summing gate (SG) reset gate (RG) 1 2 MIN. TYPICAL 18 50 193.7 20 5 5 5 10 10 3 3 3 MAX. 36 100 1/6 Tp 1/6 Tp 1/6 Tp Tp = 1 clock period Duty cycle = 50% and phase shift of the C clocks is 120 degrees. Frame Timing Sensor Output Dummy 2046 2047 2048 D Black B B B B B B B B B B D 1 2 3 H SSC L H A1 L H A2, A3, A4 L H CR L H Ahigh* L H VD L H BLC L H EXT. SHUTTER L Integration Time Line Timing SSC A1 A2 A3 A4 CR AHigh* VD BLC H L H L H L H L H L H L H L H L H L 360 Tp 66 Tp 230 Tp 138 Tp 20 Tp 138 Tp 112Tp 138 Tp 204Tp 360 Tp 30 Tp 396 Tp Pixel Timing SSC C1 C2 C3 SG RG H L H L H L H L H L H L 3127 pixels 1Tp Tp / 6 Tp = 1 / 18MHz = 55.56ns Pixel output sequence: 7 dummy, 20 black, 4 timing, 3072 active, 4 timing, 20 black Line Time: 3487 x Tp = 193.7µs * During AHigh = H the phiA high level is increased from 10V to 14V (This is necessary during readout only) VD: Frame pulse CR: Charge Reset BLC: Black Level Clamp A1 to A4: Vertical image clocks C1 to C3: Horizontal register clocks SSC: Start-Stop C-clocks SG: Summing gate RG: Reset gate Figure 3 - Timing diagrams 1999 November 6 UNIT MHz kHz µs ns ns ns ns Philips Semiconductors Product specification Full Frame CCD Image Sensor FTF3020-M Line timing SSC A1 A2 A3 A4 —> time Y / Div. : 10V (A1, A2, A3, A 4); 5V (SSC) Figure 4 - Vertical readout Pixel timing C1 C2 C3 SG RG —> time Y / Div. : 5V (C1, C2, C3); 10V (SG, RG) Figure 5 - Start horizontal readout 1999 November 7 Philips Semiconductors Product specification Full Frame CCD Image Sensor FTF3020-M Performance • Integration time = 10ms (unless specified otherwise). • The light source is a lamp of 3200K in conjunction with neutral density filters and a 1.7mm thick BG40 infrared cut-off filter. For Linear Operation measurements, a temperature conversion filter (Melles Griot type no. 03FCG261, -120 mired, thickness: 2.5mm) is applied. The test conditions for the performance characteristics are as follows: • All values are measured using typical operating conditions. • VNS is adjusted as low as possible while maintaining proper Vertical Anti-Blooming. • Sensor temperature = 60°C (333K). • Horizontal transport frequency = 18MHz. • Vertical transport frequency = 50kHz (unless specified otherwise). LINEAR OPERATION Linear dynamic range MIN. 1 TYPICAL MAX. UNIT 4200:1(12bit) Charge Transfer Efficiency 2 vertical 0.999995 Charge Transfer Efficiency 2 horizontal 0.999999 0 Image lag % % Resolution (MTF) @ 42 lp/mm 65 Responsivity 180 250 kel/lux·s Quantum efficiency @ 530 nm 20 26 % Low Pass Shading 3 Random Non-Uniformity (RNU) 4 18 VNS required for good Vertical Anti-Blooming (VAB) 2.0 5 % 0.3 5 % 24 28 V 610 Power dissipation at 2.5 frames/s mW 1 Linear dynamic range is defined as the ratio of Qlin to read-out noise (the latter reduced by Correlated Double Sampling). Charge Transfer Efficiency values are tested by evaluation and expressed as the value per gate transfer. 3 Low Pass Shading is defined as the ratio of the one- σ value of an 8x8 pixels blurred image (low-pass) to the mean signal value. 2 4 RNU is defined as the ratio of the one-σ value of the highpass image to the mean signal value at nominal light. Linear Dynamic Range 14,000 35°C 12,000 45°C LDR 10,000 55°C 8,000 6,000 4,000 2,000 0 0 5 10 15 20 25 30 35 40 Hor. Frequency (MHz) Figure 6 - Typical Linear dynamic range vs. horizontal read-out frequency and sensor temperature 1999 November 8 Philips Semiconductors Product specification Full Frame CCD Image Sensor FTF3020-M Maximum Read-out Speed 20 18 4 outputs 16 Images/sec. 14 12 2 outputs 10 8 1 output 6 4 2 0 0 10 20 30 40 50 60 70 80 90 Integration time (ms) Figure 7 - Maximum number of images/second versus integration time Quantum Efficiency 30 Quantum efficiency (%) 25 20 15 10 5 0 400 450 500 550 600 650 700 Wavelength (nm) Figure 8 - Quantum efficiency versus wavelength 1999 November 9 750 800 100 Philips Semiconductors Product specification Full Frame CCD Image Sensor FTF3020-M LINEAR/SATURATION MIN. Full-well capacity saturation level (Qmax ) 1 240 Full-well capacity shading (Qmax, shading ) 2 Full-well capacity linear operation (Qlin ) 3 180 Charge handling capacity 4 5 Overexposure handling TYPICAL MAX. UNIT 500 600 kel. 10 50 % 350 kel. 600 kel. 200 x Qmax level 1 Qmax is determined from the lowpass filtered image. Qmax, shading is the maximum difference of the full-well charges of all pixels, relative to Qmax. 3 The linear full-well capacity Qlin is calculated from linearity test (see dynamic range). The evaluation test guarantees 97% linearity. 4 Charge handling capacity is the largest charge packet that can be transported through the register and read-out through the output buffer. 5 Overexposure over entire area while maintaining good Vertical Anti-Blooming (VAB). It is tested by measuring the dark line. 2 Charge Handling vs. Integration/Transport Voltage 600 10V/14V Output Signal (kel.) 500 9V/13V 400 300 8V/12V 200 100 0 1 2 3 4 Exposure (arbitrary units) 5 Figure 9 - Charge handling versus integration/transport voltage 1999 November 10 6 Philips Semiconductors Product specification Full Frame CCD Image Sensor FTF3020-M OUTPUT BUFFERS MIN. UNIT 7.5 10 µV/el. 0 2 µV/el. Supply current 4.5 mA Bandwidth 110 MHz Output impedance buffer (Rload = 3.3kΩ, Cload = 2pF) 400 Ω 5 Matching of the four outputs is specified as ∆ACF with respect to reference measured at the operating point (Qlin/2). DARK CONDITION 1 MAX. Mutual conversion factor matching (∆ACF)1 Conversion factor 1 TYPICAL MIN. TYPICAL MAX. UNIT Dark current level @ 30° C 20 30 pA/cm2 Dark current level @ 60° C 0.3 0.6 nA/cm2 Fixed Pattern Noise 1 (FPN) @ 60° C 15 25 el. RMS readout noise @ 9MHz bandwidth after CDS 25 30 el. FPN is the one-σ value of the highpass image. Dark Current Dark Current (pA/cm2) 1000 100 10 1 0 10 20 30 40 Temp. (oC) Figure 10 - Dark current versus temperature 1999 November 11 50 60 Philips Semiconductors Product specification Full Frame CCD Image Sensor FTF3020-M Application information Current handling One of the purposes of VPS is to drain the holes that are generated during exposure of the sensor to light. Free electrons are either transported to the VRD connection and, if excessive (from overexposure), free electrons are drained to VNS. No current should flow into any VPS connection of the sensor. During high overexposure a total current 10 to 15mA through all VPS connections together may be expected. The PNP emitter follower in the circuit diagram (figure 11) serves these current requirements. emitter and the next stage short. The CCD output buffer can easily be destroyed by ESD. By using this emitter follower, this danger is suppressed; do NOT reintroduce this danger by measuring directly on the output pin of the sensor with an oscilloscope probe. Instead, measure on the output of the emitter follower. Slew rate limitation is avoided by avoiding a too-small quiescent current in the emitter follower; about 10mA should do the job. The collector of the emitter follower should be decoupled properly to suppress the Miller effect from the base-collector capacitance. A CCD output load resistor of 3.3kΩ typically results in a bandwidth of 110MHz. The bandwidth can be enlarged to about 130MHz by using a resistor of 2.2kΩ instead, which, however, also enlarges the on-chip power dissipation. VNS drains superfluous electrons as a result of overexposure. In other words, it only sinks current. During high overexposure a total current of 10 to 15mA through all VNS connections together may be expected. The NPN emitter follower in the circuit diagram meets these current requirements. The clamp circuit, consisting of the diode and electrolytic capacitor, enables the addition of a Charge Reset (CR) pulse on top of an otherwise stable VNS voltage. To protect the CCD, the current resulting from this pulse should be limited. This can be accomplished by designing a pulse generator with a rather high output impedance. Device protection The output buffers of the FTF3020-M are likely to be damaged if VPS rises above SFD or RD at any time. This danger is most realistic during power-on or power-off of the camera. The RD voltage should always be lower than the SFD voltage. Decoupling of DC voltages All DC voltages (not VNS, which has additional CR pulses as described above) should be decoupled with a 100nF decoupling capacitor. This capacitor must be mounted as close as possible to the sensor pin. Further noise reduction (by bandwidth limiting) is achieved by the resistors in the connections between the sensor and its voltage supplies. The electrons that build up the charge packets that will reach the floating diffusions only add up to a small current, which will flow through VRD. Therefore a large series resistor in the VRD connection may be used. Never exceed the maximum output current. This may damage the device permanently. The maximum output current should be limited to 10mA. Be especially aware that the output buffers of these image sensors are very sensitive to ESD damage. Outputs To limit the on-chip power dissipation, the output buffers are designed with open source outputs. Outputs to be used should therefore be loaded with a current source or more simply with a resistance to GND. In order to prevent the output (which typically has an output impedance of about 400Ω) from bandwidth limitation as a result of capacitive loading, load the output with an emitter follower built from a high-frequency transistor. Mount the base of this transistor as close as possible to the sensor and keep the connection between the Unused sections To reduce power consumption the following steps can be taken. Connect unused output register pins (C1...C3, SG, OG) and unused SFS pins to zero Volts. 1999 November Because of the fact that our CCDs are built on an n-type substrate, we are dealing with some parasitic npn transistors. To avoid activation of these transistors during switch-on and switch-off of the camera, we recommend the application diagram of figure 11. More information Detailed application information is provided in the application note AN01 entitled ‘Camera Electronics for the mK x nK CCD Image Sensor Family’. 12 Philips Semiconductors Product specification Full Frame CCD Image Sensor FTF3020-M Device Handling An image sensor is a MOS device which can be destroyed by electrostatic discharge (ESD). Therefore, the device should be handled with care. When cleaning the glass we recommend using ethanol (or possibly water). Use of other liquids is strongly discouraged: • if the cleaning liquid evaporates too quickly, rubbing is likely to cause ESD damage. Always store the device with short-circuiting clamps or on conductive foam. Always switch off all electric signals when inserting or removing the sensor into or from a camera (the ESD protection in the CCD image sensor process is less effective than the ESD protection of standard CMOS circuits). • the cover glass and its coating can be damaged by other liquids. Rub the window carefully and slowly. Being a high quality optical device, it is important that the cover glass remain undamaged. When handling the sensor, use fingercots. Dry rubbing of the window may cause electro-static charges or scratches which can destroy the device. VSFD CR pulse 0 - OUT 100 Ω BAT74 Schottky! VPS VOG 100nF VRD VCS 100nF 100nF 10kΩ 100nF BC 860C 15 Ω BAT74 Schottky! 10kΩ 10kΩ Figure 11 - Application diagram to protect the FTF3020-M 1999 November 13 <7pF! SFD BFR 92A output for preprocessing 1k Ω 100nF 0.5-1mA 0.5-1mA 3.3kΩ BAT74 27 Ω 100nF VNS keep short! 10mA BC 850C 2mA 0.5-1mA + BAT74 keep short <10mm! 1uF 100nF BC 850C Philips Semiconductors Product specification Full Frame CCD Image Sensor FTF3020-M Pin configuration The image clock phases of quadrant W are internally connected to X, and Y is connected to Z. The FTF3020-M is mounted in a Pin Grid Array (PGA) package with 96 pins in a 20x15 grid of 52.70 x 40.00 mm2. The position of pin A1 (quadrant W) is marked with a gold dot on top of the package. Symbol VNS VNS VNS VNS VPS SFD SFS VCS OG RD A1 A2 A3 A4 C1 C2 C3 SG RG OUT NC NC NC NC Name Pin # W A1 A5 C2 G1 A2 B2 D2 C1 B3 D1 B5 A3 A4 B4 F2 F1 G2 E1 E2 B1 I1 I2 H1 H2 N substrate N substrate N substrate N substrate P substrate Source Follower Drain Source Follower Source Current Source Output Gate Reset Drain Image Clock (Phase 1) Image Clock (Phase 2) Image Clock (Phase 3) Image Clock (Phase 4) Register Clock (Phase 1) Register Clock (Phase 2) Register Clock (Phase 3) Summing Gate Reset Gate Output Not Connected Not Connected Not Connected Not Connected A B C D E F G H K J L M Pin # X U1 U5 S2 M1 U2 T2 R2 S1 T3 R1 T5 U3 U4 T4 N2 N1 M2 P1 P2 T1 K1 K2 L1 L2 N P 10 9 8 7 6 TOP Z Y W X FTF3020-M 5 4 3 2 1 Figure 12 - FTF3020-M pin configuration (top view) 1999 November 14 R S Pin # Y U10 U6 S9 M10 U9 T9 R9 S10 T8 R10 T6 U8 U7 T7 N9 N10 M9 E10 P9 T10 K10 K9 L10 L9 T U Pin # Z A10 A6 C9 G10 A9 B9 D9 C10 B8 D10 B6 A8 A7 B7 F9 F10 G9 P10 E9 B10 I10 I9 H10 H9 Philips Semiconductors Product specification Full Frame CCD Image Sensor FTF3020-M Package information Top cover glass to top chip 2.4 ±0.25 Chip - bottom package 1.7 ±0.15 SENSOR CRYSTAL Chip - cover glass 1.3 ±0.20 EPOXY GLUE Cover glass 1.0 ±0.05 20 ±0.15 COVER GLASS Image sensor chip 40 ±0.40 A TOP VIEW INDEX MARK PIN 1 1.4 / 100 26.35 ±0.15 COVER GLASS STAND-OFF PIN 4.57 ±0.15 1.27 ± 0.15 52.7 ±0.53 (2.54) 0.46 ±0.05 BOTTOM VIEW 35.56 ±0.20 A is the center of the image area. Position of A: 26.35 ± 0.15 to left edge of package 20.00 ± 0.15 to upper edge of package 1.7 ± 0.15 to bottom of package Angle of rotation: less than ± 1° Sensor flatness: < 20 µm (P-V) Cover glass: Corning 7059 Thickness of cover glass: 1 ± 0.05 Refractive index: nd = 1.53 Double sided AR coating < 1% (430-660 nm) reflection All drawing units are in mm 48.26 ±0.27 Figure 13 - Mechanical drawing of the PGA package of the FTF3020-M 1999 November 15 The sensors can be ordered using the following codes: FTF3020-M sensors Description Quality Grade Order Code FTF3020-M/TG Test grade 9922 157 31431 FTF3020-M/EG Economy grade 9922 157 31451 FTF3020-M/IG Industrial grade 9922 157 31421 FTF3020-M/HG High grade 9922 157 31411 You can contact the Image Sensors division of Philips Semiconductors at the following address: Philips Semiconductors Image Sensors Internal Postbox WAG-05 Prof. Holstlaan 4 5656 AA Eindhoven The Netherlands phone fax +31 - 40 - 27 44 400 +31 - 40 - 27 44 090 www.semiconductors.philips.com/imagers/ Philips Semiconductors Philips reserves the right to change any information contained herein without notice. All information furnished by Philips is believed to be accurate. © Philips Electronics N.V. 1999 9922 157 31411 Order codes