Philips Semiconductors RF Communications Products Product specification Divide by: 64/65/72 triple modulus low power ECL prescaler DESCRIPTION SA702 FEATURES The SA702 triple modulus (Divide By 64/65/72) low power ECL prescaler is used in synthesizer systems to achieve low phase lock time, broad operating range, high reference frequency and small frequency step sizes. The minimum supply voltage is 2.7V and is compatible with the CMOS UMA1005 synthesizer from Philips and other logic circuits. The low supply current allows application in battery operated low-power equipment. Maximum input signal frequency is 1.1GHz for cellular and other land mobile applications. There is no lower frequency limit due to a fully static design. The circuit is implemented in ECL technology on the QUBiC process. The circuit will be available in an 8-pin SO package with 150 mil package width and in 8-pin dual in-line plastic package. PIN CONFIGURATION • Low voltage operation • Low current consumption • Operation up to 1.1GHz • ESD hardened N, D Package APPLICATIONS IN 1 8 IN VC 2 7 GND C MC2 3 6 MC1 OUT 4 5 OUT • Cellular phones • Cordless phones • RF LANs • Test and measurement • Military radio • VHF/UHF mobile radio • VHF/UHF hand-held radio ORDERING INFORMATION TEMPERATURE RANGE ORDER CODE 8-Pin Plastic Dual In-Line Package (DIP) DESCRIPTION -40 to +85°C SA702N DWG # 0404B 8-Pin Plastic Small Outline (SO) package (Surface-mount) -40 to +85°C SA702D 0174C ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER VCC Supply voltage VIN Voltage applied to any other pin IO Output current RATING UNITS -0.3 to +7.0 V -0.3 to (VCC + 0.3) V 10 mA Storage temperature range -65 to +125 °C TA Operating ambient temperature range -55 to +125 °C θJA Thermal impedance 158 108 °C/W TSTG June 17, 1993 D package N package 2 853-1709 10044 Philips Semiconductors RF Communications Products Product specification Divide by: 64/65/72 triple modulus low power ECL prescaler SA702 OUT OUT BLOCK DIAGRAM Q D Q Q MODULUS CONTROL LOGIC D Q D Q Q D Q Q D D Q D Q June 17, 1993 MC2 MC1 IN IN D 3 Q Philips Semiconductors RF Communications Products Product specification Divide by: 64/65/72 triple modulus low power ECL prescaler SA702 DC ELECTRICAL CHARACTERISTICS The following DC specifications are valid for TA = 25°C and VCC = 3.0V; unless otherwise stated. Test circuit Figure 1. SYMBOL PARAMETER TEST CONDITIONS LIMITS MIN VCC Power supply voltage range fIN = 1GHz, input level = 0dBm TYP 2.7 No load UNITS MAX 6.0 V ICC Supply current VOH Output high level VOL Output low level VIH MC1 input high threshold 2.0 VCC V VIL MC1 input low threshold –0.3 0.8 V VIH MC2 input high threshold 2.0 VCC V VIL MC2 input low threshold –0.3 0.8 V IIH MC1 input high current VMC1 = VCC = 6V 50 µA IIL MC1 input low current VMC1 = 0V, VCC = 6V IIH MC2 input high current VMC2 = VCC = 6V IIL MC2 input low current VMC2 = 0V, VCC = 6V IOUT = 1.2mA 4.5 mA VCC-1.4 V VCC-2.6 0.1 –100 –30 –100 –30 0.1 V µA µA 50 µA AC ELECTRICAL CHARACTERISTICS These AC specifications are valid for fIN = 1GHz, input level = 0dBm, VCC = 3.0V and TA = 25°C; unless otherwise stated. Test circuit Fig. 1. SYMBOL PARAMETER TEST CONDITIONS LIMITS MIN TYP UNITS MAX VIN Input signal amplitude1 1000pF input coupling 0.05 2.0 VP-P fIN Input signal frequency Direct coupled input2 0 1.1 GHz 1.1 GHz 1000pF input coupling RID Differential input resistance DC measurement 5 VO Output voltage kΩ VCC = 5.0V 1.6 VP-P tS Modulus set-up time1 VCC = 3.0V 1.2 5 ns tH Modulus hold time1 0 ns tPD Propagation time VP-P 10 ns NOTES: 1. Maximum limit is not tested, however, it is guaranteed by design and characterization. 2. For fIN < 50MHz, minimum input slew rate of 32V/µs is required. DESCRIPTION OF OPERATION The SA702 comprises a frequency divider circuit implemented using a divide by 4 or 5 synchronous prescaler followed by a 5 stage synchronous counter, see BLOCK DIAGRAM. The normal operating mode is for MC1 (Modulus Control) to be set high and MC2 input to be set low in which case the circuit comprises a divide by 64. For divide by 65 the MC1 singal is forced low, causing the prescaler circuit to switch into divide by 5 operation for the last cycle of the synchronous counter. For divide by 72, MC2 is set high configuring the prescaler to divide by 4 and the counter to divide by 18. A truth table for the modulus values is given below: Table 1. Modulus MC1 MC2 64 1 0 65 0 0 72 0 1 72 1 1 For minimization of propagation delay effects, the second divider circuit is synchronous to the divide by 4/5 stage output. The prescaler input is positive edge sensitive, and the output at the final count is a falling edge with propagation delay tPD relative to the input. The rising edge of the output occurs at the count 32 with delay tPD. The MC1 and MC2 inputs are TTL compatible threshold inputs operating at a June 17, 1993 4 reduced input current. CMOS and low voltage interface capability are allowed. The prescaler input is differential and ECL compatible. The output is differential ECL compatible. Philips Semiconductors RF Communications Products Product specification Divide by: 64/65/72 triple modulus low power ECL prescaler SA702 AC TIMING CHARACTERISTICS COUNT 64 65 1 32 63 64 1 IN (00) MC (2:1) (XX) (01) OUT OUT tS tP tH SWITCH FROM /65 TO /64 D COUNT 64 65 1 32 62 63 64 71 72 1 IN (00) (XX) (10) MC OUT tP D June 17, 1993 tS SWITCH FROM /65 TO /72 5 tH Philips Semiconductors RF Communications Products Product specification Divide by: 64/65/72 triple modulus low power ECL prescaler SA702 IN IN 50Ω R1 50Ω 50Ω C1 1000pF VCC R2 50Ω C2 1000pF IN IN VCC GND MC2 MC1 OUT OUT C3 0.1µF MC2 MC1 OUT R4 2.2kΩ C5 5pF OUT R3 2.2kΩ C4 5pF Figure 1. SA702 Test Circuit FREQUENCY (MHz) 0 200 400 600 800 1000 MINIMUM INPUT POWER (dBm) –5 –10 –40°C –15 VCC = 3.0V –20 25°C 85°C –25 –30 –35 –40 Figure 2. Minimum Input Power vs Frequency and Temperature June 17, 1993 6 1200 Philips Semiconductors RF Communications Products Product specification Divide by: 64/65/72 triple modulus low power ECL prescaler SA702 FREQUENCY (MHz) 0 200 400 600 800 1000 MINIMUM INPUT POWER (dBm) –5 –10 2.7V –15 3.0V TA = 25°C –20 6.0V –25 –30 –35 –40 Figure 3. Minimum Input Power vs Frequency and VCC 6 85°C 5.5 25°C ICC (mA) 5 4.5 –40°C 4 3.5 3 2.7 3 6 7 VCC (V) Figure 4. Supply Current vs Supply Voltage and Temperature With No Load June 17, 1993 7 1200 Philips Semiconductors RF Communications Products Product specification Divide by: 64/65/72 triple modulus low power ECL prescaler SA702 j1 j0.5 j2 VCC = 3V j0.2 j5 0.2 0 0.5 1 R3 4Ω INPUT 5 2 TA = 25°C L4 6nH 50 R1 C2 0.4pF 300 3000Ω C1 0.9pF –j5 –j0.2 600 EQUIVALENT INPUT IMPEDANCE 900 –j0.5 –j2 1200 –j1 Figure 5. Typical N Package Input Impedance j1 j2 j0.5 j0.2 VCC = 3V j5 TA = 25°C 0 0.2 0.5 1 R3 2Ω INPUT 5 2 L4 3nH 50 C2 0.2pF R1 3000Ω 300 –j5 –j0.2 600 EQUIVALENT INPUT IMPEDANCE 900 –j0.5 1200 –j2 –j1 Figure 6. Typical D Package Input Impedance June 17, 1993 8 C1 0.9pF