PHILIPS PCF2119SU/2

INTEGRATED CIRCUITS
DATA SHEET
PCF2119X
LCD controllers/drivers
Product specification
Supersedes data of 2002 Jan 16
2003 Jan 30
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
CONTENTS
1
FEATURES
1.1
Note
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
ORDERING INFORMATION
5
BLOCK DIAGRAM
6
PAD INFORMATION
6.1
Pad functions
7
FUNCTIONAL DESCRIPTION
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
LCD supply voltage generator
Programming ranges
LCD bias voltage generator
Oscillator
External clock
Power-on reset
Power-down mode
Registers
Busy flag
Address Counter (AC)
Display Data RAM (DDRAM)
Character Generator ROM (CGROM)
Character Generator RAM (CGRAM)
Cursor control circuit
Timing generator
LCD row and column drivers
Reset function
8
INSTRUCTIONS
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
Clear display
Return home
Entry mode set
Display control (and partial power-down mode)
Cursor or display shift
Function set
Set CGRAM address
Set DDRAM address
Read busy flag and read address
Write data to CGRAM or DDRAM
Read data from CGRAM or DDRAM
2003 Jan 30
9
EXTENDED FUNCTION SET
INSTRUCTIONS AND FEATURES
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
New instructions
Icon control
IM
IB
Normal/icon mode operation
Direct mode
Voltage multiplier control
Screen configuration
Display configuration
TC1 and TC2
Set VLCD
Reducing current consumption
10
INTERFACES TO MPU
10.1
10.2
Parallel interface
I2C-bus interface
11
LIMITING VALUES
12
HANDLING
13
DC CHARACTERISTICS
14
AC CHARACTERISTICS
15
TIMING CHARACTERISTICS
16
APPLICATION INFORMATION
16.1
16.2
16.3
16.5
16.6
General information
Charge pump characteristics
8-bit operation, 1-line display using external
reset
4-bit operation, 1-line display using external
reset
8-bit operation, 2-line display
I2C-bus operation, 1-line display
17
DEVICE PROTECTION DIAGRAMS
18
BONDING PAD LOCATIONS
19
DATA SHEET STATUS
20
DEFINITIONS
21
DISCLAIMERS
22
PURCHASE OF PHILIPS I2C COMPONENTS
16.4
2
Philips Semiconductors
Product specification
LCD controllers/drivers
1
PCF2119X
FEATURES
• Single-chip LCD controller/driver
• 2-line display of up to 16 characters + 160 icons, or
1-line display of up to 32 characters + 160 icons
• 5 × 7 character format plus cursor; 5 × 8 for kana
(Japanese) and user defined symbols
• Direct mode to save current consumption for icon mode
and Mux 1 : 9 (depending on VDD2 value and LCD liquid
properties)
• Icon mode: reduced current consumption while
displaying icons only
• Very low current consumption (20 to 200 µA):
• Icon blink function
– Icon mode: <25 µA
• On-chip:
– Power-down mode: <2 µA.
– Configurable 4 (3 and 2) times voltage multiplier
generating LCD supply voltage, independent of VDD,
programmable by instruction (external supply also
possible)
1.1
Note
Icon mode is used to save current. When only icons are
displayed, a much lower operating voltage VLCD can be
used and the switching frequency of the LCD outputs is
reduced. In most applications it is possible to use VDD as
VLCD.
– Temperature compensation of on-chip generated
VLCD: −0.16 to −0.24 %/K (programmable by
instruction)
– Generation of intermediate LCD bias voltages
– Oscillator requires no external components (external
clock also possible).
2
APPLICATIONS
• Display Data RAM: 80 characters
• Telecom equipment
• Character Generator ROM: 240, 5 × 8 characters
• Portable instruments
• Character Generator RAM: 16, 5 × 8 characters;
4 characters used to drive 160 icons, 8 characters used
if icon blink feature is used in application
• Point-of-sale terminals.
3
• 4 or 8-bit parallel bus and 2-wire I2C-bus interface
The PCF2119x is a low power CMOS LCD controller and
driver, designed to drive a dot matrix LCD display of 2-line
by 16 or 1-line by 32 characters with 5 × 8 dot format. All
necessary functions for the display are provided in a single
chip, including on-chip generation of LCD bias voltages,
resulting in a minimum of external components and lower
system current consumption. The PCF2119x interfaces to
most microcontrollers via a 4 or 8-bit bus or via the 2-wire
I2C-bus. The chip contains a character generator and
displays alphanumeric and kana (Japanese) characters.
The letter ‘x’ in PCF2119x characterizes the built-in
character set. Various character sets can be manufactured
on request.
• CMOS compatible
• 18 row and 80 column outputs
• Multiplex rates 1 : 18 (for normal operation), 1 : 9 (for
single line operation) and 1 : 2 (for icon only mode)
• Uses common 11 code instruction set (extended)
• Logic supply voltage range, VDD1 − VSS = 1.5 to 5.5 V
(chip may be driven with two battery cells)
• Display supply voltage range, VLCD − VSS = 2.2 to 6.5 V
• HVgen supply voltage range, VDD2 − VSS = 2.2 to 4 V
and VDD3 − VSS = 2.2 to 4 V
2003 Jan 30
GENERAL DESCRIPTION
3
Philips Semiconductors
Product specification
LCD controllers/drivers
4
PCF2119X
ORDERING INFORMATION
TYPE NUMBER
PCF2119AU/2
PCF2119DU/2
PCF2119FU/2
PCF2119RU/2
PCF2119SU/2
PCF2119VU/2
2003 Jan 30
PACKAGE
NAME
−
−
−
−
−
−
DESCRIPTION
chip with bumps in tray
chip with bumps in tray
chip with bumps in tray
chip with bumps in tray
chip with bumps in tray
chip with bumps in tray
4
VERSION
2
2
2
2
2
2
Philips Semiconductors
Product specification
LCD controllers/drivers
5
PCF2119X
BLOCK DIAGRAM
C1 to C80
handbook, full pagewidth
R17DUP
60 to 99,
101 to 140
R1 to R18
51 to 59,
141 to 149
100
18
80
VLCD1
44 to 49
COLUMN DRIVERS
BIAS
VOLTAGE
GENERATOR
ROW DRIVERS
80
18
DATA LATCHES
VLCD2
VLCDSENSE
37 to 43
80
VLCD
GENERATOR
36
SHIFT REGISTER 18-BIT
SHIFT REGISTER 5 × 12 BIT
5
OSCILLATOR
168
OSC
CURSOR AND DATA CONTROL
VDD1
VDD2
VDD3
5
1 to 6
7 to 14
VSS1
22 to 29
VSS2
30 to 35
T1
T2
T3
CHARACTER
GENERATOR
RAM (128 × 5)
(CGRAM)
16 CHARACTERS
15 to 18
CHARACTER
GENERATOR
ROM
(CGROM)
240 CHARACTERS
TIMING
GENERATOR
8
20
DISPLAY DATA RAM
(DDRAM)
80 CHARACTERS/BYTES
7
21
155
PD
153
7
7
DISPLAY
ADDRESS
COUNTER
ADDRESS COUNTER
(AC)
7
7
INSTRUCTION
DECODER
8
DATA
REGISTER
(DR)
INSTRUCTION
REGISTER
BUSY
FLAG
8
PCF2119x
154
8
163
DB3/SA0
I/O BUFFER
161 to 162
19
164 to 167
158
159
151,
152
156,
157
MGW571
DB1 to DB2
DB4 to DB7
E
R/W
RS
SCL
Fig.1 Block diagram.
2003 Jan 30
5
SDA
POR
Philips Semiconductors
Product specification
LCD controllers/drivers
6
PCF2119X
PAD INFORMATION
The identification of each pad and its location is given in Chapter 18.
6.1
Pad functions
Table 1
Pad function description
SYMBOL
VDD1
VDD2, VDD3
VSS1
VSS2
VLCD1
VLCD2
VLCDSENSE
E
T1 to T3
R1 to R18;
R17DUP
C1 to C80
SCL
POR
PD
SDA
R/W
RS
DB0 to DB7
OSC
DESCRIPTION
Logic supply voltage.
High voltage generator supply voltages (always put VDD2 = VDD3).
This is the ground pad for all except the high voltage generator.
This is the ground pad for the high voltage generator.
This input is used for the generation of the LCD bias levels.
This is the VLCD output pad if VLCD is generated internally then pad VLCD2 must be connected to VLCD1.
The pad must be left open-circuit when VLCD is generated externally.
This input (VLCD) is used for the voltage multiplier’s regulation circuitry. This pad must be connected to
VLCD2 when using internal LCD supply and to VLCD1 and VLCD2 when using external LCD supply.
The data bus clock input is set HIGH to signal the start of a read or write operation; data is clocked in
or out of the chip on the negative edge of the clock; note 1.
These are three test pads. T1 and T2 must be connected to VSS1; T3 is left open-circuit and is not user
accessible.
LCD row driver outputs R1 to R18; these pads output the row select waveforms to the display;
R17 and R18 drive the icons. R17 has two pads R17 and R17DUP.
LCD column driver outputs C1 to C80.
I2C-bus serial clock input; note 1.
External power-on reset input.
PD selects the chip power-down mode; for normal operation PD = 0.
I2C-bus serial data input/output; note 1.
This is the read/write input. R/W selects either the read (R/W = 1) or write (R/W = 0) operation. This
pad has an internal pull-up resistor.
The RS input selects the register to be accessed for read and write. RS = 0, selects the instruction
register for write and the busy flag and address counter for read. RS = 1, selects the data register for
both read and write. This pad has an internal pull-up resistor.
The 8-bit bidirectional data bus (3-state) transfers data between the system controller and the
PCF2119x. DB7 may be used as the busy flag, signalling that internal operations are not yet
completed. In 4-bit operations the 4 higher order lines DB7 to DB4 are used; DB3 to DB0 must be left
open-circuit. Data bus line DB3 has an alternative function (SA0), when selected this is the I2C-bus
address pad. Each data line has its own internal pull-up resistor; note 1.
Oscillator or external clock input. When the on-chip oscillator is used this pad must be connected to
VDD1.
Note
1. When the I2C-bus is used, the parallel interface pad E must be at logic 0. In the I2C-bus read mode DB7 to DB4 and
DB2 to DB0 should be connected to VDD1 or left open-circuit.
a) When the parallel bus is used, pads SCL and SDA must be connected to VSS1 or VDD1; they must not be left
open-circuit.
b) If the 4-bit interface is used without reading out from the PCF2119x (i.e. R/W is set permanently to logic 0), the
unused ports DB0 to DB4 can either be set to VSS1 or VDD1 instead of leaving them open-circuit.
2003 Jan 30
6
Philips Semiconductors
Product specification
LCD controllers/drivers
7
PCF2119X
FUNCTIONAL DESCRIPTION
7.1
When the generator and the direct mode are switched off
an external voltage may be supplied at connected pads
VLCD1. VLCD1 may be higher or lower than VDD.
LCD supply voltage generator
The LCD supply voltage may be generated on-chip. The
voltage generator is controlled by two internal 6-bit
registers: VA and VB. The nominal LCD operating voltage
at room temperature is given by the relationship:
During direct mode (program DM register bit) the internal
voltage generator is turned off and the VLCD output voltage
is directly connected to VDD2. This reduces the current
consumption during icon mode and Mux 1 : 9 (depending
on the VDD2 value and the LCD liquid properties).
V OP(nom) = ( integer value of register × 0.08 ) + 1.82
7.2
The LCD supply voltage generator ensures that, as long as
VDD is in the valid range (2.2 to 4 V), the required peak
voltage VOP = 6.5 V can be generated at any time.
Programming ranges
Programmed value: 1 to 63. Voltage: 1.90 to 6.86 V.
Tref = 27 °C.
7.3
Values producing more than 6.5 V at operating
temperature are not allowed. Operation above this
voltage may damage the device. When programming the
operating voltage the VLCD temperature coefficient must
be taken into account.
LCD bias voltage generator
The intermediate bias voltages for the LCD display are
also generated on-chip. This removes the need for an
external resistive bias chain and significantly reduces the
system current consumption. The optimum value of VLCD
depends on the multiplex rate, the LCD threshold voltage
(Vth) and the number of bias levels. Using a 5-level bias
scheme for 1 : 18 maximum rate allows VLCD < 5 V for
most LCD liquids. The intermediate bias levels for the
different multiplex rates are shown in Table 2. These bias
levels are automatically set to the given values when
switching to the corresponding multiplex rate.
Values below 2.2 V are below the specified operating
range of the chip and are therefore not allowed.
Value 0 for VA and VB switches the generator off
(i.e. VA = 0 in character mode, VB = 0 in icon mode).
Usually register VA is programmed with the voltage for
character mode and register VB with the voltage for icon
mode.
When VLCD is generated on-chip the VLCD pads should be
decoupled to VSS with a suitable capacitor. The generated
VLCD is independent of VDD and is temperature
compensated.
Table 2
Bias levels as a function of multiplex rate
MULTIPLEX
NUMBER
RATE
OF LEVELS
V1
V2
V3
V4
V5
V6
1 : 18
5
Vop
3/4(1)
1/2
1/2
1/4
Vss
1:9
5
Vop
3/4
1/2
1/2
1/4
Vss
1:2
4
Vop
2/3
2/3
1/3
1/3
Vss
Note
1. The values in the above table are given relative to Vop − Vss, e.g. 3/4 means 3/4 × (Vop − Vss).
2003 Jan 30
7
Philips Semiconductors
Product specification
LCD controllers/drivers
7.4
PCF2119X
The instruction register can be written to but not read from
by the system controller. The data register temporarily
stores data to be read from the DDRAM and CGRAM.
When reading, data from the DDRAM or CGRAM
corresponding to the address in the instruction register is
written to the data register prior to being read by the ‘read
data’ instruction.
Oscillator
The on-chip oscillator provides the clock signal for the
display system. No external components are required and
the OSC pad must be connected to VDD.
7.5
External clock
If an external clock is to be used this is input at the OSC
pad. The resulting display frame frequency is given by:
f OSC
f frame = ------------3 072
7.9
The busy flag indicates the internal status of the
PCF2119x. A logic 1 indicates that the chip is busy and
further instructions will not be accepted. The busy flag is
output to pad DB7 when RS = 0 and R/W = 1. Instructions
should only be written after checking that the busy flag is
at logic 0 or waiting for the required number of cycles.
Only in the power-down state is the clock allowed to be
stopped (OSC connected to VSS), otherwise the LCD is
frozen in a DC state.
7.6
Power-on reset
7.10
The PCF2119x must be reset externally. This is an internal
synchronous reset that requires 3 OSC cycles to be
executed after release of the external reset signal. If no
external reset is performed, the chip might start-up in an
unwanted state. The external reset is active HIGH.
7.7
Power-down mode
7.11
Display Data RAM (DDRAM)
The DDRAM stores up to 80 characters of display data
represented by 8-bit character codes. RAM locations
which are not used for storing display data can be used as
general purpose RAM. The basic RAM to display
addressing scheme is shown in Fig.2. With no display shift
the characters represented by the codes in the first
32 RAM locations starting at address 00H in line 1 are
displayed. Figures 3 and 4 show the display mapping for
right and left shift respectively.
During power-down, information in the RAMs and the chip
state are preserved. Instruction execution during
power-down is possible when pad OSC is externally
clocked.
Registers
When data is written to or read from the DDRAM
wrap-around occurs from the end of one line to the start of
the next line. When the display is shifted each line wraps
around within itself, independently of the others. Thus all
lines are shifted and wrapped around together. The
address ranges and wrap-around operations for the
various modes are shown in Table 3.
The PCF2119x has two 8-bit registers, an Instruction
Register (IR) and a Data Register (DR). The Register
Select signal (RS) determines which register will be
accessed. The instruction register stores instruction codes
such as ‘display clear’ and ‘cursor shift’, and address
information for the Display Data RAM (DDRAM) and
Character Generator RAM (CGRAM).
Table 3
Address Counter (AC)
The address counter assigns addresses to the DDRAM
and CGRAM for reading and writing and is set by the
commands ‘set CGRAM address’ and ‘set DDRAM
address’. After a read/write operation the address counter
is automatically incremented or decremented by 1. The
address counter contents are output to the bus
(DB6 to DB0) when RS = 0 and R/W = 1.
The chip can be put into power-down mode by applying an
external active HIGH level to the PD pad. In power-down
mode all static currents are switched off (no internal
oscillator, no bias level generation and all LCD outputs are
internally connected to VSS).
7.8
Busy flag
Address space and wrap-around operation
1 × 32
2 × 16
1×9
00 to 4F
00 to 27; 40 to 67
00 to 27
MODE
Address space
Read/write wrap-around (moves to next line)
4F to 00
27 to 40; 67 to 00
27 to 00
Display shift wrap-around (stays within line)
4F to 00
27 to 00; 67 to 40
27 to 00
2003 Jan 30
8
Philips Semiconductors
Product specification
LCD controllers/drivers
handbook, full pagewidth
display
position
DDRAM
address
PCF2119X
non-displayed DDRAM addresses
1 2 3 4 5
30 31 32
00 01 02 03 04
1D 1E 1F 20 21
4C 4D 4E 4F
1-line display
non-displayed DDRAM address
DDRAM
address
1 2 3 4 5
14 15 16
00 01 02 03 04
0D 0E 0F 10 11
1 2 3 4 5
14 15 16
40 41 42 43 44
4D 4E 4F 50 51
24 25 26 27
line 1
64 65 66 67
line 2
MGK892
2-line display/MUX 1 : 9 mode
Fig.2 DDRAM to display mapping: no shift.
handbook, halfpage
DDRAM
address
5
14 15 16
27 00 01 02 03
1
2 3
0C 0D 0E
1
5
10 11 12
67 40 41 42 43
4C 4D 4E
2 3
4
4
2-line display/MUX 1 : 9 mode
line 1
line 2
MGL536
Fig.3 DDRAM to display mapping: right shift.
handbook,display
halfpage
position
DDRAM
address
5
30 31 32
01 02 03 04 05
1
2 3
4
1E 1F 20
1-line display
1
DDRAM
address
5
14 15 16
01 02 03 04 05
2 3
0E 0F 10
1
5
14 15 16
41 42 43 44 45
4E 4F 50
2 3
4
4
2-line display/MUX 1 : 9 mode
line 1
line 2
MGK894
Fig.4 DDRAM to display mapping; left shift.
2003 Jan 30
9
Philips Semiconductors
Product specification
LCD controllers/drivers
7.12
PCF2119X
Character Generator ROM (CGROM)
7.15
The Character Generator ROM generates 240 character
patterns in a 5 × 8 dot format from 8-bit character codes.
Figures 6 to 10 shows the character sets that are currently
implemented.
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the data buses.
7.16
7.13
Character Generator RAM (CGRAM)
LCD row and column drivers
The PCF2119x contains 18 row and 80 column drivers,
which connect the appropriate LCD bias voltages in
sequence to the display in accordance with the data to be
displayed. R17 and R18 drive the icon rows.
Up to 16 user defined characters may be stored in the
Character Generator RAM. Some CGRAM characters
(see Fig.19) are also used to drive icons (6 if icons blink
and both icon rows are used in the application; 3 if no blink
but both icon rows are used in the application; 0 if no icons
are driven by the icon rows). The CGROM and CGRAM
use a common address space, of which the first column is
reserved for the CGRAM (see Fig.6 to Fig.10). Figure 11
shows the addressing principle for the CGRAM.
7.14
Timing generator
The bias voltages and the timing are selected
automatically when the number of lines in the display is
selected. Figures 12 to 15 show typical waveforms.
Unused outputs should be left unconnected.
Cursor control circuit
The cursor control circuit generates the cursor (underline
and/or cursor blink as shown in Fig.5) at the DDRAM
address contained in the address counter.
When the address counter contains the CGRAM address
the cursor will be inhibited.
cursor
MGA801
5 x 7 dot character font
alternating display
cursor display example
blink display example
Fig.5 Cursor and blink display examples.
2003 Jan 30
10
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
handbook, full pagewidth
upper
4 bits
0000
xxxx
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
lower
4 bits
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
MCE190
Fig.6 Character set ‘A’ in CGROM.
2003 Jan 30
11
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
handbook, full pagewidth
upper
4 bits
0000
xxxx
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
lower
4 bits
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
MCE173
Fig.7 Character set ‘D’ in CGROM.
2003 Jan 30
12
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
handbook, full pagewidth
upper
4 bits
0000
xxxx
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
lower
4 bits
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
MGU552
Fig.8 Character set ‘F’ in CGROM.
2003 Jan 30
13
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
handbook, full pagewidth
upper
4 bits
0000
xxxx
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
lower
4 bits
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
MGL535
Fig.9 Character set ‘R’ in CGROM.
2003 Jan 30
14
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
handbook, full pagewidth
upper
4 bits
0000
xxxx
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
lower
4 bits
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
MGL534
Fig.10 Character set ‘S’ in CGROM.
2003 Jan 30
15
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
character codes
handbook, full pagewidth
CGRAM
address
(DDRAM data)
7
6
5
4
3
2
higher
order
bits
0
0
0
0
0
0
1
0
6
lower
order
bits
0
0
0
0
0
0
0
0
5
4
3
2
higher
order
bits
0
1
0
0
0
0
0
0
character patterns
(CGRAM data)
1
0
4
lower
order
bits
0
1
3
higher
order
bits
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
2
1
character code
(CGRAM data)
0
4
3
2
1
0
1
1
1
1
1
1
1
0
1
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
1
0
0
1
0
1
0
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
1
1
1
0
0
1
1
0
1
0
0
0
1
0
1
0
1
0
0
0
lower
order
bits
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
character
pattern
example 1
cursor
position
character
pattern
example 2
MGE995
Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6.
CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logical OR with
the cursor. Data in the 8th position will appear in the cursor position.
Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in Figs. 7 to 10
As shown in Figs. 7 to 10, CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds
to selection for display.
Only bits 0 to 5 of the CGRAM address are set by the ‘set CGRAM address’ command. Bit 6 can be set using the ‘set DDRAM address’ command in
the valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘read busy flag and address
counter’ command.
Fig.11 Relationship between CGRAM addresses, data and display patterns.
2003 Jan 30
16
Philips Semiconductors
Product specification
LCD controllers/drivers
frame n
handbook, full pagewidth
ROW 1
PCF2119X
frame n + 1
state 1 (ON)
state 2 (OFF)
VLCD
V2
V3/V4
V5
VSS
R1
R2
R3
R4
R5
ROW 9
R6
VLCD
V2
V3/V4
V5
VSS
ROW 2
VLCD
V2
V3/V4
V5
VSS
COL1
VLCD
V2
V3/V4
V5
VSS
COL2
VLCD
V2
V3/V4
V5
VSS
R7
R8
R9
VOP
0.5VOP
0.25VOP
state 1 0 V
−0.25VOP
−0.5VOP
−VOP
VOP
0.5VOP
0.25VOP
state 2 0 V
−0.25VOP
−0.5VOP
−VOP
MGE996
1 2 3
18 1 2 3
18
Fig.12 MUX 1 : 18 LCD waveforms; character mode.
2003 Jan 30
17
Philips Semiconductors
Product specification
LCD controllers/drivers
frame n + 1
frame n
handbook, full pagewidth
ROW 1
PCF2119X
state 1 (ON)
state 2 (OFF)
VLCD
V2
V3/V4
V5
VSS
R1
R2
R3
R4
R5
ROW 2
R6
VLCD
V2
V3/V4
V5
VSS
ROW 3
VLCD
V2
V3/V4
V5
VSS
COL1
VLCD
V2
V3/V4
V5
VSS
COL2
VLCD
V2
V3/V4
V5
VSS
R7
R8
R9
VOP
0.5VOP
0.25VOP
state 1 0 V
−0.25VOP
−0.5VOP
−VOP
VOP
0.5VOP
0.25VOP
state 2 0 V
−0.25VOP
−0.5VOP
−VOP
1
9
1
9
MGK900
Fig.13 MUX 1 : 9 LCD waveforms; character mode. R10 to 18 to be left open.
2003 Jan 30
18
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
frame n + 1
frame n
handbook, full pagewidth
only icons are
driven (MUX 1 : 2)
VLCD
ROW 17
2/3
1/3
VSS
VLCD
ROW 18
2/3
1/3
VSS
VLCD
ROW 1 to 16
2/3
1/3
VSS
VLCD
COL 1 ON/OFF
2/3
1/3
VSS
VLCD
COL 2 OFF/ON
2/3
1/3
VSS
VLCD
COL 3 ON/ON
2/3
1/3
VSS
VLCD
COL 4 OFF/OFF
2/3
1/3
VSS
MGE997
Fig.14 MUX 1 : 2 LCD waveforms; icon mode.
2003 Jan 30
19
Philips Semiconductors
Product specification
LCD controllers/drivers
handbook, full pagewidth V
PIXEL
PCF2119X
frame n + 1
frame n
state 1 (ON)
state 1
COL 1 ROW 17
state 2
COL 2 ROW 17
VOP
2/3 VOP
1/3 VOP
state 2 (OFF)
R17
R18
0
R1-16
−1/3 VOP
−2/3 VOP
−VOP
state 3 (OFF)
VOP
2/3 VOP
1/3 VOP
0
−1/3 VOP
−2/3 VOP
−VOP
VOP
2/3 VOP
1/3 VOP
state 3
COL 1 0
ROW 1 to 16 −1/3 VOP
−2/3 VOP
−VOP
MGE998
VON(rms) = 0.745VOP
VOFF(rms) = 0.333VOP
V ON
D = ------------= 2.23
V OFF
Fig.15 MUX 1 : 2 LCD waveforms; icon mode.
2003 Jan 30
20
Philips Semiconductors
Product specification
LCD controllers/drivers
7.17
PCF2119X
Reset function
The PCF2119x must be reset externally when power is turned on. The reset executes a ‘clear display’, requiring
165 oscillator cycles. After the reset the chip has the state shown in Table 4.
Table 4
State after reset
STEP
FUNCTION
1
clear display
2
entry mode set
3
4
display control
function set
CONTROL BIT STATE
CONDITION
I/D = 1
+1 (increment)
S=0
no shift
D=0
display off
C=0
cursor off
B=0
cursor character blink off
DL = 1
8-bit interface
M=0
1-line display
H=0
normal instruction set
SL = 0
MUX 1 : 18 mode
5
default address pointer to DDRAM; the Busy Flag (BF) indicates the busy state (BF = 1) until
initialization ends; the busy state lasts 2 ms; the chip may also be initialized by software; see
Tables 18 and 19
6
icon control
7
display/screen configuration
L = 0; P = 0; Q = 0
default configurations
8
VLCD temperature coefficient
TC1 = 0; TC2 = 0
default temperature coefficient
9
set VLCD
VA = 0; VB = 0 (VLCD generator off)
10
I2C-bus
11
set HVgen stages
2003 Jan 30
IM, IB = 00
icons/icon blink disabled
interface reset
S1 = 1, S0 = 0
21
HVgen set to 3 internal stages
(4 voltage multipliers)
Philips Semiconductors
Product specification
LCD controllers/drivers
8
PCF2119X
INSTRUCTIONS
In normal use, category 3 instructions are used most
frequently. However, automatic incrementing by 1
(or decrementing by 1) of internal RAM addresses after
each data write lessens the MPU program load. The
display shift in particular can be performed concurrently
with display data write, enabling the designer to develop
systems in minimum time with maximum programming
efficiency.
Only two PCF2119x registers, the Instruction Register (IR)
and the Data Register (DR) can be directly controlled by
the MPU. Before internal operation, control information is
stored temporarily in these registers, to allow interfacing to
various types of MPUs which operate at different speeds
or to allow interface to peripheral control ICs. The
PCF2119x operation is controlled by the instructions
shown in Table 6 together with their execution time.
Details are explained in subsequent sections.
During internal operation, no instructions other than the
‘read busy flag’ and ‘read address’ instructions will be
executed. Because the busy flag is set to a logic 1 while an
instruction is being executed, check to ensure it is a logic 0
before sending the next instruction or wait for the
maximum instruction execution time, as given in Table 6.
An instruction sent while the busy flag is logic 1 will not be
executed.
Instructions are of 4 types, those that:
1. Designate PCF2119x functions such as display
format, data length, etc.
2. Set internal RAM addresses
3. Perform data transfer with internal RAM
4. Others.
Table 5
Instruction set for I2C-bus commands
CONTROL BYTE
Co RS 0
0
0
0
COMMAND BYTE
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 note 1
Note
1. R/W is set together with the slave address.
2003 Jan 30
I2C-BUS COMMANDS
22
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INSTRUCTION
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DESCRIPTION
REQUIRED
CLOCK
CYCLES
H = 0 or 1
NOP
0
0
0
0
0
0
0
0
0
0
no operation
3
Function set
0
0
0
0
1
DL
0
M
SL
H
sets interface Data Length (DL) and number of
display lines (M); single line/MUX 1 : 9 (SL),
extended instruction set control (H)
3
Read busy flag
and address
counter
0
1
BF
reads the Busy Flag (BF) indicating internal
operating is being performed and reads address
counter contents
0
AC
Read data
1
1
read data
reads data from CGRAM or DDRAM
3
Write data
1
0
write data
writes data from CGRAM or DDRAM
3
Clear display
0
0
0
0
0
0
0
0
0
1
clears entire display and sets DDRAM address 0
in address counter
165
Return home
0
0
0
0
0
0
0
0
1
0
sets DDRAM address 0 in address counter; also
returns shifted display to original position;
DDRAM contents remain unchanged
3
Entry mode set
0
0
0
0
0
0
0
1
I/D
S
sets cursor move direction and specifies shift of
display; these operations are performed during
data write and read
3
Display control
0
0
0
0
0
0
1
D
C
B
sets entire display on/off (D), cursor on/off (C) and
blink of cursor position character (B); D = 0
(display off) puts chip into the power-down mode
3
Cursor/display
shift
0
0
0
0
0
1
S/C
R/L
0
0
moves cursor and shifts display without changing
DDRAM contents
3
Set CGRAM
address
0
0
0
1
sets CGRAM address; bit 6 is to be set by the
command ‘set DDRAM address’; look at the
description of the commands
3
Set DDRAM
address
0
0
1
sets DDRAM address
3
0
0
0
do not use
−
Philips Semiconductors
Instruction set with parallel bus commands; note 1
LCD controllers/drivers
2003 Jan 30
Table 6
H=0
23
ACG
Reserved
0
0
0
0
0
0
1
Product specification
H=1
PCF2119X
ADD
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R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DESCRIPTION
REQUIRED
CLOCK
CYCLES
Screen
configuration
0
0
0
0
0
0
0
0
1
L
set screen configuration
3
Display
configuration
0
0
0
0
0
0
0
1
P
Q
set display configuration
3
Icon control
0
0
0
0
0
0
1
IM
IB
0
set icon mode (IM), icon blink (IB)
3
Temperature
control
0
0
0
0
0
1
0
0
Set HVgen
stages
0
0
0
1
0
0
0
0
Set VLCD
0
0
1
V
voltage
TC1 TC2 set temperature coefficient (TCx)
S1
S0
3
set internal HVgen stages (S1 = 1 and S0 = 1 not
allowed)
−
store VLCD in register VA or VB (V)
3
Philips Semiconductors
RS
LCD controllers/drivers
2003 Jan 30
INSTRUCTION
Note
1. X = don’t care.
24
Product specification
PCF2119X
Philips Semiconductors
Product specification
LCD controllers/drivers
Table 7
Explanations of symbols used in Table 6
STATE
BIT
I/D
S
D
C
B
S/C
R/L
DL
H
L (no impact, if
M = 1 or SL = 1)
P
Q
IM
IB
DM
V
M (no impact, if
SL = 1)
SL
C0
Table 8
PCF2119X
LOGIC 0
LOGIC 1
decrement
display freeze
display off
cursor off
cursor character blink off: character at cursor
position does not blink
cursor move
left shift
4 bits
use basic instruction set
left/right screen: standard connection (as in
PCF2114)
1st 16 characters of 32: columns are from
1 to 80
2nd 16 characters of 32: columns are from
1 to 80
column data: left to right (as in PCF2116);
column data is displayed from 1 to 80
row data top to bottom (as in PCF2116):
row data is displayed from 1 to 16 and icon row
data in 17 and 18
in single line mode (SL = 1) row data is
displayed from 1 to 8 and icon row data in 17
character mode; full display
icon blink disabled
direct mode disable
set VA
1-line by 32 display
increment
display shift
display on
cursor on
cursor character blink on: character at cursor
position blinks
display shift
right shift
8 bits
use extended instruction set
left/right screen: mirrored connection (as in
PCF2116)
1st 16 characters of 32: columns are from
1 to 80
2nd 16 characters of 32: columns are from
80 to 1
column data: right to left; column data is
displayed from 80 to 1
row data bottom to top:
row data is displayed from 16 to 1 and icon row
data in 18 and 17
in single line mode (SL = 1) row data is
displayed from 8 to 1 and icon row data in 17
icon mode; only icons displayed
icon blink enabled
direct mode enable
set VB
2-line by 16 display
MUX 1 : 18 (1 × 32 or 2 × 16 character display)
last control byte; see Table 5
MUX 1 : 9 (1 × 16 character display)
another control byte follows after data/command
Explanation of TC1 and TC2 used in Table 6
TC1
TC2
0
1
0
1
0
0
1
1
DESCRIPTION(1)
VLCD temperature coefficient 0
VLCD temperature coefficient 1
VLCD temperature coefficient 2
VLCD temperature coefficient 3
Note
1. For values of the temperature coefficients, see Chapter 13
2003 Jan 30
25
Philips Semiconductors
Product specification
LCD controllers/drivers
Table 9
PCF2119X
Explanation of S1 and S0 used in Table 6
S1
S0
0
o
1
1
0
1
0
1
DESCRIPTION
set internal HVgen stages to 1 (2 × voltages multiplier)
set internal HVgen stages to 2 (3 × voltages multiplier)
set internal HVgen stages to 3 (4 × voltages multiplier)
do not use
RS
R/W
E
DB7
IR7
IR3
BF
AC3
DR7
DR3
DB6
IR6
IR2
AC6
AC2
DR6
DR2
DB5
IR5
IR1
AC5
AC1
DR5
DR1
DB4
IR4
IR0
AC4
AC0
DR4
DR0
instruction
write
busy flag and
address counter read
Fig.16 4-bit transfer example.
2003 Jan 30
26
data register
read
MGA804
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
RS
R/W
E
internal
internal operation
DB7
IR7
IR3
busy
instruction
write
not
busy
AC3
busy flag
check
AC3
D7
busy flag
check
D3
instruction
write
MGA805
IR7, IR3: instruction 7th, 3rd bit.
AC3: address counter 3rd bit.
D7, D3: data 7th, 3rd bit.
Fig.17 An example of 4-bit data transfer timing sequence.
RS
R/W
E
internal
DB7
internal operation
data
instruction
write
busy
busy flag
check
busy
busy flag
check
not
busy
busy flag
check
Fig.18 Example of busy flag checking timing sequence.
2003 Jan 30
27
data
instruction
write
MGA806
Philips Semiconductors
Product specification
LCD controllers/drivers
8.1
PCF2119X
Clear display
When the display is off (D = 0) the chip is in partial
power-down mode:
‘Clear display’ writes character code 20H into all DDRAM
addresses (the character pattern for character code 20H
must be a blank pattern), sets the DDRAM address
counter to logic 0 and returns the display to its original
position, if it was shifted. Thus, the display disappears and
the cursor or blink position goes to the left edge of the
display. Sets entry mode I/D = 1 (increment mode). S of
entry mode does not change.
• The LCD outputs are connected to VSS
• The LCD generator and bias generator are turned off.
Three oscillator cycles are required after sending the
‘display off’ instruction to ensure all outputs are at VSS,
afterwards OSC can be stopped. If the oscillator is running
during partial power-down mode (‘display off’) the chip can
still execute instructions. Even lower current consumption
is obtained by inhibiting the oscillator (OSC = VSS).
The instruction ‘clear display’ requires extra execution
time. This may be allowed by checking the Busy Flag (BF)
or by waiting until the 165 clock cycles have elapsed. The
latter must be applied where no read-back options are
foreseen, as in some Chip-On-Glass (COG) applications.
8.2
To ensure IDD <1 µA, the parallel bus pads DB7 to DB0
should be connected to VDD; RS and R/W to VDD or left
open-circuit and PD to VDD. Recovery from power-down
mode: PD back to logic 0, if necessary OSC back to VDD
and send a ‘display control’ instruction with D = 1.
Return home
‘Return home’ sets the DDRAM address counter to logic 0
and returns the display to its original position if it was
shifted. DDRAM contents do not change. The cursor or
blink position goes to the left of the first display line.
I/D and S of entry mode do not change.
8.3
8.3.1
8.4.2
The cursor is displayed when C = 1 and inhibited when
C = 0. Even if the cursor disappears, the display functions
I/D, etc. remain in operation during display data write. The
cursor is displayed using 5 dots in the 8th line (see Fig.5).
Entry mode set
8.4.3
I/D
The cursor underline and the cursor character blink can be
set to display simultaneously.
S
8.5
When S = 1, the entire display shifts either to the right
(I/D = 0) or to the left (I/D = 1) during a DDRAM write. Thus
it appears as if the cursor stands still and the display
moves. The display does not shift when reading from the
DDRAM, or when writing to or reading from the CGRAM.
When S = 0, the display does not shift.
8.4
8.4.1
Cursor or display shift
‘Cursor/display shift’ moves the cursor position or the
display to the right or left without writing or reading display
data. This function is used to correct a character or move
the cursor through the display. In 2-line displays, the
cursor moves to the next line when it passes the last
position (40) of the line.
When the displayed data is shifted repeatedly all lines shift
at the same time; displayed characters do not shift into the
next line.
Display control (and partial power-down mode)
D
The display is on when D = 1 and off when D = 0. Display
data in the DDRAM is not affected and can be displayed
immediately by setting D to a logic 1.
2003 Jan 30
B
The character indicated by the cursor blinks when B = 1.
The cursor character blink is displayed by switching
between display characters and all dots on with a period of
f OSC
approximately 1 second, with f blink = ---------------52 224
When I/D = 1 (0) the DDRAM or CGRAM address
increments (decrements) by 1 when data is written into or
read from the DDRAM or CGRAM. The cursor or blink
position moves to the right when incremented and to the
left when decremented. The cursor underline and cursor
character blink are inhibited when the CGRAM is
accessed.
8.3.2
C
The Address Counter (AC) content does not change if the
only action performed is shift display, but increments or
decrements with the ‘cursor shift’.
28
Philips Semiconductors
Product specification
LCD controllers/drivers
8.6
8.6.1
PCF2119X
8.8
Function set
‘Set DDRAM address’ sets the DDRAM address ADD into
the address counter (binary A6 to A0). Data can then be
written to or read from the DDRAM.
DL (PARALLEL MODE ONLY)
Sets interface data width. Data is sent or received in bytes
(DB7 to DB0) when DL = 1 or in two nibbles (DB7 to DB4)
when DL = 0. When 4-bit width is selected, data is
transmitted in two cycles using the parallel bus. In a 4-bit
application DB3 to DB0 should be left open-circuit (internal
pull-ups). Hence in the first ‘function set’ instruction after
power-on, M, SL and H are set to logic 1. A second
‘function set’ must then be sent (2 nibbles) to set M,
SL and H to their required values.
8.9
At the same time, the value of the address counter
expressed in binary A6 to A0 is read out. The address
counter is used by both CGRAM and DDRAM, and its
value is determined by the previous instruction.
M
Selects either 1-line by 32 display (M = 0) or 2-line by
16 display (M = 1).
8.6.3
8.10
Whether the CGRAM or DDRAM is to be written into is
determined by the previous ‘set CGRAM address’ or ‘set
DDRAM address’ command. After writing, the address
automatically increments or decrements by 1, in
accordance with the entry mode. Only bits D4 to D0 of
CGRAM data are valid, bits D7 to D5 are ‘don’t care’.
H
When H = 0 the chip can be programmed via the standard
11 instruction codes used in the PCF2116 and other LCD
controllers.
8.11
The most recent ‘set address’ command determines
whether the CGRAM or DDRAM is to be read.
The ‘read data’ instruction gates the content of the Data
Register (DR) to the bus while E is HIGH. After E goes
LOW again, internal operation increments (or decrements)
the AC and stores RAM data corresponding to the new AC
into the DR.
Set CGRAM address
‘Set CGRAM address’ sets bits 5 to 0 of the CGRAM
address ACG into the address counter (binary A5 to A0).
Data can then be written to or read from the CGRAM.
Attention: the CGRAM address uses the same address
register as the DDRAM address and consists of 7 bits
(binary A6 to A0). With the ‘set CGRAM address’
command, only bits 5 to 0 are set. Bit 6 can be set using
the ‘set DDRAM address’ command first, or by using the
auto-increment feature during CGRAM write. All bits 6 to 0
can be read using the ‘read busy flag’ and ‘read address’
command.
There are only three instructions that update the data
register:
• ‘set CGRAM address’
• ‘set DDRAM address’
• ‘read data’ from CGRAM or DDRAM.
Other instructions (e.g. ‘write data’, ‘cursor/display shift’,
‘clear display’ and ‘return home’) do not modify the data
register content.
When writing to the lower part of the CGRAM, ensure that
bit 6 of the address is not set (e.g. by an earlier DDRAM
write or read action).
2003 Jan 30
Read data from CGRAM or DDRAM
‘Read data’ reads binary 8-bit data D7 to D0 from the
CGRAM or DDRAM.
When H = 1 the extended range of instructions will be
used. These are mainly for controlling the display
configuration and the icons.
8.7
Write data to CGRAM or DDRAM
‘Write data’ writes binary 8-bit data D7 to D0 to the
CGRAM or the DDRAM.
SL
Selects MUX 1 : 9, 1-line by 16 display (independent of
M and L). Only rows 1 to 8 and 17 are to be used. All other
rows must be left open-circuit. The DDRAM map is the
same as in the 2-line by 16 display mode, however, the
second line is not displayable.
8.6.4
Read busy flag and read address
‘Read busy flag’ and ‘read address’ read the Busy Flag
(BF) and Address Counter (AC). BF = 1 indicates that an
internal operation is in progress. The next instruction will
not be executed until BF = 0. It is recommended that the
BF status is checked before the next write operation is
executed.
‘Function set’ from the I2C-bus interface sets the DL bit to
logic 1.
8.6.2
Set DDRAM address
29
Philips Semiconductors
Product specification
LCD controllers/drivers
9
PCF2119X
9.4
EXTENDED FUNCTION SET INSTRUCTIONS AND
FEATURES
9.1
Icon blink control is independent of the cursor/character
blink function.
New instructions
When IB = 0, icon blink is disabled. Icon data is stored in
CGRAM character 0 to 3 (4 × 8 × 5 = 160 bits for
160 icons).
H = 1, sets the chip into alternate instruction set mode.
9.2
Icon control
When IB = 1, icon blink is enabled. In this case each icon
is controlled by two bits. Blink consists of two half phases
(corresponding to the cursor on and off phases called even
and odd phases hereafter).
The PCF2119x can drive up to 160 icons. See Fig.19 for
CGRAM to icon mapping.
9.3
IB
IM
When IM = 0, the chip is in character mode. In the
character mode characters and icons are driven
(MUX 1 : 18). The VLCD generator, if used, produces the
VLCD voltage programmed in register VA.
Icon states for the even phase are stored in CGRAM
characters 0 to 3 (4 × 8 × 5 = 160 bits for 160 icons).
These bits also define the icon state when icon blink is not
used.
When IM = 1, the chip is in icon mode. In the icon mode
only the icons are driven (MUX 1 : 2) and the VLCD voltage
generator, if used, produces the VLCD voltage as
programmed in register VB.
Icon states for the odd phase are stored in CGRAM
character 4 to 7 (another 160 bits for the 160 icons). When
icon blink is disabled CGRAM characters 4 to 6 may be
used as normal CGRAM characters.
Table 10 Blink effect for icons and cursor character blink
PARAMETER
EVEN PHASE
ODD PHASE
Cursor character blink
block (all on)
normal (display character)
Icons
state 1: CGRAM character 0 to 2
state 2: CGRAM character 4 to 6
2003 Jan 30
30
Philips Semiconductors
Product specification
LCD controllers/drivers
handbook, full pagewidth
display:
PCF2119X
COL 1 to 5
COL 6 to 10
COL 76 to 80
ROW 17 –
1
2
3
4
5
6
7
8
9
10
ROW 18 –
81
82
83
84
85
86
87
88
89
90
76
77
78
79
80
156 157 158 159 160
MGL249
block of 5 columns
icon
no.
handbook, full
pagewidth
phase
ROW/COL
character codes
7
6
5
4
3
2
CGRAM address
1
MSB
0
6
LSB
MSB
5
4
3
2
1
CGRAM data
0
4
3
2
1
LSB MSB
icon view
0
LSB
1-5
even
17/1-5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
6-10
even
17/6-10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
11-15
even
17/11-15
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
0
76-80
even
17/76-80
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
81-85
even
18/1-5
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
0
156-160
even
18/76-80
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
0
1
1-5
odd (blink)
17/1-5
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
156-160
odd (blink)
18/76-80
0
0
0
0
0
1
1
1
0
1
1
1
1
1
1
0
0
1
1
0
MGK999
CGRAM data bit = logic 1 turns the icon on, data bit = logic 0 turns the icon off.
Data in character codes 0 to 3 define the icon state when icon blink is disabled or during the even phase when icon blink is enabled.
Data in character codes 4 to 7 define the icon state during the odd phase when icon blink is enabled (not used for icons when icon blink is disabled).
Fig.19 CGRAM to icon mapping.
2003 Jan 30
31
Philips Semiconductors
Product specification
LCD controllers/drivers
9.5
PCF2119X
Normal/icon mode operation
IM
CONDITION
9.11
character mode
generates VA
1
icon mode
generates VB
9.6
The VLCD value is programmed by instruction. Two on-chip
registers hold VLCD values for the character mode and the
icon mode respectively (VA and VB). The generated VLCD
value is independent of VDD, allowing battery operation of
the chip.
VLCD
0
Direct mode
VLCD programming:
When DM = 0, the chip is not in direct mode. Either the
internal voltage generator or an external voltage may be
used to achieve the necessary VLCD value.
1. Send ‘function set’ instruction with H = 1
2. Send ‘set VLCD’ instruction to write to voltage register:
a) DB7, DB6 = 10: DB5 to DB0 are VLCD of character
mode (VA)
When DM = 1, the chip is in direct mode. The internal
voltage generator is turned off and the VLCD output is
directly connected to the HVgen supply voltage VDD2.
b) DB7, DB6 = 11: DB5 to DB0 are VLCD of icon mode
(VB)
The direct mode can be used to reduce the current
consumption when the required VLCD output voltage is
close to the VDD2 supply voltage. This can be the case in
icon mode or in Mux 1 : 9 (depending on LCD liquid
properties).
9.7
Set VLCD
c) DB5 to DB0 = 000000 switches VLCD generator off
(when selected)
d) During ‘display off’ and power-down the VLCD
generator is also disabled.
3. Send ‘function set’ instruction with H = 0 to resume
normal programming.
Voltage multiplier control
S[1:0]
9.12
A software configurable voltage multiplier is incorporated
and can be set via ‘Set HVgen stages’ command.
Reducing current consumption
Reducing current consumption can be achieved by one of
the options given in Table 11.
The voltage multiplier control can be used to reduce
current consumption by disconnecting internal voltage
multiplier stages (depending on the required VLCD output
voltage).
When VLCD lies outside the VDD range and must be
generated, it is usually more efficient to use the on-chip
generator than an external regulator.
9.8
Table 11 Reducing current consumption
Screen configuration
ORIGINAL MODE
L: default is L = 0.
ALTERNATIVE MODE
L = 0: the two halves of a split screen are connected in a
standard way i.e. column 1/81, 2/82 to 80/160.
Character mode
icon mode (control bit IM)
Display on
display off (control bit D)
L = 1: the two halves of a split screen are connected in a
mirrored way i.e. column 1/160, 2/159 to 80/81. This
allows single layer PCB or glass layout.
HV generator operating
direct mode
Any mode
power-down (PD pad)
9.9
Table 12 Use of the VA and VB registers
Display configuration
MODE
P, Q: default is P, Q = 0.
Normal operation VLCD character
mode
P = 1: mirrors the column data.
Q = 1: mirrors the row data.
9.10
TC1 and TC2
Default is TC1 and TC2 = 0. This selects the default
temperature coefficient for the internally generated VLCD.
TC1 and TC2 = 10, 01 and 11 selects alternative
temperature coefficients 1, 2 and 3 respectively.
2003 Jan 30
VA
32
VB
VLCD icon mode
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
The device that acknowledges must pull-down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration).
10 INTERFACES TO MPU
10.1
Parallel interface
The PCF2119x can send data in either two 4-bit operations
or one 8-bit operation and can thus interface to 4-bit or
8-bit microcontrollers.
A master receiver must signal an end of data to the
transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event
the transmitter must leave the data line HIGH to enable the
master to generate a STOP condition.
In 8-bit mode data is transferred as 8-bit bytes using the
8 data lines DB7 to DB0. Three further control lines
E, RS and R/W are required; see Section 6.1.
In 4-bit mode data is transferred in two cycles of 4 bits
each using pads DB7 to DB4 for the transaction. The
higher order bits (corresponding to DB7 to DB4 in 8-bit
mode) are sent in the first cycle and the lower order bits
(DB3 to DB0 in 8-bit mode) in the second. Data transfer is
complete after two 4-bit data transfers. It should be noted
that two cycles are also required for the busy flag check.
4-bit operation is selected by instruction, see Figs 16 to 18
for examples of bus protocol.
10.2.1
Before any data is transmitted on the I2C-bus, the device
which should respond is addressed first. The addressing is
always carried out with the first byte transmitted after the
START procedure. The I2C-bus configuration for the
different PCF2119x read and write cycles is shown in
Figs 24 to 26. The slow down feature of the I2C-bus
protocol (receiver holds SCL LOW during internal
operations) is not used in the PCF2119x.
In 4-bit mode, pads DB3 to DB0 must be left open-circuit.
They are pulled up to VDD internally.
10.2
I2C-BUS PROTOCOL
10.2.2
I2C-bus interface
DEFINITIONS
• Transmitter: the device which sends the data to the bus
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are the
Serial Data line (SDA) and the Serial Clock Line (SCL).
Both lines must be connected to a positive supply via
pull-up resistors. Data transfer may be initiated only when
the bus is not busy.
• Receiver: the device which receives the data from the
bus
• Master: the device which initiates a transfer, generates
clock signals and terminates a transfer
• Slave: the device addressed by a master
Each byte of eight bits is followed by an acknowledge bit.
The acknowledge bit is a HIGH level signal put on the bus
by the transmitter during which time the master generates
an extra acknowledge related clock pulse. A slave receiver
which is addressed must generate an acknowledge after
the reception of each byte.
• Multi-master: more than one master can attempt to
control the bus at the same time without corrupting the
message
Also a master receiver must generate an acknowledge
after the reception of each byte that has been clocked out
of the slave transmitter.
• Synchronization: procedure to synchronize the clock
signals of two or more devices.
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
• Arbitration: procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
MGA807
Fig.20 System configuration.
2003 Jan 30
33
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
handbook, full pagewidth
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBC621
Fig.21 Bit transfer.
handbook, full pagewidth
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
MBC622
Fig.22 Definition of START and STOP conditions.
handbook, full pagewidth
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
MBC602
Fig.23 Acknowledgement on the I2C-bus.
2003 Jan 30
34
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Philips Semiconductors
LCD controllers/drivers
handbook, full pagewidth
2003 Jan 30
acknowledgement
from PCF2119x
S
S 0 1 1 1 0 1 A 0 A 1 RS CONTROL BYTE A
DATA BYTE
A 0 RS CONTROL BYTE A
DATA BYTE
A P
0
slave address
R/W
Co
2n ≥ 0 bytes
1 byte
Co
n ≥ 0 bytes
update
data pointer
35
MGK899
S
0 1 1 1 0 1 A 0
0
PCF2119x
slave address
R/W
Product specification
PCF2119X
Fig.24 Master transmits to slave receiver; write mode.
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S
S 0 1 1 1 0 1 A 0 A 1 RS CONTROL BYTE A
DATA BYTE
A 0 RS CONTROL BYTE A
DATA BYTE(1)
Philips Semiconductors
LCD controllers/drivers
handbook, full pagewidth
2003 Jan 30
acknowledgement
A
0
slave address
2n
R/W
0 bytes
n ≥ 0 bytes
1 byte
Co
Co
36
acknowledgement
S
SLAVE
ADDRESS
S
A 1 A
0
acknowledgement
DATA BYTE
A
n bytes
R/W
Co
no acknowledgement
DATA BYTE
1 P
last byte
update
data pointer
update
data pointer
MGG003
Product specification
Fig.25 Master reads after setting word address; writes word address, set RS; ‘read data’.
PCF2119X
(1) Last data byte is a dummy byte (may be omitted).
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
acknowledgement
from PCF2113x
handbook, full pagewidth
S
SLAVE
ADDRESS
S
A 1 A
0
acknowledgement
from master
DATA BYTE
A
n bytes
R/W
Co
no acknowledgement
from master
DATA BYTE
1 P
last byte
update
data pointer
update
data pointer
MGG004
Fig.26 Master reads slave immediately after first byte; read mode (RS previously defined).
handbook, full pagewidth
SDA
t BUF
tf
t LOW
SCL
t HD;STA
t HD;DAT
tr
t HIGH
t SU;DAT
SDA
MGA728
t SU;STA
Fig.27 I2C-bus timing diagram.
2003 Jan 30
37
t
SU;STO
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
11 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD1
logic supply voltage
−0.5
+6.5
V
VDD2, VDD3
high voltage generator supply voltage
−0.5
+4.5
V
VLCD
LCD supply voltage
−0.5
+7.5
V
VDD(I/O)
any VDD related input/output voltage
−0.5
VDD + 0.5
V
VLCD(I/O)
any VLCD related input/output voltage
−0.5
VLCD + 0.5
V
II
DC input current
−10
+10
mA
IO
DC output current
IDD, ISS and ILCD VDD1, VDD2, VDD3, VSS1, VSS2 or VLCD current
−10
+10
mA
−50
+50
mA
mW
Ptot
total power dissipation
−
400
PO
power dissipation per output
−
100
mW
Tstg
storage temperature
−65
+150
°C
12 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”).
2003 Jan 30
38
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
13 DC CHARACTERISTICS
VDD1 = 1.5 to 5.5 V; VDD2 = VDD3 = 2.2 to 4.0 V; VSS = 0 V; VLCD = 2.2 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD1
logic supply voltage
VDD2,
VDD3
high voltage generator supply
voltage
VLCD
LCD supply voltage
internal VLCD generation
(VDD2 = VDD3 < VLCD)
1.5
−
5.5
V
2.2
−
4.0
V
2.2
−
6.5
V
GROUND SUPPLY CURRENT (ISS); EXTERNAL VLCD; note 1
ISS1
ground supply current 1
−
70
120
µA
ISS3
ground supply current 3
VDD = 3 V; VLCD = 5 V;
note 2
−
35
80
µA
ISS4
ground supply current 4
icon mode; VDD = 3 V;
VLCD = 2.5 V; note 2
−
25
45
µA
ISS5
ground supply current 5
power-down mode;
VDD = 3 V; VLCD = 2.5 V;
DB7 to DB0,
RS and R/W = 1; OSC = 0;
PD = 1
−
0.5
5
µA
−
190
400
µA
GROUND SUPPLY CURRENT (ISS); INTERNAL VLCD; notes 1 and 3
ISS6
ground supply current 6
ISS8
ground supply current 8
VDD = 3 V; VLCD = 5 V;
note 2
−
135
400
µA
ISS9
ground supply current 9
icon mode; VDD = 2.5 V;
VLCD = 2.5 V; note 2
−
85
−
µA
VSS1
−
0.3VDD1
V
Logic
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
0.7VDD1
−
VDD1
V
VIL(osc)
LOW-level input voltage
pad OSC
VDD = VDD(min), VDD(max)
VSS1
−
VDD1 − 1.2
V
VIH(osc)
HIGH-level voltage pad OSC
VDD = VDD(min), VDD(max)
VDD1 − 0.1
−
VDD1
V
IOL(DB)
LOW-level output current pads
DB7 to DB0
VOL = 0.4 V; VDD1 = 5 V
1.6
4
−
mA
IOH(DB)
HIGH-level output current pads
DB7 to DB0
VOH = 4 V; VDD1 = 5 V
−1
−8
−
mA
Ipu
pull-up current pads DB7 to DB0 VI = VSS, VDD(min), VDD(max)
0.04
0.15
1
µA
IL
leakage current
−1
−
+1
µA
2003 Jan 30
VI = VDD1,2,3 or VSS1,2
39
Philips Semiconductors
Product specification
LCD controllers/drivers
SYMBOL
PCF2119X
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I2C-bus
SDA AND SCL
VIL2
LOW-level input voltage
0
−
0.3VDD
V
VIH2
HIGH-level input voltage
0.7VDD
−
5.5
V
ILI
input leakage current
−1
−
+1
µA
Ci
input capacitance
−
5
−
pF
IOL(SDA)
LOW-level output current SDA
VOL = 0.4 V; VDD > 2 V
3
−
−
mA
VOL = 0.2VDD; VDD < 2 V
2
−
−
mA
VI = VDD or VSS
LCD outputs
RO(ROW)
row output resistance pads
R1 to R18
note 4
−
10
30
kΩ
RO(COL)
column output resistance pads
C1 to C80
note 4
−
15
40
kΩ
Vbias(tol)
bias tolerance pads R1 to R18
and C1 to C80
note 5
−
20
130
mV
VLCD(tol)
VLCD tolerance
Tamb = 25 °C; note 3
VLCD < 3 V
−
−
160
mV
VLCD < 4 V
−
−
200
mV
VLCD < 5 V
−
−
260
mV
VLCD < 6 V
340
mV
−
−
TC0
VLCD temperature coefficient 0
−
−0.16 −
%/K
TC1
VLCD temperature coefficient 1
−
−0.18 −
%/K
TC2
VLCD temperature coefficient 2
−
−0.21 −
%/K
TC3
VLCD temperature coefficient 3
−
−0.24 −
%/K
Notes
1. LCD outputs are open-circuit; inputs at VDD or VSS; bus inactive.
2. Tamb = 25 °C; fOSC = 200 kHz.
3. LCD outputs are open-circuit; HV generator is on; load current ILCD = 5 µA.
4. Resistance of output terminals (R1 to R18 and C1 to C80) with a load current of 10 µA; outputs measured one at a
time; external VLCD; VLCD = 3 V; VDD1 = VDD2 = VDD3 = 3 V.
5. LCD outputs open-circuit; external VLCD.
2003 Jan 30
40
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
14 AC CHARACTERISTICS
VDD1 = 1.5 to 5.5 V; VDD2 = VDD3 = 2.2 to 4.0 V; VSS = 0 V; VLCD = 2.2 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
VDD = 5.0 V
MIN.
TYP.
MAX.
UNIT
fFR
LCD frame frequency (internal clock)
45
95
147
Hz
fOSC
oscillator frequency (not available at any
pad)
140
250
450
kHz
fOSC(ext)
external clock frequency
140
−
450
kHz
tOSCST
oscillator start-up time after power-down
−
200
300
µs
note 1
Bus timing characteristics: parallel interface; note 2
WRITE OPERATION (WRITING DATA FROM MPU TO PCF2119X)
Tcy(en)
enable cycle time
500
−
−
ns
tW(en)
enable pulse width
220
−
−
ns
tsu(A)
address set-up time
50
−
−
ns
th(A)
address hold time
25
−
−
ns
tsu(D)
data set-up time
60
−
−
ns
th(D)
data hold time
25
−
−
ns
READ OPERATION (READING DATA FROM PCF2119X TO MPU)
Tcy(en)
enable cycle time
500
−
−
ns
tW(en)
enable pulse width
220
−
−
ns
tsu(A)
address set-up time
50
−
−
ns
th(A)
address hold time
25
−
−
ns
td(D)
data delay time
VDD1 > 2.2 V
−
−
150
ns
VDD1 > 1.5 V
−
−
250
ns
20
−
100
ns
th(D)
data hold time
Timing characteristics: I2C-bus interface; note 2
fSCL
SCL clock frequency
−
−
400
kHz
tLOW
SCL clock low period
1.3
−
−
µs
tHIGH
SCL clock high period
0.6
−
−
µs
tSU;DAT
data set-up time
100
−
−
ns
tHD;DAT
data hold time
0
−
−
ns
tr
SCL, SDA rise time
notes 1 and 3
15 + 0.1CB
−
300
ns
tf
SCL, SDA fall time
notes 1 and 3
15 + 0.1CB
−
300
ns
CB
capacitive bus line load
−
−
400
pF
tSU;STA
set-up time for a repeated START
condition
0.6
−
−
µs
tHD;STA
START condition hold time
0.6
−
−
µs
tSU;STO
set-up time for STOP condition
0.6
−
−
µs
tSW
tolerable spike width on bus
−
−
50
ns
tBUF
bus free time between STOP and START
condition
1.3
−
−
µs
2003 Jan 30
41
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
Notes
1. Tested on a sample basis.
2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
VIL and VIH with an input voltage swing of VSS to VDD.
3. CB = total capacitance of one bus line in pF.
15 TIMING CHARACTERISTICS
handbook, full pagewidth
RS
VIH1
V IL1
VIH1
VIL1
t su(A)
R/W
t h(A)
V IL1
VIL1
t h(A)
tW(en)
VIH1
VIH1
VIL1
E
VIL1
VIL1
t h(D)
t su(D)
VIH1
valid data
VIL1
DB0 to DB7
VIH1
VIL1
MBK474
Tcy(en)
Fig.28 Parallel bus write operation sequence; writing data from MPU to PCF2119x.
handbook, full pagewidth
RS
VIH1
V IL1
VIH1
VIL1
tsu(A)
R/W
t h(A)
VIH1
VIH1
tW(en)
E
VIL1
VIH1
t h(A)
VIH1
VIL1
DB0 to DB7
VIL1
t h(D)
t d(D)
VOH1
VOL1
VOH1
VOL1
Tcy(en)
MBK475
Fig.29 Parallel bus read operation sequence; reading data from PCF2119x to MPU.
2003 Jan 30
42
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
16 APPLICATION INFORMATION
16.1
Higher track resistance reduces performance and
increases current consumption.
General information
To avoid accidental triggering of power-on reset
(especially in COG applications), the supplies must be
adequately decoupled. Depending on power supply
quality, VDD1 may have to be raised above the specified
minimum value.
The required minimum value for the external capacitors in
an application with the PCF2119x are as follows: Cext for
VLCD and VSS1,2 = 100 nF (min.), and for VDD1,2,3 and
VSS1,2 = 470 nF. Higher capacitor values are
recommended for ripple rejection.
When external VLCD is supplied, VLCD2 should be left
open-circuit to avoid any stray current, and VLCD1 must be
connected to VLCDSENSE.
For COG applications the recommended ITO track
resistance is to be minimized for the I/O and supply
connections. Optimized values for these are below 50 Ω
for the supply and below 100 Ω for the I/O connections.
handbook, full pagewidth
P80CL51
P20
RS
P21
R/W
P22
E
P17 to P10
8
PCF2119x
R17, R18
2
R1 to R16
2 × 16 CHARACTER
LCD DISPLAY
PLUS 160 ICONS
16
C1 to C80
DB7 to DB0
80
MGK895
Fig.30 Direct connection to 8-bit MPU; 8-bit bus.
handbook, full pagewidth
P80CL51
P10
RS
P11
R/W
P12
E
P17 to P14
4
PCF2119x
R17, R18
2
R1 to R16
2 × 16 CHARACTER
LCD DISPLAY
PLUS 160 ICONS
16
C1 to C80
DB7 to DB4
80
MGK896
Fig.31 Direct connection to 8-bit MPU; 4-bit bus.
2003 Jan 30
43
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
handbook, full pagewidth
OSC
VDD
R17, R18
2
R1 to R16
2 × 16 CHARACTER
LCD DISPLAY
PLUS 160 ICONS
VDD
PCF2119x
100
nF
16
VLCD
100
nF
VSS
C1 to C80
80
VSS
8
DB7 to DB0 E
MGK897
RS R/W
Fig.32 Typical application using parallel interface.
handbook, full pagewidth
VDD VDD
VDD
OSC
VDD
DB3/SAO
2
R1 to R16
2 × 16 CHARACTER
LCD DISPLAY
PLUS 160 ICONS
VDD
PCF2119x
100
nF
R17, R18
16
VLCD
100
nF
VSS
VSS
C1 to C80
80
R17, R18
2
R1 to R16
1 × 32 CHARACTER
LCD DISPLAY
PLUS 160 ICONS
SCL SDA
VSS
OSC
VDD
DB3/SAO
VDD
PCF2119x
100
nF
VSS
SCL SDA
16
VLCD
100
nF
C1 to C80
VSS
80
SCL SDA
MASTER TRANSMITTER
PCF84C81A; P80CL410
MGK898
Fig.33 Application using I2C-bus interface.
2003 Jan 30
44
Philips Semiconductors
Product specification
LCD controllers/drivers
16.2
PCF2119X
For each multiplication factor there is a separate line. The
line ends where it is not possible to get a higher voltage
under its conditions (a higher multiplication factor is
needed to get higher voltages).
Charge pump characteristics
Typical graphs of the total power consumption of the
PCF2119x using the internal charge pump are illustrated
in Figs.34 to 36.
Connecting different displays may result in different
current consumption. This affects the efficiency and the
optimum multiplication factor to be used to generate a
certain output voltage.
The graphs were obtained under the following conditions:
• Tamb = 25 °C
• VDD1 = VDD2 = VDD3 = 2.2 V (min.), 2.7 V (typ.) and 4 V
(max.)
• Normal mode
• fosc = internal oscillator
• Mux 1 : 18
• Typical current load for ILCD = 10 µA.
MGW573
400
handbook, full pagewidth
I
DD
(µA)
350
300
(2)
250
200
(3)
150
(1)
100
50
0
0
2.75
3.5
4.25
5
5.75
(1) 2 × multiplication factor.
(2) 3 × multiplication factor.
(3) 4 × multiplication factor.
Fig.34 Typical charge pump characteristics for VDD = 2.2 V.
2003 Jan 30
45
6.5
Vop (V)
7.25
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
MGW574
300
handbook, full pagewidth
IDD
(µA)
250
(3)
200
(2)
150
(1)
100
50
0
0
2.75
3.5
4.25
5
5.75
6.5
(1) 2 × multiplication factor.
(2) 3 × multiplication factor.
(3) 4 × multiplication factor.
Vop (V)
7.25
Fig.35 Typical charge pump characteristics for VDD = 2.7 V.
MGW575
250
handbook, full pagewidth
IDD
(µA)
(3)
200
(2)
150
(1)
100
50
0
0
2.75
3.5
4.25
5
(1) 2 × multiplication factor.
(2) 3 × multiplication factor.
(3) 4 × multiplication factor.
Fig.36 Typical charge pump characteristics for VDD = 4 V.
2003 Jan 30
46
5.75
6.5
Vop (V)
7.25
Philips Semiconductors
Product specification
LCD controllers/drivers
16.3
PCF2119X
8-bit operation, 1-line display using external
reset
16.5
For a 2-line display, the cursor automatically moves from
the first to the second line after the 40th digit of the first line
has been written. Thus, if there are only 8 characters in the
first line, the DDRAM address must be set after the 8th
character is completed (see Table 6). It should be noted
that both lines of the display are always shifted together;
data does not shift from one line to the other.
Table 14 shows an example of a 1-line display in 8-bit
operation. The PCF2119x functions must be set by the
‘function set’ instruction prior to display. Since the DDRAM
can store data for 80 characters, the RAM can be used for
advertising displays when combined with display shift
operation. Since the display shift operation changes
display position only and the DDRAM contents remain
unchanged, display data entered first can be displayed
when the ‘return home’ operation is performed.
16.4
8-bit operation, 2-line display
16.6
I2C-bus operation, 1-line display
A control byte is required with most commands
(see Table 17).
4-bit operation, 1-line display using external
reset
The program must set functions prior to a 4-bit operation,
see Table 13. When power is turned on, 8-bit operation is
automatically selected and the PCF2119x attempts to
perform the first write as an 8-bit operation. Since nothing
is connected to DB0 to DB3, a rewrite is then required.
However, since one operation is completed in two
accesses of 4-bit operation, a rewrite is required to set the
functions (see Table 13 step 3). Thus, DB4 to DB7 of the
‘function set’ are written twice.
Table 13 4-bit operation, 1-line display example; using external reset
STEP
INSTRUCTION
1
power supply on (PCF2119x is initialized by
the external reset)
2
function set
RS
0
3
4
5
6
R/W
0
DB7
DB6
DISPLAY
DB5
initialized; no display appears
DB4
0
0
1
0
OPERATION
sets to 4-bit operation; in this instance operation
is handled as 8-bits by initialization and only this
instruction completes with one write
function set
0
0
0
0
1
0
0
0
0
0
0
0
sets to 4-bit operation, selects 1-line display and
VLCD = V0; 4-bit operation starts from this point
and resetting is needed
display on/off control
0
0
0
0
0
0
0
0
1
1
1
0
_
turns on display and cursor; entire display is
blank after initialization
_
sets mode to increment the address by 1 and to
shift the cursor to the right at the time of write to
the DD/CGRAM; display is not shifted
P_
writes ‘P’; the DDRAM has already been selected
by initialization at power-on; the cursor is
incremented by 1 and shifted to the right
entry mode set
0
0
0
0
0
0
0
0
0
1
1
0
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
1
1
0
0
0
0
0
2003 Jan 30
47
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INSTRUCTION
DISPLAY
1
power supply on (PCF2119x is initialized by the external
reset)
2
function set
3
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
0
0
0
0
sets to 8-bit operation, selects 1-line display and
VLCD = V0
0
0
48
0
0
0
1
1
1
0
_
turns on display and cursor; entire display is blank after
initialization
0
0
0
0
0
0
1
1
0
_
sets mode to increment the address by 1 and to shift the
cursor to the right at the time of the write to the
DD/CGRAM; display is not shifted
0
0
0
0
P_
writes ‘P’; the DDRAM has already been selected by
initialization at power-on; the cursor is incremented by 1
and shifted to the right
1
0
0
0
PH_
‘write data’ to CGRAM/DDRAM
1
6
1
entry mode set
0
5
0
display mode on/off control
0
4
initialized; no display appears
0
0
OPERATION
Philips Semiconductors
STEP
LCD controllers/drivers
2003 Jan 30
Table 14 8-bit operation, 1-line display example; using external reset
0
0
1
0
1
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
0
7 to 11
writes ‘H’
|
|
12
‘write data’ to CGRAM/DDRAM
1
13
0
1
0
0
1
1
PHILIPS_
writes ‘S’
0
0
0
0
0
0
1
1
1
PHILIPS_
sets mode for display shift at the time of write
0
0
0
0
0
0
HILIPS _
writes space
1
1
0
1
ILIPS
writes ‘M’
0
1
0
0
1
0
0
M_
|
|
|
PCF2119X
0
Product specification
‘write data’ to CGRAM/DDRAM
1
16
1
‘write data’ to CGRAM/DDRAM
1
15
0
entry mode set
0
14
0
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17
‘write data’ to CGRAM/DDRAM
18
cursor/display shift
1
0
19
0
1
1
1
1
MICROKO
writes ‘O’
0
0
1
0
0
0
0
MICROKO
shifts only the cursor position to the left
0
0
0
0
1
0
0
0
0
MICROKO
shifts only the cursor position to the left
0
0
1
0
0
0
0
1
1
ICROCO
writes ‘C’ correction; the display moves to the left
0
0
0
0
1
1
1
0
0
MICROCO
shifts the display and cursor to the right
0
0
1
0
1
0
0
MICROCO_
shifts only the cursor to the right
1
1
0
1
ICROCOM_
writes ‘M’
cursor/display shift
0
23
0
cursor/display shift
0
22
0
1
‘write data’ to CGRAM/DDRAM
1
21
0
0
OPERATION
cursor/display shift
0
20
0
DISPLAY
Philips Semiconductors
INSTRUCTION
LCD controllers/drivers
2003 Jan 30
STEP
0
0
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
0
24
|
49
|
|
25
return home
0
0
0
0
0
0
0
0
1
0
PHILIPS M
returns both display and cursor to the original position
(address 0)
Product specification
PCF2119X
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INTRODUCTION
DISPLAY
1
power supply on (PCF2119x is initialized by the external
reset)
2
function set
3
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
0
0
0
0
sets to 8-bit operation, selects 1-line display and
VLCD = V0
0
0
50
0
0
0
1
1
1
0
_
turns on display and cursor; entire display is blank after
initialization
0
0
0
0
0
0
1
1
0
_
sets mode to increment the address by 1 and to shift the
cursor to the right at the time of the write to the
DD/CGRAM; display is not shifted
0
0
0
0
0
0
_
sets the CGRAM address to position of character 0; the
CGRAM is selected
1
0
1
0
_
set CGRAM address
0
6
1
entry mode set
0
5
0
display mode on/off control
0
4
initialized; no display appears
0
0
OPERATION
Philips Semiconductors
STEP
LCD controllers/drivers
2003 Jan 30
Table 15 8-bit operation, 1-line display and icon example; using external reset
0
0
1
‘write data’ to CGRAM/DDRAM
1
0
0
0
0
0
7
writes data to CGRAM for icon even phase; icons appears
|
|
8
set CGRAM address
0
9
0
0
1
1
1
0
0
0
0
_
sets the CGRAM address to position of character 4; the
CGRAM is selected
1
0
1
0
_
writes data to CGRAM for icon odd phase
‘write data’ to CGRAM/DDRAM
1
0
0
0
0
0
10
|
|
function set
12
0
0
1
1
0
0
0
1
_
sets H = 1
0
0
0
0
1
0
1
0
_
icons blink
0
0
1
1
0
0
0
1
_
sets H = 0
icon control
0
13
0
0
function set
0
0
PCF2119X
0
Product specification
11
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0
1
0
0
0
0
0
0
0
sets the DDRAM address to the first position; DDRAM is
selected
0
0
0
0
P_
writes ‘P’; the cursor is incremented by 1 and shifted to the
right
1
0
0
0
PH_
writes ‘H’
‘write data’ to CGRAM/DDRAM
1
16
OPERATION
set DDRAM address
0
15
DISPLAY
0
0
1
0
1
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
0
17 to 20
|
|
21
Philips Semiconductors
14
INTRODUCTION
LCD controllers/drivers
2003 Jan 30
STEP
return home
0
0
0
0
0
0
0
0
1
0
PHILIPS
returns both display and cursor to the original position
(address 0)
51
Product specification
PCF2119X
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INTRODUCTION
DISPLAY
1
power supply on (PCF2119x is initialized by the external
reset)
2
function set
3
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
sets to 8-bit operation; selects 2-line display and voltage
generator off
1
1
0
0
0
0
0
0
0
0
1
1
1
0
_
turns on display and cursor; entire display is blank after
initialization
0
0
0
0
0
0
1
1
0
_
sets mode to increment the address by 1 and to shift the
cursor to the right at the time of write to the CG/DDRAM;
display is not shifted
0
0
0
0
P_
writes ‘P’; the DDRAM has already been selected by
initialization at power-on; the cursor is incremented by 1
and shifted to the right
‘write data’ to CGRAM/DDRAM
1
52
1
entry mode set
0
5
0
display on/off control
0
4
initialized; no display appears
0
0
OPERATION
Philips Semiconductors
STEP
LCD controllers/drivers
2003 Jan 30
Table 16 8-bit operation, 2-line display example; using external reset
0
0
1
0
1
6 to 10
|
|
|
11
‘write data’ to CGRAM/DDRAM
1
12
1
0
1
0
0
1
1
PHILIPS_
writes ‘S’
0
1
1
0
0
0
0
0
0
PHILIPS
_
sets DDRAM address to position the cursor at the head of
the 2nd line
1
1
0
1
PHILIPS
M_
writes ‘M’
‘write data’ to CGRAM/ DDRAM
1
0
0
1
0
0
|
|
Product specification
|
PCF2119X
14 to 19
0
set DDRAM address
0
13
0
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0
0
1
0
0
1
1
1
1
PHILIPS
MICROCO_
writes ‘O’
0
1
1
1
PHILIPS
MICROCO_
sets mode for display shift at the time of write
1
1
0
1
PHILIPS
ICROCOM_
writes ‘M’; display is shifted to the left; the first and second
lines shift together
‘write data’ to CGRAM/DDRAM
0
22
OPERATION
‘write data’ to CGRAM/DDRAM
1
21
DISPLAY
0
0
0
0
0
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
0
23
|
Philips Semiconductors
20
INTRODUCTION
LCD controllers/drivers
2003 Jan 30
STEP
|
|
24
return home
0
0
0
0
0
0
0
0
1
0
PHILIPS
MICROCOM
returns both display and cursor to the original position
(address 0)
53
Product specification
PCF2119X
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1
I2C-bus
2
slave address for write
DISPLAY
start
initialized; no display appears
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack
0
3
4
1
1
1
0
1
0
0
1
during the acknowledge cycle SDA will be pulled-down by the
PCF2119x
control byte sets RS for following data bytes
send a control byte for ‘function set’
Co
RS
0
0
0
0
0
0
Ack
0
0
0
0
0
0
0
0
1
function set
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
5
0
1
X
0
0
0
0
display on/off control
0
0
0
0
1
1
1
0
54
0
0
0
7
I2C start
8
slave address for write
0
1
1
0
_
sets mode to increment the address by 1 and to shift the cursor
to the right at the time of write to the DDRAM or CGRAM; display
is not shifted
_
for writing data to DDRAM, RS must be set to 1; therefore a
control byte is needed
1
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack
0
1
1
1
0
1
0
0
1
_
send a control byte for ‘write data’
Co
RS
0
0
0
0
0
0
Ack
0
1
0
0
0
0
0
0
1
_
‘write data’ to DDRAM
1
0
1
0
0
0
0
writes ‘P’; the DDRAM has been selected at power-up; the
cursor is incremented by 1 and shifted to the right
PH_
writes ‘H’
1
‘write data’ to DDRAM
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
1
0
0
1
0
0
0
1
Product specification
0
P_
PCF2119X
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
11
turns on display and cursor; entire display shows character 20H
(blank in ASCII-like character sets)
entry mode set
0
10
_
1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
9
selects 1-line display and VLCD = V0; SCL pulse during
acknowledge cycle starts execution of instruction
1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
6
OPERATION
Philips Semiconductors
I2C BYTE
STEP
LCD controllers/drivers
2003 Jan 30
Table 17 Example of I2C-bus operation; 1-line display (using external reset, assuming SA0 = VSS; note 1)
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12 to 15
OPERATION
|
|
|
|
16
‘write data’ to DDRAM
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
1
0
1
0
0
1
1
17
(optional I2C stop) I2C start + slave address for write
(as step 8)
18
control byte
19
Co
RS
0
0
0
0
0
0
Ack
1
0
0
0
0
0
0
0
1
55
0
21
0
0
0
0
0
1
0
I2C start
PHILIPS_
PHILIPS
sets DDRAM address 0 in address counter (also returns shifted
display to original position; DDRAM contents unchanged); this
instruction does not update the Data Register (DR)
PHILIPS
slave address for read
0
23
PHILIPS_
1
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack
22
writes ‘S’
return home
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
20
PHILIPS_
1
Philips Semiconductors
DISPLAY
LCD controllers/drivers
2003 Jan 30
I2C BYTE
STEP
1
1
1
0
1
0
1
PHILIPS
during the acknowledge cycle the content of the DR is loaded
into the internal I2C-bus interface to be shifted out; in the
previous instruction neither a ‘set address’ nor a ‘read data’ has
been performed; therefore the content of the DR was unknown;
the R/W has to be set to 1 while still in I2C-write mode
PHILIPS
DDRAM content will be read from following instructions
PHILIPS
8 × SCL; content loaded into interface during previous
acknowledge cycle is shifted out over SDA; MSB is DB7; during
master acknowledge content of DDRAM address 01 is loaded
into the I2C-bus interface
1
control byte for read
Co
RS
0
0
0
0
0
0
Ack
0
1
1
0
0
0
0
0
1
‘read data’: 8 × SCL + master acknowledge; note 2
X
X
X
X
X
X
X
0
Product specification
X
PCF2119X
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
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‘read data’: 8 × SCL + master acknowledge; note 2
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
25
1
0
0
1
0
0
0
PHILIPS
8 × SCL; code of letter ‘H’ is read first; during master
acknowledge code of ‘I’ is loaded into the I2C interface
PHILIPS
no master acknowledge; after the content of the I2C-bus
interface register is shifted out no internal action is performed;
no new data is loaded to the interface register, data register is
not updated, address counter is not incremented and cursor is
not shifted
0
‘read data’: 8 × SCL + no master acknowledge; note 2
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
26
OPERATION
1
I2C stop
0
0
1
0
0
1
1
PHILIPS
Philips Semiconductors
24
DISPLAY
LCD controllers/drivers
2003 Jan 30
I2C BYTE
STEP
Notes
1. X = don’t care.
2. SDA is left at high-impedance by the microcontroller during the read acknowledge.
56
Product specification
PCF2119X
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DESCRIPTION
power-on or unknown state
|
wait 2 ms after external reset has been applied
|
RS
R/W
DB7
DB6
DB5
0
0
0
0
1
DB4
DB3
DB2
DB1
DB0
BF cannot be checked before this instruction
1
X
X
X
X
function set (interface is 8 bits long)
|
wait 2 ms
|
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
BF cannot be checked before this instruction
0
0
0
0
1
1
X
X
X
X
function set (interface is 8 bits long)
DB4
DB3
DB2
DB1
DB0
BF cannot be checked before this instruction
1
X
X
X
X
Philips Semiconductors
STEP
LCD controllers/drivers
2003 Jan 30
Table 18 Initialization by instruction, 8-bit interface (note 1)
|
wait more than 40 µs
|
57
RS
R/W
DB7
DB6
DB5
0
0
0
0
1
|
|
RS
R/W
DB7
DB6
DB5
function set (interface is 8 bits long)
BF can be checked after the following instructions; when BF is not checked,
the waiting time between instructions is the specified instruction time
(see Table 3)
DB4
DB3
DB2
DB1
DB0
function set (interface is 8 bits long); specify the number of display lines
0
0
0
0
1
1
0
M
0
H
0
0
0
0
0
0
1
0
0
0
display off
0
0
0
0
0
0
0
0
0
1
clear display
0
0
0
0
0
0
0
1
I/D
S
entry mode set
|
Initialization ends
Product specification
1. X = don’t care.
PCF2119X
Note
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DESCRIPTION
power-on or unknown state
|
Wait 2 ms after external reset has been applied
|
RS
0
R/W
0
DB7
DB6
0
0
DB5
1
DB4
1
BF cannot be checked before this instruction
function set (interface is 8 bits long)
|
Wait 2 ms
|
RS
0
R/W
0
DB7
DB6
0
0
DB5
1
DB4
1
Philips Semiconductors
STEP
LCD controllers/drivers
2003 Jan 30
Table 19 Initialization by instruction, 4-bit interface; not applicable for I2C-bus operation
BF cannot be checked before this instruction
function set (interface is 8 bits long)
|
Wait 40 µs
|
58
RS
0
R/W
0
DB7
DB6
0
0
DB5
1
DB4
1
function set (interface is 8 bits long)
|
RS
0
R/W
0
BF can be checked after the following instructions; when BF is not checked, the waiting time
between instructions is the specified instruction time (see Table 3)
DB7
DB6
0
BF cannot be checked before this instruction
0
DB5
1
DB4
function set (set interface to 4 bits long)
0
interface is 8 bits long
0
0
0
1
0
function set (interface is 4 bits long)
0
0
0
M
0
H
specify number of display lines
0
0
0
0
0
0
0
0
1
0
0
0
display off
0
0
0
0
0
0
clear display
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
I/D
S
|
Initialization ends
entry mode set
PCF2119X
0
Product specification
0
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
17 DEVICE PROTECTION DIAGRAMS
handbook, full pagewidth
VSS2
VDD2
VSS1
VDD3
VSS1
VDD1
VSS1
VSS2
MGW576
VSS1
Fig.37 Protection of LV supplies.
LCD O/Is
handbook, full pagewidth
VLCDIN
VLCDSENSE, VLCD2,VLCD1
VSS1
VSS1
MGW577
Fig.38 Protection of HV supplies and I/Os.
handbook, full pagewidth
I 2 C-bus PADS
CONTROL PINS
VDD1
VDD1
E, T1, T2, T3, POR, PD,
RW, RS, DB0 to DB7, OSC
VSS1
VSS1
Fig.39 Protection of I/Os.
2003 Jan 30
59
MGW578
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
18 BONDING PAD LOCATIONS
handbook, full pagewidth
7.64
mm
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
C65
C64
C63
C62
C61
C60
C59
C58
C57
C56
C55
C54
C53
C52
C51
C50
C49
C48
C47
C46
C45
C44
C43
C42
C41
R17DUP
C40
C39
C38
C37
C36
C35
C34
C33
C32
C31
C30
C29
C28
C27
C26
C25
C24
C23
C22
C21
C20
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
R18
R9
R10
R11
R12
R13
R14
R15
R16
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
dummy (VSS1)
150
y
x
PC2119-2
dummy (VSS1)
R8
R7
R6
R5
R4
R3
R2
R1
R17
C80
C79
C78
C77
C76
C75
C74
C73
C72
C71
C70
C69
C68
C67
C66
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
VLCD1
VLCD1
VLCD1
VLCD1
VLCD1
VLCD1
VLCD2
VLCD2
VLCD2
VLCD2
VLCD2
VLCD2
VLCD2
VLCDSENSE
VSS2
34
33
32
31
30
29
28
27
26
25
24
23
22
VSS2
VSS2
VSS2
VSS2
VSS2
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
21
T2
20
T1
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
E
VDD3
VDD3
VDD3
VDD3
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
168
OSC
167
DB7
166
DB6
165
DB5
164
DB4
163
DB3/SA0
162
DB2
161
DB1
160
DB0
159
RS
158
RW
157
156
SDA
SDA
155
PD
154
153
POR
T3
152
151
SCL
SCL
1.81 mm
Fig.40 Bonding pad locations.
2003 Jan 30
60
MGW572
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
x
handbook, full pagewidth
A
y
1,1
2,1
1,2
2,2
3,1
x,1
D
B
1,3
F
x,y
1,y
E
MGR977
Fig.41 Tray details.
Table 20 Dimensions for Fig.41
DIM.
handbook, halfpage
PC2119-2
MGR978
The orientation of the IC in a pocket is indicated by the position of the
IC type name on the die surface with respect to the chamfer on the
upper left corner of the tray. Refer to the bonding pad location
diagram for the orientating and position of the type name on the die
surface.
Fig.42 Tray alignment.
2003 Jan 30
61
DESCRIPTION
VALUE
A
pocket pitch, x direction
10.16 mm
B
pocket pitch, y direction
4.45 mm
C
pocket width, x direction
7.74 mm
D
pocket width, y direction
1.91 mm
E
tray width, x direction
50.8 mm
F
tray width, y direction
50.8 mm
x
number of pockets in x
direction
4
y
number of pockets in y
direction
10
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
Table 21 Bonding pad locations
Dimensions in µm; all x/y coordinates are referenced to
centre of chip; see Fig.40
SYMBOL
PAD
x
y
VDD1
1
+745
−274
VDD1
2
+745
−204
VDD1
3
+745
−134
VDD1
4
+745
−64
VDD1
5
+745
+6
VDD1
6
+745
+76
VDD2
7
+745
+146
VDD2
8
+745
+216
VDD2
9
+745
+286
VDD2
10
+745
+356
VDD2
11
+745
+426
VDD2
12
+745
+496
VDD2
13
+745
+566
VDD2
14
+745
+636
VDD3
15
+745
+706
VDD3
16
+745
+776
VDD3
17
+745
+846
VDD3
18
+745
+916
E
19
+745
+986
T1
20
+745
+1196
T2
21
+745
+1406
VSS1
22
+745
+1616
VSS1
23
+745
+1686
VSS1
24
+745
+1756
VSS1
25
+745
+1826
VSS1
26
+745
+1896
VSS1
27
+745
+1966
VSS1
28
+745
+2036
VSS1
29
+745
+2106
VSS2
30
+745
+2176
VSS2
31
+745
+2246
VSS2
32
+745
+2316
VSS2
33
+745
+2386
VSS2
34
+745
+2456
VSS2
35
+745
+2666
VLCDSENSE
36
+745
+2736
VLCD2
37
+745
+2806
VLCD2
38
+745
+2876
2003 Jan 30
SYMBOL
62
PAD
x
y
VLCD2
39
+745
+2946
VLCD2
40
+745
+3016
VLCD2
41
+745
+3086
VLCD2
42
+745
+3156
VLCD2
43
+745
+3226
VLCD1
44
+745
+3296
VLCD1
45
+745
+3366
VLCD1
46
+745
+3436
VLCD1
47
+745
+3506
VLCD1
48
+745
+3576
VLCD1
49
+745
+3646
dummy (VSS1)
50
−745
+3576
R8
51
−745
+3506
R7
52
−745
+3436
R6
53
−745
+3366
R5
54
−745
+3296
R4
55
−745
+3226
R3
56
−745
+3156
R2
57
−745
+3086
R1
58
−745
+3016
R17
59
−745
+2946
C80
60
−745
+2876
C79
61
−745
+2806
C78
62
−745
+2736
C77
63
−745
+2666
C76
64
−745
+2596
C75
65
−745
+2526
C74
66
−745
+2456
C73
67
−745
+2386
C72
68
−745
+2316
C71
69
−745
+2246
C70
70
−745
+2176
C69
71
−745
+2106
C68
72
−745
+2036
C67
73
−745
+1966
C66
74
−745
+1896
C65
75
−745
+1756
C64
76
−745
+1686
C63
77
−745
+1616
C62
78
−745
+1546
C61
79
−745
+1476
Philips Semiconductors
Product specification
LCD controllers/drivers
SYMBOL
PAD
PCF2119X
x
y
SYMBOL
PAD
x
y
C60
80
−745
+1406
C20
121
−745
−1464
C59
81
−745
+1336
C19
122
−745
−1534
C58
82
−745
+1266
C18
123
−745
−1604
C57
83
−745
+1196
C17
124
−745
−1674
C56
84
−745
+1126
C16
125
−745
−1744
C55
85
−745
+1056
C15
126
−745
−1884
C54
86
−745
+986
C14
127
−745
−1954
C53
87
−745
+916
C13
128
−745
−2024
C52
88
−745
+846
C12
129
−745
−2094
C51
89
−745
+776
C11
130
−745
−2164
C50
90
−745
+706
C10
131
−745
−2234
C49
91
−745
+636
C9
132
−745
−2304
C48
92
−745
+566
C8
133
−745
−2374
C47
93
−745
+496
C7
134
−745
−2444
C46
94
−745
+426
C6
135
−745
−2514
C45
95
−745
+356
C5
136
−745
−2584
C44
96
−745
+286
C4
137
−745
−2654
C43
97
−745
+216
C3
138
−745
−2724
C42
98
−745
+146
C2
139
−745
−2794
C41
99
−745
+76
C1
140
−745
−2864
R17DUP
100
−745
+6
R18
141
−745
−2934
C40
101
−745
−64
R9
142
−745
−3004
C39
102
−745
−134
R10
143
−745
−3074
C38
103
−745
−204
R11
144
−745
−3144
C37
104
−745
−274
R12
145
−745
−3214
C36
105
−745
−344
R13
146
−745
−3284
C35
106
−745
−414
R14
147
−745
−3354
C34
107
−745
−484
R15
148
−745
−3424
C33
108
−745
−554
R16
149
−745
−3494
C32
109
−745
−624
dummy (VSS1)
150
−745
−3704
C31
110
−745
−694
SCL
151
+745
−3704
C30
111
−745
−764
SCL
152
+745
−3634
C29
112
−745
−834
T3
153
+745
−3494
C28
113
−745
−904
POR
154
+745
−3424
C27
114
−745
−974
PD
155
+745
−3214
C26
115
−745
−1044
SDA
156
+745
−3004
C25
116
−745
−1114
SDA
157
+745
−2934
C24
117
−745
−1184
R/W
158
+745
−2584
C23
118
−745
−1254
RS
159
+745
−2374
C22
119
−745
−1324
DB0
160
+745
−2164
C21
120
−745
−1394
DB1
161
+745
−1954
2003 Jan 30
63
Philips Semiconductors
Product specification
LCD controllers/drivers
SYMBOL
PAD
PCF2119X
x
y
DB2
162
+745
−1744
DB3/SA0
163
+745
−1534
DB4
164
+745
−1324
DB5
165
+745
−1114
DB6
166
+745
−904
DB7
167
+745
−694
OSC
168
+745
−484
−
+745
−2689
Rec.Pat. 1
Rec.Pat. 2
−
+745
+2561
Rec.Pat. 3
−
−745
+3681
Rec.Pat. 4
−
−745
−3599
Table 22 Bump size
PARAMETER
VALUE
UNIT
galvanic pure Au
−
50 ±6
µm
Bump length
90 ±6
µm
Bump height
17.5 ±5
µm
<2
µm
Convex deformation
<5
µm
Pad size, aluminium
62 × 100
µm
Passivation opening CBB
36 × 76
µm
Wafer thickness
380 ±25
µm
Type
Bump width
Height difference in one die
2003 Jan 30
64
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
19 DATA SHEET STATUS
LEVEL
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
Development
DEFINITION
I
Objective data
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Production
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
20 DEFINITIONS
21 DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Jan 30
65
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
22 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2003 Jan 30
66
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119X
NOTES
2003 Jan 30
67
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected].
SCA75
© Koninklijke Philips Electronics N.V. 2003
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
403512/04/pp68
Date of release: 2003
Jan 30
Document order number:
9397 750 10483