INTEGRATED CIRCUITS DATA SHEET SAA7108AE; SAA7109AE HD-CODEC Product specification Supersedes data of 2003 Mar 26 2004 Jun 29 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE CONTENTS 10 INPUT/OUTPUT INTERFACES AND PORTS OF DIGITAL VIDEO DECODER PART 10.1 10.2 10.3 10.4 10.5 10.6 Analog terminals Audio clock signals Clock and real-time synchronization signals Video expansion port (X port) Image port (I port) Host port for 16-bit extension of video data I/O (H port) Basic input and output timing diagrams for the I and X ports 1 FEATURES 1.1 1.2 1.3 1.4 Video decoder Video scaler Video encoder Common features 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 QUICK REFERENCE DATA 11 BOUNDARY SCAN TEST 6 BLOCK DIAGRAMS 7 PINNING 11.1 11.2 Initialization of boundary scan circuit Device identification codes 8 FUNCTIONAL DESCRIPTION OF DIGITAL VIDEO ENCODER PART 12 LIMITING VALUES 13 THERMAL CHARACTERISTICS 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 Reset conditions Input formatter RGB LUT Cursor insertion RGB Y-CB-CR matrix Horizontal scaler Vertical scaler and anti-flicker filter FIFO Border generator Oscillator and Discrete Time Oscillator (DTO) Low-pass Clock Generation Circuit (CGC) Encoder RGB processor Triple DAC HD data path Timing generator Pattern generator for HD sync pulses I2C-bus interface Power-down modes Programming the graphics acquisition scaler of the video encoder Input levels and formats 14 CHARACTERISTICS OF THE DIGITAL VIDEO ENCODER PART 15 CHARACTERISTICS OF THE DIGITAL VIDEO DECODER PART 16 TIMING 16.1 16.2 Digital video encoder part Digital video decoder part 17 APPLICATION INFORMATION 17.1 17.2 17.3 Reconstruction filter Analog output voltages Suggestions for a board layout 18 I2C-BUS DESCRIPTION 18.1 18.2 Digital video encoder part Digital video decoder part 19 PROGRAMMING START SET-UP OF DIGITAL VIDEO DECODER PART 19.1 19.2 19.3 19.4 Decoder part Audio clock generation part Data slicer and data type control part Scaler and interfaces 20 PACKAGE OUTLINE 21 SOLDERING 22 DATA SHEET STATUS 23 DEFINITIONS 24 DISCLAIMERS 25 PURCHASE OF PHILIPS I2C COMPONENTS 8.21 9 9.1 9.2 9.3 9.4 9.5 9.6 10.7 FUNCTIONAL DESCRIPTION OF DIGITAL VIDEO DECODER PART Decoder Decoder output formatter Scaler VBI data decoder and capture (subaddresses 40H to 7FH) Image port output formatter (subaddresses 84H to 87H) Audio clock generation (subaddresses 30H to 3FH) 2004 Jun 29 2 Philips Semiconductors Product specification HD-CODEC 1 1.1 SAA7108AE; SAA7109AE FEATURES Video decoder • Six analog inputs, internal analog source selectors, e.g. 6 × CVBS or (2 × Y/C and 2 × CVBS) or (1 × Y/C and 4 × CVBS) • Enhanced ITU 656 output format on IPD output bus containing: • Two analog preprocessing channels in differential CMOS style for best S/N performance • Fully programmable static gain or Automatic Gain Control (AGC) for the selected CVBS or Y/C channel – active video • Switchable white peak control – raw CVBS data for INTERCAST applications (27 MHz data rate) • Two built-in analog anti-aliasing filters – decoded VBI data • Detection of copy protected input signals according to the Macrovision(1) standard. Can be used to prevent unauthorized recording of pay-TV or video tape signals. • Two 9-bit video CMOS Analog-to-Digital Converters (ADCs), digitized CVBS or Y/C signals are available on the Image Port Data (IPD) port under I2C-bus control • On-chip clock generator 1.2 • Line-locked system clock frequencies Video scaler • Both up and downscaling • Digital PLL for horizontal sync processing and clock generation, horizontal and vertical sync detection • Conversion to square pixel format • NTSC to 288 lines (video phone) • Requires only one crystal (either 24.576 MHz or 32.11 MHz) for all standards • Phase accuracy better than 1/64 pixel or line, horizontally or vertically • Automatic detection of 50 and 60 Hz field frequency, and automatic switching between PAL and NTSC standards • Independent scaling definitions for odd and even fields • Anti-alias filter for horizontal scaling • Luminance and chrominance signal processing for PAL BGHI, PAL N, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC N, NTSC 4.43 and SECAM • Provides output as: – scaled active video – raw CVBS data for INTERCAST, WAVE-PHORE, POPCON applications or general VBI data decoding (27 MHz or sample rate converted) • User programmable luminance peaking or aperture correction • Local video output for Y-CB-CR 4 : 2 : 2 format (VMI, VIP, ZV). • Cross-colour reduction for NTSC by chrominance comb filtering • PAL delay line for correcting PAL phase errors • Brightness Contrast Saturation (BCS) and hue control on-chip • Two multi functional real-time output pins controlled by the I2C-bus • Multi-standard VBI data slicer decoding World Standard Teletext (WST), North-American Broadcast Text System (NABTS), Closed Caption (CC), Wide Screen Signalling (WSS), Video Programming System (VPS), Vertical Interval Time Code (VITC) variants (EBU/SMPTE) etc. • Standard ITU 656 Y-CB-CR 4 : 2 : 2 format (8-bit) on IPD output bus 2004 Jun 29 (1) Macrovision is a trademark of the Macrovision Corporation. 3 Philips Semiconductors Product specification HD-CODEC 1.3 SAA7108AE; SAA7109AE • Adjustable output levels for the DACs Video encoder • Digital PAL/NTSC encoder with integrated high quality scaler and anti-flicker filter for TV output from a PC • Programmable horizontal and vertical input synchronization phase • Supports Intel Digital Video Out (DVO) low voltage interfacing to graphics controller • Programmable horizontal sync output phase • 27 MHz crystal-stable subcarrier generation • Optional support of various Vertical Blanking Interval (VBI) data insertion • Internal Colour Bar Generator (CBG) • Maximum graphics pixel clock 85 MHz at double edged clocking, synthesized on-chip or from external source • Macrovision Pay-per-View copy protection system rev. 7.01, rev. 6.1 and rev. 1.03 (525p) as option; this applies to SAA7108AE only. The device is protected by USA patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductors sales office for more information. • Programmable assignment of clock edge to bytes (in double edged mode) • Synthesizable pixel clock (PIXCLK) with minimized output jitter, can be used as reference clock for the VGC, as well • PIXCLK output and bi-phase PIXCLK input (VGC clock loop-through possible) • Hot-plug detection through dedicated interrupt pin • Supported VGA resolutions for PAL or NTSC legacy video output up to 1280 × 1024 graphics data at 60 or 50 Hz frame rate 1.4 Common features • 5 V tolerant digital I/O ports • Supported VGA resolutions for HDTV output up to 1920 × 1080 interlaced graphics data at 60 or 50 Hz frame rate • I2C-bus controlled (full read-back ability by an external controller, bit rate up to 400 kbits/s) • Three Digital-to-Analog Converters (DACs) for CVBS (BLUE, CB), VBS (GREEN, CVBS) and C (RED, CR) at 27 MHz sample rate (signals in parenthesis are optionally selected), all at 10-bit resolution • Boundary scan test circuit complies with the “IEEE Std. 1149.b1-1994” (separate ID codes for decoder and encoder) • Versatile power-save modes • Monolithic CMOS 3.3 V device • Non-interlaced CB-Y-CR or RGB input at maximum 4 : 4 : 4 sampling • BGA156 package • Downscaling and upscaling from 50 to 400 % • Moisture Sensitive Level (MSL): e3. • Optional interlaced CB-Y-CR input of Digital Versatile Disk (DVD) signals 2 • Optional non-interlaced RGB output to drive second VGA monitor (bypass mode, maximum 85 MHz) • Notebook (low-power consumption) • PCMCIA card application • 3 × 256 bytes RGB Look-Up Table (LUT) • AGP based graphics cards • Support for hardware cursor • PC editing • HDTV up to 1920 × 1080 interlaced and 1280 × 720 progressive, including 3-level sync pulses • Image processing • Video phone applications • Programmable border colour of underscan area • INTERCAST and PC teletext applications • Programmable 5 line anti-flicker filter • Security applications • On-chip 27 MHz crystal oscillator (3rd-harmonic or fundamental 27 MHz crystal) • Hybrid satellite set-top boxes. • Fast I2C-bus control port (400 kHz) • Encoder can be master or slave 2004 Jun 29 APPLICATIONS 4 Philips Semiconductors Product specification HD-CODEC 3 SAA7108AE; SAA7109AE All inputs intended to interface to the host graphics controller are designed for low-voltage signals down to 1.1 V and up to 3.45 V. GENERAL DESCRIPTION The SAA7108AE; SAA7109AE is a new multi-standard video decoder and encoder chip, offering high quality video input and TV output processing as required by PC-99 specifications. It enables hardware manufacturers to implement versatile video functions on a significantly reduced printed-circuit board area at very competitive costs. The video decoder, a 9-bit video input processor, is a combination of a 2-channel analog pre-processing circuit including source selection, anti-aliasing filter and Analog-to-Digital Converter (ADC), automatic clamp and gain control, a Clock Generation Circuit (CGC), and a digital multi-standard decoder (PAL BGHI, PAL M, PAL N, combination PAL N, NTSC M, NTSC-Japan, NTSC N, NTSC 4.43 and SECAM). Separate pins for supply voltages as well as for I2C-bus control and boundary scan test have been provided for the video encoder and decoder sections to ensure both flexible handling and optimized noise behaviour. The decoder includes a brightness, contrast and saturation control circuit, a multi-standard VBI data slicer and a 27 MHz VBI data bypass. The pure 3.3 V (5 V compatible) CMOS circuit SAA7108AE; SAA7109AE, consisting of an analog front-end and digital video decoder, a digital video encoder and analog back-end, is a highly integrated circuit especially designed for desktop video applications. The video encoder is used to encode PC graphics data at maximum 1280 × 1024 resolution (optionally 1920 × 1080 interlaced) to PAL (50 Hz) or NTSC (60 Hz) video signals. A programmable scaler and anti-flicker filter (maximum 5 lines) ensures properly sized and flicker-free TV display as CVBS or S-video output. Alternatively, the three Digital-to-Analog Converters (DACs) can output RGB signals together with a TTL composite sync to feed SCART connectors. The decoder is based on the principle of line-locked clock decoding and is able to decode the colour of PAL, SECAM and NTSC signals into ITU-R BT.601 compatible colour component values. When the scaler/interlacer is bypassed, a second VGA monitor can be connected to the RGB outputs and separate H and V-syncs as well, thereby serving as an auxiliary monitor at maximum 1280 × 1024 resolution/60 Hz (PIXCLK < 85 MHz). Alternatively this port can provide Y, PB and PR signals for HDTV monitors. The encoder can operate fully independently at its own variable pixel clock, transporting graphics input data, and at the line-locked, single crystal-stable video encoding clock. As an option, it is possible to slave the video PAL/NTSC encoding to the video decoder clock with the encoder FIFO acting as a buffer to decouple the line-locked decoder clock from the crystal-stable encoder clock. The encoder section includes a sync/clock generator and on-chip DACs. 4 ORDERING INFORMATION TYPE NUMBER SAA7108AE PACKAGE NAME DESCRIPTION VERSION BGA156 plastic ball grid array package; 156 balls; body 15 × 15 × 1.15 mm SOT472-1 SAA7109AE 2004 Jun 29 5 Philips Semiconductors Product specification HD-CODEC 5 SAA7108AE; SAA7109AE QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDDD digital supply voltage 3.15 3.3 3.45 V VDDA analog supply voltage 3.15 3.3 3.45 V Tamb ambient temperature 0 − 70 °C PA+D analog and digital power dissipation − − 1.7 W note 1 Note 1. Power dissipation is extremely dependent on programming and selected application. 6 BLOCK DIAGRAMS digital video input and output handbook, full pagewidth X port analog video input CVBS, Y/C ANALOG VIDEO ACQUISITION AND DEMODULATOR SCALER I port (IPD) digital video output VIDEO DECODER PART VIDEO ENCODER PART digital video Y-CB-CR/RGB graphics input PD SCALER AND INTERLACER VIDEO ENCODER CVBS, Y/C RGB MHB903 Fig.1 Simplified block diagram. 2004 Jun 29 6 analog video output This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... PIXCLKI INPUT FORMATTER FIFO AND UPSAMPLING LUT AND CURSOR RGB TO Y-CB-CR DECIMATOR 4 : 4 : 4 to 4 : 2 : 2 HORIZONTAL SCALER VERTICAL SCALER VERTICAL FILTER FIFO BORDER GENERATOR VIDEO ENCODER TRIPLE DAC MATRIX F2 7 C6 C7 C8 HD OUTPUT SAA7108AE SAA7109AE D7 D8 PIXEL CLOCK SYNTHESIZER A5 A6 C3 G1 F1 G3 F12 I2C-BUS CONTROL TIMING GENERATOR CRYSTAL OSCILLATOR E3 G2 C4 E2 GREEN_VBS_CVBS RED_CR_C_CVBS VSM HSM_CSYNC TVD D2 XTALIe XTALOe TTX_SRES 27 MHz VSVGC FSVGC CBO HSVGC SDAe TTXRQ_XCLKO2 Fig.2 Block diagram (video encoder part). RESe SCLe MBL785 Product specification andbook, full pagewidth G4 BLUE_CB_CVBS SAA7108AE; SAA7109AE PIXCLKO Philips Semiconductors HD-CODEC 2004 Jun 29 PD11 to PD0 C1, C2, B1, B2, A2, B4, B3, A3, F3, H1, H2, H3 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... RTCO XPD [7:0] XCLK RTS1 XRV XDQ XRH TEST5 XTRI HPD [7:0] XRDY SDAd SCLd TEST3 TEST4 TEST1 TEST2 TEST0 (1) M14 L14 L13 K13 L10 M3 M4 REAL-TIME OUTPUT CE XTOUTd XTALId XTALOd AI11 AI12 AI21 AI22 8 AI23 AI24 AOUT AI1D AI2D L12 A13, D12, C12, B12, A12, C11, B11, A11 M11 J2 J1 J3 C10 B10 H13 I2C-BUS I/O CONTROL M12 X PORT I/O FORMATTING N14 P4 P2 CLOCK GENERATION AND POWER-ON CONTROL chrominance of 16-bit input PROGRAMMING REGISTER ARRAY P3 E14, D14, C14, B14, E13, D13, C13, B13 SAA7108AE SAA7109AE A/B REGISTER MUX H14 P13 G12 P11 P10 P9 P7 ANALOG DUAL ADC P6 EVENT CONTROLLER DIGITAL DECODER WITH ADAPTIVE COMB FILTER FIR-PREFILTER HORIZONTAL LINE VERTICAL PRESCALER FINE FIFO SCALING AND (PHASE) BUFFER SCALER BCS SCALING M10 VIDEO FIFO P12 P8 N10 AUDIO CLOCK GENERATION BOUNDARY SCAN TEST N4 M6 M5 N6 N5 GENERAL PURPOSE VBI DATA SLICER TEXT FIFO 32 to 8(16) MUX F13 F14 G13 H12 J14 L8 K12 J13 K14 J12 M7, D11, F11, D10, G11, M8, M9, E11, K4, H4, H11, N7 to N9, J4, J11, N11 L6, M13 N12, N13 K11 L7, L9 P5 L4, L11 VIDEO/TEXT ARBITER G14 MBL791 TCLKd TDId AMCLK TRSTd TMSd TDOd ASCLK VDDXd ALRCLK AMXCLK (1) VDDId VSSXd VDDAd VDDEd VSSEd VSSId Fig.3 Block diagram (video decoder part). IDQ IGPH IGPV IGP0 IGP1 ICLK ITRDY ITRI Product specification (1) The pins RTCO and ALRCLK are used for configuration of the I2C-bus interface and the definition of the crystal oscillator frequency at RESET (pin strapping). VSSAd IPD [7:0] SAA7108AE; SAA7109AE AGND EXPANSION PORT PIN MAPPING K1 IMAGE PORT PIN MAPPING RESd N2 L5 N3 K2, K3, L1 to L3 M1, M2, N1 Philips Semiconductors LLC RTS0 HD-CODEC k, full pagewidth 2004 Jun 29 LLC2 Philips Semiconductors Product specification HD-CODEC 7 SAA7108AE; SAA7109AE PINNING PIN TYPE(1) PD7 A2 I MSB of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for pin assignment PD4 A3 I MSB − 3 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for pin assignment TRSTe A4 I/pu test reset input for Boundary Scan Test (BST) (encoder); active LOW; with internal pull-up; notes 2 and 3 XTALIe A5 I 27 MHz crystal input (encoder) XTALOe A6 O 27 MHz crystal output (encoder) DUMP A7 O DAC reference pin (encoder), 12 Ω resistor connected to VSSAe SYMBOL DESCRIPTION VSSXe A8 S ground for oscillator (encoder) RSET A9 O DAC reference pin (encoder), 1 kΩ resistor connected to VSSAe VDDAe A10 S 3.3 V analog supply voltage (encoder) HPD0 A11 I/O MSB − 7 of Host Port Data (HPD) output bus HPD3 A12 I/O MSB − 4 of HPD output bus HPD7 A13 I/O MSB of HPD output bus PD9 B1 I see Tables 9, 14 and 15 for pin assignment with different encoder input formats PD8 B2 I see Tables 9, 14 and 15 for pin assignment with different encoder input formats PD5 B3 I MSB − 2 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for pin assignment PD6 B4 I MSB − 1 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for pin assignment TDIe B5 I/pu VDDAe B6 S DUMP B7 O DAC reference pin (encoder); connected to A7 VSSAe B8 S analog ground (encoder) VDDAe B9 S 3.3 V analog supply voltage (encoder) TEST1 B10 I scan test input 1, do not connect HPD1 B11 I/O MSB − 6 of HPD output bus HPD4 B12 I/O MSB − 3 of HPD output bus IPD0 B13 O MSB − 7 of IPD output bus IPD4 B14 O MSB − 3 of Image Port Data (IPD) output bus PD11 C1 I see Tables 9, 14 and 15 for pin assignment with different encoder input formats PD10 C2 I see Tables 9, 14 and 15 for pin assignment with different encoder input formats TTX_SRES C3 I teletext input or sync reset input (encoder) TTXRQ_XCLKO2 C4 O teletext request output or 13.5 MHz clock output of the crystal oscillator (encoder) VSSIe C5 S digital ground core (encoder) BLUE_CB_CVBS C6 O BLUE or CB or CVBS output 2004 Jun 29 test data input for BST (encoder); note 4 3.3 V analog supply voltage (encoder) 9 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE SYMBOL PIN TYPE(1) GREEN_VBS_CVBS C7 O DESCRIPTION GREEN or VBS or CVBS output RED_CR_C_CVBS C8 O RED or CR or C or CVBS output VDDAe C9 S 3.3 V analog supply voltage (encoder) TEST2 C10 I scan test input 2, do not connect HPD2 C11 I/O MSB − 5 of HPD output bus HPD5 C12 I/O MSB − 2 of HPD output bus IPD1 C13 O MSB − 6 of IPD output bus IPD5 C14 O MSB − 2 of IPD output bus TDOe D1 O test data output for BST (encoder); note 4 RESe D2 I reset input (encoder); active LOW TMSe D3 I/pu VDDIEe D4 S 3.3 V digital supply voltage for core and peripheral cells (encoder) VSSIe D5 S digital ground core (encoder) VDDXe D6 S 3.3 V supply voltage for oscillator (encoder) VSM D7 O vertical synchronization output to VGA monitor (non-interlaced) HSM_CSYNC D8 O horizontal synchronization output to VGA monitor (non-interlaced) or composite sync for RGB-SCART VDDAe D9 S 3.3 V analog supply voltage (encoder) test mode select input for BST (encoder); note 4 VDDEd D10 S 3.3 V digital supply voltage for peripheral cells (decoder) VDDId D11 S 3.3 V digital supply voltage for core (decoder) HPD6 D12 I/O MSB − 1 of HPD output bus IPD2 D13 O MSB − 5 of IPD output bus IPD6 D14 O MSB − 1 of IPD output bus TCKe E1 I/pu SCLe E2 I HSVGC E3 I/O VSSEe E4 S digital ground peripheral cells (encoder) VSSId E11 S digital ground core (decoder) n.c. E12 − not connected IPD3 E13 O MSB − 4 of IPD output bus IPD7 E14 O MSB of IPD output bus VSVGC F1 I/O vertical synchronization output to VGC (optional input) PIXCLKI F2 I pixel clock input (looped through) PD3 F3 I MSB − 4 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for pin assignment test clock input for BST (encoder); note 4 I2C-bus serial clock input (encoder) horizontal synchronization output to Video Graphics Controller (VGC) (optional input) VDD(DVO) F4 S digital supply voltage for DVO cells VDDId F11 S 3.3 V digital supply voltage for core (decoder) TVD F12 O TV Detector; hot-plug interrupt pin, HIGH if TV is connected IGPV F13 O multi-purpose vertical reference output with IPD output bus IGP0 F14 O general purpose output signal 0 with IPD output bus 2004 Jun 29 10 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE PIN TYPE(1) FSVGC G1 I/O frame synchronization output to VGC (optional input) SDAe G2 I/O I2C-bus serial data input/output (encoder) CBO G3 O composite blanking output to VGC; active LOW PIXCLKO G4 O pixel clock output to VGC SYMBOL DESCRIPTION VDDEd G11 S 3.3 V digital supply voltage for peripheral cells (decoder) IGPH G12 O multi-purpose horizontal reference output with IPD output bus IGP1 G13 O general purpose output signal 1 with IPD output bus ITRI G14 I/(O) PD2 H1 I MSB − 5 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for pin assignment PD1 H2 I MSB − 6 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for pin assignment PD0 H3 I MSB − 7 of encoder input bus with CB-Y-CR 4 : 2 : 2; see Tables 9 to 15 for pin assignment VSSEd H4 S digital ground for peripheral cells (decoder) VSSEd H11 S digital ground for peripheral cells (decoder) ICLK H12 I/O clock for IPD output bus (optional clock input) TEST0 H13 O scan test output, do not connect IDQ H14 O data qualifier for IPD output bus TEST4 J1 O scan test output, do not connect TEST5 J2 I scan test input, do not connect TEST3 J3 I scan test input, do not connect VDDId J4 S 3.3 V digital supply voltage for core (decoder) programmable control signals for IPD output bus VDDId J11 S 3.3 V digital supply voltage for core (decoder) AMXCLK J12 I audio master external clock input ALRCLK J13 (I/)O ITRDY J14 I target ready input for IPD output bus XTRI K1 I control signal for all X port pins XPD7 K2 I/O XPD6 K3 I/O VSSId K4 S digital ground core (decoder) VSSId K11 S digital ground core (decoder) AMCLK K12 O audio master clock output, must be less than 50 % of crystal clock RTS0 K13 O real-time status or sync information line 0 ASCLK K14 O audio serial clock output XPD5 L1 I/O MSB − 2 of XPD bus XPD4 L2 I/O MSB − 3 of XPD bus XPD3 L3 I/O MSB − 4 of XPD bus VDDId L4 S XRV L5 I/O 2004 Jun 29 audio left/right clock output; can be strapped to supply via a 3.3 kΩ resistor to indicate that the default 24.576 MHz crystal (ALRCLK = 0; internal pull-down) has been replaced by a 32.110 MHz crystal (ALRCLK = 1); notes 5 and 6 MSB of XPD bus MSB − 1 of XPD bus 3.3 V digital supply voltage for core (decoder) vertical reference for XPD bus 11 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE PIN TYPE(1) VSSEd L6 S digital ground for peripheral cells (decoder) VDDEd L7 S 3.3 V digital supply voltage for peripheral cells (decoder) VDDXd L8 S 3.3 V supply voltage for oscillator (decoder) VDDEd L9 S 3.3 V digital supply voltage for peripheral cells (decoder) RTS1 L10 O real-time status or sync information line 1 VDDId L11 S 3.3 V digital supply voltage for core (decoder) SDAd L12 I/O RTCO L13 (I/)O LLC2 L14 O line-locked 1⁄2 clock output (13.5 MHz nominal) XPD2 M1 I/O MSB − 5 of XPD bus XPD1 M2 I/O MSB − 6 of XPD bus XCLK M3 I/O clock for XPD bus XDQ M4 I/O data qualifier for XPD bus TMSd M5 I/pu test mode select input for BST (decoder); note 4 TCKd M6 I/pu test clock input for BST (decoder); note 4 VSSAd M7 S analog ground (decoder) VDDAd M8 S 3.3 V analog supply voltage (decoder) SYMBOL DESCRIPTION I2C-bus serial data input/output (decoder) real-time control output; contains information about actual system clock frequency, field rate, odd/even sequence, decoder status, subcarrier frequency and phase and PAL sequence (see external document “RTC Functional Description”, available on request); the RTCO pin is enabled via I2C-bus bit RTCE; see notes 5 and 7 and Table 150 VDDAd M9 S 3.3 V analog supply voltage (decoder) AOUT M10 O analog test output (do not connect) SCLd M11 I I2C-bus serial clock input (decoder) RESd M12 O reset output signal; active LOW (decoder) VSSEd M13 S digital ground for peripheral cells (decoder) LLC M14 O line-locked clock output (27 MHz nominal) XPD0 N1 I/O MSB − 7 of XPD bus XRH N2 I/O horizontal reference for XPD bus XRDY N3 O data input ready for XPD bus TRSTd N4 I/pu TDOd N5 O TDId N6 I/pu VSSAd N7 S analog ground (decoder) VSSAd N8 S analog ground (decoder) VSSAd N9 S analog ground (decoder) AGND N10 S analog ground (decoder) connected to substrate VDDAd N11 S 3.3 V analog supply voltage (decoder) VSSAd N12 S analog ground (decoder) VSSAd N13 S analog ground (decoder) CE N14 I chip enable or reset input (with internal pull-up) 2004 Jun 29 test reset input for BST (decoder); active LOW; with internal pull-up; notes 2 and 3 test data output for BST (decoder); note 4 test data input for BST (decoder); note 4 12 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE PIN TYPE(1) XTALId P2 I 27 MHz crystal input (decoder) XTALOd P3 O 27 MHz crystal output (decoder) XTOUTd P4 O crystal oscillator output signal (decoder); auxiliary signal VSSXd P5 S ground for crystal oscillator (decoder) AI24 P6 I analog input 24 AI23 P7 I analog input 23 AI2D P8 I differential analog input for channel 2; connect to ground via a capacitor AI22 P9 I analog input 22 AI21 P10 I analog input 21 AI12 P11 I analog input 12 AI1D P12 I differential analog input for channel 1; connect to ground via a capacitor AI11 P13 I analog input 11 SYMBOL DESCRIPTION Notes 1. Pin type: I = input, O = output, S = supply, pu = pull-up. 2. For board design without boundary scan implementation connect TRSTe and TRSTd to ground. 3. This pin provides easy initialization of the Boundary Scan Test (BST) circuit. TRSTe and TRSTd can be used to force the Test Access Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once. 4. In accordance with the “IEEE1149.1” standard the pads TDIe (TDId), TMSe (TMSd), TCKe (TCKd) and TRSTe (TRSTd) are input pads with an internal pull-up resistor and TDOe (TDOd) is a 3-state output pad. 5. Pin strapping is done by connecting the pin to supply via a 3.3 kΩ resistor. During the power-up reset sequence the corresponding pins are switched to input mode to read the strapping level. For the default setting no strapping resistor is necessary (internal pull-down). 6. Pin ALRCLK: 0 = 24.576 MHz crystal (default); 1 = 32.110 MHz crystal. 7. Pin RTCO: operates as I2C-bus slave address pin; RTCO = 0 slave address 42H/43H (default); RTCO = 1 slave address 40H/41H. MBL788 handbook, halfpage P N M L K J H G F E D C B A SAA7108AE SAA7109AE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Fig.4 Pin configuration. 2004 Jun 29 13 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1 A 2 3 4 5 6 7 8 PD7 PD4 TRSTe XTALIe XTALOe DUMP VSSXe VDDAe DUMP VSSAe 9 10 11 12 13 14 RSET VDDAe HPD0 HPD3 HPD7 VDDAe TEST1 HPD1 HPD4 IPD0 IPD4 BLUE_ GREEN_ RED_CR_C_ VDDAe TEST2 HPD2 CB_CVBS VBS_CVBS CVBS HPD5 IPD1 IPD5 VDDId HPD6 IPD2 IPD6 14 B PD9 PD8 PD5 PD6 TDIe C PD11 PD10 TTX_ SRES TTXRQ_ XCLKO2 VSSIe D TDOe RESe TMSe VDDIEe VSSIe E TCKe SCLe HSVGC VSSEe VSSId n.c. IPD3 IPD7 F VSVGC PIXCLKI PD3 VDD(DVO) VDDId TVD IGPV IGP0 G FSVGC SDAe CBO PIXCLKO VDDEd IGPH IGP1 ITRI ICLK TEST0 IDQ VDDXe VSM HSM_CSYNC VDDAe VDDEd PD1 PD0 VSSEd VSSEd J TEST4 TEST5 TEST3 VDDId VDDId AMXCLK ALRCLK ITRDY K XTRI XPD7 XPD6 VSSId VSSId AMCLK RTS0 ASCLK L XPD5 XPD4 XPD3 VDDId XRV VSSEd VDDEd VDDXd VDDEd RTS1 VDDId SDAd RTCO LLC2 M XPD2 XPD1 XCLK XDQ TMSd TCKd VSSAd VDDAd VDDAd AOUT SCLd RESd VSSEd LLC N XPD0 XRH XRDY TRSTd TDOd TDId VSSAd VSSAd VSSAd AGND VDDAd VSSAd VSSAd CE VSSXd AI24 AI23 AI2D AI22 AI1D AI11 P XTALId XTALOd XTOUTd AI21 AI12 Product specification PD2 SAA7108AE; SAA7109AE H Philips Semiconductors Pin assignment (top view) HD-CODEC 2004 Jun 29 Table 1 Philips Semiconductors Product specification HD-CODEC 8 SAA7108AE; SAA7109AE FUNCTIONAL DESCRIPTION OF DIGITAL VIDEO ENCODER PART For ease of analog post filtering the signals are twice oversampled to 27 MHz before digital-to-analog conversion. The digital video encoder encodes digital luminance and colour difference signals (CB-Y-CR) or digital RGB signals into analog CVBS, S-video and, optionally, RGB or CR-Y-CB signals. NTSC M, PAL B/G and sub-standards are supported. The total filter transfer characteristics (scaler and anti-flicker filter are not taken into account) are illustrated in Figs 5 to 10. All three DACs are realized with full 10-bit resolution. The CR-Y-CB to RGB dematrix can be bypassed (optionally) in order to provide the upsampled CR-Y-CB input signals. The SAA7108AE; SAA7109AE can be directly connected to a PC video graphics controller with a maximum resolution of 1280 × 1024 (progressive) or 1920 × 1080 (interlaced) at a 50 or 60 Hz frame rate. A programmable scaler scales the computer graphics picture so that it will fit into a standard TV screen with an adjustable underscan area. Non-interlaced-to-interlaced conversion is optimized with an adjustable anti-flicker filter for a flicker-free display at a very high sharpness. The 8-bit multiplexed CB-Y-CR formats are “ITU-R BT.656” (D1 format) compatible, but the SAV and EAV codes can be decoded optionally, when the device is operated in slave mode. For assignment of the input data to the rising or falling clock edge see Tables 9 to 15. In order to display interlaced RGB signals through a euro-connector TV set, a separate digital composite sync signal (pin HSM_CSYNC) can be generated; it can be advanced up to 31 periods of the 27 MHz crystal clock in order to be adapted to the RGB processing of a TV set. Besides the most common 16-bit 4 : 2 : 2 CB-Y-CR input format (using 8 pins with double edge clocking), other CB-Y-CR and RGB formats are also supported; see Tables 9 to 15. The SAA7108AE; SAA7109AE synthesizes all necessary internal signals, colour subcarrier frequency and synchronization signals from that clock. A complete 3 × 256 bytes Look-Up Table (LUT), which can be used, for example, as a separate gamma corrector, is located in the RGB domain; it can be loaded either through the video input port PD (Pixel Data) or via the I2C-bus. It is also possible to connect pin RTCO of the decoder section to pin RTCI of the encoder section. Thus, information containing actual subcarrier frequency, PAL-ID etc. is available in case the line-locked clock of the decoder section is used for re-encoding of the encoder section. The SAA7108AE; SAA7109AE supports a 32 × 32 × 2-bit hardware cursor, the pattern of which can also be loaded through the video input port or via the I2C-bus. It is also possible to encode interlaced 4 : 2 : 2 video signals such as PC-DVD; for that the anti-flicker filter, and in most cases the scaler, will simply be bypassed. Wide screen signalling data can be loaded via the I2C-bus and is inserted into line 23 for standards using a 50 Hz field rate. Besides the applications for video output, the SAA7108AE; SAA7109AE can also be used for generating a kind of auxiliary VGA output, when the RGB non-interlaced input signal is fed to the DACs. This may be of interest for example, when the graphics controller provides a second graphics window at its video output port. VPS data for program dependent automatic start and stop of such featured VCRs is loadable via the I2C-bus. The IC also contains Closed Caption and extended data services encoding (line 21), and supports teletext insertion for the appropriate bit stream format at a 27 MHz clock rate (see Fig.51). It is also possible to load data for the copy generation management system into line 20 of every field (525/60 line counting). The basic encoder function consists of subcarrier generation, colour modulation and insertion of synchronization signals at a crystal-stable clock rate of 13.5 MHz (independent of the actual pixel clock used at the input side), corresponding to an internal 4 : 2 : 2 bandwidth in the luminance/colour difference domain. Luminance and chrominance signals are filtered in accordance with the standard requirements of “RS-170-A” and “ITU-R BT.470-3”. 2004 Jun 29 A number of possibilities are provided for setting different video parameters such as: • Black and blanking level control • Colour subcarrier frequency • Variable burst amplitude etc. 15 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE MBE737 handbook, full 6 pagewidth Gv (dB) 0 −6 −12 −18 −24 (1) (2) −30 −36 −42 −48 −54 0 2 4 6 8 10 (1) SCBW = 1. (2) SCBW = 0. Fig.5 Chrominance transfer characteristic 1. MBE735 handbook, halfpage 2 Gv (dB) 0 (1) (2) −2 −4 −6 0 0.4 0.8 1.2 f (MHz) 1.6 (1) SCBW = 1. (2) SCBW = 0. Fig.6 Chrominance transfer characteristic 2. 2004 Jun 29 16 12 f (MHz) 14 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE MGD672 6 Gv full pagewidth handbook, (dB) (4) 0 (2) (3) −6 (1) −12 −18 −24 −30 −36 −42 −48 −54 0 2 4 6 8 10 12 14 f (MHz) (1) (2) (3) (4) CCRS1 = 0; CCRS0 = 1. CCRS1 = 1; CCRS0 = 0. CCRS1 = 1; CCRS0 = 1. CCRS1 = 0; CCRS0 = 0. Fig.7 Luminance transfer characteristic 1 (excluding scaler). MBE736 handbook, halfpage 1 Gv (dB) (1) 0 −1 −2 −3 −4 −5 0 2 4 f (MHz) 6 (1) CCRS1 = 0; CCRS0 = 0. Fig.8 Luminance transfer characteristic 2 (excluding scaler). 2004 Jun 29 17 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE MGB708 handbook, full pagewidth Gv 6 (dB) 0 −6 −12 −18 −24 −30 −36 −42 −48 −54 0 2 4 6 8 10 12 f (MHz) 14 Fig.9 Luminance transfer characteristic in RGB (excluding scaler). MGB706 handbook, full pagewidth Gv 6 (dB) 0 −6 −12 −18 −24 −30 −36 −42 −48 −54 0 2 4 6 8 10 Fig.10 Colour difference transfer characteristic in RGB (excluding scaler). 2004 Jun 29 18 12 f (MHz) 14 Philips Semiconductors Product specification HD-CODEC 8.1 SAA7108AE; SAA7109AE Reset conditions If Y-CB-CR is being applied as a 27 Mbyte/s data stream, the output of the input formatter can be used directly to feed the video encoder block. To activate the reset a pulse at least of 2 crystal clocks duration is required. The horizontal upscaling is supported via the input formatter. According to the programming of the pixel clock dividers (see Section 8.10), it will upsample the data stream to 1 ×, 2 × or 4 × the input data rate. An optional interpolation filter is available. The clock domain transition is handled by a 4 entries wide FIFO which gets initialized every field or explicitly at request. A bypass for the FIFO is available, especially for high input data rates. During reset (RESET = LOW) plus an extra 32 crystal clock periods, FSVGC, VSVGC, CBO, HSVGC and TTX_SRES are set to input mode and HSM_CSYNC and VSM are set to 3-state. A reset also forces the I2C-bus interface to abort any running bus transfer and sets it into receive condition. After reset, the state of the I/Os and other functions is defined by the strapping pins until an I2C-bus access redefines the corresponding registers; see Table 2. Table 2 8.3 The three 256-byte RAMs of this block can be addressed by three 8-bit wide signals, thus it can be used to build any transformation, e.g. a gamma correction for RGB signals. In the event that the indexed colour data is applied, the RAMs are addressed in parallel. Strapping pins PIN FSVGC (pin G1) TIED PRESET LOW NTSC M encoding, PIXCLK fits to 640 × 480 graphics input The LUTs can either be loaded by an I2C-bus write access or can be part of the pixel data input through the PD port. In the latter case, 256 × 3 bytes for the R, G and B LUT are expected at the beginning of the input video line, two lines before the line that has been defined as first active line, until the middle of the line immediately preceding the first active line. The first 3 bytes represent the first RGB LUT data, and so on. HIGH PAL B/G encoding, PIXCLK fits to 640 × 480 graphics input VSVGC (pin F1) LOW 4 : 2 : 2 Y-CB-CR graphics input (format 0) HIGH 4 : 4 : 4 RGB graphics input (format 3) CBO (pin G3) LOW input demultiplex phase: LSB = LOW 8.4 LOW input demultiplex phase: MSB = LOW HIGH input demultiplex phase: MSB = HIGH TTXRQ_XCLKO2 (pin C4) LOW slave (FSVGC, VSVGC and HSVGC are inputs, internal colour bar is active) The cursor bit map is set up as follows: each pixel occupies 2 bits. The meaning of these bits depends on the CMODE I2C-bus register as described in Table 5. Transparent means that the input pixels are passed through, the ‘cursor colours’ can be programmed in separate registers. HIGH master (FSVGC, VSVGC and HSVGC are outputs) 8.2 Input formatter The bit map is stored with 4 pixels per byte, aligned to the least significant bit. So the first pixel is in bits 0 and 1, the next pixel in bits 3 and 4 and so on. The first index is the column, followed by the row; index 0,0 is the upper left corner. The input formatter converts all accepted PD input data formats, either RGB or Y-CB-CR, to a common internal RGB or Y-CB-CR data stream. When double-edge clocking is used, the data is internally split into portions PPD1 and PPD2. The clock edge assignment must be set according to the I2C-bus control bits SLOT and EDGE for correct operation. 2004 Jun 29 Cursor insertion A 32 × 32 dots cursor can be overlaid as an option; the bit map of the cursor can be uploaded by an I2C-bus write access to specific registers or in the pixel data input via the PD port. In the latter case the 256 bytes defining the cursor bit map (2 bits per pixel) are expected immediately following the last RGB LUT data in the line preceding the first active line. HIGH input demultiplex phase: LSB = HIGH HSVGC (pin E3) RGB LUT 19 Philips Semiconductors Product specification HD-CODEC Table 3 D7 SAA7108AE; SAA7109AE Layout of a byte in the cursor bit map D6 D5 D4 D3 D2 pixel n + 3 pixel n + 2 pixel n + 1 D1 D1 D1 D0 D0 D0 Table 5 D1 D0 CURSOR PATTERN pixel n D1 D0 For each direction, there are 2 registers controlling the position of the cursor, one controls the position of the ‘hot spot’, the other register controls the insertion position. The hot spot is the ‘tip’ of the pointer arrow. It can have any position in the bit map. The actual position registers describe the co-ordinates of the hot spot. Again 0,0 is the upper left corner. While it is not possible to move the hot spot beyond the left respectively upper screen border this is perfectly legal for the right respectively lower border. It should be noted that the cursor position is described relative to the input resolution. Table 4 BYTE D6 D5 D4 D3 D2 D1 row 0 column 3 row 0 column 2 row 0 column 1 row 0 column 0 1 row 0 column 7 row 0 column 6 row 0 column 5 row 0 column 4 2 row 0 row 0 row 0 column 11 column 10 column 9 row 0 column 8 ... ... ... 6 row 0 row 0 row 0 row 0 column 27 column 26 column 25 column 24 7 row 0 row 0 row 0 row 0 column 31 column 30 column 29 column 28 ... ... 254 row 31 row 31 row 31 row 31 column 27 column 26 column 25 column 24 255 row 31 row 31 row 31 row 31 column 31 column 30 column 29 column 28 ... ... ... ... CMODE = 0 CMODE = 1 second cursor colour second cursor colour 01 first cursor colour first cursor colour 10 transparent transparent 11 inverted input auxiliary cursor colour RGB Y-CB-CR matrix RGB input signals to be encoded to PAL or NTSC are converted to the Y-CB-CR colour space in this block. The colour difference signals are fed through low-pass filters and formatted to a ITU-R BT.601 like 4 : 2 : 2 data stream for further processing. A gain adjust option corrects the level swing of the graphics world (black-to-white as 0 to 255) to the required range of 16 to 235. D0 0 CURSOR MODE 00 8.5 Cursor bit map D7 Cursor modes The matrix and formatting blocks can be bypassed for Y-CB-CR graphics input. When the auxiliary VGA mode is selected, the output of the cursor insertion block is immediately directed to the triple DAC. 8.6 Horizontal scaler The high quality horizontal scaler operates on the 4 : 2 : 2 data stream. Its control engines compensate the colour phase offset automatically. The scaler starts processing after a programmable horizontal offset and continues with a number of input pixels. Each input pixel is a programmable fraction of the current output pixel (XINC/4096). A special case is XINC = 0, this sets the scaling factor to 1. ... If the SAA7108AE; SAA7109AE input data is in accordance with “ITU-R BT.656”, the scaler enters another mode. In this event, XINC needs to be set to 2048 for a scaling factor of 1. With higher values, upscaling will occur. The phase resolution of the circuit is 12 bits, giving a maximum offset of 0.2 after 800 input pixels. Small FIFOs rearrange a 4 : 2 : 2 data stream at the scaler output. 2004 Jun 29 20 Philips Semiconductors Product specification HD-CODEC 8.7 SAA7108AE; SAA7109AE 8.10 Vertical scaler and anti-flicker filter Oscillator and Discrete Time Oscillator (DTO) The master clock generation is realized as a 27 MHz crystal oscillator, which can operate with either a fundamental wave crystal or a 3rd-harmonic crystal. The functions scaling, Anti-Flicker Filter (AFF) and re-interlacing are implemented in the vertical scaler. Besides the entire input frame, it receives the first and last lines of the border to allow anti-flicker filtering. The crystal clock supplies the DTO of the pixel clock synthesizer, the video encoder and the I2C-bus control block. It also usually supplies the triple DAC, with the exception of the auxiliary VGA mode, where the triple DAC is clocked by the pixel clock (PIXCLK). The circuit generates the interlaced output fields by scaling down the input frames with different offsets for odd and even fields. Increasing the YSKIP setting reduces the anti-flicker function. A YSKIP value of 4095 switches it off; see Table 120. The DTO can be programmed to synthesize all relevant pixel clock frequencies between circa 40 and 85 MHz. Two programmable dividers provide the actual clock to be used externally and internally. The dividers can be programmed to factors of 1, 2, 4 and 8. For the internal pixel clock, a divider ratio of 8 makes no sense and is thus forbidden. An additional, programmable vertical filter supports the anti-flicker function. This filter is not available at upscaling factors of more than 2. The programming is similar to the horizontal scaler. For the re-interlacing, the resolutions of the offset registers are not sufficient, so the weighting factors for the first lines can also be adjusted. YINC = 0 sets the scaling factor to 1; YIWGTO and YIWGTE must not be 0. The internal clock can be switched completely to the pixel clock input. In this event, the input FIFO is useless and will be bypassed. Due to the re-interlacing, the circuit can perform upscaling by a maximum factor of 2. The maximum factor depends on the setting of the anti-flicker function and can be derived from the formulae given in Section 8.20. An additional upscaling mode enables the upscaling factor to be increased to a maximum of 4 as it is required for the old VGA modes like 320 × 240. The entire pixel clock generation can be locked to the vertical frequency. Both pixel clock dividers get re-initialized every field. Optionally, the DTO can be cleared with each V-sync. At proper programming, this will make the pixel clock frequency a precise multiple of the vertical and horizontal frequencies. This is required for some graphic controllers. 8.8 8.11 FIFO Low-pass Clock Generation Circuit (CGC) The FIFO acts as a buffer to translate from the PIXCLK clock domain to the XTAL clock domain. The write clock is PIXCLK and the read clock is XTAL. An underflow or overflow condition can be detected via the I2C-bus read access. This block reduces the phase jitter of the synthesized pixel clock. It works as a tracking filter for all relevant synthesized pixel clock frequencies. In order to avoid underflows and overflows, it is essential that the frequency of the synthesized PIXCLK matches to the input graphics resolution and the desired scaling factor. 8.12.1 8.9 8.12 VIDEO PATH The encoder generates luminance and colour subcarrier output signals from the Y, CB and CR baseband signals, which are suitable for use as CVBS or separate Y and C signals. Border generator Input to the encoder, at 27 MHz clock (e.g. DVD), is either originated from computer graphics at pixel clock, fed through the FIFO and border generator, or a ITU-R BT.656 style signal. When the graphics picture is to be displayed as interlaced PAL, NTSC, S-video or RGB on a TV screen, it is desired in many cases not to lose picture information due to the inherent overscanning of a TV set. The desired amount of underscan area, which is achieved through appropriate scaling in the vertical and horizontal direction, can be filled in the border generator with an arbitrary true colour tint. 2004 Jun 29 Encoder Luminance is modified in gain and in offset (the offset is programmable in a certain range to enable different black level set-ups). A blanking level can be set after insertion of a fixed synchronization pulse tip level, in accordance with standard composite synchronization schemes. 21 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE 8.12.3 Other manipulations used for the Macrovision anti-taping process, such as additional insertion of AGC super-white pulses (programmable in height), are supported by the SAA7108AE only. Five bytes of VPS information can be loaded via the I2C-bus and will be encoded in the appropriate format into line 16. To enable easy analog post filtering, luminance is interpolated from a 13.5 MHz data rate to a 27 MHz data rate, thereby providing luminance in a 10-bit resolution. The transfer characteristics of the luminance interpolation filter are illustrated in Figs 7 and 8. Appropriate transients at start/end of active video and for synchronization pulses are ensured. 8.12.4 The actual line number in which data is to be encoded, can be modified in a certain range. The data clock frequency is in accordance with the definition for NTSC M standard 32 times horizontal line frequency. Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE. The amplitude (beginning and ending) of the inserted burst, is programmable in a certain range that is suitable for standard signals and for special effects. After the succeeding quadrature modulator, colour is provided on the subcarrier in 10-bit resolution. It is also possible to encode Closed Caption data for 50 Hz field frequencies at 32 times the horizontal line frequency. 8.12.5 ANTI-TAPING (SAA7108AE ONLY) For more information contact your nearest Philips Semiconductors sales office. The numeric ratio between the Y and C outputs is in accordance with the standards. 8.13 TELETEXT INSERTION AND ENCODING (NOT SIMULTANEOUSLY WITH REAL-TIME CONTROL) RGB processor This block contains a dematrix in order to produce RED, GREEN and BLUE signals to be fed to a SCART plug. Pin TTX_SRES receives a WST or NABTS teletext bitstream sampled at the crystal clock. At each rising edge of the output signal (TTXRQ) a single teletext bit has to be provided after a programmable delay at input pin TTX_SRES. Before Y, CB and CR signals are de-matrixed, individual gain adjustment for Y and colour difference signals and 2 times oversampling for luminance and 4 times oversampling for colour difference signals is performed. The transfer curves of luminance and colour difference components of RGB are illustrated in Figs 9 and 10. Phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines. 8.14 TTXRQ_XCLKO2 provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines which can be selected independently for both fields. The internal insertion window for text is set to 360 (PAL WST), 296 (NTSC WST) or 288 (NABTS) teletext bits including clock run-in bits. The protocol and timing are illustrated in Fig.51. Triple DAC Both Y and C signals are converted from digital-to-analog in a 10-bit resolution at the output of the video encoder. Y and C signals are also combined into a 10-bit CVBS signal. The CVBS output signal occurs with the same processing delay as the Y, C and optional RGB or CR-Y-CB outputs. Absolute amplitude at the input of the DAC for CVBS is reduced by 15⁄16 with respect to Y and C DACs to make maximum use of the conversion ranges. Alternatively, this pin can be provided with a buffered crystal clock (XCLK) of 13.5 MHz. 2004 Jun 29 CLOSED CAPTION ENCODER Using this circuit, data in accordance with the specification of Closed Caption or extended data service, delivered by the control interface, can be encoded (line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. Chrominance is modified in gain (programmable separately for CB and CR), and a standard dependent burst is inserted, before baseband colour signals are interpolated from a 6.75 MHz data rate to a 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be used for the Y and C output. The transfer characteristics of the chrominance interpolation filter are illustrated in Figs 5 and 6. 8.12.2 VIDEO PROGRAMMING SYSTEM (VPS) ENCODING 22 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE RED, GREEN and BLUE signals are also converted from digital-to-analog, each providing a 10-bit resolution. Alternatively, the device can be triggered by auxiliary codes in a ITU-R BT.656 data stream via PD7 to PD0. The reference currents of all three DACs can be adjusted individually in order to adapt for different output signals. In addition, all reference currents can be adjusted commonly to compensate for small tolerances of the on-chip band gap reference voltage. Only vertical frequencies of 50 and 60 Hz are allowed with the SAA7108AE; SAA7109AE. In slave mode, it is not possible to lock the encoders colour carrier to the line frequency with the PHRES bits. In the (more common) master mode, the time base of the circuit is continuously free-running. The IC can output a frame sync at pin FSVGC, a vertical sync at pin VSVGC, a horizontal sync at pin HSVGC and a composite blanking signal at pin CBO. All of these signals are defined in the PIXCLK domain. The duration of HSVGC and VSVGC are fixed, they are 64 clocks for HSVGC and 1 line for VSVGC. The leading slopes are in phase and the polarities can be programmed. Alternatively, all currents can be switched off to reduce power dissipation. All three outputs can be used to sense for an external load (usually 75 Ω) during a pre-defined output. A flag in the I2C-bus status byte reflects whether a load is applied or not. An automatic sense mode can also be activated, which will immediately indicate any 75 Ω load at any of the three outputs at the dedicated interrupt pin TVD. The input line length can be programmed. The field length is always derived from the field length of the encoder and the pixel clock frequency that is being used. If the SAA7108AE; SAA7109AE is required to drive a second (auxiliary) VGA monitor or an HDTV set, the DACs receive the signal coming from the HD data path. In this event, the DACs are clocked at the incoming PIXCLKI instead of the 27 MHz crystal clock used in the video encoder. 8.15 CBO acts as a data request signal. The circuit accepts input data at a programmable number of clocks after CBO goes active. This signal is programmable and it is possible to adjust the following (see Figs 49 and 50): HD data path • The horizontal offset This data path enables the SAA7108AE; SAA7109AE to be used with VGA or HDTV monitors. It receives its data directly from the cursor generator and supports RGB and Y-PB-PR output formats (RGB not with Y-PB-PR input formats). No scaling is done in this mode. • The length of the active part of the line A gain adjustment either leads the full level swing to the digital-to-analog converters or reduces the amplitude by a factor of 0.69. This enables sync pulses to be added to the signal as it is required for display units that require signals with sync pulses, either regular or 3-level syncs. In most cases, the vertical offsets for odd and even fields are equal. If they are not, then the even field will start later. The SAA7108AE; SAA7109AE will also request the first input lines in the even field, the total number of requested lines will increase by the difference of the offsets. 8.16 • The distance from active start to first expected data • The vertical offset separately for odd and even fields • The number of lines per input field. As stated above, the circuit can be programmed to accept the look-up and cursor data in the first 2 lines of each field. The timing generator provides normal data request pulses for these lines; the duration is the same as for regular lines. The additional request pulses will be suppressed with LUTL set to logic 0; see Table 143. The other vertical timings do not change in this case, so the first active line can be number 2, counted from 0. Timing generator The synchronization of the SAA7108AE; SAA7109AE is able to operate in two modes; slave mode and master mode. In slave mode, the circuit accepts sync pulses on the bidirectional FSVGC (frame sync), VSVGC (vertical sync) and HSVGC (horizontal sync) pins: the polarities of the signals can be programmed. The frame sync signal is only necessary when the input signal is interlaced, in other cases it may be omitted. If the frame sync signal is present, it is possible to derive the vertical and the horizontal phase from it by setting the HFS and VFS bits. HSVGC and VSVGC are not necessary in this case, so it is possible to switch the pins to output mode. 2004 Jun 29 23 Philips Semiconductors Product specification HD-CODEC 8.17 SAA7108AE; SAA7109AE Pattern generator for HD sync pulses Each index of this table points to a particular line of the next table in the linked list. This table is called the line pattern array and each of the up to seven entries stores up to four pairs of a duration in pixel clock cycles and an index to a value table. The table entries are used to define portions of a line representing a certain value for a certain number of clock cycles. The pattern generator provides an appropriate synchronization pattern for the video data path in auxiliary monitor or HDTV mode, respectively. It provides maximum flexibility in terms of raster generation for all interlaced and non-interlaced computer graphics or ATSC formats. The sync engine is capable of providing a combination of event-value pairs which can be used to insert certain values at specified times in the outgoing data stream. It can also be used to generate digital signals associated with time events. They can be used as digital horizontal and vertical synchronization signals on pins HSM_CSYNC and VSM. The value specified in this table is actually another 3-bit index into a value array which can hold up to eight 8-bit values. If bit 4 (MSB) of the index is logic 1, the value is inserted into the G or Y signal only; if bit 4 = 0, the associated value is inserted into all three signals. Two additional bits of the entries in the value array (LSBs of the second byte) determine if the associated events appear as a digital pulse on the HSM_CSYNC and/or VSM outputs. The picture position is adjustable through the programmable relationship between the sync pulses and the video contents. The generation of embedded analog sync pulses is bound to a number of events which can be defined for a line. Several of these line timing definitions can exist in parallel. For the final sync raster composition a certain sequence of lines with different sync event properties has to be defined. The sequence specifies a series of line types and the number of occurrences of this specific line type. After the sequence has been completed, it restarts from the beginning. All pulse shapes are filtered internally in order to avoid ringing after analog post filters. To ease the trigger set-up for the sync generation module, a set of registers is provided to set up the screen raster defined as width and height. A trigger position can be specified as an x, y co-ordinate within the overall dimensions of the screen raster. If the x, y counter matches the specified co-ordinates, a trigger pulse is generated which pre-loads the tables with their initial values. Table 6 outlines an example on how to set up the sync tables for a 1080i HD raster. The sequence of the generated pulse stream must fit precisely to the incoming data stream in terms of the total number of pixels per line and lines per frame. Important note: Due to a problem in the programming interface, writing to the line pattern array (address D2) might destroy the data of the line type array (address D1). A work around is to write the line pattern array data before writing the line type array. Reading of the arrays is possible but all address pointers must be initialized before the next write operation. The sync engines flexibility is achieved by using a sequence of linked lists carrying the properties for the image, the lines as well as fractions of lines. Figure 11 illustrates the context between the various tables. The first table serves as an array to hold the correct sequence of lines composing the synchronization raster. It can contain up to 16 entries. Each entry holds a 4-bit index to the next table and a 10-bit counter value which specifies how often this particular line is invoked. If the necessary line count for a particular line exceeds the 10 bits, it has to use two table entries. The 4-bit index in the line count array points to the line type array. It holds up to 15 entries where, index 0 is not used, index 1 points to the first entry, index 2 to the second entry of the line type array etc. Each entry of the line type array can hold up to 8 index pointers to another table. These indices point to portions of a line pulse pattern: A line could be split up e.g. into a sync, a blank, and an active portion followed by another blank portion, occupying four entries in one table line. 2004 Jun 29 24 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE handbook, full pagewidth 4-bit line type index 10-bit line count line count pointer LINE COUNT ARRAY 16 entries 3 3 3 3 3 3 3 3 line type pointer LINE TYPE ARRAY pattern pointer 15 entries 3 3 3 3 3 3 3 3 event type pointer 10-bit duration 10-bit duration 10-bit duration 10-bit duration 4-bit value index 4-bit value index 4-bit value index 4-bit value index 8 + 2-bit value LINE PATTERN ARRAY 7 entries VALUE ARRAY 8 entries line pattern pointer MBL797 Fig.11 Context between the pattern generator tables for DH sync pulses. 2004 Jun 29 25 Philips Semiconductors Product specification HD-CODEC Table 6 SAA7108AE; SAA7109AE Example for set-up of the sync tables SEQUENCE COMMENT Write to subaddress D0H 00 points to first entry of line count array (index 0) 05 20 generate 5 lines of line type index 2 (remember, it is the second entry of the line type array); will be the first vertical raster pulse 01 40 generate 1 line of line type index 4; will be sync-black-sync-black sequence after the first vertical pulse 0E 60 generate 14 lines of line type index 6; will be the following lines with sync-black sequence 1C 12 generate 540 lines of line type index 1; will be lines with sync and active video 02 60 generate 2 lines of line type index 6; will be the following lines with sync-black sequence 01 50 generate 1 line of line type index 5; will be the following line (line 563) with sync-black-sync-black-null sequence (null is equivalent to sync tip) 04 20 generate 4 lines of line type index 2; will be the second vertical raster pulse 01 30 generate 1 line of line type index 3; will be the following line with sync-null-sync-black sequence 0F 60 generate 15 lines of line type index 6; will be the following lines with sync-black sequence 1C 12 generate 540 lines of line type index 1; will be lines with sync and active video 02 60 generate 2 lines of line type index 6; will be the following lines with sync-black sequence; now, 1125 lines are defined Write to subaddress D2H (insertion is done into all three analog output signals) 00 points to first entry of line pattern array (index 1) 6F 33 2B 30 00 00 00 00 880 × value(3) + 44 × value(3); (subtract 1 from real duration) 6F 43 2B 30 00 00 00 00 880 × value(4) + 44 × value(3) 3B 30 BF 03 BF 03 2B 30 60 × value(3) + 960 × value(0) + 960 × value(0) + 44 × value(3) 2B 10 2B 20 57 30 00 00 44 × value(1) + 44 × value(2) + 88 × value(3) 3B 30 BF 33 BF 33 2B 30 60 × value(3) + 960 × value(3) + 960 × value(3) + 44 × value(3) Write to subaddress D1H 00 points to first entry of line type array (index 1) 34 00 00 00 use pattern entries 4 and 3 in this sequence (for sync and active video) 24 24 00 00 use pattern entries 4, 2, 4 and 2 in this sequence (for 2 × sync-black-null-black) 24 14 00 00 use pattern entries 4, 2, 4 and 1 in this sequence (for sync-black-null-black-null) 14 14 00 00 use pattern entries 4, 1, 4 and 1 in this sequence (for sync-black-sync-black) 14 24 00 00 use pattern entries 4, 1, 4 and 2 in this sequence (for sync-black-sync-black-null) 54 00 00 00 use pattern entries 4 and 5 in this sequence (for sync-black) 2004 Jun 29 26 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE SEQUENCE COMMENT Write to subaddress D3H (no signals are directed to pins HSM_CSYNC and VSM) 00 points to first entry of value array (index 0) CC 00 black level, to be added during active video 80 00 sync level LOW (minimum output voltage) 0A 00 sync level HIGH (3-level sync) CC 00 black level (needed elsewhere) 80 00 null (identical with sync level LOW) Write to subaddress DCH 0B 8.18 insertion is active, gain for signal is adapted accordingly So in most cases, DOWNA and DOWND should be set to logic 1 simultaneously. If the EIDIV bit is logic 1, it should be set to logic 0 before power-down. I2C-bus interface The I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are read and write, except two read only status bytes. 8.20 The encoder section needs to provide a continuous data stream at its analog outputs as well as receive a continuous stream from its data source. Due to the fact that there is no frame memory isolating the data streams, restrictions apply to the input frame timings. The register bit map consists of an RGB Look-Up Table (LUT), a cursor bit map and control registers. The LUT contains three banks of 256 bytes, where each RGB triplet is assigned to one address. Thus a write access needs the LUT address and three data bytes following subaddress FFH. For further write access auto-incrementing of the LUT address is performed. The cursor bit map access is similar to the LUT access but contains only a single byte per address. Input and output processing of the encoder section are only coupled through the vertical frequencies. In master mode, the encoder provides a vertical sync and an odd/even pulse to the input processing, in slave mode, the encoder receives them. The I2C-bus slave address is defined as 88H. 8.19 The parameters of the input field are mainly given by the memory capacity of the encoder section. The rule is that the scaler and thus the input processing needs to provide the video data in the same time frames as the encoder reads them. So the vertical active video times (and the vertical frequencies) need to be the same. Power-down modes In order to reduce the power consumption, the SAA7108AE; SAA7109AE supports 2 Power-down modes, accessible via the I2C-bus. The analog Power-down mode (DOWNA = 1) turns off the digital-to-analog converters and the pixel clock synthesizer. The digital down mode turns off all internal clocks and sets the digital outputs to LOW except the I2C-bus interface. The IC retains its programming and can still be accessed in this mode, but not all registers can be read from or written to. Reading or writing to the look-up tables, the cursor and the HD sync generator require a valid pixel clock. The typical supply current in full power-down is approximately 5 mA. The second rule is that there has to be data in the buffer FIFO when the encoder enters the active video area. So the vertical offset in the input path needs to be a bit shorter than the offset of the encoder. The following gives the set of equations required to program the IC for the most common application: A post processor in master mode with non-interlaced video input data. Due to the fact that the analog Power-down mode turns off the pixel clock synthesizer, there are limitations in some applications. If there is no pixel clock, the IC is not able to set its outputs to LOW. 2004 Jun 29 Programming the graphics acquisition scaler of the video encoder 27 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE 262.5 × 1716 × TXclk Thus: TPclk = ---------------------------------------------------------------------------------------- (60 Hz) InLin + 2 InPpl × integer ---------------------- × 262.5 OutLin Some variables are defined below: • InPix: the number of active pixels per input line • InPpl: the length of the entire input line in pixel clocks 312.5 × 1728 × TXclk TPclk = ---------------------------------------------------------------------------------------- (50 Hz) InLin + 2 InPpl × integer ---------------------- × 312.5 OutLin • InLin: the number of active lines per input field/frame • TPclk: the pixel clock period • RiePclk: the ratio of internal to external pixel clock and for the pixel clock generator TXclk 20 + PCLE PCL = --------------- × 2 (all frequencies); TPclk see Tables 102, 104 and 105. The divider PCLE should be set according to Table 104. PCLI may be set to a lower or the same value. Setting a lower value means that the internal pixel clock is higher and the data get sampled up. The difference may be 1 at 640 × 480 pixels resolution and 2 at resolutions with 320 pixels per line as a rule of thumb. This allows horizontal upscaling by a maximum factor of 2 respectively 4 (this is the parameter RiePclk). • OutPix: the number of active pixels per output line • OutLin: the number of active lines per output field • TXclk: the encoder clock period (37.037 ns). 8.20.1 TV DISPLAY WINDOW At 60 Hz, the first visible pixel has the index 256, 710 pixels can be encoded; at 50 Hz, the index is 284, 702 pixels can be visible. The output lines should be centred on the screen. It should be noted that the encoder has 2 clocks per pixel; see Table 93. log RiePclk PCLI = PCLE – ---------------------------- (all frequencies) log 2 ADWHS = 256 + 710 − OutPix (60 Hz); ADWHS = 284 + 702 − OutPix (50 Hz); ADWHE = ADWHS + OutPix × 2 (all frequencies) The equations ensure that the last line of the field has the full number of clock cycles. Many graphic controllers require this. Note that the bit PCLSY needs to be set to ensure that there is not even a fraction of a clock left at the end of the field. For vertical, the procedure is the same. At 60 Hz, the first line with video information is number 19, 240 lines can be active. For 50 Hz, the numbers are 23 and 287; see Table 99. 8.20.3 240 – OutLin FAL = 19 + --------------------------------- (60 Hz); 2 XOFS can be chosen arbitrarily, the condition being that XOFS + XPIX ≤ HLEN is fulfilled. Values given by the VESA display timings are preferred. 287 – OutLin FAL = 23 + --------------------------------- (50 Hz); 2 LAL = FAL + OutLin (all frequencies) HLEN = InPpl × RiePclk − 1 InPix XPIX = ------------- × RiePclk 2 Most TV sets use overscan, and not all pixels respectively lines are visible. There is no standard for the factor, it is highly recommended to make the number of output pixels and lines adjustable. A reasonable underscan factor is 10 %, giving approximately 640 output pixels per line. 8.20.2 4096 OutPix XINC = ------------------ × -------------------InPix RiePclk XINC needs to be rounded up, it needs to be set to 0 for a scaling factor of 1. INPUT FRAME AND PIXEL CLOCK 8.20.4 The total number of pixel clocks per line and the input horizontal offset need to be chosen next. The only constraint is that the horizontal blanking has at least 10 clock pulses. VERTICAL SCALER The input vertical offset can be taken from the assumption that the scaler should have just finished writing the first line when the encoder starts reading it: FAL × 1716 × TXclk YOFS = ---------------------------------------------------- – 2.5 (60 Hz) InPpl × TPclk The required pixel clock frequency can be determined in the following way: Due to the limited internal FIFO size, the input path has to provide all pixels in the same time frame as the encoders vertical active time. The scaler also has to process the first and last border lines for the anti-flicker function. 2004 Jun 29 HORIZONTAL SCALER FAL × 1728 × TXclk YOFS = ---------------------------------------------------- – 2.5 (50 Hz) InPpl × TPclk 28 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated for by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up. In most cases the vertical offsets will be the same for odd and even fields. The results should be rounded down. YPIX = InLin YSKIP defines the anti-flicker function. 0 means maximum flicker reduction but minimum vertical bandwidth, 4095 gives no flicker reduction and maximum bandwidth. Note that the maximum value for YINC is 4095. It might be necessary to reduce the value of YSKIP to fulfil this requirement. The RGB, respectively CR-Y-CB path features an individual gain setting for luminance (GY) and colour difference signals (GCD). Reference levels are measured with a colour bar, 100 % white, 100 % amplitude and 100 % saturation. OutLin YSKIP YINC = ---------------------- × 1 + ----------------- × 4096 InLin + 2 4095 The encoder section of the SAA7108AE; SAA7109AE has special input cells for the VGC port. They operate at a wider supply voltage range and have a strict input threshold at 1/2VDD(DVO). To achieve full speed of these cells, the EIDIV bit needs to be set to logic 1. In this case the impedance of these cells is approximately 6 kΩ. This may cause trouble with the bootstrapping pins of some graphic chips. So the power-on reset forces the bit to logic 0, the input impedance is regular in this mode. YINC YIWGTO = -------------- + 2048 2 YINC – YSKIP YIWGTE = -------------------------------------2 When YINC = 0 it sets the scaler to scaling factor 1. The initial weighting factors must not be set to 0 in this case. YIWGTE may go negative. In this event, YINC should be added and YOFSE incremented. This can be repeated as often as necessary to make YIWGTE positive. Table 7 SIGNALS(1) COLOUR Note that these equations assume that the input is non-interlaced while the output is interlaced. If the input is interlaced, the initial weighting factors need to be adapted to get the proper phase offsets in the output frame. If vertical upscaling beyond the upper capabilities is required, the parameter YUPSC may be set to 1. This extends the maximum vertical scaling factor by a factor 2. Only the parameter YINC gets affected, it needs to be divided by 2 to get the same effect. There are restrictions in this mode: • The vertical filter YFILT is not available in this mode; the circuit will ignore this value CB CR White 235 128 128 Yellow 210 16 146 Cyan 170 166 16 Green 145 54 Magenta 106 202 Red 81 90 Blue 41 Black 16 R G B 235 235 235 235 235 16 16 235 235 34 16 235 16 222 235 16 235 240 235 16 16 240 110 16 16 235 128 128 16 16 16 1. Transformation: a) R = Y + 1.3707 × (CR − 128) b) G = Y − 0.3365 × (CB − 128) − 0.6982 × (CR − 128) Or the upscaling factor needs to be limited to 1.5 and the horizontal upscaling factor is also limited to less than ∼1.5. In this case a normal blanking length is sufficient. c) B = Y + 1.7324 × (CB − 128). Input levels and formats The SAA7108AE; SAA7109AE accepts digital Y, CB, CR or RGB data with levels (digital codes) in accordance with “ITU-R BT.601”. An optional gain adjustment also allows data to be accepted with the full level swing of 0 to 255. 2004 Jun 29 Y Note • The horizontal blanking needs to be long enough to transfer an output line between 2 memory locations. This is 710 internal pixel clocks 8.21 “ITU-R BT.601” signal component levels 29 Philips Semiconductors Product specification HD-CODEC Table 8 SAA7108AE; SAA7109AE Usage of bits SLOT and EDGE Table 10 Pin assignment for input format 1 5 + 5 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB DATA SLOT CONTROL (EXAMPLE FOR FORMAT 0) SLOT EDGE 0 0 1st DATA FALLING CLOCK EDGE PIN 2nd DATA RISING CLOCK EDGE at rising edge G3/Y3 at falling edge R7/CR7 PD7 G2 X PD6 G1 R4 0 1 at falling edge G3/Y3 at rising edge R7/CR7 PD5 G0 R3 PD4 B4 R2 1 0 at rising edge R7/CR7 at falling edge G3/Y3 PD3 B3 R1 1 1 at falling edge R7/CR7 at rising edge G3/Y3 PD2 B2 R0 PD1 B1 G4 PD0 B0 G3 Table 9 Pin assignment for input format 0 Table 11 Pin assignment for input format 2 8 + 8 + 8-BIT 4 : 4 : 4 NON-INTERLACED RGB/CB-Y-CR FALLING CLOCK EDGE RISING CLOCK EDGE PD11 G3/Y3 R7/CR7 PD10 G2/Y2 PD9 G1/Y1 PD8 5 + 6 + 5-BIT 4 : 4 : 4 NON-INTERLACED RGB FALLING CLOCK EDGE RISING CLOCK EDGE PD7 G2 R4 R6/CR6 PD6 G1 R3 R5/CR5 PD5 G0 R2 G0/Y0 R4/CR4 PD4 B4 R1 PD7 B7/CB7 R3/CR3 PD3 B3 R0 PD6 B6/CB6 R2/CR2 PD2 B2 G5 PD5 B5/CB5 R1/CR1 PD1 B1 G4 PD4 B4/CB4 R0/CR0 PD0 B0 G3 PD3 B3/CB3 G7/Y7 PD2 B2/CB2 G6/Y6 PD1 B1/CB1 G5/Y5 PD0 B0/CB0 G4/Y4 PIN PIN Table 12 Pin assignment for input format 3 8 + 8 + 8-BIT 4 : 2 : 2 NON-INTERLACED CB-Y-CR FALLING CLOCK EDGE n RISING CLOCK EDGE n FALLING CLOCK EDGE n+1 RISING CLOCK EDGE n+1 PD7 CB7(0) Y7(0) CR7(0) Y7(1) PD6 CB6(0) Y6(0) CR6(0) Y6(1) PD5 CB5(0) Y5(0) CR5(0) Y5(1) PD4 CB4(0) Y4(0) CR4(0) Y4(1) PD3 CB3(0) Y3(0) CR3(0) Y3(1) PD2 CB2(0) Y2(0) CR2(0) Y2(1) PD1 CB1(0) Y1(0) CR1(0) Y1(1) PD0 CB0(0) Y0(0) CR0(0) Y0(1) PIN 2004 Jun 29 30 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 13 Pin assignment for input format 4 Table 15 Pin assignment for input format 6 8 + 8 + 8-BIT 4 : 2 : 2 INTERLACED CB-Y-CR (ITU-R BT.656, 27 MHz CLOCK) RISING CLOCK EDGE n RISING CLOCK EDGE n+1 RISING CLOCK EDGE n+2 RISING CLOCK EDGE n+3 PD7 CB7(0) Y7(0) CR7(0) Y7(1) PD6 CB6(0) Y6(0) CR6(0) Y6(1) PD5 CB5(0) Y5(0) CR5(0) Y5(1) PD4 CB4(0) Y4(0) CR4(0) Y4(1) PD3 CB3(0) Y3(0) CR3(0) Y3(1) PD2 CB2(0) Y2(0) CR2(0) Y2(1) PD1 CB1(0) Y1(0) CR1(0) Y1(1) PD0 CB0(0) Y0(0) CR0(0) Y0(1) PIN 8 + 8 + 8-BIT 4 : 4 : 4 NON-INTERLACED RGB/CB-Y-CR Table 14 Pin assignment for input format 5; note 1 8-BIT NON-INTERLACED INDEX COLOUR FALLING CLOCK EDGE RISING CLOCK EDGE PD11 X X PD10 X X PD9 X X PD8 X X PD7 INDEX7 X PD6 INDEX6 X PD5 INDEX5 X PD4 INDEX4 X PD3 INDEX3 X PD2 INDEX2 X PD1 INDEX1 X PD0 INDEX0 X PIN Note 1. X = don’t care. 2004 Jun 29 FALLING CLOCK EDGE RISING CLOCK EDGE PD11 G4/Y4 R7/CR7 PD10 G3/Y3 R6/CR6 PD9 G2/Y2 R5/CR5 PD8 B7/CB7 R4/CR4 PD7 B6/CB6 R3/CR3 PD6 B5/CB5 G7/Y7 PD5 B4/CB4 G6/Y6 PD4 B3/CB3 G5/Y5 PD3 G0/Y0 R2/CR2 PD2 B2/CB2 R1/CR1 PD1 B1/CB1 R0/CR0 PD0 B0/CB0 G1/Y1 PIN 31 Philips Semiconductors Product specification HD-CODEC 9 SAA7108AE; SAA7109AE FUNCTIONAL DESCRIPTION OF DIGITAL VIDEO DECODER PART 9.1 9.1.1 Decoder ANALOG INPUT PROCESSING The SAA7108AE; SAA7109AE offers six analog signal inputs, two analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video 9-bit CMOS ADC; see Fig.15. 9.1.2 ANALOG CONTROL CIRCUITS The anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit. The characteristics are illustrated in Fig.12. During the vertical blanking period, gain and clamping control is frozen. MGD138 6 V (dB) 0 −6 −12 −18 −24 −30 −36 −42 0 2 4 6 8 Fig.12 Anti-alias filter. 2004 Jun 29 32 10 12 f (MHz) 14 Philips Semiconductors Product specification HD-CODEC 9.1.2.1 SAA7108AE; SAA7109AE Clamping The AGC (automatic gain control for luminance) is used to amplify a CVBS or Y signal to the required signal amplitude, which is matched to the ADCs input voltage range. The AGC active time is the sync bottom of the video signal. The clamping control circuit controls the correct clamping of the analog input signals. A coupling capacitor is used to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. The clamping levels for the two ADC channels are fixed for luminance (60) and chrominance (128). Clamping time in normal use is set with the HCL pulse at the back porch of the video signal. 9.1.2.2 Signal (white) peak control limits the gain at signal overshoots. The influence of supply voltage variation within the specified range is automatically eliminated by clamping and automatic gain control. The flow charts show more details of the AGC; see Figs 16 and 17. Gain control The gain control circuit receives (via the I2C-bus) the static gain levels for the two analog amplifiers, or controls one of these amplifiers automatically via a built-in Automatic Gain Control (AGC) as part of the Analog Input Control (AICO). TV line analog line blanking analog input level 255 GAIN +3 dB CLAMP 0 dB 60 maximum range 9 dB 0 dB (1 V (p-p) 18/56 Ω) −6 dB 1 HCL HSY MGL065 minimum MHB325 Fig.13 Analog line with clamp (HCL) and gain range (HSY). 2004 Jun 29 controlled ADC input level Fig.14 Automatic gain range. 33 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... AI2D AI22 AI21 AOUT P6 P7 P8 P9 Philips Semiconductors AI23 M10 HD-CODEC ndbook, full pagewidth 2004 Jun 29 AI24 TEST SELECTOR AND BUFFER AOSL [1:0] SOURCE SWITCH ANALOG AMPLIFIER DAC9 CLAMP CIRCUIT P10 ANTI-ALIAS FILTER BYPASS SWITCH ADC2 FUSE [1:0] AI12 AI1D AI11 P11 P12 P13 ANALOG AMPLIFIER DAC9 CLAMP CIRCUIT SOURCE SWITCH ANTI-ALIAS FILTER BYPASS SWITCH ADC1 FUSE [1:0] 34 MODE CONTROL CLAMP CONTROL HCL GLIMB HSY GLIMT WIPA SLTCA ANTI-ALIAS CONTROL HOLDG GAFIX WPOFF GUDL [1:0] GAI [28:20] GAI [18:10] HLNRS UPTCV VERTICAL BLANKING CONTROL VBSL VBLNK SVREF 9 9 9 ANALOG CONTROL CROSS MULTIPLEXER 9 CVBS/LUM 9 CVBS/CHR AD2BYP AD1BYP Fig.15 Analog input processing using the SAA7108AE; SAA7109AE as differential front-end with 9-bit ADC. MHB892 Product specification 9 SAA7108AE; SAA7109AE MODE3 MODE2 MODE1 MODE0 GAIN CONTROL Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE ANALOG INPUT gain AMPLIFIER 9 DAC ANTI-ALIAS FILTER ADC 9 1 NO ACTION VBLK 1 LUMA/CHROMA DECODER 0 0 HOLDG 1 0 X 1 0 0 <4 > 254 1 1 1 1 0 <1 +1/F STOP > 248 > 254 0 X=1 X=0 1 0 HSY 0 +1/L +1/LLC2 −1/LLC2 +/− 0 −1/LLC2 GAIN ACCUMULATOR (18 BITS) ACTUAL GAIN VALUE 9-BIT (AGV) [−3/+6 dB] 1 0 X 1 0 HSY 1 AGV X = system variable. Y = (IAGV − FGVI) > GUDL. UPDATE 0 FGV GAIN VALUE 9-BIT MHB531 VBLK = vertical blanking pulse. HSY = horizontal sync pulse. AGV = actual gain value. FGV = frozen gain value. Fig.16 Gain flow chart. 2004 Jun 29 Y 35 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE ANALOG INPUT ADC 1 NO BLANKING ACTIVE VBLK 0 <- CLAMP 1 1 + CLAMP CLL HCL 0 1 0 0 − CLAMP GAIN -> NO CLAMP + GAIN SBOT HSY 1 − GAIN 0 1 fast − GAIN WIPE 0 slow + GAIN MGC647 WIPE = white peak level (254). SBOT = sync bottom level (1). CLL = clamp level [60 Y (128 C)]. HSY = horizontal sync pulse. HCL = horizontal clamp pulse. Fig.17 Clamp and gain flow. 2004 Jun 29 36 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... SUBTRACTOR CHR QUADRATURE MODULATOR UV INTERPOLATION LOW-PASS 3 LUBW QUADRATURE DEMODULATOR LOW-PASS 1 DOWNSAMPLING SUBCARRIER GENERATION 2 37 CHROMINANCE INCREMENT DELAY HUEC SET_RAW CCOMB SET_VBI YCOMB LDEL BYPS LDEL YCOMB UV LOW-PASS 2 DBRI [ 7:0] DCON [ 7:0] DSAT [ 7:0] RAWG [ 7:0] RAWO [ 7:0] COLO BRIGHTNESS CONTRAST SATURATION CONTROL CHBW RAW DATA GAIN AND OFFSET CONTROL SECAM PROCESSING UV CHROMINANCE INCREMENT DTO-RESET PHASE DEMODULATOR SUBCARRIER INCREMENT GENERATION AND DIVIDER AMPLITUDE DETECTOR CHROMA GAIN CONTROL BURST GATE ACCUMULATOR UVADJUSTMENT CDTO INCS CSTD [ 2:0] FCTC ACGC CGAIN [ 6:0] IDEL [ 3:0] CODE SECS Fig.18 Chrominance and luminance processing. SECAM RECOMBINATION SET_RAW SET_VBI DCVF MHB532 fH /2 switch signal UV-OUT HREF-OUT SET_RAW SET_VBI PAL DELAY LINE LOOP FILTER Y-OUT/ CVBS-OUT Product specification RTCO ADAPTIVE COMB FILTER SET_RAW SET_VBI Y/CVBS SAA7108AE; SAA7109AE SUBCARRIER GENERATION 1 LCBW [ 2:0] LUFI [ 3:0] CSTD [ 2:0] YDEL [ 2:0] UV handbook, full pagewidth CVBS-IN or CHR-IN LUMINANCE-PEAKING OR LOW-PASS, Y-DELAY ADJUSTMENT Philips Semiconductors Y DELAY COMPENSATION CHROMINANCE AND LUMINANCE PROCESSING LDEL YCOMB HD-CODEC 9.1.3 2004 Jun 29 CVBS-IN or Y-IN Philips Semiconductors Product specification HD-CODEC 9.1.3.1 SAA7108AE; SAA7109AE • Baseband ‘bell’ filters to reconstruct the amplitude and phase equalized 0° and 90° FM signals Chrominance path The 9-bit CVBS or chrominance input signal is fed to the input of a quadrature demodulator, where it is multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 1 (0 and 90° phase relationship to the demodulator axis). The frequency is dependent on the chosen colour standard. • Phase demodulator and differentiator (FM demodulation) • De-emphasis filter to compensate the pre-emphasized input signal, including frequency offset compensation (DB or DR white carrier values are subtracted from the signal, controlled by the SECAM switch signal). The time-multiplexed output signals of the multipliers are low-pass filtered (low-pass 1). Eight characteristics are programmable via LCBW3 to LCBW0 to achieve the desired bandwidth for the colour difference signals (PAL, NTSC) or the 0° and 90° FM signals (SECAM). The succeeding chrominance gain control block amplifies or attenuates the CB-CR signal according to the required ITU 601/656 levels. It is controlled by the output signal from the amplitude detection circuit within the burst processing block. The chrominance low-pass 1 characteristic also influences the grade of cross-luminance reduction during horizontal colour transients (large chrominance bandwidth means strong suppression of cross-luminance). If the Y comb filter is disabled when YCOMB = 0 the filter directly influences the width of the chrominance notch within the luminance path (large chrominance bandwidth means wide chrominance notch resulting to lower luminance bandwidth). The burst processing block provides the feedback loop of the chrominance PLL and contains the following: • Burst gate accumulator • Colour identification and killer • Comparison nominal/actual burst amplitude (PAL/NTSC standards only) • Loop filter chrominance gain control (PAL/NTSC standards only) The low-pass filtered signals are fed to the adaptive comb filter block. The chrominance components are separated from the luminance via a two-line vertical stage (four lines for PAL standards) and a decision logic circuit between the filtered and the non-filtered output signals: this block is bypassed for SECAM signals. The comb filter logic can be enabled independently for the succeeding luminance and chrominance processing by YCOMB (subaddress 09H, bit 6) and/or CCOMB (subaddress 0EH, bit 0). It is always bypassed during VBI or raw data lines, programmable by the LCRn registers (subaddresses 41H to 57H); see Section 9.2. • Loop filter chrominance PLL (only active for PAL/NTSC standards) • PAL/SECAM sequence detection, H/2-switch generation. The increment generation circuit produces the Discrete Time Oscillator (DTO) increment for both subcarrier generation blocks. It contains a division by the increment of the line-locked clock generator to create a stable phase-locked sine signal under all conditions (e.g. for non-standard signals). The PAL delay line block eliminates crosstalk between the chrominance channels in accordance with the PAL standard requirements. For NTSC colour standards, the delay line can be used as an additional vertical filter. If desired, it can be switched off by DCVF = 1. It is always disabled during VBI or raw data lines programmable by the LCRn registers (subaddresses 41H to 57H); see Section 9.2. The embedded line delay is also used for SECAM recombination (cross-over switches). The separated CB-CR components are further processed by a second filter stage (low-pass 2) to modify the chrominance bandwidth without influencing the luminance path. It’s characteristic is controlled by CHBW (subaddress 10H, bit 3). For the complete transfer characteristic of low-pass filters 1 and 2 see Figs 19 and 20. The SECAM processing (bypassed for QAM standards) contains the following blocks: 2004 Jun 29 38 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE MHB533 3 V (dB) 0 −3 −6 −9 −12 (1) −15 (2) −18 (3) −21 (4) −24 −27 −30 −33 −36 −39 −42 −45 (1) (2) (3) (4) LCBW[2:0] = 000. LCBW[2:0] = 010. LCBW[2:0] = 100. LCBW[2:0] = 110. −48 −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz) 3 V (dB) 0 −3 −6 −9 −12 −15 (5) −18 (6) −21 (7) −24 (8) −27 −30 −33 −36 −39 −42 −45 (5) (6) (7) (8) LCBW[2:0] = 001. LCBW[2:0] = 011. LCBW[2:0] = 101. LCBW[2:0] = 111. −48 −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz) Fig.19 Transfer characteristics of the chrominance low-pass at CHBW = 0. 2004 Jun 29 39 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE MHB534 3 V (dB) 0 −3 −6 −9 −12 (1) −15 (2) −18 (3) −21 (4) −24 −27 −30 −33 −36 −39 −42 −45 (1) (2) (3) (4) LCBW[2:0] = 000. LCBW[2:0] = 010. LCBW[2:0] = 100. LCBW[2:0] = 110. −48 −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz) 3 V (dB) 0 −3 −6 −9 −12 −15 (5) −18 (6) −21 (7) −24 (8) −27 −30 −33 −36 −39 −42 −45 (5) (6) (7) (8) LCBW[2:0] = 001. LCBW[2:0] = 011. LCBW[2:0] = 101. LCBW[2:0] = 111. −48 −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (MHz) Fig.20 Transfer characteristics of the chrominance low-pass at CHBW = 1. 2004 Jun 29 40 Philips Semiconductors Product specification HD-CODEC 9.1.3.2 SAA7108AE; SAA7109AE Luminance path The frequency characteristic of the separated luminance signal can be further modified by the succeeding luminance filter block. It can be configured as peaking (resolution enhancement) or low-pass block by LUFI3 to LUFI0 (subaddress 09H, bits 3 to 0). The 16 resulting frequency characteristics can be seen in Fig.25. The LUFI3 to LUFI0 settings can be used as a user programmable sharpness control. The rejection of the chrominance components within the 9-bit CVBS or Y input signal is done by subtracting the re-modulated chrominance signal from the CVBS input. The comb filtered CB-CR components are interpolated (upsampled) by the low-pass 3 block. It’s characteristic is controlled by LUBW (subaddress 09H, bit 4) to modify the width of the chrominance ‘notch’ without influencing the chrominance path. The programmable frequency characteristics available, in conjunction with the LCBW2 to LCBW0 settings, can be seen in Figs 21 to 24. It should be noted that these frequency curves are only valid for Y comb disabled filter mode (YCOMB = 0). In comb filter mode the frequency response is flat. The centre frequency of the notch is automatically adapted to the chosen colour standard. The luminance filter block also contains the adjustable Y delay part; programmable by YDEL2 to YDEL0 (subaddress 11H, bits 2 to 0). The interpolated CB-CR samples are multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 2. This second DTO is locked to the first subcarrier generator by an increment delay circuit matched to the processing delay, which is different for PAL and NTSC standards according to the chosen comb filter algorithm. The two modulated signals are finally added to create the re-modulated chrominance signal. 2004 Jun 29 41 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE MHB535 3 V (dB) 0 −3 −6 −9 −12 −15 −18 −21 (1) (2) (3) (4) −24 −27 −30 −33 −36 −39 −42 −45 −48 (1) (2) (3) (4) LCBW[2:0] = 000. LCBW[2:0] = 010. LCBW[2:0] = 100. LCBW[2:0] = 110. −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) 3 V (dB) 0 −3 −6 −9 −12 −15 −18 −21 −24 (5) (6) (7) (8) −27 −30 −33 −36 −39 −42 −45 −48 (5) (6) (7) (8) LCBW[2:0] = 001. LCBW[2:0] = 011. LCBW[2:0] = 101. LCBW[2:0] = 111. −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) Fig.21 Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at LUBW = 0. 2004 Jun 29 42 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE MHB536 3 V (dB) 0 −3 −6 −9 (1) −12 (2) −15 (3) −18 (4) −21 −24 −27 −30 −33 −36 −39 −42 −45 −48 (1) (2) (3) (4) LCBW[2:0] = 000 LCBW[2:0] = 010 LCBW[2:0] = 100 LCBW[2:0] = 110 −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) 3 V (dB) 0 −3 −6 −9 −12 −15 −18 −21 −24 (5) (6) (7) (8) −27 −30 −33 −36 −39 −42 −45 −48 (5) (6) (7) (8) LCBW[2:0] = 001 LCBW[2:0] = 011 LCBW[2:0] = 101 LCBW[2:0] = 111 −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) Fig.22 Transfer characteristics of the luminance notch filter in 3.58 MHz mode (Y-comb filter disabled) at LUBW =1. 2004 Jun 29 43 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE MHB537 3 V (dB) 0 −3 −6 −9 −12 (1) −15 (2) −18 (3) −21 (4) −24 −27 −30 −33 −36 −39 −42 −45 −48 (1) (2) (3) (4) LCBW[2:0] = 000. LCBW[2:0] = 010. LCBW[2:0] = 100. LCBW[2:0] = 110. −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) 3 V (dB) 0 −3 −6 −9 −12 (5) −15 (6) −18 (7) −21 (8) −24 −27 −30 −33 −36 −39 −42 −45 −48 (5) (6) (7) (8) LCBW[2:0] = 001. LCBW[2:0] = 011. LCBW[2:0] = 101. LCBW[2:0] = 111. −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) Fig.23 Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at LUBW = 0. 2004 Jun 29 44 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE MHB538 3 V (dB) 0 −3 −6 −9 −12 (1) −15 (2) −18 (3) −21 (4) −24 −27 −30 −33 −36 −39 −42 −45 −48 (1) (2) (3) (4) LCBW[2:0] = 000. LCBW[2:0] = 010. LCBW[2:0] = 100. LCBW[2:0] = 110. −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) 3 V (dB) 0 −3 −6 −9 −12 (5) −15 (6) −18 (7) −21 (8) −24 −27 −30 −33 −36 −39 −42 −45 −48 (5) (6) (7) (8) LCBW[2:0] = 001. LCBW[2:0] = 011. LCBW[2:0] = 101. LCBW[2:0] = 111. −51 −54 −57 −60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 f (MHz) Fig.24 Transfer characteristics of the luminance notch filter in 4.43 MHz mode (Y-comb filter disabled) at LUBW = 1. 2004 Jun 29 45 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE MHB539 9 V (dB) 8 (1) (2) 7 (3) (4) (5) 6 (6) (7) 5 (8) 4 3 (1) (2) (3) (4) (5) (6) (7) (8) LUFI[3:0] = 0001. LUFI[3:0] = 0010. LUFI[3:0] = 0011. LUFI[3:0] = 0100. LUFI[3:0] = 0101. LUFI[3:0] = 0110. LUFI[3:0] = 0111. LUFI[3:0] = 0000. 2 1 0 −1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 f (MHz) 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 f (MHz) 6.0 3 V (dB) 0 −3 −6 (9) (10) (11) (12) (13) (14) (15) (16) −9 −12 −15 −18 −21 (9) LUFI[3:0] = 1000. (10) LUFI[3:0] = 1001. (11) LUFI[3:0] = 1010. (12) LUFI[3:0] = 1011. (13) LUFI[3:0] = 1100. (14) LUFI[3:0] = 1101. (15) LUFI[3:0] = 1110. (16) LUFI[3:0] = 1111. −24 −27 −30 −33 −36 −39 0 0.5 1.0 1.5 Fig.25 Transfer characteristics of the luminance peaking/low-pass filter (sharpness). 2004 Jun 29 46 Philips Semiconductors Product specification HD-CODEC 9.1.3.3 SAA7108AE; SAA7109AE Brightness Contrast Saturation (BCS) control and decoder output levels The resulting Y (CVBS) and CB-CR signals are fed to the BCS block, which contains the following functions: • Chrominance saturation control by DSAT7 to DSAT0 • Luminance contrast and brightness control by DCON7 to DCON0 and DBRI7 to DBRI0 • Raw data (CVBS) gain and offset adjustment by RAWG7 to RAWG0 and RAWO7 to RAWO0 • Limiting Y-CB-CR or CVBS to the values 1 (minimum) and 254 (maximum) to fulfil “ITU Recommendation 601/656”. +255 handbook, full pagewidth +235 +128 white LUMINANCE 100% +255 +240 blue 100% +255 +240 red 100% +212 blue 75% +212 red 75% +128 colourless +128 colourless CB-COMPONENT +16 black CR-COMPONENT +44 yellow 75% +44 cyan 75% +16 yellow 100% +16 cyan 100% 0 0 0 MHB730 a. Y output range. b. CB output range. c. CR output range. “ITU Recommendation 601/656” digital levels with default BCS (decoder) settings DCON[7:0] = 44H, DBRI[7:0] = 80H and DSAT[7:0] = 40H. Equations for modification to the Y-CB-CR levels via BCS control I2C-bus bytes DBRI, DCON and DSAT. Luminance: DCON Y OUT = Int ----------------- × ( Y – 128 ) + DBRI 68 DSAT Chrominance: ( C R C B ) OUT = Int ---------------- × ( C R, C B – 128 ) + 128 64 It should be noted that the resulting levels are limited to 1 to 254 in accordance with “ITU Recommendation 601/656”. Fig.26 Y-CB-CR range for scaler input and X port output. 2004 Jun 29 47 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE +255 +255 +209 white +199 LUMINANCE +71 +60 LUMINANCE black black shoulder +60 black shoulder = black SYNC SYNC 1 white 1 sync bottom sync bottom MGD700 a. Sources containing 7.5 IRE black level offset (e.g. NTSC M). b. Sources not containing black level offset. CVBS levels with default settings RAWG[7:0] = 64 and RAWO[7:0] = 128. Equation for modification of the raw data levels via bytes RAWG and RAWO: RAWG CVBS OUT = Int ------------------ × ( CVBS nom – 128 ) + RAWO 64 It should be noted that the resulting levels are limited to 1 to 254 in accordance with “ITU Recommendation 601/656”. Fig.27 CVBS (raw data) range for scaler input, data slicer and X port output. 2004 Jun 29 48 Philips Semiconductors Product specification HD-CODEC 9.1.4 SAA7108AE; SAA7109AE The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal PLL. It is a multiple of the line frequency: SYNCHRONIZATION The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is further reduced to 1 MHz by a low-pass filter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop filter to accumulate all phase deviations. Internal signals (e.g. HCL and HSY) are generated in accordance with analog front-end requirements. The loop filter signal drives an oscillator to generate the line frequency control signal (LFCO); see Fig.28. 6.75 MHz = 429 × fH (50 Hz), or 6.75 MHz = 432 × fH (60 Hz). The LFCO signal is multiplied internally by a factor of 2 and 4 in the PLL circuit (including phase detector, loop filtering, VCO and frequency divider) to obtain the output clock signals. The rectangular output clocks have a 50 % duty cycle. Table 16 Decoder clock frequencies The detection of ‘pseudo syncs’ as part of the Macrovision copy protection standard is also done within the synchronization circuit. CLOCK XTAL The result is reported as flag COPRO within the decoder status byte at subaddress 1FH. 9.1.5 FREQUENCY (MHz) CLOCK GENERATION CIRCUIT 24.576 or 32.110 LLC 27 LLC2 13.5 LLC4 (internal) 6.75 LLC8 (virtual) 3.375 The internal CGC generates all clock signals required for the video input processor. LFCO BAND PASS FC = LLC/4 ZERO CROSS DETECTION PHASE DETECTION LOOP FILTER OSCILLATOR LLC DIVIDER 1/2 DIVIDER 1/2 LLC2 MHB330 Fig.28 Block diagram of the clock generation circuit. 9.1.6 POWER-ON RESET AND CE INPUT A missing clock, insufficient digital or analog VDDAd supply voltages (below 2.7 V) will start the reset sequence; all outputs are forced to 3-state (see Fig.29). The indicator output RESd is LOW for approximately 128 LLC after the internal reset and can be applied to reset other circuits of the digital TV system. It is possible to force a reset by pulling the Chip Enable (CE) to ground. After the rising edge of CE and sufficient power supply voltage, the outputs LLC, LLC2 and SDAd return from 3-state to active, while the other signals have to be activated via programming. 2004 Jun 29 49 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE POC V DDA ANALOG POC V DDD DIGITAL CLOCK PLL LLC CE POC LOGIC POC DELAY RES RESINT CLK0 CE XTALO LLCINT RESINT LLC RES (internal reset) some ms 20 to 200 µs PLL-delay 896 LCC digital delay <1 ms POC = Power-on Control. CE = chip enable input. XTALO = crystal oscillator output. LLCINT = internal system clock. RESINT = internal reset. LLC = line-locked clock output. RES = reset output. Fig.29 Power-on control circuit. 2004 Jun 29 50 128 LCC MHB331 Philips Semiconductors Product specification HD-CODEC 9.2 SAA7108AE; SAA7109AE Decoder output formatter For each LCR value, from 2 to 23, the data type can be programmed individually. LCR2 to LCR23 refer to line numbers. The selection in LCR24 values is valid for the rest of the corresponding field. The upper nibble contains the value for field 1 (odd), the lower nibble for field 2 (even). The relationship between LCR values and line numbers can be adjusted via VOFF8 to VOFF0, located in subaddresses 5BH (bit 4) and 5AH (bits 7 to 0) and FOFF subaddress 5BH (bit 7). The recommended values are VOFF[8:0] = 03H for 50 Hz sources (with FOFF = 0) and VOFF[8:0] = 06H for 60 Hz sources (with FOFF = 1), to accommodate line number conventions as used for PAL, SECAM and NTSC standards; see Tables 18 to 21. The output interface block of the decoder part contains the ITU 656 formatter for the expansion port data output XPD7 to XPD0 (see Section 10.4.1) and the control circuit for the signals needed for the internal paths to the scaler and data slicer part. It also controls the selection of the reference signals for the RT port (RTCO, RTS0 and RTS1) and the expansion port (XRH, XRV and XDQ). The generation of the decoder data type control signals SET_RAW and SET VBI is also done within this block. These signals are decoded from the requested data type for the scaler input and/or the data slicer, selectable by the control registers LCR2 to LCR24; see Section 18.2.4.2. Table 17 Data formats at decoder output DATA TYPE NUMBER 2004 Jun 29 DATA TYPE DECODER OUTPUT DATA FORMAT 0 teletext EuroWST, CCST raw 1 European Closed Caption raw 2 Video Programming Service (VPS) raw 3 Wide screen signalling bits raw 4 US teletext (WST) raw 5 US Closed Caption (line 21) raw Y-CB-CR 4 : 2 : 2 6 video component signal, VBI region 7 CVBS data raw 8 teletext raw 9 VITC/EBU time codes (Europe) raw 10 VITC/SMPTE time codes (USA) raw 11 reserved raw 12 US NABTS raw 13 MOJI (Japanese) raw 14 Japanese format switch (L20/22) raw 15 video component signal, active video region 51 Y-CB-CR 4 : 2 : 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 521 522 Line number (2nd field) 259 260 523 524 525 1 262 263 264 active video 261 3 4 equalization pulses active video LCR 2 265 6 7 269 270 serration pulses 266 267 equalization pulses 24 5 268 3 4 9 equalization pulses serration pulses 2 8 271 272 equalization pulses 5 6 7 8 Philips Semiconductors Line number (1st field) HD-CODEC 2004 Jun 29 Table 18 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 1) Vertical line offset, VOFF[8:0] = 06H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 1 (subaddress 5BH[7]) 9 Table 19 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part 2) Vertical line offset, VOFF[8:0] = 06H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 1 (subaddress 5BH[7]) Line number (1st field) 10 Line number (2nd field) 273 LCR 10 11 12 13 14 15 16 17 18 19 20 21 22 nominal VBI lines F1 274 275 276 277 278 279 12 13 14 15 280 16 24 25 active video 281 282 283 284 285 nominal VBI lines F2 11 23 286 287 288 active video 17 18 19 20 21 22 23 24 52 Table 20 Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 1) Vertical line offset, VOFF[8:0] = 03H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 0 (subaddress 5BH[7]) 621 Line number (2nd field) 309 622 623 624 active video 625 1 2 equalization pulses 310 311 active video 312 4 serration pulses 313 equalization pulses LCR 3 314 equalization pulses 315 316 serration pulses 24 5 317 318 equalization pulses 2 3 4 5 Table 21 Relationship of LCR to line numbers in 625 lines/50 Hz systems (part 2) Vertical line offset, VOFF[8:0] = 03H (subaddresses 5BH[4] and 5AH[7:0]); horizontal pixel offset, HOFF[10:0] = 347H (subaddresses 5BH[2:0] and 59H[7:0]); FOFF = 0 (subaddress 5BH[7]) 6 Line number (2nd field) 319 320 321 322 323 324 325 6 7 8 9 10 11 12 LCR 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 nominal VBI lines F1 326 327 328 329 330 331 332 333 334 335 336 16 17 18 19 20 21 22 23 nominal VBI lines F2 13 14 15 24 25 active video 337 338 active video 24 Product specification Line number (1st field) SAA7108AE; SAA7109AE Line number (1st field) Philips Semiconductors Product specification HD-CODEC ITU counting single field counting SAA7108AE; SAA7109AE 622 309 623 310 624 311 625 312 1 1 2 2 3 3 4 4 5 5 6 6 7 7 ... ... 22 22 23 23 CVBS HREF F_ITU656 V123 (1) VSTO [8:0] = 134H VGATE FID VSTA [8:0] = 15H (a) 1st field ITU counting single field counting 309 309 310 310 311 311 312 312 313 313 314 1 315 2 316 3 317 4 318 5 319 6 ... ... 335 22 336 23 CVBS HREF F_ITU656 V123 (1) VSTO [8:0] = 134H VGATE FID (b) 2nd field VSTA [8:0] = 15H MHB540 (1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table: NAME HREF RTS0 (PIN K13) RTS1 (PIN L10) XRH (PIN N2) XRV (PIN L5) X X X − F_ITU656 − − − X V123 X X − X VGATE X X − − FID X X − − For further information see programming section, Tables 171, 172 and 173. Fig.30 Vertical timing diagram for 50 Hz/625 line systems. 2004 Jun 29 53 Philips Semiconductors Product specification HD-CODEC ITU counting single field counting SAA7108AE; SAA7109AE 525 262 1 1 3 3 2 2 4 4 5 5 6 6 7 7 8 8 9 9 10 10 ... ... 21 21 22 22 CVBS HREF F_ITU656 V123 (1) VSTO [8:0] = 101H VGATE FID VSTA [8:0] = 011H (a) 1st field ITU counting single field counting 262 262 263 263 264 1 265 2 266 3 267 4 268 5 269 6 270 7 271 8 272 9 ... ... 284 21 285 22 CVBS HREF F_ITU656 V123 (1) VSTO [8:0] = 101H VGATE FID (b) 2nd field VSTA [8:0] = 011H MHB541 (1) The inactive going edge of the V123 signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the field is ODD (field 1). If HREF is inactive during the falling edge of V123, the field is EVEN. The specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to the following table: NAME HREF RTS0 (PIN K13 RTS1 (PIN L10) XRH (PIN N2) XRV (PIN L5) X X X − F_ITU656 − − − X V123 X X − X VGATE X X − − FID X X − − For further information see programming section, Tables 171, 172 and 173. Fig.31 Vertical timing diagram for 60 Hz/525 line systems. 2004 Jun 29 54 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE burst CVBS input processing delay ADC to expansion port: 140 × 1/LLC expansion port data output sync clipped HREF (50 Hz) 12 × 2/LLC 144 × 2/LLC 720 × 2/LLC CREF CREF2 5 × 2/LLC 2 × 2/LLC HS (50 Hz) programming range 108 (step size: 8/LLC) −107 0 HREF (60 Hz) 16 × 2/LLC 720 × 2/LLC 138 × 2/LLC CREF CREF2 1 × 2/LLC 2 × 2/LLC HS (60 Hz) programming range (step size: 8/LLC) 107 −106 0 MHB542 The signals HREF, HS, CREF2 and CREF are available on pins RTS0 and/or RTS1 (see Section 18.2.2.19 Tables 171 and 172); their polarity can be inverted via RTP0 and/or RTP1. The signals HREF and HS are available on pin XRH (see Section 18.2.2.20 Table 173). Fig.32 Horizontal timing diagram (50/60 Hz). 2004 Jun 29 55 Philips Semiconductors Product specification HD-CODEC 9.3 SAA7108AE; SAA7109AE The overall H and V zooming (HV_zoom) is restricted by the input/output data rate relationships. With a safety margin of 2 % for running in and running out, the maximum HV_zoom is equal to: T_input_field – T_v_blanking 0.98 × -------------------------------------------------------------------------------------------------------------------------------------in_pixel × in_lines × out_cycle_per_pix × T_out_clk Scaler The High Performance video Scaler (HPS) is based on the system as implemented in the SAA7140, but enhanced in some aspects. Vertical upsampling is supported and the processing pipeline buffer capacity is enhanced, to allow more flexible video stream timing at the image port, discontinuous transfers and handshake. The internal data flow from block to block is discontinuous dynamically, due to the scaling process. For example: 1. Input from decoder: 50 Hz, 720 pixel, 288 lines, 16-bit data at 13.5 MHz data rate, 1 cycle per pixel; output: 8-bit data at 27 MHz, 2 cycles per pixel; the maximum HV_zoom is equal to: 20 ms – 24 × 64 µs 0.98 × -------------------------------------------------------- = 1.18 720 × 288 × 2 × 37 ns The flow is controlled by internal data valid and data request flags (internal handshake signalling) between the sub-blocks. Therefore the entire scaler acts as a pipeline buffer. Depending on the actually programmed scaling parameters the effective buffer can exceed to an entire line. The access/bandwidth requirements to the VGA frame buffer are reduced significantly. 2. Input from X port: 60 Hz, 720 pixel, 240 lines, 8-bit data at 27 MHz data rate (ITU 656), 2 cycles per pixel; output via I + H port: 16-bit data at 27 MHz clock, 1 cycle per pixel; the maximum HV_zoom is equal to: 16.666 ms – 22 × 64 µs 0.98 × -------------------------------------------------------------- = 2.34 720 × 240 × 1 × 37 ns The high performance video scaler in the SAA7108AE; SAA7109AE has the following major blocks. • Acquisition control (horizontal and vertical timer) and task handling (the region/field/frame based processing) The video scaler receives its input signal from the video decoder or from the expansion port (X port). It gets 16-bit Y-CB-CR 4 : 2 : 2 input data at a continuous rate of 13.5 MHz from the decoder. A discontinuous data stream can be accepted from the expansion port, normally 8-bit wide ITU 656 like Y-CB-CR data, accompanied by a pixel qualifier on XDQ. • Prescaler, for horizontal downscaling by an integer factor, combined with appropriate band limiting filters, especially anti-aliasing for CIF format • Brightness, saturation and contrast control for scaled output data • Line buffer, with asynchronous read and write, to support vertical upscaling (e.g. for videophone application, converting 240 into 288 lines, Y-CB-CR 4 : 2 : 2) The input data stream is sorted into two data paths, one for luminance (or raw samples), and one for time multiplexed chrominance CB and CR samples. A Y-CB-CR 4 : 1 : 1 input format is converted to 4 : 2 : 2 for the horizontal prescaling and vertical filter scaling operation. • Vertical scaling, with phase accurate Linear Phase Interpolation (LPI) for zoom and downscaling, or phase accurate Accumulation Mode (ACM) for large downscaling ratios and better anti-alias suppression The scaler operation is defined by two programming pages A and B, representing two different tasks that can be applied field alternating or to define two regions in a field (e.g. with different scaling range, factors, and signal source during odd and even fields). • Variable Phase Delay (VPD), operates as horizontal phase accurate interpolation for arbitrary non-integer scaling ratios, supporting conversion between square and rectangular pixel sampling Each programming page contains control for: • Output formatter for scaled Y-CB-CR 4 : 2 : 2, Y-CB-CR 4 : 1 : 1 and Y only (format also for raw data) • Signal source selection and formats • FIFO, 32-bit wide, with 64 pixel capacity in Y-CB-CR formats • Task handling and trigger conditions • Output interface, 8 or 16-bit (only if extended by H port) data pins wide, synchronous or asynchronous operation, with stream events on discrete pins, or coded in the data stream. • H prescaler, V scaler and H phase scaling. 2004 Jun 29 • Input and output acquisition window definition Raw VBI data will be handled as specific input format and need its own programming page (equals own task). 56 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE 9.3.1.1 In VBI pass through operation the processing of prescaler and vertical scaling has to be disabled, however the horizontal fine scaling VPD can be activated. Upscaling (oversampling, zooming), free of frequency folding, up to factor 3.5 can be achieved, as required by some software data slicing algorithms. The trigger event for the field sequence detection from external signals (X port) are defined in subaddress 92H. The state of the scalers horizontal reference signal at the time of the vertical reference edge is taken from the X port as field sequence identifier (FID). For example, if the falling edge of the XRV input signal is the reference and the state of XRH input is logic 0 at that time, the detected field ID is logic 0. These raw samples are transported through the image port as valid data and can be output as Y only format. The lines are framed by SAV and EAV codes. 9.3.1 The bits XFDV[92H[7]] and XFDH[92H[6]] define the detection event and state of the flag from the X port. For the default setting of XFDV and XFDH at ‘00’ is taken from the state of the horizontal input at the falling edge of the vertical input. ACQUISITION CONTROL AND TASK HANDLING (SUBADDRESSES 80H, 90H, 91H, 94H TO 9FH AND C4H TO CFH) The acquisition control receives horizontal and vertical synchronization signals from the decoder section or from the X port. The acquisition window is generated via pixel and line counters at the appropriate places in the data path. Only qualified pixels and lines (lines with qualified pixel) are counted from the X port. The scaler gets corresponding field ID information directly from the SAA7108AE; SAA7109AE decoder path. The FID flag is used to determine whether the first or second field of a frame is going to be processed within the scaler, and it is also used as trigger conditions for the task handling (see bits STRC[1:0] 90H[1:0]). The acquisition window parameters are as follows: • Signal source selection: input video stream and formats from the decoder, or from the X port (programming bits SCSRC[1:0] 91H[5:4] and FSC[2:0] 91H[2:0]) According to ITU 656, FID at logic 0 means first field of a frame. To ease the application, the polarities of the detection results on the X port signals and the internal decoder ID can be changed via XFDH. Remark: The input of raw VBI data from the internal decoder should be controlled via the decoder output formatter and the LCR registers (see Section 9.2) As the V sync from the decoder path has a half line timing (due to the interlaced video signal), but the scaler processing only recognises full lines, during 1st fields from the decoder the line count of the scaler can possibly shift by one line, compared to the 2nd field. This can be compensated for by switching the vertical trigger event, as defined by XDV0, to the opposite V sync edge or by using the vertical scalers phase offsets. The vertical timing of the decoder can be seen in Figs 30 and 31. • Vertical offset: defined in lines of the video source, parameter YO[11:0] 99H[3:0] 98H[7:0] • Vertical length: defined in lines of the video source, parameter YS[11:0] 9BH[3:0] 9AH[7:0] • Vertical length: defined in number of target lines, as a result of vertical scaling, parameter YD[11:0] 9FH[3:0] 9EH[7:0] • Horizontal offset: defined in number of pixels of the video source, parameter XO[11:0] 95H[3:0] 94H[7:0] As the horizontal and vertical reference events inside the ITU 656 data stream (from X port) and the real-time reference signals from the decoder path are processed differently, the trigger events for the input acquisition also have to be programmed differently. • Horizontal length: defined in number of pixels of the video source, parameter XS[11:0] 97H[3:0] 96H[7:0] • Horizontal destination size: defined in target pixels after fine scaling, parameter XD[11:0] 9DH[3:0] 9CH[7:0]. The source start offset XO(11:0) and YO(11:0) opens the acquisition window, and the target size (XD11 to XD0, YD11 to YD0) closes the window, however the window is cut vertically if there are less output lines than required. The trigger events for the pixel and line counts are the horizontal and vertical reference edges as defined in subaddress 92H. The task handling is controlled by subaddress 90H; see Section 9.3.1.2. 2004 Jun 29 Input field processing 57 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 22 Processing trigger and start XDV1 92H[5] XDV0 92H[4] XDH 92H[2] DESCRIPTION Internal decoder: The processing triggers at the falling edge of the V123 pulse (see Figs 30 (50 Hz) and 31 (60 Hz)), and starts earliest with the rising edge of the decoder HREF at line number: 0 1 0 0 0 0 0 0 0 9.3.1.2 4/7 (50/60 Hz, 1st field), respectively 3/6 (50/60 Hz, 2nd field) (decoder count) 2/5 (50/60 Hz, 1st field), respectively 2/5 (50/60 Hz, 2nd field) (decoder count) External ITU 656 stream: The processing starts earliest with SAV at line number 23 (50 Hz system), respectively line 20 (60 Hz system) (according ITU 656 count) Task handling Remarks: • To activate a task, the start condition must be fulfilled and the acquisition window offsets must be reached. For example, in case of ‘start immediately’, and two regions are defined for one field, the offset of the lower region must be greater than (offset + length) of the upper region, if not, the actual counted H and V position at the end of the upper task is beyond the programmed offsets and the processing will ‘wait for next V’. The task handler controls the switching between the two programming register sets. It is controlled by subaddresses 90H and C0H. A task is enabled via the global control bits TEA[80H[4]] and TEB[80H[5]]. The handler is then triggered by events which can be defined for each register set. In the event of a programming error the task handling and the complete scaler can be reset to the initial states by the software reset bit SWRST[88H[5]] being set to logic 0. A software reset must be done after programming especially if the programming registers, related acquisition window and scaler are reprogrammed while a task is active. • Basically, the trigger conditions are checked when a task is activated. It is important to know that they are not checked while a task is inactive. So it is not possible to trigger to the next logic 0 or logic 1 with overlapping offset and active video ranges between the tasks (e.g. task A STRC[2:0] = 2, YO[11:0] = 310 and task B STRC[2:0] = 3, YO[11:0] = 310 results in an output field rate of 50⁄3 Hz). The difference in the disabling/enabling of a task, which is evaluated at the end of a running task (when SWRST is set to logic 0) is that it sets the internal state machines directly to their idle states. • After power-on or software reset (via SWRST[88H[5]]) task B gets priority over task A. The start condition for the handler is defined by bits STRC[1:0] 90H[1:0] and means: start immediately, wait for next V sync, next FID at logic 0 or next FID at logic 1. The FID is evaluated if the vertical and horizontal offsets are reached. With RPTSK[90H[2]] at logic 1 the actual running task is repeated (under the defined trigger conditions) before handing control over to the alternate task. To support field rate reduction, the handler is also enabled to skip fields (bits FSKP[2:0] 90H[5:3]) before executing the task. A TOGGLE flag is generated (used for the correct output field processing), which changes state at the beginning of a task every time a task is activated; examples are given in Section 9.3.1.3. 2004 Jun 29 58 Philips Semiconductors Product specification HD-CODEC 9.3.1.3 SAA7108AE; SAA7109AE Output field processing When OFIDC = 0, the scalers input field ID is available as output field ID on bit 6 of SAV and EAV, and respectively on pin IGP0 (IGP1), if the FID output is selected. As a reference for the output field processing, two signals are available for the back-end hardware. When OFIDC[90H[6]] = 1, the TOGGLE information is available as output field ID on bit 6 of SAV and EAV, and respectively on pin IGP0 (IGP1) if the FID output is selected. These signals are the input field ID from the scaler source and a TOGGLE flag, which shows that an active task is used an odd (1, 3, 5...) or even (2, 4, 6...) number of times. Using a single or both tasks and reducing the field or frame rate with the task handling functionality, the TOGGLE information can be used to reconstruct an interlaced scaled picture at a reduced frame rate. The TOGGLE flag is not synchronized to the input field detection, as it is only dependent on the interpretation of this information by the external hardware i.e. whether the output of the scaler is processed correctly; see Section 9.3.3. 2004 Jun 29 Additionally bit 7 of SAV and EAV can be defined via CONLH[90H[7]]. When CONLH[90H[7]] = 0 (default) it sets bit 7 to logic 1; a logic 1 inverts the SAV/EAV bit 7. So it is possible to mark the output of both tasks by different SAV/EAV codes. This bit can also be seen as ‘task flag’ on pins IGP0 (IGP1), if the TASK output is selected. 59 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... SUBJECT EXAMPLE 1(1) EXAMPLE 2(2)(3) EXAMPLE 3(2)(4)(5) EXAMPLE 4(2)(4)(6) 1/1 1/2 2/1 1/1 1/2 2/1 2/2 1/1 1/2 2/1 2/2 3/1 3/2 1/1 1/2 2/1 2/2 3/1 3/2 Processed by task A A A B A B A B B A B B A B B A B B A State of detected ITU 656 FID 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 TOGGLE flag 1 0 1 1 1 0 0 1 0 1 1 0 0 0(7) 1 1 1(7) 0 0 Bit 6 of SAV/EAV byte 0 1 0 0 1 0 1 1 0 1 1 0 0 0(7) 1 1 1(7) 0 0 UP ↓ UP LO ↓ LO UP ↓ UP UP ↓ UP LO ↓ LO UP ↓ UP LO ↓ LO UP ↓ LO LO ↓ UP UP ↓ LO LO ↓ LO UP ↓ UP LO ↓ UP UP ↓ UP LO ↓ LO UP ↓ LO LO ↓ LO UP ↓ UP LO ↓ UP O O O O O O O O O O O O O NO O O NO O O Required sequence conversion at the vertical scaler(8) Output(9) Philips Semiconductors FIELD SEQUENCE FRAME/FIELD HD-CODEC 2004 Jun 29 Table 23 Example for field processing Notes 1. Single task every field; OFIDC = 0; subaddress 90H at 40H; TEB[80H[5]] = 0. 2. Tasks are used to scale to different output windows, priority on task B after SWRST. 60 3. Both tasks at 1⁄2 frame rate; OFIDC = 0; subaddresses 90H at 43H and C0H at 42H. 4. In examples 3 and 4 the association between input FID and tasks can be flipped, dependent on which time the SWRST is de-asserted. 5. Task B at 2⁄3 frame rate constructed from neighbouring motion phases; task A at 1⁄3 frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90H at 41H and C0H at 45H. 6. Task A and B at 1⁄3 frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90H at 41H and C0H at 49H. 8. It is assumed that input/output FID = 0 (upper lines); UP = upper lines; LO = lower lines. 9. O = data output; NO = no output. Product specification SAA7108AE; SAA7109AE 7. State of prior field. Philips Semiconductors Product specification HD-CODEC 9.3.2 SAA7108AE; SAA7109AE • The bit XC2_1[A2H[3]], which defines the weighting of the incoming pixels during the averaging process HORIZONTAL SCALING The overall horizontal scaling factor has to be split into a binary and a rational value according to the following output pixel equation: H scale ratio = -----------------------------input pixel – XC2_1 = 0 ⇒ 1 + 1...+ 1 + 1 – XC2_1 = 1 ⇒ 1 + 2...+ 2 + 1. The prescaler creates a prescale dependent FIR low-pass, with up to 64 + 7 filter taps. The parameter XACL[5:0] can be used to vary the low-pass characteristic for a given integer prescale of 1⁄XPSC[5:0]. The user can therewith decide between signal bandwidth (sharpness impression) and alias. 1 1024 H scale ratio = ---------------------------- × ------------------------------XPSC[5:0] XSCY[12:0] where, the parameter of the prescaler XPSC[5:0] = 1 to 63 and the parameter of VPD phase interpolation XSCY[12:0] = 300 to 8191 (0 to 299 are only theoretical values). For example, 1⁄3.5 is split into 1⁄4 × 1.14286. The binary factor is processed by the prescaler, the arbitrary non-integer ratio is achieved via the variable phase delay VPD circuitry, called horizontal fine scaling. The latter calculates horizontally interpolated new samples with a 6-bit phase accuracy, which relates to less than 1 ns jitter for regular sampling schemes. Together the prescaler and fine scaler form the horizontal scaler of the SAA7108AE; SAA7109AE. The equation for the XPSC[5:0] calculation is: Npix_in XPSC[5:0] = lower integer of ----------------------Npix_out Where: the range is 1 to 63 (value 0 is not allowed); Npix_in = number of input pixel, and Npix_out = number of desired output pixel over the complete horizontal scaler. Using the accumulation length function of the prescaler (XACL[5:0] A1H[5:0]), application and destination dependent (e.g. scale for display or for a compression machine), a compromise between visible bandwidth and alias suppression can be found. 9.3.2.1 The use of the prescaler results in a XACL[5:0] and XC2_1 dependent gain amplification. The amplification can be calculated according to the equation: DC gain = [(XACL[5:0] − XC2_1) + 1] × (XC2_1 + 1) It is recommended to use sequence lengths and weights, which results in a 2N DC gain amplification, as these amplitudes can be renormalized by the XDCG[2:0] 1 controlled -----shifter of the prescaler. N 2 Horizontal prescaler (subaddresses A0H to A7H and D0H to D7H) The prescaling function consists of an FIR anti-alias filter stage and an integer prescaler, which together form an adaptive prescale dependent low-pass filter to balance the sharpness and aliasing effects. The renormalization range of XDCG[2:0] is 1, 1⁄2... down to 1⁄128. The FIR pre-filter stage implements different low-pass characteristics to reduce the anti-alias for downscales in the range of 1 to 1⁄2. A CIF optimized filter is built-in, which reduces artefacts for CIF output formats (to be used in combination with the prescaler set to 1⁄2 scale); see Table 24. Other amplifications have to be normalized by using the following BCS control circuitry. In these cases the prescaler has to be set to an overall gain ≤1, e.g. for an accumulation sequence of ‘1 + 1 + 1’ (XACL[5:0] = 2 and XC2_1 = 0), XDCG[2:0] must be set to ‘010’, which equals 1⁄4 and the BCS has to amplify the signal to 4⁄3 (SATN[7:0] and CONT[7:0] value = lower integer of 4⁄ × 64). 3 The function of the prescaler is defined by: • An integer prescaling ratio XPSC[5:0] A0H[5:0] (equals 1 to 63), which covers the integer downscale range 1 to 1⁄63 The use of XACL[5:0] is XPSC[5:0] dependent. XACL[5:0] must be <2 × XPSC[5:0]. • An averaging sequence length XACL[5:0] A1H[5:0] (equals 0 to 63); range 1 to 64 XACL[5:0] can be used to find a compromise between bandwidth (sharpness) and alias effects. • A DC gain renormalization XDCG[2:0] A2H[2:0]; 1 down to 1⁄128) 2004 Jun 29 61 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE For example, if XACL[5:0] = 5, XC2_1 = 1, then DC gain = 10 and the required XDCG[2:0] = 4. Remark: Due to bandwidth considerations XPSC[5:0] and XACL[5:0] can be chosen differently to the previously mentioned equations or Table 25, as the horizontal phase scaling is able to scale in the range from zooming up by factor 3 to downscaling by a factor of 1024⁄8191. The horizontal source acquisition timing and the prescaling ratio is identical for both the luminance and chrominance path, but the FIR filter settings can be defined differently in the two channels. Figs 35 and 36 show some frequency characteristics of the prescaler. Fade-in and fade-out of the filters is achieved by copying an original source sample each as first and last pixel after prescaling. Table 25 shows the recommended prescaler programming. Other programming, than given in Table 25, may result in better alias suppression, but the resulting DC gain amplification needs to be compensated by the BCS control, according to the equation: Figs 33 and 34 show the frequency characteristics of the selectable FIR filters. XDCG[2:0] 2 CONT[7:0] = SATN[7:0] = lower integer of ---------------------------------DC gain × 64 Where: 2XDCG[2:0] ≥ DC gain DC gain = (XC2_1 + 1) × XACL[5:0] + (1 − XC2_1). Table 24 FIR prefilter functions PFUV[1:0] A2H[7:6] PFY[1:0] A2H[5:4] LUMINANCE FILTER COEFFICIENTS CHROMINANCE COEFFICIENTS 00 bypassed bypassed 01 121 121 10 −1 1 1.75 4.5 1.75 1 −1 3 8 10 8 3 11 12221 12221 2004 Jun 29 62 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE MHB543 6 V 3 (dB) 0 −3 −6 (1) −9 (2) −12 −15 (3) −18 −21 −24 −27 −30 −33 −36 −39 (1) PFY[1:0] = 01. (2) PFY[1:0] = 10. (3) PFY[1:0] = 11. −42 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 f_sig/f_clock 0.5 Fig.33 Luminance prefilter characteristic. MHB544 6 V 3 (dB) 0 −3 (1) −6 −9 (2) −12 (3) −15 −18 −21 −24 −27 −30 −33 −36 −39 (1) PFUV[1:0] = 01. (2) PFUV[1:0] = 10. (3) PFUV[1:0] = 11. −42 0 0.025 0.05 0.075 0.1 0.125 0.15 Fig.34 Chrominance prefilter characteristic. 2004 Jun 29 63 0.175 0.2 0.225 0.25 f_sig/f_clock Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE MHB545 6 V 3 (dB) 0 −3 −6 (5) (4) (3) (2) (1) −9 −12 −15 −18 −21 −24 −27 −30 −33 −36 XC2_1 = 0; Zero’s at 1 f = n × ------------------------XACL + 1 with XACL = (1), (2), (3), (4) or (5) −39 −42 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 f_sig/f_clock 0.5 Fig.35 Examples for prescaler filter characteristics: effect of increasing XACL[5:0]. MHB546 6 V 3 (dB) 0 (1) −3 3 dB at 0.25 (2) −6 (6) (5) (4) 6 dB at 0.33 (3) −9 −12 −15 −18 −21 (1) XC2_1 = 0 and XACL[5:0] = 1. (2) XC2_1 = 1 and XACL[5:0] = 2. (3) XC2_1 = 0 and XACL[5:0] = 3. (4) XC2_1 = 1 and XACL[5:0] = 4. (5) XC2_1 = 0 and XACL[5:0] = 7. (6) XC2_1 = 1 and XACL[5:0] = 8. −24 −27 −30 −33 −36 −39 −42 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 Fig.36 Examples for prescaler filter characteristics: setting XC2_1 = 1. 2004 Jun 29 64 0.4 0.45 f_sig/f_clock 0.5 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 25 Example of XACL[5:0] usage RECOMMENDED VALUES PRESCALE XPSC RATIO [5:0] FOR LOWER BANDWIDTH REQUIREMENTS XC2_1 XDCG[2:0] XACL[5:0] XC2_1 XDCG[2:0] 0 0 0 0 0 to 2 2 1 0 1 0 to 2 2 2 3 2 3 2 3 3 3 3 4 3 1 1 0 0 2 2 1 (1 2 1) × 3 4 1⁄ (1) 4 4 7 (1 1) × 1 (1 2 2 2 1) × 1⁄ 4 3 3 1⁄ (1) 8 5 8 0 3 1 4 (1 2 2 2 2 2 2 2 1) × 1⁄ 6 6 8 (1 2 2 2 2 2 2 2 1) × 1⁄ 7 7 8 7 4 7 4 7 (1 2 2 2 2 2 2 2 1) × 1⁄16(1) 1⁄ 8 8 15 0 (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) × 1⁄ 9 9 15 0 10 10 16 1 4 8 1⁄ (1) 16 4 1⁄ 1⁄ 1⁄ (1) 8 0 1⁄ (1) 8 0 (1) 32 1 1⁄ (1) 16 4 3 (1 2 2 2 2 2 2 2 1) × 1⁄16(1) 8 1⁄ 1 (1 2 2 2 2 2 2 2 1) × 8 5 (1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1) × 1⁄ 0 (1 1 1 1 1 1 1 1) × 1⁄8(1) (1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1) × 1⁄16(1) 1⁄ 1 (1 1 1 1 1 1 1 1) × (1) 16 1 1⁄ (1) 4 (1 1 1 1 1 1 1 1) × (1) 16 1 1⁄ 0 (1 2 2 2 1) × 1⁄8(1) 4 1⁄ 1⁄ (1) 2 (1 1 1 1) × (1 1 1 1 1 1 1 1) × 1⁄8(1) 1⁄ 5 FIR PREFILTER PFY[1:0]/ PFUV[1:0] XACL[5:0] 1⁄ 2 1⁄ 3 FOR HIGHER BANDWIDTH REQUIREMENTS 1 (1 2 2 2 2 2 2 2 1) × 4 3 1⁄ (1) 16 13 13 16 1 5 16 1 5 3 15 15 31 0 5 16 1 5 3 16 16 31 0 5 16 1 5 3 1⁄ 19 19 32 1 6 32 1 6 3 1⁄ 31 31 32 1 6 32 1 6 3 1⁄ 32 32 63 1 7 32 1 6 3 35 35 63 1 7 63 1 7 3 1⁄ Note 1. Resulting FIR function. 2004 Jun 29 65 Philips Semiconductors Product specification HD-CODEC 9.3.2.2 SAA7108AE; SAA7109AE Horizontal fine scaling (variable phase delay filter; subaddresses A8H to AFH and D8H to DFH) 9.3.3.1 The line FIFO buffer is a dual ported RAM structure for 768 pixels, with asynchronous write and read access. The line buffer can be used for various functions, but not all functions may be available simultaneously. The horizontal fine scaling (VPD) should operate at scaling ratios between 1⁄2 and 2 (0.8 and 1.6), but can also be used for direct scaling in the range from 1⁄7.999 to (theoretical) zoom 3.5 (restriction due to the internal data path architecture), without prescaler. The line buffer can buffer a complete unscaled active video line or more than one shorter lines (only for non-mirror mode), for selective repetition for vertical zoom-up. In combination with the prescaler a compromise between sharpness impression and alias can be found, which is signal source and application dependent. For zooming up from 240 lines to 288 lines e.g., every fourth line is requested (read) twice from the vertical scaling circuitry for calculation. For the luminance channel a filter structure with 10 taps is implemented, for the chrominance a filter with 4 taps. For conversion of a 4 : 2 : 0 or 4 : 1 : 0 input sampling scheme (MPEG, video phone, Indeo YUV-9) to ITU like sampling scheme 4 : 2 : 2, the chrominance line buffer is read twice or four times, before being refilled again by the source. By means of the input acquisition window definition it has to be preserved, that the processing starts with a line containing luminance and chrominance information for 4 : 2 : 0 and 4 : 1 : 0 input. The bits FSC[2:1] 91H[2:1] define the distance between the Y/C lines. In case of 4 : 2 : 2 and 4 : 1 : 1 FSC2 and FSC1 have to be set to ‘00’. Luminance and chrominance scale increments (XSCY[12:0] A9H[4:0] A8H[7:0] and XSCC[12:0] ADH[4:0] ACH[7:0]) are defined independently, but must be set in a 2 : 1 relationship in the actual data path implementation. The phase offsets XPHY[7:0] AAH[7:0] and XPHC[7:0] AEH[7:0] can be used to shift the sample phases slightly. XPHY[7:0] and XPHC[7:0] covers the phase offset range 7.999T to 1⁄32T. The phase offsets should also be programmed in a 2 : 1 ratio. The underlying phase controlling DTO has a 13-bit resolution. The line buffer can also be used for mirroring, i.e. for flipping the image left to right, for the vanity picture in video phone application (bit YMIR[B4H[4]]). In mirror mode only one active prescaled line can be held in the FIFO at a time. According to the equations 1 Npix_in XSCY[12:0] = 1024 × ---------------------------- × ----------------------- and XPSC[5:0] Npix_out The line buffer can be utilized as excessive pipeline buffer for discontinuous and variable rate transfer conditions at the expansion port or image port. XSCY[12:0] XSCC[12:0] = ------------------------------2 The VPD covers the scale range from 0.125 to zoom 3.5. The VPD acts equivalent to a polyphase filter with 64 possible phases. In combination with the prescaler, it is possible to get high accurate samples from a highly anti-aliased integer downscaled input picture. 9.3.3 9.3.3.2 Vertical scaler (subaddresses B0H to BFH and E0H to EFH) Vertical scaling of any ratio from 64 (theoretical zoom) to 1⁄63 (icon) can be applied. The vertical scaling block consists of another line delay, and the vertical filter structure, that can operate in two different modes. These are the Linear Phase Interpolation (LPI) and Accumulation (ACM) modes, controlled by YMODE[B4H[0]]. VERTICAL SCALING The vertical scaler of the SAA7108AE; SAA7109AE decoder part consists of a line FIFO buffer for line repetition and the vertical scaler block, which implements the vertical scaling on the input data stream in 2 different operational modes from theoretical zoom by 64 down to icon size 1⁄64. The vertical scaler is located between the BCS and horizontal fine scaler, so that the BCS can be used to compensate for the DC gain amplification of the ACM mode (see Section 9.3.3.2) as the internal RAMs are only 8-bit wide. 2004 Jun 29 Line FIFO buffer (subaddresses 91H, B4H and C1H, E4H) 66 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE • BCS value to compensate DC gain in ACM mode (contrast and saturation have to be set): CONT[7:0] A5H[7:0] respectively SATN[7:0] A6H[7:0] • LPI mode: In the linear phase interpolation mode (YMODE = 0) two neighbouring lines of the source video stream are added together, but weighted by factors corresponding to the vertical position (phase) of the target output line relative to the source lines. This linear interpolation has a 6-bit phase resolution, which equals 64 intra line phases. It interpolates between two consecutive input lines only. The LPI mode should be applied for scaling ratios around 1 (down to 1⁄2), it must be applied for vertical zooming. Nline_out = lower integer of ------------------------- × 64 , or Nline_in 1024 = lower integer of ------------------------------- × 64 YSCY[15:0] 9.3.3.3 • ACM mode: The vertical Accumulation (ACM) mode (YMODE = 1) represents a vertical averaging window over multiple lines, sliding over the field. This mode also generates phase correct output lines. The averaging window length corresponds to the scaling ratio, resulting in an adaptive vertical low-pass effect, to greatly reduce aliasing artefacts. ACM can be applied for downscales only from ratio 1 down to 1⁄64. ACM results in a scale dependent DC gain amplification, which has to be precorrected by the BCS control of the scaler part. As shown in Section 9.3.1.3, the scaler processing may run randomly over the interlaced input sequence. Additionally the interpretation and timing between ITU 656 field ID and real-time detection by means of the state of H sync at the falling edge of V sync may result in different field ID interpretation. A vertically scaled interlaced output also gets a larger vertical sampling phase error, if the interlaced input fields are processed, without regard to the actual scale at the starting point of operation (see Fig.37). The phase and scale controlling DTO calculates in 16-bit resolution, controlled by parameters YSCY[15:0] B1H[7:0] B0H[7:0] and YSCC[15:0] B3H[7:0] B2H[7:0], continuously over the entire filed. A start offset can be applied to the phase processing by means of the parameters YPY3[7:0] to YPY0[7:0] in BFH[7:0] to BCH[7:0] and YPC3[7:0] to YPC0[7:0] in BBH[7:0] to B8H[7:0]. The start phase covers the range of 255⁄32 to 1⁄32 lines offset. The four events to be considered are illustrated in Fig.38. In Tables 26 and 27 PHO is a usable common phase offset. It should be noted that the equations in Fig.38 also produce an interpolated output for the unscaled case, as the geometrical reference position for all conversions is the position of the first line of the lower field; see Table 26. By programming appropriate, opposite, vertical start phase values (subaddresses B8H to BFH and E8H to EFH) depending on odd/even field ID of the source video stream and A/B page cycle, frame ID conversion and field rate conversion are supported (i.e. de-interlacing, re-interlacing). If there is no need for UP-LO and LO-UP conversion and the input field ID is the reference for the back-end operation, then it is UP-LO = UP-UP and LO-UP = LO-LO and the 1⁄2 line phase shift (PHO + 16) that can be skipped; this case is given in Table 27. The SAA7108AE; SAA7109AE supports 4 phase offset registers per task and component (luminance and chrominance). The value of 20H represents a phase shift of one line. Figs 37 and 38 and Tables 26 and 27 describe the use of the offsets. Remark: The vertical start phase, as well as the scaling ratio are defined independently for luminance and chrominance channels, but must be set to the same values in the actual implementation for accurate 4 : 2 : 2 output processing. The registers are assigned to the following events; e.g. subaddresses B8H to BBH: • B8H: 00 = input field ID 0, task status bit 0 (toggle status, see Section 9.3.1.3) The vertical processing communicates on its input side with the line FIFO buffer. The scale related equations are: • B9H: 01 = input field ID 0, task status bit 1 • BAH: 10 = input field ID 1, task status bit 0 • Scaling increment calculation for ACM and LPI mode, downscale and zoom: YSCY[15:0] and YSCC[15:0] • BBH: 11 = input field ID 1, task status bit 1. Nline_in = lower integer of 1024 × ------------------------- Nline_out 2004 Jun 29 Use of the vertical phase offsets 67 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Depending on the input signal (interlaced or non-interlaced) and the task processing (50 Hz or field reduced processing with one or two tasks, see examples in Section 9.3.1.3), other combinations may also be possible, but the basic equations are the same. scaled output, no phase offset unscaled input field 1 field 2 field 1 scaled output, with phase offset field 2 field 1 field 2 correct scale dependent position scale dependent start offset mismatched vertical line distances MHB547 Fig.37 Basic problem of interlaced vertical scaling (example: downscale 3⁄5). 2004 Jun 29 68 Philips Semiconductors Product specification HD-CODEC handbook, full pagewidth SAA7108AE; SAA7109AE field 1 field 2 field 1 field 2 field 1 field 2 upper lower case UP-UP case LO-LO case UP-LO case LO-UP B A C D MHB548 1024 Offset = ------------- = 32 = 1 line shift 32 1 YSCY[15:0] C = --- scale increment = ------------------------------2 64 1 A = --- input line shift = 16 2 D = no offset = 0 1 1 YSCY[15:0] B = --- input line shift + --- scale increment = ------------------------------- + 16 2 2 64 Fig.38 Derivation of the phase related equations (example: interlace vertical scaling down to 3⁄5, with field conversion). Table 26 Examples for vertical phase offset usage: global equations INPUT FIELD UNDER PROCESSING OUTPUT FIELD INTERPRETED AS Upper input lines upper output lines UP-UP PHO + 16 Upper input lines lower output lines UP-LO YSCY[15:0] PHO + ------------------------------- + 16 64 Lower input lines upper output lines LO-UP PHO Lower input lines lower output lines LO-LO YSCY[15:0] PHO + ------------------------------64 2004 Jun 29 USED ABBREVIATION 69 EQUATION FOR PHASE OFFSET CALCULATION (DECIMAL VALUES) Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 27 Vertical phase offset usage; assignment of the phase offsets DETECTED INPUT FIELD ID 0 = upper lines TASK STATUS BIT 0 VERTICAL PHASE OFFSET YPY0[7:0] and YPC0[7:0] CASE EQUATION TO BE USED case 1(1) UP-UP (PHO) case 2(2) UP-UP case 3(3) UP-LO 0 = upper lines 1 = lower lines 1 = lower lines 1 0 1 YPY1[7:0] and YPC1[7:0] YPY2[7:0] and YPC2[7:0] YPY3[7:0] and YPC3[7:0] case 1 UP-UP (PHO) case 2 UP-LO case 3 UP-UP case 1 YSCY[15:0] LO-LO PHO + ------------------------------- – 16 64 case 2 LO-UP case 3 LO-LO case 1 YSCY[15:0] LO-LO PHO + ------------------------------- – 16 64 case 2 LO-LO case 3 LO-UP Notes 1. Case 1: OFIDC[90H[6]] = 0; scaler input field ID as output ID; back-end interprets output field ID at logic 0 as upper output lines. 2. Case 2: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 0 as upper output lines. 3. Case 3: OFIDC[90H[6]] = 1; task status bit as output ID; back-end interprets output field ID at logic 1 as upper output lines. 9.4 VBI data decoder and capture (subaddresses 40H to 7FH) For lines 2 to 24 of a field, per VBI line, 1 of 16 standards can be selected (LCRxxx[41:57[7:0]]: 23 × 2 × 4-bit programming bits). The definition for line 24 is valid for the rest of the corresponding field, normally no text data (video data) should be selected there (LCR24 = FFH) to stop the activity of the VBI data slicer during active video. The SAA7108AE; SAA7109AE contains a versatile VBI data decoder. The implementation and programming model accords to the VBI data slicer the built-in multimedia video data acquisition circuit of the SAA5284. To adjust the slicers processing to the input signal source, there are offsets in the horizontal and vertical direction available (parameters HOFF[5B,59[2:0,7:0]], VOFF[5B,5A[4,7:0]] and FOFF[5B[7]]). The circuitry recovers the actual clock phase during the clock run-in period, slices the data bits with the selected data rate, and groups them into bytes. The result is buffered into a dedicated VBI data FIFO with a capacity of 2 × 56 bytes (2 × 14 Dwords). The clock frequency, signal source, field frequency and accepted error count must be defined in subaddress 40H. In difference to the scalers counting, the slicers offsets define the position of the horizontal and vertical trigger events related to the processed video field. The trigger events are the falling edge of HREF and the falling edge of V123 from the decoder processing part. The VBI data standards that are supported are given in Table 28. 2004 Jun 29 The relationship of these programming values to the input signal and the recommended values can be seen in Tables 18 to 21. 70 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 28 Data types supported by the data slicer block DATA TYPE NUMBER DATA RATE (Mbits/s) STANDARD TYPE FRAMING CODE FC WINDOW 0000 teletext EuroWST, CCST 6.9375 27H WST625 0001 European Closed Caption 0.500 001 CC625 0010 VPS 5 9951H VPS 0011 wide screen signalling bits 5 1E3C1FH WSS 0100 US teletext (WST) 5.7272 27H WST525 0101 US Closed Caption (line 21) 0.503 001 CC525 0110 (video data selected) 5 none disable 0111 (raw data selected) 5 none disable 1000 teletext 6.9375 programmable general text 1001 VITC/EBU time codes (Europe) 1.8125 programmable VITC625 1010 VITC/SMPTE time codes (USA) 1.7898 programmable VITC525 1011 5 programmable open 1100 US NABTS 5.7272 programmable NABTS 1101 MOJI (Japanese) 5.7272 programmable (A7H) Japtext 1110 Japanese format switch (L20/22) 5 programmable open 1111 no sliced data transmitted (video data selected) none disable 9.5 5 Image port output formatter (subaddresses 84H to 87H) HAM CHECK always always optional optional The disconnected data stream at the scaler output is accompanied by a data valid flag (or data qualifier), or is transported via a gated clock. Clock cycles with invalid data on the I port data bus (including the HPD pins in 16-bit output mode) are marked with code 00H. The output interface consists of a FIFO for video and for sliced text data, an arbitration circuit, which controls the mixed transfer of video and sliced text data over the I port, and a decoding and multiplexing unit, which generates the 8 or 16-bit wide output data stream together with the accompanying reference and help information. The output interface also arbitrates the transfer between scaled video data and sliced text data over the I port output. The clock for the output interface can be derived from an internal clock, decoder, expansion port or an externally provided clock which is appropriate, for example, for the VGA and frame buffer. The clock can be up to 33 MHz. The scaler provides the following video related timing reference events (signals), which are available on pins as defined by subaddresses 84H and 85H: The bits VITX1 and VITX0 (subaddress 86H) are used to control the arbitration. • Output field ID For handshaking with the VGA controller, or other memory or bus interface circuitry, programmable FIFO flags are provided; see Section 9.5.2. The serialization of the internal 32-bit Dwords to 8-bit or 16-bit output (optional), as well as the insertion of the extended ITU 656 codes (SAV/EAV for video data, ANC or SAV/EAV codes for sliced text data) are also done here. • Start and end of vertical active video range • Start and end of active video line • Data qualifier or gated clock • Actually activated programming page (if CONLH is used) • Threshold controlled FIFO filling flags (empty, full, filled) • Sliced data marker. 2004 Jun 29 71 Philips Semiconductors Product specification HD-CODEC 9.5.1 SAA7108AE; SAA7109AE SCALER OUTPUT FORMATTER (SUBADDRESSES 93H AND C3H) FSI[2:0] defines the horizontal packing of the data, FOI[1:0] defines how many Y only lines are expected before a Y/C line will be formatted. If FYSK is set to logic 0 preceding Y only lines will be skipped, and the output will always start with a Y/C line. The output formatter organizes the packing into the output FIFO. The following formats are available: Y-CB-CR 4 : 2 : 2, Y-CB-CR 4 : 1 : 1, Y-CB-CR 4 : 2 : 0, Y-CB-CR 4 : 1 : 0, Y only (e.g. for raw samples). The formatting is controlled by FSI[2:0] 93H[2:0], FOI[1:0] 93H[4:3] and FYSK[93H[5]]. Additionally the output formatter limits the amplitude range of the video data (controlled by ILLV[85H[5]]); see Table 31. The data formats are defined on Dwords, or multiples thereof, and are similar to the video formats as recommended for PCI multimedia applications (see SAA7146A). Planar formats are not supported. Table 29 Byte stream for different output formats OUTPUT FORMAT BYTE SEQUENCE FOR 8-BIT OUTPUT MODES Y-CB-CR 4 : 2 : 2 CB0 Y0 CR0 Y1 CB2 Y2 CR2 Y3 CB4 Y4 CR4 Y5 CB6 Y6 Y-CB-CR 4 : 1 : 1 CB0 Y0 CR0 Y1 CB4 Y2 CR4 Y3 Y4 Y5 Y6 Y7 CB8 Y8 Y only Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Table 30 Explanation to Table 29 NAME EXPLANATION CB (B − Y) colour difference component, pixel number n = 0, 2, 4 to 718 CBn Yn Y (luminance) component, pixel number n = 0, 1, 2, 3 to 719 CRn CR (R − Y) colour difference component, pixel number n = 0, 2, 4 to 718 Table 31 Limiting range on I port VALID RANGE SUPPRESSED CODES (HEXADECIMAL VALUE) LIMIT STEP ILLV[85H[5]] DECIMAL VALUE HEXADECIMAL VALUE LOWER RANGE UPPER RANGE 0 1 to 254 01 to FE 00 FF 1 8 to 247 08 to F7 00 to 07 F8 to FF 2004 Jun 29 72 Philips Semiconductors Product specification HD-CODEC 9.5.2 SAA7108AE; SAA7109AE The decoded VBI data is collected in the dedicated VBI data FIFO. Once the capture of a line is completed, the FIFO can be streamed through the image port, preceded by a header, giving the line number and standard. VIDEO FIFO (SUBADDRESS 86H) The video FIFO at the scaler output contains 32 Dwords. That corresponds to 64 pixels in 16-bit Y-CB-CR 4 : 2 : 2 format. But as the entire scaler can act as a pipeline buffer, the actually available buffer capacity for the image port is much higher, and can exceed beyond a video line. The VBI data period can be signalled via the sliced data flag on pin IGP0 or IGP1. The decoded VBI data is lead by the ITU ancillary data header (DID[5:0] 5DH[5:0] at value <3EH) or by SAV/EAV codes selected by DID[5:0] at value 3EH or 3FH. IGP0 or IGP1 is set if the first byte of the ANC header is valid on the I port bus; it is reset if an SAV occurs. Therefore it may frame multiple lines of text data output, in case the video processing starts with a distance of several video lines to the region of text data. Valid sliced data from the text FIFO is available on the I port as long as the IGP0 or IGP1 flag is set and the data qualifier is active on pin IDQ. The image port and the video FIFO, can operate with the video source clock (synchronous mode) or with an externally provided clock (asynchronous, and burst mode), as appropriate for the VGA controller or attached frame buffer. The video FIFO provides 4 internal flags, which report to what extent the FIFO is actually filled. These are: • The FIFO Almost Empty (FAE) flag • The FIFO Combined (FC) flag or FIFO filled, which is set at almost full level and reset, with hysteresis, only after the level crosses below the almost empty mark The decoded VBI data is presented in two different data formats, controlled by bit RECODE. • The FIFO Almost Full (FAF) flag RECODE = 1: values 00H and FFH will be recoded to even parity values 03H and FCH • The FIFO Overflow (FOVL) flag. RECODE = 0: values 00H and FFH may occur in the data stream as detected. The trigger levels for FAE and FAF are programmable by FFL[1:0] 86H[3:2] (16, 24, 28, full) and FEL[1:0] 86H[1:0] (16, 8, 4, empty). 9.5.4 The state of this flag can be seen on pins IGP0 or IGP1. The pin mapping is defined by subaddresses 84H and 85H; see Section 10.5. 9.5.3 Sliced text data and scaled video data are transferred over the same bus, the I port. The mixed transfer is controlled by an arbitration circuit. If the video data is transferred without any interrupt and the video FIFO does not need to buffer any output pixel, the text data is inserted after the end of a scaled video line, normally during the video blanking interval. TEXT FIFO The data of the terminal VBI data slicer is collected in the text FIFO before transmission over the I port is requested (normally before the video window starts) and partitioned into two FIFO sections. A complete line is fed into the FIFO before a data transfer is requested. So normally, one line of text data is ready for transfer while the next text line is collected. Thus sliced text data is delivered as a block of qualified data, without any qualification gaps in the byte stream of the I port. 2004 Jun 29 VIDEO AND TEXT ARBITRATION (SUBADDRESS 86H) 73 Philips Semiconductors Product specification HD-CODEC 9.5.5 SAA7108AE; SAA7109AE DATA STREAM CODING AND REFERENCE SIGNAL GENERATION (SUBADDRESSES 84H, 85H AND 93H) If ITU 656 like codes are not required, they can be suppressed in the output stream. As horizontal and vertical reference signals are logic 1, active gate signals are generated, which frame the transfer of the valid output data. Alternatively, the horizontal and vertical trigger pulses can be generated on the rising edges of the gates. As a further option, it is possible to provide the scaler with an external gating signal on pin ITRDY. It is therefore possible to hold the data output for a certain time and to get valid output data in bursts of a guaranteed length. The sketched reference signals and events can be mapped to the I port output pins IDQ, IGPH, IGPV, IGP0 and IGP1. The polarities of all the outputs can be modified to enable flexible use. The default polarity for the qualifier and reference signals is logic 1 (active). Due to the dynamic FIFO behaviour of the complete scaler path, the output signal timing has no fixed timing relationship to the real-time input video stream. Thus fixed propagation delays, in terms of clock cycles, related to the analog input can not be defined. Table 32 shows the relevant and supported SAV and EAV coding. The data stream is accompanied by a data qualifier. Additionally invalid data cycles are marked with code 00H. Table 32 SAV/EAV codes on the I port SAV/EAV CODES ON I PORT(1) (HEX) EVENT DESCRIPTION MSB(2) OF SAV/EAV BYTE = 0 MSB(2) OF SAV/EAV BYTE = 1 COMMENT FIELD ID = 0 FIELD ID = 1 FIELD ID = 0 FIELD ID = 1 Next pixel is FIRST pixel of any active line 0E 49 80 C7 HREF = active; VREF = active Previous pixel was LAST pixel of any active line, but not the last 13 54 9D DA HREF = inactive; VREF = active Next pixel is FIRST pixel of any V-blanking line 25 62 AB EC HREF = active; VREF = inactive Previous pixel was LAST pixel of the last active line or of any V-blanking line 38 7F B6 F1 HREF = inactive; VREF = inactive No valid data, do not capture and do not increment pointer 00 IDQ pin inactive Notes 1. The leading byte sequence is: FFH-00H-00H. 2. The MSB of the SAV/EAV code byte is controlled by: a) Scaler output data: task A ⇒ MSB = CONLH[90H[7]]; task B ⇒ MSB = CONLH[C0H[7]]. b) VBI data slicer output data: DID[5:0] 5DH[5:0] = 3EH ⇒ MSB = 1; DID[5:0] 5DH[5:0] = 3FH ⇒ MSB = 0. 2004 Jun 29 74 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... ... FF FF 00 00 00 00 00 00 internal header SAV SDID DC IDI1 sliced data IDI2 D1_3 D1_4 D2_1 and filling data ... DDC_3 DDC_4 CS D1_1 D1_2 EAV ANC header 00 FF internal header FF DID SDID DC IDI1 invalid data FF 00 00 00 EAV ANC data output is only filled up to the Dword boundary sliced data IDI2 D1_3 D1_4 ... DDC_3 DDC_4 CS BC timing reference code BC 00 00 00 ... MHB549 ... Philips Semiconductors timing reference code HD-CODEC 2004 Jun 29 ... invalid data or end of raw VBI line ANC header active for DID (subaddress 5DH) <3EH Fig.39 Sliced data formats on the I port in 8-bit mode. Table 33 Explanation to Fig.39 NAME EXPLANATION 75 SAV start of active data; see Table 34 SDID sliced data identification: NEP(1), EP(2), SDID5 to SDID0, freely programmable via I2C-bus subaddress 5EH, bits 5 to 0, e. g. to be used as source identifier DC Dword count: NEP(1), EP(2), DC5 to DC0. DC describes the number of succeeding 32-bit words: • For SAV/EAV mode DC is fixed to 11 Dwords (byte value 4BH) • For ANC mode it is: DC = 1⁄4(C + n), where C = 2 (the two data identification bytes IDI1 and IDI2) and n = number of decoded bytes according to the chosen text standard. Note that the number of valid bytes inside the stream can be seen in the BC byte. internal data identification 1: OP(3), FID (field 1 = 0, field 2 = 1), LineNumber8 to LineNumber3 = Dword 1 byte 1; see Table 34 IDI2 internal data identification 2: OP(3), LineNumber2 to LineNumber0, DataType3 to DataType0 = Dword 1 byte 2; see Table 34 Dword number n, byte number m last Dword byte 4, note: for SAV/EAV framing DC is fixed to 0BH, missing data bytes are filled up; the fill value is A0H CS the check sum byte, the check sum is accumulated from the SAV (respectively DID) byte to the DDC_4 byte BC number of valid sliced bytes counted from the IDI1 byte EAV end of active data; see Table 34 Notes 1. Inverted EP (bit 7); for EP see note 2. 2. Even parity (bit 6) of bits 5 to 0. 3. Odd parity (bit 7) of bits 6 to 0. Product specification Dn_m DDC_4 SAA7108AE; SAA7109AE IDI1 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 34 Bytes stream of the data slicer NICK NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 NEP(1) EP(2) 0 1 0 FID(3) I1(4) I0(4) subaddress 5DH; bit 5 = 1 NEP EP 0 subaddress 5DH bit 5 = 3EH; note 5 1 FID(3) V(6) H(7) P3 P2 P1 P0 subaddress 5DH bit 5 = 3FH; note 5 0 FID(3) V(6) H(7) P3 P2 P1 P0 programmable via subaddress 5EH NEP EP DC(8) NEP EP(2) DC5 DC4 DC3 DC2 DC1 DC0 IDI1 OP(9) FID(3) LN8(10) LN7(10) LN6(10) LN5(10) LN4(10) LN3(10) IDI2 OP LN2(10) LN1(10) LN0(10) DT3(11) DT2(11) DT1(11) DT0(11) DID, SAV, EAV SDID COMMENT subaddress 5DH = 00H D4[5DH] D3[5DH] D2[5DH] D1[5DH] D0[5DH] D5[5EH] D4[5EH] D3[5EH] D2[5EH] D1[5EH] D0[5EH] CS check sum byte CS6 CS6 CS5 CS4 CS3 CS2 CS1 CS0 BC valid byte count OP 0 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 Notes 1. NEP = inverted EP (see note 2). 2. EP = Even Parity of bits 5 to 0. 3. FID = 0: field 1; FID = 1: field 2. 4. I1 = 0 and I0 = 0: before line 1; I1 = 0 and I0 = 1: lines 1 to 23; I1 = 1 and I0 = 0: after line 23; I1 = 1 and I0 = 1: line 24 to end of field. 5. Subaddress 5DH at 3EH and 3FH are used for ITU 656 like SAV/EAV header generation; recommended value. 6. V = 0: active video; V = 1: blanking. 7. H = 0: start of line; H = 1: end of line. 8. DC = Data Count in Dwords according to the data type. 9. OP = Odd Parity of bits 6 to 0. 10. LN = Line Number. 11. DT = Data Type according to table. 2004 Jun 29 76 Philips Semiconductors Product specification HD-CODEC 9.6 SAA7108AE; SAA7109AE • Audio master Clocks Per Field, ACPF[17:0] 32H[1:0] 31H[7:0] 30H[7:0] according to the equation: Audio clock generation (subaddresses 30H to 3FH) audio frequency ACPF[17:0] = round ------------------------------------------ field frequency The SAA7108AE; SAA7109AE incorporates the generation of a field-locked audio clock, as an auxiliary function for video capture. An audio sample clock, that is locked to the field frequency, ensures that there is always the same predefined number of audio samples associated with a field, or a set of fields. This ensures synchronous playback of audio and video after digital recording (e.g. capture to hard disk), MPEG or other compression or non-linear editing. 9.6.1 • Audio master Clocks Nominal Increment, ACNI[21:0] 36H[5:0] 35H[7:0] 34H[7:0] according to the equation: audio frequency 23 ACNI[21:0] = round --------------------------------------------- × 2 crystal frequency See Table 35 for examples. Remark: For standard applications the synthesized audio clock AMCLK can be used directly as master clock and as input clock for port AMXCLK (short cut) to generate ASCLK and ALRCLK. For high-end applications it is recommended to use an external analog PLL circuit to enhance the performance of the generated audio clock. MASTER AUDIO CLOCK The audio clock is synthesized from the same crystal frequency as the line-locked video clock is generated. The master audio clock is defined by the parameters: Table 35 Programming examples for audio master clock generation CRYSTAL FREQUENCY (MHz) FIELD (Hz) ACPF DECIMAL ACNI HEX DECIMAL HEX AMCLK = 256 × 48 kHz (12.288 MHz) 32.11 24.576 50 245760 3C000 3210190 30FBCE 59.94 205005 320CD 3210190 30FBCE 50 − − − − 59.94 − − − − AMCLK = 256 × 44.1 kHz (11.2896 MHz) 32.11 24.576 50 225792 37200 2949362 2D00F2 59.94 188348 2DFBC 2949362 2D00F2 50 225792 37200 3853517 3ACCCD 59.94 188348 2DFBC 3853 517 3ACCCD 163840 28000 2140127 20A7DF 59.94 136670 215DE 2140127 20A7DF 50 163840 28000 2796203 2AAAAB 59.94 136670 215DE 2796203 2AAAAB AMCLK = 256 × 32 kHz (8.192 MHz) 32.11 24.576 2004 Jun 29 50 77 Philips Semiconductors Product specification HD-CODEC 9.6.2 SAA7108AE; SAA7109AE SIGNALS ASCLK AND ALRCLK Two binary divided signals ASCLK and ALRCLK are provided for slower serial digital audio signal transmission and for channel-select. The frequencies of these signals are defined by the parameters: f AMXCLK f AMXCLK • SDIV[5:0] 38H[5:0] according to the equation: f ASCLK = ------------------------------------- ⇒ SDIV[5:0] = -------------------- – 1 ( SDIV + 1 ) × 2 2f ASCLK f ASCLK f ASCLK • LRDIV[5:0] 39H[5:0] according to the equation: f ALRCLK = -------------------------- ⇒ LRDIV[5:0] = ----------------------LRDIV × 2 2f ALRCLK See Table 36 for examples. Table 36 Programming examples for ASCLK/ALRCLK clock generation AMXCLK (MHz) 12.288 11.2896 8.192 9.6.3 SDIV ASCLK (kHz) DECIMAL HEX 1536 3 03 768 7 07 1411.2 3 03 2822.4 1 01 1024 3 03 2048 1 01 ALRCLK (kHz) LRDIV DECIMAL HEX 16 10 48 44.1 32 8 08 16 10 32 10 16 10 32 10 OTHER CONTROL SIGNALS Further control signals are available to define reference clock edges and vertical references; see Table 37. Table 37 Control signals CONTROL SIGNAL APLL[3AH[3]] DESCRIPTION Audio PLL mode: 0: PLL closed 1: PLL open AMVR[3AH[2]] Audio Master clock Vertical Reference: 0: internal vertical reference 1: external vertical reference LRPH[3AH[1]] ALRCLK Phase: 0: invert ASCLK, ALRCLK edges triggered by falling edge of ASCLK 1: do not invert ASCLK, ALRCLK edges triggered by rising edge of ASCLK SCPH[3AH[0]] ASCLK Phase: 0: invert AMXCLK, ASCLK edges triggered by falling edge of AMXCLK 1: do not invert AMXCLK, ASCLK edges triggered by rising edge of AMXCLK 2004 Jun 29 78 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE 10 INPUT/OUTPUT INTERFACES AND PORTS OF DIGITAL VIDEO DECODER PART 10.1 Analog terminals The SAA7108AE; SAA7109AE has 6 analog inputs AI21 to AI24, AI11 and AI12 (see Table 38) for composite video CVBS or S-video Y/C signal pairs. Additionally, there are two differential reference inputs, which must be connected to ground via a capacitor equivalent to the decoupling capacitors at the 6 inputs. There are no peripheral components required other than the decoupling capacitors and 18 Ω/56 Ω termination resistors, one set per connected input signal (see also application example in Fig.53). Two anti-alias filters are integrated, and self adjusting via the clock frequency. The SAA7108AE; SAA7109AE has 5 different I/O interfaces. These are: • Analog video input interface, for analog CVBS and/or Y and C input signals • Audio clock port • Digital real-time signal port (RT port) • Digital video expansion port (X port), for unscaled digital video input and output • Digital image port (I port) for scaled video data output and programming Clamp and gain control for the two ADCs are also integrated. An analog video output pin (AOUT) is provided for testing purposes. • Digital host port (H port) for extension of the image port or expansion port from 8 to 16-bit. Table 38 Analog pin description SYMBOL PIN AI24 to AI21 P6, P7, P9 and P10 AI12 and AI11 P11 and P13 AOUT M10 AI1D and AI2D P12 and P8 10.2 I/O DESCRIPTION BIT I analog video signal inputs, e.g. 2 CVBS signals and two Y/C pairs can be connected simultaneously MODE3 to MODE0 O analog video output, for test purposes AOSL1 and AOSL0 I analog reference pins for differential ADC operation − Audio clock signals The SAA7108AE; SAA7109AE also synchronizes the audio clock and sampling rate to the video frame rate, via a very slow PLL. This ensures that the multimedia capture and compression processes always gather the same predefined number of samples per video frame. An audio master clock AMCLK and two divided clocks, ASCLK and ALRCLK, are generated; see Table 39. • ASCLK: can be used as audio serial clock • ALRCLK: audio left/right channel clock. The ratios are programmable; see Section 9.6. Table 39 Audio clock pin description SYMBOL PIN I/O DESCRIPTION BIT AMCLK K12 O audio master clock output ACPF[17:0] 32H[1:0] 31H[7:0] 30H[7:0] and ACNI[21:0] 36H[5:0] 35H[7:0] 34H[7:0] AMXCLK J12 I external audio master clock input for the clock division circuit, can be directly connected to output AMCLK for standard applications − ASCLK K14 O serial audio clock output, can be synchronized to rising or falling edge of AMXCLK SDIV[5:0] 38H[5:0] and SCPH[3AH[0]] ALRCLK J13 O audio channel (left/right) clock output, can be synchronized to rising or falling edge of ASCLK LRDIV[5:0] 39H[5:0] and LRPH[3AH[1]] 2004 Jun 29 79 Philips Semiconductors Product specification HD-CODEC 10.3 SAA7108AE; SAA7109AE Clock and real-time synchronization signals The Line-Locked Clock (LLC) is the double pixel clock at a nominal 27 MHz. It is locked to the selected video input, generating baseband video pixels according to “ITU recommendation 601”. In order to support interfacing circuits, a direct pixel clock LLC2 is also provided. A crystal accurate frequency reference is required for the generation of the line-locked video (pixel) clock LLC, and the frame-locked audio serial bit clock. An oscillator is built-in, for fundamental or 3rd-harmonic crystals. The supported crystal frequencies are 32.11 or 24.576 MHz (defined during reset by strapping pin ALRCLK). The pins for line and field timing reference signals are RTCO, RTS1 and RTS0. Various real-time status information can be selected for the RTS pins. The signals are always available (output) and reflect the synchronization operation of the decoder part in the SAA7108AE; SAA7109AE. The function of the RTS1 and RTS0 pins can be defined by bits RTSE1[3:0] 12H[7:4] and RTSE0[3:0] 12H[3:0]; see Table 40. Alternatively pins XTALId and XTALIe can be driven from an external single-ended oscillator. The crystal oscillation can be propagated as clock to other ICs in the system via pin XTOUTd. Table 40 Clock and real-time synchronization signals SYMBOL PIN I/O DESCRIPTION BIT Crystal oscillator XTALId P2 I input for crystal oscillator, or reference clock − XTALOd P3 O output of crystal oscillator − XTOUTd P4 O reference (crystal) clock output drive (optional) XTOUTE[14H[3]] Real-time signals (RT port) LLC M14 O line-locked clock; nominal 27 MHz, double pixel clock locked to the selected video input signal − LLC2 L14 O line-locked pixel clock; nominal 13.5 MHz − RTCO L13 O real-time control output; transfers real-time status information supporting RTC level 3.1 (see external document “RTC Functional Description”, available on request) − RTS0 K13 O real-time status information line 0; can be programmed to carry various real-time informations; see Table 171 RTSE0[3:0] 12H[3:0] RTS1 L10 O real-time status information line 1; can be programmed to carry various real-time informations; see Table 172 RTSE1[3:0] 12H[7:4] 2004 Jun 29 80 Philips Semiconductors Product specification HD-CODEC 10.4 SAA7108AE; SAA7109AE Video expansion port (X port) As output, these are direct copies of the decoder signals. The data transfers through the expansion port represent a single D1 port, with half duplex mode. The SAV and EAV codes may be inserted optionally for data input (controlled by bit XCODE[92H[3]]). The input/output direction is switched for complete fields only. The expansion port is intended for transporting video streams of image data from other digital video circuits such as MPEG encoder/decoder and video phone codec, to the image port (I port); see Table 41. The expansion port consists of two groups of signals/pins: • 8-bit data, I/O, regular video components Y-CB-CR 4 : 2 : 2, i.e. CB-Y-CR-Y, byte serial, exceptionally raw video samples (e.g. ADC test). In input mode the data bus can be extended to 16-bit by pins HPD7 to HPD0. • Clock, synchronization and auxiliary signals, accompanying the data stream, I/O. Table 41 Signals dedicated to the expansion port SYMBOL PIN I/O DESCRIPTION BIT K2, K3, L1 to L3, M1, M2 and N1 I/O X port data: in output mode controlled by decoder section, for data format see Table 42; in input mode Y-CB-CR 4 : 2 : 2 serial input data or luminance part of a 16-bit Y-CB-CR 4 : 2 : 2 input OFTS[2:0] 13H[2:0], 91H[7:0] and C1H[7:0] XCLK M3 I/O clock at expansion port: if output, then copy of LLC; as input normally a double pixel clock of up to 32 MHz or a gated clock (clock gated with a qualifier) XCKS[92H[0]] XDQ M4 I/O data valid flag of the expansion port input (qualifier): if output, then decoder (HREF and VGATE) gate (see Fig.32) − XRDY N3 O data request flag = ready to receive, to work with optional buffer in external device, to prevent internal buffer overflow; second function: input related task flag A/B XRQT[83H[2]] XRH N2 I/O horizontal reference signal for the X port: as output: HREF or HS from the decoder (see Fig.32); as input: a reference edge for horizontal input timing and a polarity for input field ID detection can be defined XRHS[13H[6]], XFDH[92H[6]] and XDH[92H[2]] XRV L5 I/O vertical reference signal for the X port: as output: V123 or field ID from the decoder, see Figs 30 and 31; as input: a reference edge for vertical input timing and for input field ID detection can be defined XRVS[1:0] 13H[5:4], XFDV[92H[7]] and XDV[1:0] 92H[5:4] XTRI K1 I port control: switches X port input to 3-state XPE[1:0] 83H[1:0] XPD7 to XPD0 2004 Jun 29 81 Philips Semiconductors Product specification HD-CODEC 10.4.1 SAA7108AE; SAA7109AE • Raw samples (data types 0 to 5 and 7 to 14): CB-CR samples are similar to data type 6, but CVBS samples are transferred instead of processed luminance samples within the Y time slots. X PORT CONFIGURED AS OUTPUT If the data output is enabled at the expansion port, then the data stream from the decoder is present. The data format of the 8-bit data bus is dependent on the chosen data type which is selectable by the line control registers LCR2 to LCR24; see Table 17. In contrast to the image port, the sliced data format is not available on the expansion port. Instead, raw CVBS samples are always transferred if any sliced data type is selected. The amplitude and offset of the CVBS signal is programmable via RAWG7 to RAWG0 and RAWO7 to RAWO0, see Chapter 18, Tables 178 and 179. For nominal levels see Fig.27. The relationship of LCR programming to line numbers is described in Section 9.2; see Tables 18 to 21. Details of some of the data types on the expansion port are as follows: The data type selections by LCR are overruled by setting OFTS2 = 1 (subaddress 13H bit 2). This setting is mainly intended for device production testing. The VPO-bus carries the upper or lower 8 bits of the two ADCs depending on the OFTS[1:0] 13H[1:0] settings; see Table 173. The output configuration is done via MODE[3:0] 02H[3:0] settings; see Table 155. If a Y/C mode is selected, the expansion port carries the multiplexed output signals of both ADCs, in CVBS mode the output of only one ADC. No timing reference codes are generated in this mode. • Active video: (data type 15) contains components Y-CB-CR 4 : 2 : 2 signal, 720 active pixels per line. The amplitude and offsets are programmable via DBRI7 to DBRI0, DCON7 to DCON0, DSAT7 to DSAT0, OFFU1, OFFU0, OFFV1 and OFFV0. For nominal levels see Fig.26. • Test line: (data type 6) is similar to the active video format, with some constraints within the data processing: – adaptive chrominance comb filter, vertical filter (chrominance comb filter for NTSC standards, PAL phase error correction) within the chrominance processing are disabled Remark: The LSBs (bit 0) of the ADCs are also available on pin RTS0; see Table 171. The SAV/EAV timing reference codes define the start and end of valid data regions. The ITU-blanking code sequence ‘- 80 - 10 - 80 - 10 -...’ is transmitted during the horizontal blanking period, between EAV and SAV. – adaptive luminance comb filter, peaking and chrominance trap are bypassed within the luminance processing. This data type is defined for future enhancements. It can be activated for lines containing standard test signals within the vertical blanking period. Currently most sources do not contain test lines. For nominal levels see Fig.26. The position of the F bit is constant according to ITU 656; see Tables 44 and 45. The V bit can be generated in two different ways (see Tables 44 and 45) controlled via OFTS1 and OFTS0; see Table 173. F and V bits change synchronously with the EAV code. Table 42 Data format on the expansion port BLANKING PERIOD ... 80 10 TIMING REFERENCE CODE (HEX)(1) 720 PIXELS Y-CB-CR 4 : 2 : 2 DATA(2) TIMING REFERENCE CODE (HEX)(1) BLANKING PERIOD FF 00 00 SAV CB0 Y0 CR0 Y1 CB2 Y2 ... CR718 Y719 FF 00 00 EAV 80 10 ... Notes 1. The generation of the timing reference codes can be suppressed by setting OFTS[2:0] to ‘010’; see Table 173. In this event the code sequence is replaced by the standard ‘- 80 - 10 -’ blanking values. 2. If raw samples or sliced data are selected by the line control registers (LCR2 to LCR24), the Y samples are replaced by CVBS samples. 2004 Jun 29 82 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 43 SAV/EAV format on expansion port XPD7 to XPD0 BIT 6 (F) BIT 7 1 BIT 5 (V) field bit BIT 4 (H) vertical blanking bit BIT 3 BIT 2 BIT 1 BIT 0 (P3) (P2) (P1) (P0) format 1st field: F = 0 VBI: V = 1 H = 0 in SAV format 2nd field: F = 1 active video: V = 0 H = 1 in EAV format reserved; evaluation not recommended (protection bits according to ITU 656) for vertical timing see Tables 44 and 45 Table 44 525 lines/60 Hz vertical timing V LINE NUMBER 1 to 3 F (ITU 656) 1 OFTS[2:0] = 000 (ITU 656) OFTS[2:0] = 001 1 according to selected VGATE position type via VSTA and VSTO (subaddresses 15H to 17H); see Tables 175 to 177 4 to 19 0 1 20 0 0 21 0 0 22 to 261 0 0 262 0 0 263 0 0 264 and 265 0 1 266 to 282 1 1 283 1 0 284 1 0 285 to 524 1 0 525 1 0 Table 45 625 lines/50 Hz vertical timing V LINE NUMBER F (ITU 656) OFTS[2:0] = 000 (ITU 656) OFTS[1:0] = 10 according to selected VGATE position type via VSTA and VSTO (subaddresses 15H to 17H); see Tables 175 to 177 1 to 22 0 1 23 0 0 24 to 309 0 0 310 0 0 311 and 312 0 1 313 to 335 1 1 336 1 0 337 to 622 1 0 623 1 0 624 and 625 1 1 2004 Jun 29 83 Philips Semiconductors Product specification HD-CODEC 10.4.2 SAA7108AE; SAA7109AE X PORT CONFIGURED AS INPUT The data formats at the image port are defined in Dwords of 32 bits (4 bytes), such as the related FIFO structures. However, the physical data stream at the image port is only 16-bit or 8-bit wide; in 16-bit mode data pins HPD7 to HPD0 are used for chrominance data. The four bytes of the Dwords are serialized in words or bytes. If data input mode is selected at the expansion port, then the scaler can choose its input data stream from the on-chip video decoder, or from the expansion port (controlled by bit SCSRC[1:0] 91H[5:4]). Byte serial Y-CB-CR 4 : 2 : 2, or subsets for other sampling schemes, or raw samples from an external ADC may be input (see also bits FSC[2:0] 91H[2:0]). The input data stream must be accompanied by an external clock XCLK, qualifier XDQ and reference signals XRH and XRV. Instead of the reference signal, embedded SAV and EAV codes, according to ITU 656, can also be accepted. The protection bits are not evaluated. The available formats are as follows: • Y-CB-CR 4 : 2 : 2 • Y-CB-CR 4 : 1 : 1 • Raw samples • Decoded VBI data. For handshaking with the receiving VGA controller, or other memory or bus interface circuitry, F, H and V reference signals and programmable FIFO flags are provided. The information is provided on pins IGP0, IGP1, IGPH and IGPV. The function on these pins is controlled via subaddresses 84H and 85H. XRH and XRV carry the horizontal and vertical synchronization signals for the digital video stream through the expansion port. The field ID of the input video stream is carried in the phase (edge) of XRV and state of XRH, or directly as FS (frame sync, odd/even signal) on the XRV pin (controlled by XFDV[92H[7]], XFDH[92H[6]] and XDV[1:0] 92H[5:4]). VBI data is collected over an entire line in its own FIFO and transferred as an uninterrupted block of bytes. Decoded VBI data can be signed by the VBI flag on pins IGP0 and IGP1. The trigger events on XRH (rising/falling edge) and XRV (rising/falling both edges) for the scalers acquisition window are defined by XDV[1:0] 92H[5:4] and XDH[92H[2]]. The signal polarity of the qualifier can also be defined by bit XDQ[92H[1]]. As an alternative to the qualifier, the input clock can be applied to a gated clock (clock gated with a data qualifier, controlled by bit XCKS[92H[0]]). In this event, all input data will be qualified. 10.5 Because scaled video data and decoded VBI data may come from different and asynchronous sources, an arbitration scheme is needed. Normally the VBI data slicer has priority. The image port consists of the pins and/or signals, as given in Table 46. Image port (I port) For pin constrained applications, or interfaces, the relevant timing and data reference signals can also be encoded into the data stream. Therefore the corresponding pins do not need to be connected. The minimum image port configuration requires 9 pins only, i.e. 8 pins for data including codes, and 1 pin for clock or gated clock. The inserted codes are defined in close relationship to the ITU-R BT.656 (D1) recommendation, where possible. The image port transfers data from the scaler as well as from the VBI data slicer, if selected (maximum 33 MHz). The reference clock is available at the ICLK pin as an output or as an input (maximum 33 MHz). As an output, the ICLK is derived from the line-locked decoder or expansion port input clock. The data stream from the scaler output is normally discontinuous. Therefore valid data during a clock cycle is accompanied by a data qualifying (data valid) flag on pin IDQ. For pin constrained applications the IDQ pin can be programmed to function as a gated clock output (bit ICKS2[80H[2]]). 2004 Jun 29 84 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE • VBI raw sample streams are enveloped with SAV and EAV, like normal video The following deviations from “ITU 656 recommendation” are implemented at the SAA7108AE; SAA7109AEs image port interface: • Decoded VBI data is transported as Ancillary (ANC) data, two modes: • SAV and EAV codes are only present in those lines, where data is to be transferred, i.e. active video lines, or VBI raw samples, no codes for empty lines – direct decoded VBI data bytes (8-bit) are directly placed in the ANC data field, 00H and FFH codes may appear in the data block (violation to ITU-R BT.656) • There may be more or less than 720 pixels between SAV and EAV • The data content and number of clock cycles during horizontal and vertical blanking is undefined, and may be not constant – recoded VBI data bytes (8-bit) directly placed in ANC data field, 00H and FFH codes will be recoded to even parity codes 03H and FCH to suppress invalid ITU-R BT.656 codes. • The data stream may be interleaved with not-valid data codes, 00H, but SAV and EAV 4-byte codes are not interleaved with not-valid data codes There are no empty cycles in the ancillary code or its data field. The data codes 00H and FFH are suppressed (changed to 01H or FEH respectively) in the active video stream, as well as in the VBI raw sample stream (VBI pass-through). As an option the number range can be limited further. • There may be an irregular pattern of not-valid data, or IDQ, and as a result, ‘CB - Y - CR - Y -’ is not in a fixed phase to a regular clock divider Table 46 Signals dedicated to the image port SYMBOL PIN I/O E14, D14, C14, B14, E13, D13, C13 and B13 I/O I port data ICODE[93H[7]], ISWP[1:0] 85H[7:6] and IPE[1:0] 87H[1:0] ICLK H12 I/O continuous reference clock at image port, can be input or output, as output decoder LLC or XCLK from X port ICKS[1:0] 80H[1:0] and IPE[1:0] 87H[1:0] IDQ H14 O data valid flag at image port, qualifier, with programmable polarity; secondary function: gated clock ICKS2[80H[2]], IDQP[85H[0]] and IPE[1:0] 87H[1:0] IGPH G12 O horizontal reference output signal, copy of IDH[1:0] 84H[1:0], IRHP[85H[1]] and the horizontal gate signal of the scaler, with IPE[1:0] 87H[1:0] programmable polarity; alternative function: HRESET pulse IGPV F13 O vertical reference output signal, copy of the vertical gate signal of the scaler, with programmable polarity; alternative function: VRESET pulse IDV[1:0] 84H[3:2], IRVP[85H[2]] and IPE[1:0] 87H[1:0] IGP1 G13 O general purpose output signal for I port IDG12[86H[4]], IDG1[1:0] 84H[5:4], IG1P[85H[3]] and IPE[1:0] 87H[1:0] IGP0 F14 O general purpose output signal for I port IDG02[86H[5]], IDG0[1:0] 84H[7:6], IG0P[85H[4]] and IPE[1:0] 87H[1:0] ITRDY J14 I target ready input signals − ITRI G14 I port control, switches I port into 3-state IPE[1:0] 87H[1:0] IPD7 to IPD0 2004 Jun 29 DESCRIPTION 85 BIT Philips Semiconductors Product specification HD-CODEC 10.6 SAA7108AE; SAA7109AE Host port for 16-bit extension of video data I/O (H port) The H port, pins HPD, can be used to extend the data I/O paths to 16-bit. The I port has functional priority. If I8_16[93H[6]] is set to logic 1 the output drivers of the H port are enabled and are dependent on the I port enable control. When I8_16 = 0, the HPD output is disabled. Table 47 Signals dedicated to the host port SYMBOL HPD7 to HPD0 10.7 PIN I/O DESCRIPTION A13, D12, C12, B12, I/O 16-bit extension for digital I/O A12, C11, B11 and A11 (chrominance component) Basic input and output timing diagrams for the I and X ports 10.7.1 BIT 10.7.2 IPE[1:0] 87H[1:0], ITRI[8FH[6]] and I8_16[93H[6]] X PORT INPUT TIMING The input timing requirements at the X port are the same as those for the I port output. However, the following differences should be noted: I PORT OUTPUT TIMING The following diagrams (Figs 40 to 46) illustrate the output timing via the I port. IGPH and IGPV are indicated as logic 1 active gate signals. If reference pulses are programmed, these pulses are generated on the rising edge of the logic 1 active gates. Valid data is accompanied by the output data qualifier on pin IDQ. In addition, invalid cycles are marked with output code 00H. • It is not necessary to mark invalid cycles with a 00H code • No constraints on the input qualifier (can be a random pattern) • XCLK may by a gated clock (XCLK AND external XDQ). Remark: All timings illustrated are given for an uninterrupted output stream (no handshake with the external hardware). The IDQ output pin may be defined to be a gated clock output signal (ICLK AND internal IDQ). ICLK IDQ IPD [ 7:0 ] 00 FF 00 00 SAV 00 CB CR Y Y 00 CB Y CR Y 00 IGPH MHB550 Fig.40 Output timing at the I port for serial 8-bit data at start of a line (ICODE = 1). 2004 Jun 29 86 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE ICLK IDQ IPD [ 7:0 ] CB 00 CR Y Y 00 CB Y CR Y 00 IGPH MHB551 Fig.41 Output timing at the I port for serial 8-bit data at start of a line (ICODE = 0). ICLK IDQ IPD [ 7:0 ] 00 CB Y CR Y 00 CB CR Y Y 00 FF 00 00 EAV 00 IGPH MHB552 Fig.42 Output timing at the I port for serial 8-bit data at end of a line (ICODE = 1). 2004 Jun 29 87 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE ICLK IDQ IPD [ 7:0 ] 00 CB Y CR Y 00 CB Y CR Y 00 IGPH MHB553 Fig.43 Output timing at the I port for serial 8-bit data at end of a line (ICODE = 0). ICLK IDQ IPD [ 7:0 ] 00 FF 00 00 Y0 Y1 00 Y2 Y3 Yn − 1 Yn 00 FF 00 00 HPD [ 7:0 ] 00 00 SAV 00 CB CR 00 CB CR CB CR 00 00 EAV 00 IGPH MHB554 Fig.44 Output timing for 16-bit data output via the I and H port with codes (ICODE = 1), timing is like 8-bit output, but packages of 2 bytes per valid cycle. 2004 Jun 29 88 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE handbook, full pagewidth IDQ IGPH IGPV MHB555 Fig.45 Horizontal and vertical gate output timing. handbook, full pagewidth ICLK IDQ IPD [ 7:0 ] 00 00 FF FF DID HPD [ 7:0 ] 00 FF 00 00 SAV SDID XX YY ZZ CS BC 00 00 00 BC FF 00 00 EAV sliced data flag on IGP0 or IGP1 MHB733 Fig.46 Output timing for sliced VBI data in 8-bit serial output mode (dotted graphs for SAV/EAV mode). 2004 Jun 29 89 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE The Boundary Scan Test (BST) functions BYPASS, EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all supported; see Table 48. Details about the JTAG BST-TEST can be found in the specification “IEEE Std. 1149.1”. Two files containing the detailed Boundary Scan Description Language (BSDL) of the SAA7108AE; SAA7109AE are available on request. 11 BOUNDARY SCAN TEST The SAA7108AE; SAA7109AE has built-in logic and 2 times 5 dedicated pins to support boundary scan testing, separately for the encoder and decoder part, which allows board testing without special hardware (nails). The SAA7108AE; SAA7109AE follows the “IEEE Std. 1149.1 Standard Test Access Port and Boundary-Scan Architecture” set by the Joint Test Action Group (JTAG) chaired by Philips. The 10 special pins are Test Mode Select (TMSe and TMSd), Test Clock (TCKe and TCKd), Test Reset (TRSTe and TRSTd), Test Data Input (TDIe and TDId) and Test Data Output (TDOe and TDOd), where extension ‘e’ refers to the encoder part and extension ‘d’ refers to the decoder part. Table 48 BST instructions supported by the SAA7108AE; SAA7109AE INSTRUCTION 11.1 DESCRIPTION BYPASS This mandatory instruction provides a minimum length serial path (1 bit) between TDIe (or TDId) and TDOe (or TDOd) when no test operation of the component is required. EXTEST This mandatory instruction allows testing of off-chip circuitry and board level interconnections. SAMPLE This mandatory instruction can be used to take a sample of the inputs during normal operation of the component. It can also be used to preload data values into the latched outputs of the boundary scan register. CLAMP This optional instruction is useful for testing when not all ICs have BST. This instruction addresses the bypass register while the boundary scan register is in external test mode. IDCODE This optional instruction will provide information on the components manufacturer, part number and version number. INTEST This optional instruction allows testing of the internal logic (no support for customers available). USER1 This private instruction allows testing by the manufacturer (no support for customers available). Initialization of boundary scan circuit is the possibility to check for the correct ICs mounted after production and to determine the version number of the ICs during field service. The Test Access Port (TAP) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS. When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected between TDIe (or TDId) and TDOe (or TDOd) of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller, this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to TDIe or TDId) and bit 0 is the least significant bit (nearest to TDOe or TDOd); see Fig.47. To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting the TRSTe or TRSTd pin LOW. 11.2 Device identification codes A device identification register is specified in “IEEE Std. 1149.1b-1994”. It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage 2004 Jun 29 90 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE MSB handbook, full pagewidth 31 TDIe (or TDId) LSB 28 27 nnnn 4-bit version code 12 11 1 0111000100000100 (0111000100010100) 0 16-bit part number TDOe (or TDOd) 1 00000010101 11-bit manufacturer identification MBL786 a. SAA7108AE. MSB handbook, full pagewidth 31 TDIe (or TDId) LSB 28 27 nnnn 4-bit version code 12 11 1 0111000100000101 (0111000100010100) 1 00000010101 16-bit part number 0 11-bit manufacturer identification TDOe (or TDOd) MBL787 b. SAA7109AE. Fig.47 32 bits of identification code. 12 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); all ground pins connected together and grounded (0 V); all supply pins connected together. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDDD digital supply voltage −0.5 +4.6 V VDDA analog supply voltage −0.5 +4.6 V Vi(A) input voltage at analog inputs −0.5 +4.6 V Vi(n) input voltage at pins XTALI, SDA and SCL Vi(D) input voltage at digital inputs or I/O pins −0.5 VDDD + 0.5 V outputs in 3-state −0.5 +4.6 V outputs in 3-state; note 1 −0.5 +5.5 V ∆VSS voltage difference between VSSA(n) and VSSD(n) − 100 mV Tstg storage temperature −65 +150 °C Tamb ambient temperature 0 70 °C Vesd electrostatic discharge voltage ±2000 V ±150 V human body model; − note 2 machine model; note 3 − Notes 1. Condition for maximum voltage at digital inputs or I/O pins: 3.0 V < VDDD < 3.6 V. 2. Class 2 according to EIA/JESD22-114-B. 3. Class A according to EIA/JESD22-115-A. 2004 Jun 29 91 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE 13 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS thermal resistance from junction to ambient VALUE UNIT 32(1) K/W in free air Note 1. The overall Rth(j-a) value can vary depending on the board layout. To minimize the effective Rth(j-a) all power and ground pins must be connected to the power and ground layers directly. An ample copper area direct under the SAA7108AE; SAA7109AE with a number of through-hole plating, which connect to the ground layer (four-layer board: second layer), can also reduce the effective Rth(j-a). Please do not use any solder-stop varnish under the chip. In addition the usage of soldering glue with a high thermal conductance after curing is recommended. 14 CHARACTERISTICS OF THE DIGITAL VIDEO ENCODER PART Tamb = 0 to 70 °C (typical values measured at Tamb = 25 °C); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA analog supply voltage 3.15 3.3 3.45 V VDDIe digital supply voltage 3.15 3.3 3.45 V VDD(DVO) digital supply voltage (DVO) 1.045 1.1 1.155 V 1.425 1.5 1.575 V 1.71 1.8 1.89 V 2.375 2.5 2.625 V 3.135 3.3 3.465 V IDDA analog supply current note 1 1 110 115 mA IDDD digital supply current note 2 1 175 200 mA LOW-level input voltage VDD(DVO) = 1.1 V, 1.5 V, 1.8 V or 2.5 V; note 3 −0.1 − +0.2 V VDD(DVO) = 3.3 V; note 3 −0.5 − +0.8 V pins RESe, TMSe, TCKe, TRSTe and TDIe −0.5 − +0.8 V VDD(DVO) = 1.1 V, 1.5 V, 1.8 V or 2.5 V; note 3 VDD(DVO) − 0.2 − VDD(DVO) + 0.1 V VDD(DVO) = 3.3 V; note 3 2 − VDD(DVO) + 0.3 V pins RESe, TMSe, TCKe, TRSTe and TDIe 2 − VDDIe + 0.3 V − − 10 µA clocks − − 10 pF data − − 10 pF I/Os at high-impedance − − 10 pF Inputs VIL VIH HIGH-level input voltage ILI input leakage current Ci input capacitance 2004 Jun 29 92 Philips Semiconductors Product specification HD-CODEC SYMBOL SAA7108AE; SAA7109AE PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Outputs VOL VOH LOW-level output voltage VDD(DVO) = 1.1 V, 1.5 V, 1.8 V or 2.5 V; note 3 0 − 0.1 V VDD(DVO) = 3.3 V; note 3 0 − 0.4 V pins TDOe, TTXRQ_XCLKO2, VSM and HSM_CSYNC 0 − 0.4 V VDD(DVO) − 0.1 − VDD(DVO) V HIGH-level output voltage VDD(DVO) = 1.1 V, 1.5 V, 1.8 V or 2.5 V; note 3 VDD(DVO) = 3.3 V; note 3 2.4 − VDD(DVO) V pins TDOe, TTXRQ_XCLKO2, VSM and HSM_CSYNC 2.4 − VDDIe V I2C-bus; pins SDAe and SCLe VIL LOW-level input voltage −0.5 − 0.3VDDIe V VIH HIGH-level input voltage 0.7VDDIe − VDDIe + 0.3 V Ii input current Vi = LOW or HIGH −10 − +10 µA VOL LOW-level output voltage (pin SDAe) IOL = 3 mA − − 0.4 V Io output current during acknowledge 3 − − mA Clock timing; pins PIXCLKI and PIXCLKO TPIXCLK cycle time note 4 12 − − ns td(CLKD) delay from PIXCLKO to PIXCLKI note 5 − − − ns δ duty factor tHIGH/TPIXCLK note 4 40 50 60 % duty factor tHIGH/TCLKO2 output 40 50 60 % tr rise time note 4 − − 1.5 ns tf fall time note 4 − − 1.5 ns Input timing tSU;DAT input data set-up time pins PD11 to PD0 2 − − ns tHD;DAT input data hold time pins PD11 to PD0 0.9 − − ns tSU;DAT input data set-up time pins HSVGC, VSVGC and FSVGC; note 6 2 − − ns tHD;DAT input data hold time pins HSVGC, VSVGC and FSVGC; note 6 1.5 − − ns − 27 − MHz −50 − +50 10−6 Crystal oscillator fnom nominal frequency ∆f/fnom permissible deviation of nominal frequency 2004 Jun 29 note 7 93 Philips Semiconductors Product specification HD-CODEC SYMBOL SAA7108AE; SAA7109AE PARAMETER CONDITIONS MIN. TYP. MAX. UNIT CRYSTAL SPECIFICATION Tamb ambient temperature 0 − 70 °C CL load capacitance 8 − − pF RS series resistance − − 80 Ω C1 motional capacitance (typical) 1.2 1.5 1.8 fF C0 parallel capacitance (typical) 2.8 3.5 4.2 pF 8 − 40 pF Data and reference signal output timing CL output load capacitance to(h)(gfx) output hold time to graphics controller pins HSVGC, VSVGC, FSVGC and CBO 1.5 − − ns to(d)(gfx) output delay time to graphics controller pins HSVGC, VSVGC, FSVGC and CBO − − 10 ns to(h) output hold time pins TDOe, TTXRQ_XCLKO2, VSM and HSM_CSYNC 3 − − ns to(d) output delay time pins TDOe, TTXRQ_XCLKO2, VSM and HSM_CSYNC − − 25 ns Vo(CVBS)(p-p) output voltage CVBS (peak-to-peak value) see Table 49 − 1.23 − V Vo(VBS)(p-p) output voltage VBS (S-video) (peak-to-peak value) see Table 49 − 1 − V Vo(C)(p-p) output voltage C (S-video) (peak-to-peak value) see Table 49 − 0.89 − V Vo(RGB)(p-p) output voltage R, G, B (peak-to-peak value) see Table 49 − 0.7 − V ∆Vo inequality of output signal voltages − 2 − % RL output load resistance − 37.5 − Ω BDAC output signal bandwidth of DACs − 170 − MHz ILElf(DAC) low frequency integral linearity error of DACs − − ±3 LSB DLElf(DAC) low frequency differential linearity error of DACs − − ±1 LSB CVBS and RGB outputs 2004 Jun 29 −3 dB; note 8 94 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Notes 1. Minimum value for I2C-bus bit DOWNA = 1. 2. Minimum value for I2C-bus bit DOWND = 1. 3. Levels refer to pins PD11 to PD0, FSVGC, PIXCLKI, VSVGC, PIXCLKO, CBO, TVD, and HSVGC, being inputs or outputs directly connected to a graphics controller. Input sensitivity is 1/2VDD(DVO) + 100 mV for HIGH and 1/2VDD(DVO) − 100 mV for LOW. The reference voltage 1/2VDD(DVO) is generated on chip. 4. The data is for both input and output direction. 5. This parameter is arbitrary, if PIXCLKI is looped through the VGC. 6. Tested with programming IFBP = 1. 7. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 1 B –3 dB = ----------------------------------------------------------- with Cext = 20 pF (typical). 2π ( R o(L) ( C ext + 5 pF ) ) 8. 15 CHARACTERISTICS OF THE DIGITAL VIDEO DECODER PART VDDD = 3.0 to 3.6 V; VDDA = 3.1 to 3.5 V; Tamb = 0 to 70 °C (typical values measured at Tamb = 25 °C); timings and levels refer to drawings and conditions illustrated in Fig.52; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDD digital supply voltage 3.15 3.3 3.45 V IDDD digital supply current − 90 − mA PD power dissipation digital part − 300 − mW VDDA analog supply voltage 3.15 3.3 3.45 V IDDA analog supply current PA power dissipation analog part Ptot(A+D) total power dissipation analog and digital part X port 3-state; 8-bit I port AOSL1 and AOSL0 = 0 CVBS mode − 47 − mA Y/C mode − 72 − mA CVBS mode − 150 − mW Y/C mode − 240 − mW CVBS mode − 450 − mW Y/C mode − 540 − mW Ptot(A+D)(pd) total power dissipation analog and digital part in Power-down mode CE pulled down to ground − 5 − mW Ptot(A+D)(ps) total power dissipation analog and digital part in power-save mode I2C-bus controlled via address 88H = 0FH − 75 − mW clamping current VI = 0.9 V DC − ±8 − µA Analog part Iclamp 2004 Jun 29 95 Philips Semiconductors Product specification HD-CODEC SYMBOL Vi(p-p) SAA7108AE; SAA7109AE PARAMETER CONDITIONS MIN. TYP. MAX. input voltage (peak-to-peak value) for normal video levels − 1 V (p-p), −3 dB termination 27/47 Ω and AC coupling required; coupling capacitor = 22 nF 0.7 − clamping current off Zi input impedance Ci input capacitance αcs channel crosstalk UNIT V 200 − − kΩ − − 10 pF fi < 5 MHz − − −50 dB at −3 dB − 7 − MHz 9-bit analog-to-digital converters B analog bandwidth φdiff differential phase (amplifier plus anti-alias filter bypassed) − 2 − deg Gdiff differential gain (amplifier plus anti-alias filter bypassed) − 2 − % fclk(ADC) ADC clock frequency 12.8 − 14.3 MHz DLEdc(d) DC differential linearity error − 0.7 − LSB ILEdc(i) DC integral linearity error − 1 − LSB VIL(SDAd,SCLd) LOW-level input voltage pins SDAd and SCLd −0.5 − +0.3VDDD V VIH(SDAd,SCLd) HIGH-level input voltage pins SDAd and SCLd 0.7VDDD − VDDD + 0.5 V VIL(XTALId) LOW-level CMOS input voltage pin XTALId −0.3 − +0.8 V VIH(XTALId) HIGH-level CMOS input voltage pin XTALId 2.0 − VDDD + 0.3 V VIL(n) LOW-level input voltage all other inputs −0.3 − +0.8 V VIH(n) HIGH-level input voltage all other inputs 2.0 − 5.5 V ILI input leakage current − − 1 µA ILI/O I/O leakage current − − 10 µA Ci input capacitance I/O at high-impedance − − 8 pF SDAd at 3 mA sink current − − 0.4 V Digital inputs Digital outputs; note 1 VOL(SDAd) LOW-level output voltage pin SDAd VOL(clk) LOW-level output voltage for clocks −0.5 − +0.6 V VOH(clk) HIGH-level output voltage for clocks 2.4 − VDDD + 0.5 V 2004 Jun 29 96 Philips Semiconductors Product specification HD-CODEC SYMBOL SAA7108AE; SAA7109AE PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VOL LOW-level output voltage all other digital outputs 0 − 0.4 V VOH HIGH-level output voltage all other digital outputs 2.4 − VDDD + 0.5 V 15 − 50 pF pin LLC 35 − 39 ns pin LLC2 70 − 78 ns CL = 40 pF 40 − 60 % Clock output timing (LLC and LLC2); note 2 CL(LLC) output load capacitance Tcy cycle time δ duty factors for tLLCH/tLLC and tLLC2H/tLLC2 tr rise time LLC and LLC2 0.2 V to VDDD − 0.2 V − − 5 ns tf fall time LLC and LLC2 VDDD − 0.2 V to 0.2 V − − 5 ns td(LLC-LLC2) delay time between LLC and LLC2 output measured at 1.5 V; CL = 25 pF −4 − +8 ns 50 Hz field − 15625 − Hz 60 Hz field − 15734 − Hz − − 5.7 % Horizontal PLL fH(nom) nominal line frequency ∆fH/fH(nom) permissible static deviation Subcarrier PLL fsc(nom) ∆fsc nominal subcarrier frequency PAL BGHI − 4433619 − Hz NTSC M − 3579545 − Hz PAL M − 3575612 − Hz PAL N − 3582056 − Hz ±400 − − Hz − 32.11 − lock-in range Crystal oscillator for 32.11 MHz; note 3 fxtal(nom) nominal frequency 3rd-harmonic MHz 10−6 ∆fxtal(nom) permissible nominal frequency deviation − − ±70 × ∆fxtal(nom)(T) permissible nominal frequency deviation with temperature − − ±30 × 10−6 0 − 70 °C CRYSTAL SPECIFICATION (X1) Tamb(X1) ambient temperature CL load capacitance 8 − − pF Rs series resonance resistor − 40 80 Ω C1 motional capacitance − 1.5 ±20 % − fF C0 parallel capacitance − 4.3 ±20 % − pF − 24.576 − − − ±50 × 10−6 Crystal oscillator for 24.576 MHz; note 3 fxtal(nom) nominal frequency ∆fxtal(nom) permissible nominal frequency deviation 2004 Jun 29 3rd-harmonic 97 MHz Philips Semiconductors Product specification HD-CODEC SYMBOL ∆fxtal(nom)(T) SAA7108AE; SAA7109AE PARAMETER CONDITIONS permissible nominal frequency deviation with temperature MIN. TYP. MAX. − − ±20 × UNIT 10−6 CRYSTAL SPECIFICATION (X1) Tamb(X1) ambient temperature 0 − 70 °C CL load capacitance 8 − − pF 80 Rs series resonance resistor − 40 C1 motional capacitance − 1.5 ±20 % − fF Ω C0 parallel capacitance − 3.5 ±20 % − pF 31 − ns Clock input timing (XCLK) Tcy cycle time 45 δ duty factors for tLLCH/tLLC 40 50 60 % tr rise time − − 5 ns tf fall time − − 5 ns Data and control signal input timing X port, related to XCLK input tSU;DAT input data set-up time − 10 − ns tHD;DAT input data hold time − 3 − ns Clock output timing CL output load capacitance 15 − 50 pF Tcy cycle time 35 − 39 ns δ duty factors for tXCLKH/tXCLKL 35 − 65 % tr rise time 0.6 to 2.6 V − − 5 ns tf fall time 2.6 to 0.6 V − − 5 ns Data and control signal output timing X port, related to XCLK output (for XPCK[1:0] 83H[5:4] = 00 is default); note 2 CL output load capacitance tOHD;DAT output hold time tPD propagation delay from positive edge of XCLK output 15 − 50 pF CL = 15 pF − 14 − ns CL = 15 pF − 24 − ns 15 − 50 pF Control signal output timing RT port, related to LLC output CL output load capacitance tOHD;DAT output hold time CL = 15 pF − 14 − ns tPD propagation delay from positive edge of LLC output CL = 15 pF − 24 − ns 15 − 50 pF ICLK output timing CL output load capacitance Tcy cycle time 31 − 45 ns δ duty factors for tICLKH/tICLKL 35 − 65 % 2004 Jun 29 98 Philips Semiconductors Product specification HD-CODEC SYMBOL SAA7108AE; SAA7109AE PARAMETER CONDITIONS MIN. TYP. MAX. UNIT tr rise time 0.6 to 2.6 V − − 5 ns tf fall time 2.6 to 0.6 V − − 5 ns Data and control signal output timing I port, related to ICLK output (for IPCK[1:0] 87H[5:4] = 00 is default) CL output load capacitance at all outputs tOHD;DAT output data hold time to(d) output delay time 15 − 50 pF CL = 15 pF − 12 − ns CL = 15 pF − 22 − ns 31 − 100 ns ICLK input timing Tcy cycle time Notes 1. The levels must be measured with load circuits; 1.2 kΩ at 3 V (TTL load); CL = 50 pF. 2. The effects of rise and fall times are included in the calculation of tOHD;DAT and tPD. Timings and levels refer to drawings and conditions illustrated in Fig.52. 3. The crystal oscillator drive level is 0.28 mW (typ.). 16 TIMING 16.1 Digital video encoder part TPIXCLK handbook, full pagewidth tHIGH VOH PIXCLKO 0.5VDD(DVO) VOL tf td(CLKD) tr VIH PIXCLKI 0.5VDD(DVO) VIL tHD;DAT tHD;DAT tSU;DAT tSU;DAT VIH PDn VIL to(d) to(h) VOH any output VOL MBL789 Fig.48 Input/output timing specification. 2004 Jun 29 99 Philips Semiconductors Product specification HD-CODEC handbook, full pagewidth SAA7108AE; SAA7109AE HSVGC CBO PD XOFS IDEL XPIX HLEN MHB905 Fig.49 Horizontal input timing. handbook, full pagewidth HSVGC VSVGC CBO YOFS YPIX Fig.50 Vertical input timing. 2004 Jun 29 100 MHB906 Philips Semiconductors Product specification HD-CODEC 16.1.1 SAA7108AE; SAA7109AE TELETEXT TIMING Time tFD is the time needed to interpolate input data TTX and insert it into the CVBS and VBS output signal, such that it appears at tTTX = 9.78 µs (PAL) or tTTX = 10.5 µs (NTSC) after the leading edge of the horizontal synchronization pulse. Time tPD is the pipeline delay time introduced by the source that is gated by TTXRQ_XCLKO2 in order to deliver TTX data. This delay is programmable by register TTXHD. For every active HIGH state at output pin TTXRQ_XCLKO2, a new teletext bit must be provided by the source. Since the beginning of the pulses representing the TTXRQ signal and the delay between the rising edge of TTXRQ and valid teletext input data are fully programmable (TTXHS and TTXHD), the TTX data is always inserted at the correct position after the leading edge of the outgoing horizontal synchronization pulse. Time ti(TTXW) is the internally used insertion window for TTX data; it has a constant length that allows insertion of 360 teletext bits at a text data rate of 6.9375 Mbits/s (PAL), 296 teletext bits at a text data rate of 5.7272 Mbits/s (world standard TTX) or 288 teletext bits at a text data rate of 5.7272 Mbits/s (NABTS). The insertion window is not opened if the control bit TTXEN is zero. Using appropriate programming, all suitable lines of the odd field (TTXOVS and TTXOVE) plus all suitable lines of the even field (TTXEVS and TTXEVE) can be used for teletext insertion. It is essential to note that the two pins used for teletext insertion must be configured for this purpose by the correct I2C-bus register settings. handbook, full pagewidth CVBS/Y t TTX text bit #: 1 t i(TTXW) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 TTX_SRES t PD t FD TTXRQ_XCLKO2 MHB891 Fig.51 Teletext timing. 2004 Jun 29 101 24 Philips Semiconductors Product specification HD-CODEC 16.2 SAA7108AE; SAA7109AE Digital video decoder part Tcy handbook, full pagewidth t XCLKH 2.4 V clock input XCLK 1.5 V 0.6 V t SU;DAT tf tr t HD;DAT 2.0 V data and control inputs (X port) not valid 0.8 V t SU;DAT t HD;DAT 2.0 V input XDQ 0.8 V t o(d) t OHD;DAT −2.4 V data and control outputs X port, I port −0.6 V t X(I)CLKL t X(I)CLKH −2.6 V clock outputs LLC, LLC2, XCLK, ICLK and ICLK input −1.5 V −0.6 V tf tr Fig.52 Data input/output timing diagram (X port, RT port and I port). 2004 Jun 29 102 MHB735 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE 17 APPLICATION INFORMATION VDD(EL9) VDD(EL7) VDD(ID11) VDD(IF11) VDD(EG11) VDD(ED10) VDD(IJ4) VDD(IJ11) handbook, full pagewidth VDD(IL4) VDD(IL11) VDD(AM8) VDD(AM9) VDD(XL8) 32.11 MHz VDDP AUDIO2 L8 E12 F12 24.576 MHz DGND SDAd SCLd XPD7 XPD6 XPD5 XPD4 XPD3 XPD2 XPD1 XPD0 JP43 fXTAL R12 4.7 kΩ R27 0 Ω n.c. TVD VDDXd VDDId VDDId D11 F11 J4 J11 L4 L11 VDDId VDDId VDDId VDDId D10 G11 L7 L9 VDDEd VDDEd VDDEd VDDEd N11 M9 M8 VDDAd VDDAd VDDAd VDD(AN11) ’strapping’ L12 M11 SDA SCL R28 0 Ω XPD[0:7] K2 K3 L1 L2 L3 M1 M2 N1 XPD7 XPD6 XPD5 XPD4 XPD3 XPD2 XPD1 XPD0 K1 L5 N2 M3 M4 N3 XPCON5 XPCON4 XPCON3 XPCON2 XPCON1 XPCON0 A13 D12 C12 B12 A12 C11 B11 A11 HPD7 HPD6 HPD5 HPD4 HPD3 HPD2 HPD1 HPD0 E14 D14 C14 B14 E13 D13 C13 B13 IPD7 IPD6 IPD5 IPD4 IPD3 IPD2 IPD1 IPD0 G14 F13 G12 G13 F14 H12 H14 J14 IPCON7 IPCON6 IPCON5 IPCON4 IPCON3 IPCON2 IPCON1 IPCON0 J12 J13 K14 K12 AUDIO3 AUDIO2 AUDIO1 AUDIO0 L10 K13 L13 RCON2 RCON1 RCON0 I2C-BUS_Adr:40H/42H VDDP RCON0 DGND 4.7 kΩ AI24 AI23 AI22 AI21 XTRI XRV XRH XCLK XDQ XRDY JP44 R13 ’strapping’ R19 C100 18 Ω 47 nF R17 C97 18 Ω 47 nF R16 C98 18 Ω 47 nF R18 C99 18 Ω 47 nF C109 P6 P7 P9 P10 P8 HPD7 HPD6 HPD5 HPD4 HPD3 HPD2 HPD1 HPD0 AI24 AI23 IPD7 IPD6 IPD5 IPD4 IPD3 IPD2 IPD1 IPD0 AI22 AI21 AI2D SAA7108AE SAA7109AE 47 nF AI12 AI11 R15 C101 18 Ω 47 nF R20 C102 18 Ω P11 P13 ITRI IGPV IGPH IGP1 IGP0 ICLK IDQ ITRDY AI12 AI11 47 nF R21 56 Ω R22 56 Ω R23 56 Ω R24 56 Ω R25 56 Ω R26 56 Ω C110 P12 AI1D 47 nF AMXCLK ALRCLK ASCLK AMCLK AGND R29 AOUT M10 0Ω AOUT RTS1 RTS0 RTCO LLC2 LLC RESd CE XPCON[0:5] HPD[0:7] IPD[0:7] IPCON[0:7] AUDIO[0:3] RCON[0:2] R37 33 Ω L14 M14 LLC2 LLC R38 33 Ω M12 N14 RES R47 VDDP open TMSd TCLKd TRSTd TDId TDOd VDD(AM8) VDD(AM9) VDD(AN11) VDD(EL9) VDD(EL7) VDD(EG11) TEST5 TEST4 TEST3 TEST2 TEST1 TEST0 VDD(ED10) VDD(ID11) C52 C48 C51 C49 C50 C60 C56 C59 C57 C58 C61 100 nF 100 nF 100 nF L36 ferrite 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF AGND VSSXd VSSId VSSId VSSId VSSEd VSSEd VSSEd VSSEd TEST5 TEST4 TEST3 TEST2 TEST1 TEST0 P4 P3 P2 XTOUT Y1 24.576 MHz L34 10 µH C107 1 nF DGND DXGND AGND DGND DXGND DGND 0Ω DGND Fig.53 Application circuit (decoder part). 2004 Jun 29 BSC[0:2] TDI_D TDO_D C103 10 pF C104 10 pF R49 open AGND XTOUTd XTALOd XTALId BSC0 BSC1 BSC2 J2 J1 J3 C10 B10 H13 P5 C54 E11 K4 K11 C53 H4 H11 L6 M13 C55 AGND VSSAd VSSAd VSSAd VSSAd VDD(IL11) VDD(XL8) N13 N12 N10 N9 N8 N7 M7 VDD(IJ11) VDD(IL4) VSSAd VSSAd VDD(IF11) VDD(IJ4) M5 M6 N4 N6 N5 103 open 3PAD AGND MBL790 JP45 CE_Dec. DGND This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1 nF 0.1 µF DGND F4 AGND 10 pF 0.1 µH DGND VDD(DVO) 0.1 µF 10 pF 27 MHz use one capacitor for each VDDAe and VDDXe VDDIEe XTALIe XTALOe VDDAe and VDDXe D4 A5 A6 A10, B6, B9, C9, D9 and D6 D7 VSM D8 HSM_CSYNC C7 GREEN_VBS_CVBS FLTR0 75 Ω 104 AGND digital inputs and outputs SAA7108AE SAA7109AE C8 75 Ω AGND UY AGND RED_CR_C_CVBS FLTR1 75 Ω AGND BLUE_CB_CVBS 75 Ω A8 B8 A9 A7 B7 VSSIe VSSXe VSSAe RSET DUMP DUMP 75 Ω AGND UC AGND FLTR2 AGND 75 Ω AGND UCVBS AGND 12 Ω MBL784 AGND AGND AGND AGND Fig.54 Application circuit (encoder part). Product specification DGND SAA7108AE; SAA7109AE C6 C5, D5, E4 1 kΩ Philips Semiconductors +3.3 V analog AGND 0.1 µF HD-CODEC 2004 Jun 29 handbook, full pagewidth +3.3 V digital Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE C16 handbook, halfpage 120 pF L2 L3 2.7 µH 2.7 µH C10 390 pF C13 560 pF AGND JP11 JP12 FIN FOUT FILTER 1 = byp. ll act. MHB912 Fig.55 FLTR0, FLTR1 and FLTR2 as shown in Fig.54. 2004 Jun 29 105 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE handbook, full pagewidth SAA7108AE SAA7109AE P2 SAA7108AE SAA7109AE P3 XTALId P2 XTALOd 15 pF P3 XTALId 32.11 MHz 4.7 µH SAA7108AE SAA7109AE P2 XTALOd 32.11 MHz 15 pF 33 pF P3 XTALId XTALOd 32.11 MHz 33 pF 10 pF 10 pF 1 nF MBL796 (1a) With 3rd-harmonic quartz. Crystal load = 8 pF. (1b) With fundamental quartz. Crystal load = 20 pF. (1c) With fundamental quartz. Crystal load = 8 pF handbook, full pagewidth SAA7108AE SAA7109AE P2 SAA7108AE SAA7109AE P3 XTALId P2 XTALOd 18 pF P3 XTALId 24.576 MHz 4.7 µH SAA7108AE SAA7109AE P2 XTALOd 24.576 MHz 18 pF 39 pF P3 XTALId XTALOd 24.576 MHz 39 pF 15 pF 15 pF 1 nF MBL795 (2a) With 3rd-harmonic quartz. (2b) With fundamental quartz. (2c) With fundamental quartz. Crystal load = 8 pF. Crystal load = 20 pF. Crystal load = 8 pF. SAA7108AE SAA7109AE P2 SAA7108AE SAA7109AE P3 XTALId P2 XTALOd P3 XTALId XTALOd Rs 32.11 MHz or 24.576 MHz n.c. clock MBL794 (3a) With direct clock. (3b) With fundamental quartz and restricted drive level. When Pdrive of the internal oscillator is too high, a resistance Rs can be placed in series with the oscillator output XTALOd. Note: The decreased crystal amplitude results in a lower drive level but on the other hand the jitter performance will decrease. Fig.56 Oscillator application for decoder part. 2004 Jun 29 106 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE handbook, full pagewidth SAA7108AE SAA7109AE SAA7108AE SAA7109AE A5 A6 XTALIe A5 XTALOe 27.00 MHz 4.7 µH 18 pF A6 XTALIe XTALOe 27.00 MHz 18 pF 39 pF 39 pF 1 nF MBL792 (1a) With 3rd-harmonic quartz. Crystal load = 8 pF. (1b) With fundamental quartz. Crystal load = 20 pF. SAA7108AE SAA7109AE SAA7108AE SAA7109AE handbook, full pagewidth A5 A6 XTALIe A5 XTALOe XTALIe A6 XTALOe Rs 27.00 MHz n.c. clock MBL793 (2a) With direct clock. (2b) With fundamental quartz and restricted drive level. When Pdrive of the internal oscillator is too high, a resistance Rs can be placed in series with the oscillator output XTALOe. Note: The decreased crystal amplitude results in a lower drive level but on the other hand the jitter performance will decrease. Fig.57 Oscillator application for encoder part. 2004 Jun 29 107 Philips Semiconductors Product specification HD-CODEC 17.1 SAA7108AE; SAA7109AE Reconstruction filter Figure 55 shows a possible reconstruction filter for the digital-to-analog converters. Due to its cut-off frequency of ∼6 MHz, it is not suitable for HDTV applications. 17.2 Analog output voltages The analog output voltages are dependent on the total load (typical value 37.5 Ω), the digital gain parameters and the I2C-bus settings of the DAC reference currents (analog settings). By setting the reference currents of the DACs as shown in Table 49, standard compliant amplitudes can be achieved for all signal combinations; it is assumed that in subaddress 16H, parameter DACF = 0000b, that means the fine adjustment for all DACs in common is set to 0 %. If S-video output is desired, the adjustment for the C (chrominance subcarrier) output should be identical to the one for VBS (luminance plus sync) output. The digital output signals in front of the DACs under nominal (nominal here stands for the settings given in Tables 75 to 82 for example a standard PAL or NTSC signal) conditions occupy different conversion ranges, as indicated in Table 49 for a 100⁄100 colour bar signal. Table 49 Digital output signals conversion range SET/OUT Digital settings Digital output Analog settings Analog output 17.3 CVBS, SYNC TIP-TO-WHITE VBS, SYNC TIP-TO-WHITE RGB, BLACK-TO-WHITE see Tables 75 to 82 see Tables 75 to 82 see Table 70 1014 881 876 e.g. B DAC = 1FH e.g. G DAC = 1BH e.g. R DAC = G DAC = B DAC = 0BH 1.23 V (p-p) 1.00 V (p-p) 0.70 V (p-p) Suggestions for a board layout Use separate ground planes for analog and digital ground. Connect these planes only at one point directly under the device, by using a 0 Ω resistor directly at the supply stage. Use separate supply lines for the analog and digital supply. Place the supply decoupling capacitors close to the supply pins. Use serial resistors in clock, sync and data lines, to avoid clock or data reflection effects and to soften data energy. The SAA7108AE; SAA7109AE crystal temperature depends on the PCB it is soldered on. For normal airflow conditions at a maximum ambient temperature of 70 °C it will be sufficient to provide: • PCB dimensions at least 2000 mm2 Use Lbead (ferrite coil) in each digital supply line close to the decoupling capacitors to minimize radiation energy (EMC). • PCB at least 4 layers Place the analog coupling (clamp) capacitors close to the analog input pins. Place the analog termination resistors close to the coupling capacitors. • Metal coverage at least 60 % on at least 2 PCB layers near the chip. • At least 50 vias (connecting PCB layers) close to the chip Be careful of hidden layout capacitors around the crystal application. 2004 Jun 29 108 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Digital video encoder part Table 50 Slave receiver bit allocation map (slave address 88H) REGISTER FUNCTION Status byte (read only) Null Common DAC adjust fine R DAC adjust coarse G DAC adjust coarse 109 D6 D5 D4 D3 D2 D1 D0 00 01 to 15 16 17 18 VER2 VER1 VER0 CCRDO CCRDE (1) FSEQ O_E (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) RDACC4 DACF3 RDACC3 DACF2 RDACC2 DACF1 RDACC1 DACF0 RDACC0 (1) (1) (1) 19 1A 1B 1C 26 27 28 29 2A 2B 2C 2D 2E to 36 37 38 39 3A 54 55 56 57 58 59 (1) (1) (1) MSMT7 MSM CID7 WSS7 WSSON MSMT6 MSA CID6 WSS6 GDACC3 BDACC3 MSMT3 (1) (1) (1) (1) SRES CG07 CG15 CGEN VBSEN (1) CG06 CG14 MSMT5 MSOE CID5 WSS5 WSS13 BS5 BE5 CG05 CG13 GDACC4 BDACC4 MSMT4 CID4 WSS4 WSS12 BS4 BE4 CG04 CG12 (1) (1) (1) CVBSEN0 CEN GDACC1 BDACC1 MSMT1 GCOMP CID1 WSS1 WSS9 BS1 BE1 CG01 CG09 CG17 CVBSEN2 GDACC0 BDACC0 MSMT0 BCOMP CID0 WSS0 WSS8 BS0 BE0 CG00 CG08 CG16 CVBSEN1 CID3 WSS3 WSS11 BS3 BE3 CG03 CG11 CG19 ENCOFF GDACC2 BDACC2 MSMT2 RCOMP CID2 WSS2 WSS10 BS2 BE2 CG02 CG10 CG18 CLK2EN (1) (1) (1) (1) (1) (1) (1) (1) YFIL0 GY4 GCD4 SYMP GPEN VPS54 VPS114 VPS124 VPS134 VPS144 (1) GY3 GCD3 DEMOFF CZOOM GY2 GCD2 CSYNC (1) (1) VPS53 VPS113 VPS123 VPS133 VPS143 VPS52 VPS112 VPS122 VPS132 VPS142 IGAIN GY1 GCD1 Y2C EDGE VPS51 VPS111 VPS121 VPS131 VPS141 XINT GY0 GCD0 UV2C SLOT VPS50 VPS110 VPS120 VPS130 VPS140 (1) (1) YUPSC YFIL1 (1) (1) (1) (1) (1) (1) CBENB VPSEN VPS57 VPS117 VPS127 VPS137 VPS147 (1) SYNTV GPVAL VPS55 VPS115 VPS125 VPS135 VPS145 (1) VPS56 VPS116 VPS126 VPS136 VPS146 (1) Product specification D7 SAA7108AE; SAA7109AE B DAC adjust coarse MSM threshold Monitor sense mode Chip ID (02B or 03B, read only) Wide screen signal Wide screen signal Real-time control, burst start Sync reset enable, burst end Copy generation 0 Copy generation 1 CG enable, copy generation 2 Output port control Null Input path control Gain luminance for RGB Gain colour difference for RGB Input port control 1 VPS enable, input control 2 VPS byte 5 VPS byte 11 VPS byte 12 VPS byte 13 VPS byte 14 SUB ADDR. (HEX) Philips Semiconductors 18.1 HD-CODEC 2004 Jun 29 18 I2C-BUS DESCRIPTION This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... D4 D3 D2 D1 D0 Chrominance phase Gain U 5A 5B CHPS7 GAINU7 CHPS6 GAINU6 CHPS5 GAINU5 CHPS4 GAINU4 CHPS3 GAINU3 CHPS2 GAINU2 CHPS1 GAINU1 CHPS0 GAINU0 Gain V Gain U MSB, black level 5C 5D GAINV7 GAINU8 GAINV6 Gain V MSB, blanking level CCR, blanking level VBI Null Standard control Burst amplitude Subcarrier 0 Subcarrier 1 Subcarrier 2 Subcarrier 3 Line 21 odd 0 Line 21 odd 1 Line 21 even 0 Line 21 even 1 Null Trigger control Trigger control Multi control Closed Caption, teletext enable Active display window horizontal start Active display window horizontal end MSBs ADWH 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 GAINV8 CCRS1 (1) CCRS0 GAINV5 BLCKL5 BLNNL5 BLNVB5 GAINV4 BLCKL4 BLNNL4 BLNVB4 GAINV3 BLCKL3 BLNNL3 BLNVB3 GAINV2 BLCKL2 BLNNL2 BLNVB2 GAINV1 BLCKL1 BLNNL1 BLNVB1 GAINV0 BLCKL0 BLNNL0 BLNVB0 (1) (1) (1) (1) (1) (1) (1) (1) DOWND RTCE FSC07 FSC15 FSC23 FSC31 L21O07 L21O17 L21E07 L21E17 DOWNA BSTA6 FSC06 FSC14 FSC22 FSC30 L21O06 L21O16 L21E06 L21E16 INPI BSTA5 FSC05 FSC13 FSC21 FSC29 L21O05 L21O15 L21E05 L21E15 YGS BSTA4 FSC04 FSC12 FSC20 FSC28 L21O04 L21O14 L21E04 L21E14 (1) BSTA3 FSC03 FSC11 FSC19 FSC27 L21O03 L21O13 L21E03 L21E13 SCBW BSTA2 FSC02 FSC10 FSC18 FSC26 L21O02 L21O12 L21E02 L21E12 PAL BSTA1 FSC01 FSC09 FSC17 FSC25 L21O01 L21O11 L21E01 L21E11 FISE BSTA0 FSC00 FSC08 FSC16 FSC24 L21O00 L21O10 L21E00 L21E10 (1) (1) (1) (1) (1) (1) (1) (1) HTRIG7 HTRIG10 NVTRIG CCEN1 ADWHS7 HTRIG6 HTRIG9 BLCKON CCEN0 ADWHS6 HTRIG5 HTRIG8 PHRES1 TTXEN ADWHS5 HTRIG4 VTRIG4 PHRES0 SCCLN4 ADWHS4 HTRIG3 VTRIG3 LDEL1 SCCLN3 ADWHS3 HTRIG2 VTRIG2 LDEL0 SCCLN2 ADWHS2 HTRIG1 VTRIG1 FLC1 SCCLN1 ADWHS1 HTRIG0 VTRIG0 FLC0 SCCLN0 ADWHS0 71 ADWHE7 ADWHE6 ADWHE5 ADWHE4 ADWHE3 ADWHE2 ADWHE1 ADWHE0 72 (1) 73 74 75 76 77 TTXHS7 ADWHE9 TTXHS5 ADWHE8 TTXHS4 (1) TTX request horizontal start TTX request horizontal delay CSYNC advance TTX odd request vertical start TTX odd request vertical end ADWHE10 TTXHS6 (1) (1) (1) (1) ADWHS10 TTXHS2 TTXHD2 ADWHS9 TTXHS1 TTXHD1 ADWHS8 TTXHS0 TTXHD0 (1) (1) (1) TTXOVS2 TTXOVE2 TTXOVS1 TTXOVE1 TTXOVS0 TTXOVE0 CSYNCA4 TTXOVS7 TTXOVE7 (1) CSYNCA3 CSYNCA2 CSYNCA1 TTXOVS6 TTXOVS5 TTXOVS4 TTXOVE6 TTXOVE5 TTXOVE4 TTXHS3 TTXHD3 CSYNCA0 TTXOVS3 TTXOVE3 Product specification D5 SAA7108AE; SAA7109AE D6 Philips Semiconductors 110 D7 HD-CODEC 2004 Jun 29 SUB ADDR. (HEX) REGISTER FUNCTION This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... D4 D3 D2 D1 D0 TTX even request vertical start TTX even request vertical end 78 79 TTXEVS7 TTXEVE7 TTXEVS6 TTXEVE6 TTXEVS5 TTXEVE5 TTXEVS4 TTXEVE4 TTXEVS3 TTXEVE3 TTXEVS2 TTXEVE2 TTXEVS1 TTXEVE1 TTXEVS0 TTXEVE0 First active line Last active line TTX mode, MSB vertical 7A 7B 7C FAL7 LAL7 TTX60 FAL6 LAL6 LAL8 FAL5 LAL5 TTXO FAL4 LAL4 FAL8 FAL3 LAL3 TTXEVE8 FAL2 LAL2 TTXOVE8 FAL1 LAL1 TTXEVS8 FAL0 LAL0 TTXOVS8 Null Disable TTX line Disable TTX line FIFO status (read only) 7D 7E 7F 80 (1) (1) (1) (1) (1) (1) (1) (1) LINE12 LINE20 LINE11 LINE19 LINE10 LINE18 LINE9 LINE17 LINE8 LINE16 LINE7 LINE15 LINE6 LINE14 LINE5 LINE13 (1) (1) (1) (1) PCL07 PCL15 PCL23 DCLK EIDIV PCL06 PCL14 PCL22 PCLSY PCL05 PCL13 PCL21 IFRA PCL04 PCL12 PCL20 IFBP (1) (1) (1) IFERR PCL03 PCL11 PCL19 PCLE1 FILI3 BFERR PCL02 PCL10 PCL18 PCLE0 FILI2 OVFL PCL01 PCL09 PCL17 PCLI1 FILI1 UDFL PCL00 PCL08 PCL16 PCLI0 FILI0 (1) (1) (1) (1) (1) (1) (1) (1) XOFS7 XPIX7 YOFSO7 YOFSE7 YOFSE9 YPIX7 EFS HFS HLEN7 IDEL3 XINC7 YINC7 YINC11 XOFS6 XPIX6 YOFSO6 YOFSE6 YOFSE8 YPIX6 PCBN VFS HLEN6 IDEL2 XINC6 YINC6 YINC10 XOFS5 XPIX5 YOFSO5 YOFSE5 YOFSO9 YPIX5 SLAVE OFS HLEN5 IDEL1 XINC5 YINC5 YINC9 XOFS4 XPIX4 YOFSO4 YOFSE4 YOFSO8 YPIX4 ILC PFS HLEN4 IDEL0 XINC4 YINC4 YINC8 XOFS3 XPIX3 YOFSO3 YOFSE3 XPIX9 YPIX3 YFIL OVS HLEN3 HLEN11 XINC3 YINC3 XINC11 XOFS2 XPIX2 YOFSO2 YOFSE2 XPIX8 YPIX2 XOFS1 XPIX1 YOFSO1 YOFSE1 XOFS9 YPIX1 YPIX9 OHS HLEN1 HLEN9 XINC1 YINC1 XINC9 XOFS0 XPIX0 YOFSO0 YOFSE0 XOFS8 YPIX0 YPIX8 PHS HLEN0 HLEN8 XINC0 YINC0 XINC8 Pixel clock 0 Pixel clock 1 Pixel clock 2 Pixel clock control FIFO control Null Horizontal offset Pixel number Vertical offset odd Vertical offset even MSBs Line number Scaler CTRL, MCB YPIX Sync control Line length Input delay, MSB line length Horizontal increment Vertical increment MSBs vertical and horizontal increment Weighting factor odd Weighting factor even Weighting factor MSB 81 82 83 84 85 86 to 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F YIWGTO7 YIWGTO6 YIWGTO5 YIWGTE7 YIWGTE6 YIWGTE5 YIWGTE11 YIWGTE10 YIWGTE9 (1) PVS HLEN2 HLEN10 XINC2 YINC2 XINC10 YIWGTO4 YIWGTO3 YIWGTO2 YIWGTO1 YIWGTE4 YIWGTE3 YIWGTE2 YIWGTE1 YIWGTE8 YIWGTO11 YIWGTO10 YIWGTO9 YIWGTO0 YIWGTE0 YIWGTO8 Product specification D5 SAA7108AE; SAA7109AE D6 Philips Semiconductors 111 D7 HD-CODEC 2004 Jun 29 SUB ADDR. (HEX) REGISTER FUNCTION This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... D4 Vertical line skip Blank enable for NI-bypass, vertical line skip MSB A0 A1 YSKIP7 BLEN YSKIP6 YSKIP5 YSKIP4 YSKIP3 YSKIP2 YSKIP1 YSKIP0 (1) (1) (1) YSKIP11 YSKIP10 YSKIP9 YSKIP8 Border colour Y Border colour U Border colour V HD sync line count array HD sync line type array HD sync line pattern array HD sync value array HD sync trigger state 1 HD sync trigger state 2 HD sync trigger state 3 HD sync trigger state 4 HD sync trigger phase x A2 A3 A4 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 BCY7 BCU7 BCV7 BCY6 BCU6 BCV6 BCY5 BCU5 BCV5 BCY1 BCU1 BCV1 BCY0 BCU0 BCV0 HLCT7 HLCPT3 HDCT7 HTX7 HLCT6 HLCPT2 HDCT6 HEPT2 HTX6 (1) (1) HTY7 HTY6 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) CC1R7 CC1G7 CC1B7 CC2R7 CC2G7 CC2B7 AUXR7 AUXG7 AUXB7 XCP7 XHS4 YCP7 YHS4 CC1R6 CC1G6 CC1B6 CC2R6 CC2G6 CC2B6 AUXR6 AUXG6 AUXB6 XCP6 XHS3 YCP6 YHS3 CC1R5 CC1G5 CC1B5 CC2R5 CC2G5 CC2B5 AUXR5 AUXG5 AUXB5 XCP5 XHS2 YCP5 YHS2 CC1R4 CC1G4 CC1B4 CC2R4 CC2G4 CC2B4 AUXR4 AUXG4 AUXB4 XCP4 XHS1 YCP4 YHS1 HDSYE CC1R3 CC1G3 CC1B3 CC2R3 CC2G3 CC2B3 AUXR3 AUXG3 AUXB3 XCP3 XHS0 YCP3 YHS0 HDTC CC1R2 CC1G2 CC1B2 CC2R2 CC2G2 CC2B2 AUXR2 AUXG2 AUXB2 XCP2 XCP10 YCP2 HLCT1 HLCT9 HDCT1 HDCT9 HTX1 HTX9 HTY1 HTY9 HDGY CC1R1 CC1G1 CC1B1 CC2R1 CC2G1 CC2B1 AUXR1 AUXG1 AUXB1 XCP1 XCP9 YCP1 HLCT0 HLCT8 HDCT0 HDCT8 HTX0 HTX8 HTY0 HTY8 HDIP CC1R0 CC1G0 CC1B0 CC2R0 CC2G0 CC2B0 AUXR0 AUXG0 AUXB0 XCP0 XCP8 YCP0 (1) YCP9 YCP8 HD sync trigger phase y HD output control Cursor colour 1 R Cursor colour 1 G Cursor colour 1 B Cursor colour 2 R Cursor colour 2 G Cursor colour 2 B Auxiliary cursor colour R Auxiliary cursor colour G Auxiliary cursor colour B Horizontal cursor position Horizontal hot spot, MSB XCP Vertical cursor position Vertical hot spot, MSB YCP DA DB DC F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC (1) D3 D2 BCY4 BCY3 BCY2 BCU4 BCU3 BCU2 BCV4 BCV3 BCV2 RAM address (see Table 123) RAM address (see Table 125) RAM address (see Table 127) RAM address (see Table 129) HLCT5 HLCT4 HLCT3 HLCT2 HLCPT1 HLCPT0 HLPPT1 HLPPT0 HDCT5 HDCT4 HDCT3 HDCT2 (1) (1) HEPT1 HEPT0 HTX5 HTX4 HTX3 HTX2 (1) (1) HTX11 HTX10 HTY5 HTY4 HTY3 HTY2 D1 D0 Product specification D5 SAA7108AE; SAA7109AE D6 Philips Semiconductors 112 D7 HD-CODEC 2004 Jun 29 SUB ADDR. (HEX) REGISTER FUNCTION This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... D6 D5 Input path control FD LUTOFF CMODE LUTL Cursor bit map Colour look-up table FE FF D4 D3 D2 D1 D0 IF2 IF1 IF0 MATOFF DFOFF RAM address (see Table 144) RAM address (see Table 145) Note Philips Semiconductors D7 HD-CODEC 2004 Jun 29 SUB ADDR. (HEX) REGISTER FUNCTION 1. All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements. 113 Product specification SAA7108AE; SAA7109AE Philips Semiconductors Product specification HD-CODEC 18.1.1 SAA7108AE; SAA7109AE I2C-BUS FORMAT Table 51 I2C-bus write access to control registers; see Table 57 S 10001000 A SUBADDRESS A DATA 0 A -------- DATA n A P DATA n A P DATA n A P -------- P Table 52 I2C-bus write access to the HD line count array (subaddress D0H); see Table 57 S 1 0 0 0 1 0 0 0 A D0H A RAM ADDRESS A DATA 00 A DATA 01 A -------- Table 53 I2C-bus write access to cursor bit map (subaddress FEH); see Table 57 S 1 0 0 0 1 0 0 0 A FEH A RAM ADDRESS A DATA 0 A -------- Table 54 I2C-bus write access to colour look-up table (subaddress FFH); see Table 57 S 10001000 A FFH A RAM ADDRESS A DATA 0R A DATA 0G A DATA 0B A Table 55 I2C-bus read access to control registers; see Table 57 S 10001000 A SUBADDRESS A Sr 1 0 0 0 1 0 0 1 A DATA 0 Am -------- DATA n Am P Table 56 I2C-bus read access to cursor bit map or colour LUT; see Table 57 S 1 0 0 0 1 0 0 0 A FEH A RAM ADDRESS A Sr 1 0 0 0 1 0 0 1 A DATA 0 Am -------- DATA n Am P or FFH Table 57 Explanations of Tables 51 to 56 CODE DESCRIPTION S START condition Sr repeated START condition 1 0 0 0 1 0 0 X; note 1 slave address A acknowledge generated by the slave Am acknowledge generated by the master SUBADDRESS; note 2 subaddress byte DATA data byte -------- continued data bytes and acknowledges P STOP condition RAM ADDRESS start address for RAM access Notes 1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read. 2. If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed. 2004 Jun 29 114 Philips Semiconductors Product specification HD-CODEC 18.1.2 SAA7108AE; SAA7109AE SLAVE RECEIVER Table 58 Subaddress 16H DATA BYTE DACF DESCRIPTION output level adjustment fine in 1 % steps for all DACs; default after reset is 00H; see Table 59 Table 59 Fine adjustment of DAC output voltage BINARY GAIN (%) 0111 7 0110 6 0101 5 0100 4 0011 3 0010 2 0001 1 0000 0 1000 0 1001 −1 1010 −2 1011 −3 1100 −4 1101 −5 1110 −6 1111 −7 Table 60 Subaddresses 17H to 19H DATA BYTE DESCRIPTION RDACC output level coarse adjustment for RED DAC; default after reset is 1BH for output of C signal 00000b ≡ 0.585 V to 11111b ≡ 1.240 V at 37.5 Ω nominal for full-scale conversion GDACC output level coarse adjustment for GREEN DAC; default after reset is 1BH for output of VBS signal 00000b ≡ 0.585 V to 11111b ≡ 1.240 V at 37.5 Ω nominal for full-scale conversion BDACC output level coarse adjustment for BLUE DAC; default after reset is 1FH for output of CVBS signal 00000b ≡ 0.585 V to 11111b ≡ 1.240 V at 37.5 Ω nominal for full-scale conversion Table 61 Subaddress 1AH DATA BYTE MSMT 2004 Jun 29 DESCRIPTION monitor sense mode threshold for DAC output voltage, should be set to 70 115 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 62 Subaddress 1BH DATA BYTE MSM MSA MSOE LOGIC LEVEL DESCRIPTION 0 monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default after reset 1 monitor sense mode on 0 automatic monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default after reset 1 automatic monitor sense mode on if MSM = 0 0 pin TVD is active 1 pin TVD is 3-state; default after reset RCOMP (read only) 0 check comparator at DAC on pin RED_CR_C_CVBS is active, output is loaded 1 check comparator at DAC on pin RED_CR_C_CVBS is inactive, output is not loaded GCOMP (read only) 0 check comparator at DAC on pin GREEN_VBS_CVBS is active, output is loaded 1 check comparator at DAC on pin GREEN_VBS_CVBS is inactive, output is not loaded BCOMP (read only) 0 check comparator at DAC on pin BLUE_CB_CVBS is active, output is loaded 1 check comparator at DAC on pin BLUE_CB_CVBS is inactive, output is not loaded Table 63 Subaddresses 26H and 27H DATA BYTE WSS LOGIC LEVEL − DESCRIPTION wide screen signalling bits 3 to 0 = aspect ratio 7 to 4 = enhanced services 10 to 8 = subtitles 13 to 11 = reserved WSSON 0 wide screen signalling output is disabled; default after reset 1 wide screen signalling output is enabled Table 64 Subaddress 28H DATA BYTE BS LOGIC LEVEL − DESCRIPTION REMARKS starting point of burst in clock cycles PAL: BS = 33 (21H); default after reset if strapping pin FSVGC tied to HIGH NTSC: BS = 25 (19H); default after reset if strapping pin FSVGC tied to LOW 2004 Jun 29 116 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 65 Subaddress 29H DATA BYTE SRES BE LOGIC LEVEL DESCRIPTION REMARKS 0 pin TTX_SRES accepts a teletext bit stream (TTX) default after reset 1 pin TTX_SRES accepts a sync reset input (SRES) a HIGH impulse resets synchronization of the encoder (first field, first line) − ending point of burst in clock cycles PAL: BE = 29 (1DH); default after reset if strapping pin FSVGC tied to HIGH NTSC: BE = 29 (1DH); default after reset if strapping pin FSVGC tied to LOW Table 66 Subaddresses 2AH to 2CH DATA BYTE CG CGEN LOGIC LEVEL − DESCRIPTION LSB of the respective bytes are encoded immediately after run-in, the MSBs of the respective bytes have to carry the CRCC bits, in accordance with the definition of copy generation management system encoding format. 0 copy generation data output is disabled; default after reset 1 copy generation data output is enabled Table 67 Subaddress 2DH DATA BYTE VBSEN CVBSEN1 CVBSEN0 CEN ENCOFF CLK2EN CVBSEN2 2004 Jun 29 LOGIC LEVEL DESCRIPTION 0 pin GREEN_VBS_CVBS provides a component GREEN signal (CVBSEN1 = 0) or CVBS signal (CVBSEN1 = 1) 1 pin GREEN_VBS_CVBS provides a luminance (VBS) signal; default after reset 0 pin GREEN_VBS_CVBS provides a component GREEN (G) or luminance (VBS) signal; default after reset 1 pin GREEN_VBS_CVBS provides a CVBS signal 0 pin BLUE_CB_CVBS provides a component BLUE (B) or colour difference BLUE (CB) signal 1 pin BLUE_CB_CVBS provides a CVBS signal; default after reset 0 pin RED_CR_C_CVBS provides a component RED (R) or colour difference RED (CR) signal 1 pin RED_CR_C_CVBS provides a chrominance signal (C) as modulated subcarrier for S-video; default after reset 0 encoder is active; default after reset 1 encoder bypass, DACs are provided with RGB signal after cursor insertion block 0 pin TTXRQ_XCLKO2 provides a teletext request signal (TTXRQ) 1 pin TTXRQ_XCLKO2 provides the buffered crystal clock divided by two (13.5 MHz); default after reset 0 pin RED_CR_C_CVBS provides a signal according to CEN; default after reset 1 pin RED_CR_C_CVBS provides a CVBS signal 117 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 68 Subaddress 37H DATA BYTE LOGIC LEVEL YUPSC DESCRIPTION 0 normal operation of the vertical scaler; default after reset 1 vertical upscaling is enabled YFIL − controls the vertical interpolation filter, see Table 69; the filter is not available if YUPSC = 1 CZOOM 0 normal operation of the cursor generator; default after reset 1 the cursor will be zoomed by a factor of 2 in both directions 0 expected input level swing is 16 to 235 (8-bit RGB); default after reset 1 expected input level swing is 0 to 255 (8-bit RGB) 0 no horizontal interpolation filter; default after reset 1 interpolation filter for horizontal upscaling is active IGAIN XINT Table 69 Logic levels and function of YFIL DATA BYTE DESCRIPTION YFIL1 YFIL0 0 0 no filter active; default after reset 0 1 filter is inserted before vertical scaling 1 0 filter is inserted after vertical scaling; YSKIP should be logic 0 1 1 reserved Table 70 Subaddresses 38H and 39H DATA BYTE DESCRIPTION GY4 to GY0 Gain luminance of RGB (CR, Y and CB) output, ranging from (1 − 16⁄32) to (1 + 15⁄32). Suggested nominal value = 0, depending on external application. GCD4 to GCD0 Gain colour difference of RGB (CR, Y and CB) output, ranging from (1 − 16⁄32) to (1 + 15⁄32). Suggested nominal value = 0, depending on external application. Table 71 Subaddress 3AH DATA BYTE CBENB LOGIC LEVEL DESCRIPTION 0 data from input ports is encoded 1 colour bar with fixed colours is encoded SYNTV 0 in slave mode, the encoder is only synchronized at the beginning of an odd field; default after reset 1 in slave mode, the encoder receives a vertical sync signal SYMP 0 horizontal and vertical trigger is taken from FSVGC or both VSVGC and HSVGC; default after reset 1 horizontal and vertical trigger is decoded out of “ITU-R BT.656” compatible data at PD port 2004 Jun 29 118 Philips Semiconductors Product specification HD-CODEC DATA BYTE DEMOFF CSYNC Y2C UV2C SAA7108AE; SAA7109AE LOGIC LEVEL DESCRIPTION 0 Y-CB-CR to RGB dematrix is active; default after reset 1 Y-CB-CR to RGB dematrix is bypassed 0 pin HSM_CSYNC provides a horizontal sync for non-interlaced VGA components output (at PIXCLK) 1 pin HSM_CSYNC provides a composite sync for interlaced components output (at XTAL clock) 0 input luminance data is twos complement from PD input port 1 input luminance data is straight binary from PD input port; default after reset 0 input colour difference data is twos complement from PD input port 1 input colour difference data is straight binary from PD input port; default after reset Table 72 Subaddress 54H DATA BYTE LOGIC LEVEL DESCRIPTION VPSEN 0 1 video programming system data insertion in line 16 is enabled GPVAL 0 pin VSM provides a LOW level if GPEN = 1 1 pin VSM provides a HIGH level if GPEN = 1 0 pin VSM provides a vertical sync for a monitor; default after reset 1 pin VSM provides a constant signal according to GPVAL 0 input data is sampled with inverse clock edges 1 input data is sampled with the clock edges specified in Tables 9 to 14; default after reset 0 normal assignment of the input data to the clock edge; default after reset 1 correct time misalignment due to inverted assignment of input data to the clock edge GPEN EDGE SLOT video programming system data insertion is disabled; default after reset Table 73 Subaddresses 55H to 59H DATA BYTE DESCRIPTION REMARKS VPS5 fifth byte of video programming system data VPS11 eleventh byte of video programming system data VPS12 twelfth byte of video programming system data VPS13 thirteenth byte of video programming system data VPS14 fourteenth byte of video programming system data 2004 Jun 29 119 in line 16; LSB first; all other bytes are not relevant for VPS Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 74 Subaddress 5AH; note 1 DATA BYTE CHPS DESCRIPTION VALUE RESULT phase of encoded colour subcarrier (including burst) relative to horizontal sync; can be adjusted in steps of 360/256 degrees 6BH PAL B/G and data from input ports in master mode 16H PAL B/G and data from look-up table 25H NTSC M and data from input ports in master mode 46H NTSC M and data from look-up table Note 1. The default value after reset is 00H. Table 75 Subaddresses 5BH and 5DH DATA BYTE GAINU DESCRIPTION variable gain for CB signal; input representation in accordance with “ITU-R BT.601” CONDITIONS REMARKS white-to-black = 92.5 IRE GAINU = −2.17 × nominal to +2.16 × nominal GAINU = 0 output subcarrier of U contribution = 0 GAINU = 118 (76H) output subcarrier of U contribution = nominal white-to-black = 100 IRE GAINU = −2.05 × nominal to +2.04 × nominal GAINU = 0 output subcarrier of U contribution = 0 GAINU = 125 (7DH) output subcarrier of U contribution = nominal Table 76 Subaddresses 5CH and 5EH DATA BYTE GAINV DESCRIPTION variable gain for CR signal; input representation in accordance with “ITU-R BT.601” CONDITIONS REMARKS white-to-black = 92.5 IRE GAINV = −1.55 × nominal to +1.55 × nominal GAINV = 0 output subcarrier of V contribution = 0 GAINV = 165 (A5H) output subcarrier of V contribution = nominal white-to-black = 100 IRE GAINV = −1.46 × nominal to +1.46 × nominal GAINV = 0 output subcarrier of V contribution = 0 GAINV = 175 (AFH) output subcarrier of V contribution = nominal Table 77 Subaddress 5DH DATA BYTE BLCKL DESCRIPTION variable black level; input representation in accordance with “ITU-R BT.601” CONDITIONS REMARKS white-to-sync = 140 IRE; note 1 recommended value: BLCKL = 58 (3AH) BLCKL = 0; note 1 output black level = 29 IRE BLCKL = 63 (3FH); note 1 output black level = 49 IRE white-to-sync = 143 IRE; note 2 recommended value: BLCKL = 51 (33H) BLCKL = 0; note 2 output black level = 27 IRE BLCKL = 63 (3FH); note 2 output black level = 47 IRE Notes 1. Output black level/IRE = BLCKL × 2/6.29 + 28.9. 2. Output black level/IRE = BLCKL × 2/6.18 + 26.5. 2004 Jun 29 120 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 78 Subaddress 5EH DATA BYTE BLNNL DESCRIPTION variable blanking level CONDITIONS REMARKS white-to-sync = 140 IRE; note 1 recommended value: BLNNL = 46 (2EH) BLNNL = 0; note 1 output blanking level = 25 IRE BLNNL = 63 (3FH); note 1 output blanking level = 45 IRE white-to-sync = 143 IRE; note 2 recommended value: BLNNL = 53 (35H) BLNNL = 0; note 2 output blanking level = 26 IRE BLNNL = 63 (3FH); note 2 output blanking level = 46 IRE Notes 1. Output black level/IRE = BLNNL × 2/6.29 + 25.4. 2. Output black level/IRE = BLNNL × 2/6.18 + 25.9; default after reset: 35H. Table 79 Subaddress 5FH DATA BYTE DESCRIPTION CCRS select cross-colour reduction filter in luminance; see Table 80 BLNVB variable blanking level during vertical blanking interval is typically identical to value of BLNNL Table 80 Logic levels and function of CCRS CCRS1 CCRS0 DESCRIPTION 0 0 no cross-colour reduction; for overall transfer characteristic of luminance see Fig.7 0 1 cross-colour reduction #1 active; for overall transfer characteristic see Fig.7 1 0 cross-colour reduction #2 active; for overall transfer characteristic see Fig.7 1 1 cross-colour reduction #3 active; for overall transfer characteristic see Fig.7 Table 81 Subaddress 61H DATA BYTE DOWND LOGIC LEVEL DESCRIPTION 0 digital core in normal operational mode; default after reset 1 digital core in sleep mode and is reactivated with an I2C-bus address DOWNA 0 DACs in normal operational mode; default after reset 1 DACs in Power-down mode INPI 0 PAL switch phase is nominal; default after reset 1 PAL switch is inverted compared to nominal if RTCE = 1 0 luminance gain for white − black 100 IRE 1 luminance gain for white − black 92.5 IRE including 7.5 IRE set-up of black 0 enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 5 and 6) 1 standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 5 and 6); default after reset YGS SCBW 2004 Jun 29 121 Philips Semiconductors Product specification HD-CODEC DATA BYTE SAA7108AE; SAA7109AE LOGIC LEVEL DESCRIPTION PAL 0 NTSC encoding (non-alternating V component) 1 PAL encoding (alternating V component) FISE 0 864 total pixel clocks per line 1 858 total pixel clocks per line Table 82 Subaddress 62H DATA BYTE RTCE BSTA LOGIC LEVEL DESCRIPTION CONDITIONS REMARKS 0 no real-time control of generated subcarrier frequency; default after reset 1 real-time control of generated subcarrier frequency through a Philips video decoder; for a specification of the RTC protocol see document “RTC Functional Description”, available on request − recommended value: amplitude of colour burst; input white-to-black = 92.5 IRE; representation in accordance burst = 40 IRE; NTSC encoding BSTA = 63 (3FH) with “ITU-R BT.601” BSTA = 0 to 2.02 × nominal white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding recommended value: BSTA = 45 (2DH) BSTA = 0 to 2.82 × nominal white-to-black = 100 IRE; recommended value: burst = 43 IRE; NTSC encoding BSTA = 67 (43H) BSTA = 0 to 1.90 × nominal white-to-black = 100 IRE; burst = 43 IRE; PAL encoding BSTA = 0 to 3.02 × nominal recommended value: BSTA = 47 (2FH); default after reset Table 83 Subaddresses 63H to 66H (four bytes to program subcarrier frequency) DATA BYTE FSC0 to FSC3 DESCRIPTION CONDITIONS REMARKS ffsc = subcarrier frequency (in multiples of line frequency); fllc = clock frequency (in multiples of line frequency) f fsc 32 FSC = round -------- × 2 ; f llc FSC3 = most significant byte; FSC0 = least significant byte note 1 Note 1. Examples: a) NTSC M: ffsc = 227.5, fllc = 1716 → FSC = 569408543 (21F07C1FH). b) PAL B/G: ffsc = 283.7516, fllc = 1728 → FSC = 705268427 (2A098ACBH). Table 84 Subaddresses 67H to 6AH DATA BYTE L21O0 L21O1 L21E0 L21E1 2004 Jun 29 DESCRIPTION REMARKS first byte of captioning data, odd field LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes second byte of captioning data, odd field have to carry the parity bit, in accordance with the definition first byte of extended data, even field of line 21 encoding format. second byte of extended data, even field 122 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 85 Subaddresses 6CH and 6DH DATA BYTE HTRIG DESCRIPTION sets the horizontal trigger phase related to chip-internal horizontal input values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases delays of all internally generated timing signals; the default value is 0 Table 86 Subaddress 6DH DATA BYTE VTRIG DESCRIPTION sets the vertical trigger phase related to chip-internal vertical input increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines; variation range of VTRIG = 0 to 31 (1FH); the default value is 0 Table 87 Subaddress 6EH DATA BYTE LOGIC LEVEL NVTRIG BLCKON DESCRIPTION 0 values of the VTRIG register are positive 1 values of the VTRIG register are negative 0 encoder in normal operation mode; default after reset 1 output signal is forced to blanking level PHRES − selects the phase reset mode of the colour subcarrier generator; see Table 88 LDEL − selects the delay on luminance path with reference to chrominance path; see Table 89 FLC − field length control; see Table 90 Table 88 Logic levels and function of PHRES DATA BYTE DESCRIPTION PHRES1 PHRES0 0 0 no subcarrier reset 0 1 subcarrier reset every two lines 1 0 subcarrier reset every eight fields 1 1 subcarrier reset every four fields Table 89 Logic levels and function of LDEL DATA BYTE DESCRIPTION LDEL1 LDEL0 0 0 no luminance delay; default after reset 0 1 1 LLC luminance delay 1 0 2 LLC luminance delay 1 1 3 LLC luminance delay 2004 Jun 29 123 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 90 Logic levels and function of FLC DATA BYTE DESCRIPTION FLC1 FLC0 0 0 interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset 0 1 non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz 1 0 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz 1 1 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz Table 91 Subaddress 6FH DATA BYTE LOGIC LEVEL DESCRIPTION CCEN − enables individual line 21 encoding; see Table 92 TTXEN 0 disables teletext insertion; default after reset 1 enables teletext insertion − selects the actual line, where Closed Caption or extended data are encoded; line = (SCCLN + 4) for M-systems; line = (SCCLN + 1) for other systems SCCLN Table 92 Logic levels and function of CCEN DATA BYTE DESCRIPTION CCEN1 CCEN0 0 0 line 21 encoding off; default after reset 0 1 enables encoding in field 1 (odd) 1 0 enables encoding in field 2 (even) 1 1 enables encoding in both fields Table 93 Subaddresses 70H to 72H DATA BYTE ADWHS DESCRIPTION active display window horizontal start; defines the start of the active TV display portion after the border colour values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed ADWHE active display window horizontal end; defines the end of the active TV display portion before the border colour values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed Table 94 Subaddress 73H DATA BYTE TTXHS DESCRIPTION start of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0); see Fig.51 REMARKS TTXHS = 42H; is default after reset if strapped to PAL TTXHS = 54H; is default after reset if strapped to NTSC 2004 Jun 29 124 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 95 Subaddress 74H DATA BYTE TTXHD DESCRIPTION REMARKS indicates the delay in clock cycles between rising edge of TTXRQ minimum value: TTXHD = 2; output signal on pin TTXRQ_XCLKO2 (CLK2EN = 0) and valid data at is default after reset pin TTX_SRES Table 96 Subaddress 75H DATA BYTE CSYNCA DESCRIPTION advanced composite sync against RGB output from 0 XTAL clocks to 31 XTAL clocks Table 97 Subaddresses 76H, 77H and 7CH DATA BYTE TTXOVS DESCRIPTION REMARKS first line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in odd field line = (TTXOVS + 4) for M-systems line = (TTXOVS + 1) for other systems TTXOVE last line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in odd field line = (TTXOVE + 3) for M-systems line = TTXOVE for other systems TTXOVS = 05H; is default after reset if strapped to PAL TTXOVS = 06H; is default after reset if strapped to NTSC TTXOVE = 16H; is default after reset if strapped to PAL TTXOVE = 10H; is default after reset if strapped to NTSC Table 98 Subaddresses 78H, 79H and 7CH DATA BYTE TTXEVS DESCRIPTION REMARKS first line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in even field line = (TTXEVS + 4) for M-systems line = (TTXEVS + 1) for other systems TTXEVE last line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in even field line = (TTXEVE + 3) for M-systems line = TTXEVE for other systems TTXEVS = 04H; is default after reset if strapped to PAL TTXEVS = 05H; is default after reset if strapped to NTSC TTXEVE = 16H; is default after reset if strapped to PAL TTXEVE = 10H; is default after reset if strapped to NTSC Table 99 Subaddresses 7AH to 7CH DATA BYTE FAL DESCRIPTION first active line = FAL + 4 for M-systems and FAL + 1 for other systems, measured in lines FAL = 0 coincides with the first field synchronization pulse LAL last active line = LAL + 3 for M-systems and LAL for other system, measured in lines LAL = 0 coincides with the first field synchronization pulse 2004 Jun 29 125 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 100 Subaddress 7CH DATA BYTE TTX60 TTXO LOGIC LEVEL DESCRIPTION 0 enables NABTS (FISE = 1) or European TTX (FISE = 0); default after reset 1 enables world standard teletext 60 Hz (FISE = 1) 0 new teletext protocol selected; at each rising edge of TTXRQ a single teletext bit is requested (see Fig.51); default after reset 1 old teletext protocol selected; the encoder provides a window of TTXRQ going HIGH; the length of the window depends on the chosen teletext standard (see Fig.51) Table 101 Subaddresses 7EH and 7FH DATA BYTE LINE DESCRIPTION individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective bits, disabled line = LINExx (50 Hz field rate) this bit mask is effective only if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE Table 102 Subaddresses 81H to 83H DATA BYTE PCL DESCRIPTION defines the frequency of the synthesized pixel clock PIXCLKO; PCL ×8;f f PIXCLK = ---------×f XTAL = 27 MHz nominal, e.g. 640 × 480 to NTSC M: PCL = 20F63BH; 24- XTAL 2 640 × 480 to PAL B/G: PCL = 1B5A73H (as by strapping pins) Table 103 Subaddress 84H DATA BYTE DCLK PCLSY LOGIC LEVEL DESCRIPTION 0 pixel clock input is differential, pin PIXCLKI receives the inverted clock; default after reset 1 pixel clock input is single ended, pin PIXCLKI has no function 0 pixel clock generator runs free; default after reset 1 pixel clock generator gets synchronized with the vertical sync 0 input FIFO gets reset explicitly at falling edge 1 input FIFO gets reset every field; default after reset 0 input FIFO is active 1 input FIFO is bypassed; default after reset PCLE − controls the divider for the external pixel clock; see Table 104 PCLI − controls the divider for the internal pixel clock; see Table 105 IFRA IFBP 2004 Jun 29 126 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 104 Logic levels and function of PCLE DATA BYTE DESCRIPTION PCLE1 PCLE0 0 0 divider ratio for PIXCLK output is 1 0 1 divider ratio for PIXCLK output is 2; default after reset 1 0 divider ratio for PIXCLK output is 4 1 1 divider ratio for PIXCLK output is 8 Table 105 Logic levels and function of PCLI DATA BYTE DESCRIPTION PCLI1 PCLI0 0 0 divider ratio for internal PIXCLK is 1 0 1 divider ratio for internal PIXCLK is 2; default after reset 1 0 divider ratio for internal PIXCLK is 4 1 1 not allowed Table 106 Subaddress 85H DATA BYTE EIDIV FILI LOGIC LEVEL DESCRIPTION 0 input dividers are off; inputs are high-impedance; default after reset 1 input dividers are on; inputs have lower impedance − threshold for FIFO internal transfers; nominal value is 8; default after reset Table 107 Subaddresses 90H and 94H DATA BYTE XOFS DESCRIPTION horizontal offset; defines the number of PIXCLKs from horizontal sync (HSVGC) output to composite blanking (CBO) output Table 108 Subaddresses 91H and 94H DATA BYTE XPIX DESCRIPTION pixel in X direction; defines half the number of active pixels per input line (identical to the length of CBO pulses) Table 109 Subaddresses 92H and 94H DATA BYTE YOFSO 2004 Jun 29 DESCRIPTION vertical offset in odd field; defines (in the odd field) the number of lines from VSVGC to first line with active CBO; if no LUT data is requested, the first active CBO will be output at YOFSO + 2; usually, YOFSO = YOFSE with the exception of extreme vertical downscaling and interlacing 127 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 110 Subaddresses 93H and 94H DATA BYTE YOFSE DESCRIPTION vertical offset in even field; defines (in the even field) the number of lines from VSVGC to first line with active CBO; if no LUT data is requested, the first active CBO will be output at YOFSE + 2; usually, YOFSE = YOFSO with the exception of extreme vertical downscaling and interlacing Table 111 Subaddresses 95H and 96H DATA BYTE YPIX DESCRIPTION defines the number of requested input lines from the feeding device; number of requested lines = YPIX + YOFSE − YOFSO Table 112 Subaddress 96H DATA BYTE EFS PCBN SLAVE ILC YFIL LOGIC LEVEL DESCRIPTION 0 frame sync signal at pin FSVGC ignored in slave mode 1 frame sync signal at pin FSVGC accepted in slave mode 0 normal polarity of CBO signal (HIGH during active video) 1 inverted polarity of CBO signal (LOW during active video) 0 the SAA7108AE; SAA7109AE is timing master to the graphics controller 1 the SAA7108AE; SAA7109AE is timing slave to the graphics controller 0 if hardware cursor insertion is active, set LOW for non-interlaced input signals 1 if hardware cursor insertion is active, set HIGH for interlaced input signals 0 luminance sharpness booster disabled 1 luminance sharpness booster enabled Table 113 Subaddress 97H DATA BYTE HFS VFS OFS PFS OVS 2004 Jun 29 LOGIC LEVEL DESCRIPTION 0 horizontal sync is directly derived from input signal (slave mode) at pin HSVGC 1 horizontal sync is derived from a frame sync signal (slave mode) at pin FSVGC (only if EFS is set HIGH) 0 vertical sync (field sync) is directly derived from input signal (slave mode) at pin VSVGC 1 vertical sync (field sync) is derived from a frame sync signal (slave mode) at pin FSVGC (only if EFS is set HIGH) 0 pin FSVGC is switched to input 1 pin FSVGC is switched to active output 0 polarity of signal at pin FSVGC in output mode (master mode) is active HIGH; rising edge of the input signal is used in slave mode 1 polarity of signal at pin FSVGC in output mode (master mode) is active LOW; falling edge of the input signal is used in slave mode 0 pin VSVGC is switched to input 1 pin VSVGC is switched to active output 128 Philips Semiconductors Product specification HD-CODEC DATA BYTE PVS OHS PHS SAA7108AE; SAA7109AE LOGIC LEVEL DESCRIPTION 0 polarity of signal at pin VSVGC in output mode (master mode) is active HIGH; rising edge of the input signal is used in slave mode 1 polarity of signal at pin VSVGC in output mode (master mode) is active LOW; falling edge of the input signal is used in slave mode 0 pin HSVGC is switched to input 1 pin HSVGC is switched to active output 0 polarity of signal at pin HSVGC in output mode (master mode) is active HIGH; rising edge of the input signal is used in slave mode 1 polarity of signal at pin HSVGC in output mode (master mode) is active LOW; falling edge of the input signal is used in slave mode Table 114 Subaddresses 98H and 99H DATA BYTE HLEN DESCRIPTION number of PIXCLKs horizontal length; HLEN = ----------------------------------------------------- – 1 line Table 115 Subaddress 99H DATA BYTE IDEL DESCRIPTION input delay; defines the distance in PIXCLKs between the active edge of CBO and the first received valid pixel Table 116 Subaddresses 9AH and 9CH DATA BYTE XINC DESCRIPTION number of output pixels -------------------------------------------------------------line incremental fraction of the horizontal scaling engine; XINC = -------------------------------------------------------------- × 4096 number of input pixels ---------------------------------------------------------line Table 117 Subaddresses 9BH and 9CH DATA BYTE YINC DESCRIPTION number of active output lines incremental fraction of the vertical scaling engine; YINC = ---------------------------------------------------------------------------- × 4096 number of active input lines Table 118 Subaddresses 9DH and 9FH DATA BYTE YIWGTO 2004 Jun 29 DESCRIPTION YINC weighting factor for the first line of the odd field; YIWGTO = -------------- + 2048 2 129 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 119 Subaddresses 9EH and 9FH DATA BYTE YIWGTE DESCRIPTION YINC – YSKIP weighting factor for the first line of the even field; YIWGTE = -------------------------------------2 Table 120 Subaddresses A0H and A1H DATA BYTE YSKIP DESCRIPTION vertical line skip; defines the effectiveness of the anti-flicker filter; YSKIP = 0: most effective; YSKIP = 4095: anti-flicker filter switched off Table 121 Subaddress A1H DATA BYTE BLEN LOGIC LEVEL DESCRIPTION 0 no internal blanking for non-interlaced graphics in bypass mode; default after reset 1 forced internal blanking for non-interlaced graphics in bypass mode Table 122 Subaddresses A2H to A4H DATA BYTE BCY, BCU and BCV DESCRIPTION luminance and colour difference portion of border colour in underscan area Table 123 Subaddress D0H DATA BYTE DESCRIPTION HLCA RAM start address for the HD sync line count array; the byte following subaddress D0 points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition. Each line count array entry consists of 2 bytes; see Table 124. The array has 15 entries. HLC HD line counter. The system will repeat the pattern described in ‘HLT’ HLC times and then start with the next entry in line count array. HLT HD line type pointer. If not 0, the value points into the line type array, index HLT − 1 with the description of the current line. 0 means the entry is not used. Table 124 Layout of the data bytes in the line count array BYTE DESCRIPTION 0 HLC7 HLC6 HLC5 HLC4 HLC3 HLC2 HLC1 HLC0 1 HLT3 HLT2 HLT1 HLT0 0 0 HLC9 HLC8 2004 Jun 29 130 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 125 Subaddress D1H DATA BYTE DESCRIPTION HLTA RAM start address for the HD sync line type array; the byte following subaddress D1 points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition. Each line type array entry consists of 4 bytes; see Table 126. The array has 15 entries. HLP HD line type; if not 0, the value points into the line pattern array. The index used is HLP − 1. It consists of value-duration pairs. Each entry consists of 8 pointers, used from index 0 to 7. The value 0 means that the entry is not used. Table 126 Layout of the data bytes in the line type array BYTE DESCRIPTION 0 0 HLP12 HLP11 HLP10 0 HLP02 HLP01 HLP00 1 0 HLP32 HLP31 HLP30 0 HLP22 HLP21 HLP20 2 0 HLP52 HLP51 HLP50 0 HLP42 HLP41 HLP40 3 0 HLP72 HLP71 HLP70 0 HLP62 HLP61 HLP60 Table 127 Subaddress D2H DATA BYTE DESCRIPTION HLPA RAM start address for the HD sync line pattern array; the byte following subaddress D2 points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition. Each line pattern array entry consists of 4 value-duration pairs occupying 2 bytes; see Table 128. The array has 7 entries. HPD HD pattern duration. The value defines the time in pixel clocks (HPD + 1) the corresponding value HPV is added to the HD output signal. If 0, this entry will be skipped. HPV HD pattern value pointer. This gives the index in the HD value array containing the level to be inserted into the HD output path. If the MSB of HPV is logic 1, the value will only be inserted into the y/green channel of the HD data path, the other channels remain unchanged. Table 128 Layout of the data bytes in the line pattern array BYTE DESCRIPTION 0 HPD07 HPD06 HPD05 HPD04 HPD03 HPD02 HPD01 HPD00 1 HPV03 HPV02 HPV01 HPV00 0 0 HPD09 HPD08 2 HPD17 HPD16 HPD14 HPD14 HPD13 HPD12 HPD11 HPD10 3 HPV13 HPV12 HPV11 HPV10 0 0 HPD19 HPD18 4 HPD27 HPD26 HPD25 HPD24 HPD23 HPD22 HPD21 HPD20 5 HPV23 HPV22 HPV21 HPV20 0 0 HPD29 HPD28 6 HPD37 HPD36 HPD35 HPD34 HPD33 HPD32 HPD31 HPD30 7 HPV33 HPV32 HPV31 HPV30 0 0 HPD39 HPD38 2004 Jun 29 131 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 129 Subaddress D3H DATA BYTE DESCRIPTION HPVA RAM start address for the HD sync value array; the byte following subaddress D3 points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition. Each line pattern array entry consists of 2 bytes. The array has 8 entries. HPVE HD pattern value entry. The HD path will insert a level of (HPV + 52) × 0.66 IRE into the data path. The value is signed 8-bits wide; see Table 130. HHS HD horizontal sync. If the HD engine is active, this value will be provided at pin HSM; see Table 130. HVS HD vertical sync. If the HD engine is active, this value will be provided at pin VSM; see Table 130. Table 130 Layout of the data bytes in the value array BYTE DESCRIPTION 0 HPVE7 HPVE6 HPVE5 HPVE4 HPVE3 HPVE2 HPVE1 HPVE0 1 0 0 0 0 0 0 HVS HHS Table 131 Subaddresses D4H and D5H DATA BYTE DESCRIPTION HLCT state of the HD line counter after trigger, note that it counts backwards HLCPT state of the HD line type pointer after trigger HLPPT state of the HD pattern pointer after trigger Table 132 Subaddresses D6H and D7H DATA BYTE DESCRIPTION HDCT state of the HD duration counter after trigger, note that it counts backwards HEPT state of the HD event type pointer in the line type array after trigger Table 133 Subaddresses D8H and D9H DATA BYTE HTX DESCRIPTION horizontal trigger phase for the HD sync engine in pixel clocks Table 134 Subaddresses DAH and DBH DATA BYTE HTY DESCRIPTION vertical trigger phase for the HD sync engine in input lines Table 135 Subaddress DCH DATA BYTE HDSYE HDTC 2004 Jun 29 LOGIC LEVEL DESCRIPTION 0 the HD sync engine is off; default after reset 1 the HD sync engine is active 0 HD output path processes RGB; default after reset 1 HD output path processes YUV 132 Philips Semiconductors Product specification HD-CODEC DATA BYTE SAA7108AE; SAA7109AE LOGIC LEVEL DESCRIPTION HDGY 0 gain in the HD output path is reduced, insertion of sync pulses is possible; default after reset 1 full level swing at the input causes full level swing at the DACs in HD mode HDIP 0 interpolator for the colour difference signal in the HD output path is active; default after reset 1 interpolator for the colour difference signals in the HD output path is off Table 136 Subaddresses F0H to F2H DATA BYTE CC1R, CC1G and CC1B DESCRIPTION RED, GREEN and BLUE portion of first cursor colour Table 137 Subaddresses F3H to F5H DATA BYTE CC2R, CC2G and CC2B DESCRIPTION RED, GREEN and BLUE portion of second cursor colour Table 138 Subaddresses F6H to F8H DATA BYTE DESCRIPTION AUXR, AUXG and AUXB RED, GREEN and BLUE portion of auxiliary cursor colour Table 139 Subaddresses F9H and FAH DATA BYTE XCP DESCRIPTION horizontal cursor position Table 140 Subaddress FAH DATA BYTE XHS DESCRIPTION horizontal hot spot of cursor Table 141 Subaddresses FBH and FCH DATA BYTE YCP DESCRIPTION vertical cursor position Table 142 Subaddress FCH DATA BYTE YHS 2004 Jun 29 DESCRIPTION vertical hot spot of cursor 133 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 143 Subaddress FDH DATA BYTE LUTOFF CMODE LOGIC LEVEL DESCRIPTION 0 colour look-up table is active 1 colour look-up table is bypassed 0 cursor mode; input colour will be inverted 1 auxiliary cursor colour will be inserted LUTL 0 LUT loading via input data stream is inactive 1 colour and cursor LUTs are loaded via input data stream IF 0 input format is 8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB or CB-Y-CR 1 input format is 5 + 5 + 5-bit 4 : 4 : 4 non-interlaced RGB 2 input format is 5 + 6 + 5-bit 4 : 4 : 4 non-interlaced RGB 3 input format is 8 + 8 + 8-bit 4 : 2 : 2 non-interlaced CB-Y-CR 4 input format is 8 + 8 + 8-bit 4 : 2 : 2 interlaced CB-Y-CR (ITU-R BT.656, 27 MHz clock) (in subaddresses 91H and 94H set XPIX = number of active pixels/line) 5 input format is 8-bit non-interlaced index colour 6 input format is 8 + 8 + 8-bit 4 : 4 : 4 non-interlaced RGB or CB-Y-CR (special bit ordering) 0 RGB to CR-Y-CB matrix is active 1 RGB to CR-Y-CB matrix is bypassed MATOFF DFOFF 0 down formatter (4 : 4 : 4 to 4 : 2 : 2) in input path is active 1 down formatter is bypassed Table 144 Subaddress FEH DATA BYTE CURSA DESCRIPTION RAM start address for cursor bit map; the byte following subaddress FEH points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition Table 145 Subaddress FFH DATA BYTE COLSA DESCRIPTION RAM start address for colour LUT; the byte following subaddress FFH points to the first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing until stop condition In subaddresses 5BH, 5CH, 5DH, 5EH, 62H and D3H all IRE values are rounded up. 2004 Jun 29 134 Philips Semiconductors Product specification HD-CODEC 18.1.3 SAA7108AE; SAA7109AE SLAVE TRANSMITTER Table 146 Slave transmitter (slave address 89H) REGISTER FUNCTION DATA BYTE SUBADDRESS D7 D6 D5 D4 D3 D2 D1 D0 Status byte 00H VER2 VER1 VER0 CCRDO CCRDE 0 FSEQ O_E Chip ID 1CH CID7 CID6 CID5 CID4 CID3 CID2 CID1 CID0 FIFO status 80H 0 0 0 0 0 0 OVFL UDFL Table 147 Subaddress 00H DATA BYTE LOGIC LEVEL DESCRIPTION VER − version identification of the device: it will be changed with all versions of the IC that have different programming models; current version is 101 binary CCRDO 1 Closed Caption bytes of the odd field have been encoded 0 the bit is reset after information has been written to the subaddresses 67H and 68H; it is set immediately after the data has been encoded CCRDE FSEQ O_E 1 Closed Caption bytes of the even field have been encoded 0 the bit is reset after information has been written to the subaddresses 69H and 6AH; it is set immediately after the data has been encoded 1 during first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields) 0 not first field of a sequence 1 during even field 0 during odd field Table 148 Subaddress 1CH DATA BYTE CID DESCRIPTION chip ID of SAA7108AE = 04H; chip ID of SAA7109AE = 05H Table 149 Subaddress 80H DATA BYTE IFERR BFERR OVFL UDFL 2004 Jun 29 LOGIC LEVEL DESCRIPTION 0 normal FIFO state 1 input FIFO overflow/underflow has occurred 0 normal FIFO state 1 buffer FIFO overflow, only if YUPSC = 1 0 no FIFO overflow 1 FIFO overflow has occurred; this bit is reset after this subaddress has been read 0 no FIFO underflow 1 FIFO underflow has occurred; this bit is reset after this subaddress has been read 135 Philips Semiconductors Product specification HD-CODEC 18.2 SAA7108AE; SAA7109AE Digital video decoder part 18.2.1 I2C-BUS FORMAT S SLAVE ADDRESS W ACK-s ACK-s SUBADDRESS ACK-s DATA data transferred (n bytes + acknowledge) P MHB339 a. Write procedure. S SLAVE ADDRESS W ACK-s SUBADDRESS ACK-s Sr SLAVE ADDRESS R ACK-s DATA ACK-m data transferred (n bytes + acknowledge) P MHB340 b. Read procedure (combined). Fig.58 I2C-bus format. Table 150 Description of I2C-bus format; note 1 CODE DESCRIPTION S START condition Sr repeated START condition SLAVE ADDRESS W ‘0100 0010’ (42H, default) or ‘0100 0000’ (40H; note 2) SLAVE ADDRESS R ‘0100 0011’ (43H, default) or ‘0100 0001’ (41H; note 2) ACK-s acknowledge generated by the slave ACK-m acknowledge generated by the master SUBADDRESS subaddress byte; see Tables 151 and 152 DATA data byte; see Table 152; if more than one byte DATA is transmitted the subaddress pointer is automatically incremented P STOP condition X read/write control bit (LSB slave address); X = 0, order to write (the circuit is slave receiver); X = 1, order to read (the circuit is slave transmitter) Notes 1. The SAA7108AE; SAA7109AE supports the ‘fast mode’ I2C-bus specification extension (data rate up to 400 kbits/s). 2. If pin RTCO is strapped to VDDD via a 3.3 kΩ resistor. 2004 Jun 29 136 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 151 Subaddress description and access SUBADDRESS DESCRIPTION 00H chip version F0H to FFH reserved ACCESS (READ/WRITE) read only − Video decoder: 01H to 2FH 01H to 05H front-end part read and write 06H to 19H decoder part read and write 1AH to 1EH reserved 1FH video decoder status byte 20H to 2FH reserved − read only − Audio clock generation: 30H to 3FH 30H to 3AH audio clock generator 3BH to 3FH reserved read and write − General purpose VBI data slicer: 40H to 7FH 40H to 5EH VBI data slicer 5FH reserved 60H to 62H VBI data slicer status 63H to 7FH reserved read and write − read only − X port, I port and the scaler: 80H to EFH 80H to 8FH task independent global settings read and write 90H to BFH task A definition read and write C0H to EFH task B definition read and write 2004 Jun 29 137 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... SUB ADDR. (HEX) D7 D6 D5 D4 D3 D2 D1 D0 00 ID7 ID6 ID5 ID4 − − − − Chip version: register 00H Chip version (read only) Video decoder: registers 01H to 2FH Philips Semiconductors REGISTER FUNCTION HD-CODEC 2004 Jun 29 Table 152 I2C-bus receiver/transmitter overview FRONT-END PART: REGISTERS 01H TO 05H Increment delay 01 (1) (1) (1) (1) IDEL3 IDEL2 IDEL1 IDEL0 Analog input control 1 02 FUSE1 FUSE0 GUDL1 GUDL0 MODE3 MODE2 MODE1 MODE0 Analog input control 2 03 (1) HLNRS VBSL WPOFF HOLDG GAFIX GAI28 GAI18 Analog input control 3 04 GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10 Analog input control 4 05 GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20 DECODER PART: REGISTERS 06H TO 2FH 138 Horizontal sync start 06 HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 HSB0 Horizontal sync stop 07 HSS7 HSS6 HSS5 HSS4 HSS3 HSS2 HSS1 HSS0 Sync control 08 AUFD FSEL FOET HTC1 HTC0 HPLL VNOI1 VNOI0 BYPS YCOMB LDEL LUBW LUFI3 LUFI2 LUFI1 LUFI0 0A DBRI7 DBRI6 DBRI5 DBRI4 DBRI3 DBRI2 DBRI1 DBRI0 Luminance contrast control 0B DCON7 DCON6 DCON5 DCON4 DCON3 DCON2 DCON1 DCON0 Chrominance saturation control 0C DSAT7 DSAT6 DSAT5 DSAT4 DSAT3 DSAT2 DSAT1 DSAT0 Chrominance hue control 0D HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0 Chrominance control 1 0E CDTO CSTD2 CSTD1 CSTD0 DCVF FCTC (1) CCOMB Chrominance gain control 0F ACGC CGAIN6 CGAIN5 CGAIN4 CGAIN3 CGAIN2 CGAIN1 CGAIN0 Chrominance control 2 10 OFFU1 OFFU0 OFFV1 OFFV0 CHBW LCBW2 LCBW1 LCBW0 Mode/delay control 11 COLO RTP1 HDEL1 HDEL0 RTP0 YDEL2 YDEL1 YDEL0 RT signal control 12 RTSE13 RTSE12 RTSE11 RTSE10 RTSE03 RTSE02 RTSE01 RTSE00 RT/X port output control 13 RTCE XRHS XRVS1 XRVS0 HLSEL OFTS2 OFTS1 OFTS0 Analog/ADC/compatibility control 14 CM99 UPTCV AOSL1 AOSL0 XTOUTE OLDSB APCK1 APCK0 VGATE start, FID change 15 VSTA7 VSTA6 VSTA5 VSTA4 VSTA3 VSTA2 VSTA1 VSTA0 VGATE stop 16 VSTO7 VSTO6 VSTO5 VSTO4 VSTO3 VSTO2 VSTO1 VSTO0 Product specification 09 Luminance brightness control SAA7108AE; SAA7109AE Luminance control This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... D6 D5 D4 D3 D2 D1 D0 Miscellaneous, VGATE configuration and MSBs 17 LLCE LLC2E (1) (1) (1) VGPS VSTO8 VSTA8 Raw data gain control 18 RAWG7 RAWG6 RAWG5 RAWG4 RAWG3 RAWG2 RAWG1 RAWG0 Raw data offset control 19 RAWO7 RAWO6 RAWO5 RAWO4 RAWO3 RAWO2 RAWO1 RAWO0 1A to 1E (1) (1) (1) (1) (1) (1) (1) (1) Status byte video decoder (read only, OLDSB = 0) 1F INTL HLVLN FIDT GLIMT GLIMB WIPA COPRO RDCAP Status byte video decoder (read only, OLDSB = 1) 1F INTL HLCK FIDT GLIMT GLIMB WIPA SLTCA CODE 20 to 2F (1) (1) (1) (1) (1) (1) (1) (1) ACPF1 ACPF0 Reserved Reserved Philips Semiconductors D7 HD-CODEC 2004 Jun 29 SUB ADDR. (HEX) REGISTER FUNCTION Audio clock generator part: registers 30H to 3FH Audio master clock cycles per field 139 ACPF7 ACPF6 ACPF5 ACPF4 ACPF3 ACPF2 31 ACPF15 ACPF14 ACPF13 ACPF12 ACPF11 ACPF10 ACPF9 ACPF8 32 (1) (1) (1) (1) (1) (1) ACPF17 ACPF16 Reserved 33 (1) (1) (1) (1) (1) (1) (1) (1) Audio master clock nominal increment 34 ACNI7 ACNI6 ACNI5 ACNI4 ACNI3 ACNI2 ACNI1 ACNI0 35 ACNI15 ACNI14 ACNI13 ACNI12 ACNI11 ACNI10 ACNI9 ACNI8 36 (1) (1) ACNI21 ACNI20 ACNI19 ACNI18 ACNI17 ACNI16 Reserved 37 (1) (1) (1) (1) (1) (1) (1) (1) Clock ratio AMXCLK to ASCLK 38 (1) (1) SDIV5 SDIV4 SDIV3 SDIV2 SDIV1 SDIV0 Clock ratio ASCLK to ALRCLK 39 (1) (1) LRDIV5 LRDIV4 LRDIV3 LRDIV2 LRDIV1 LRDIV0 Audio clock generator basic set-up 3A (1) (1) (1) (1) APLL AMVR LRPH SCPH 3B to 3F (1) (1) (1) (1) (1) (1) (1) (1) Reserved General purpose VBI data slicer part: registers 40H to 7FH (1) HAM_N FCE HUNT_N (1) (1) (1) (1) LCR2 to LCR24 (n = 2 to 24) 41 to 57 LCRn_7 LCRn_6 LCRn_5 LCRn_4 LCRn_3 LCRn_2 LCRn_1 LCRn_0 Programmable framing code 58 FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 Horizontal offset for slicer 59 HOFF7 HOFF6 HOFF5 HOFF4 HOFF3 HOFF2 HOFF1 HOFF0 Vertical offset for slicer 5A VOFF7 VOFF6 VOFF5 VOFF4 VOFF3 VOFF2 VOFF1 VOFF0 Product specification 40 Slicer control 1 SAA7108AE; SAA7109AE 30 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... D6 D5 D4 D3 D2 D1 D0 Field offset and MSBs for horizontal and vertical offset 5B FOFF RECODE (1) VOFF8 (1) HOFF10 HOFF9 HOFF8 Reserved (for testing) 5C (1) (1) (1) (1) (1) (1) (1) (1) Header and data identification (DID) code control 5D FVREF (1) DID5 DID4 DID3 DID2 DID1 DID0 Sliced data identification (SDID) code 5E (1) (1) SDID5 SDID4 SDID3 SDID2 SDID1 SDID0 Reserved 5F (1) (1) (1) (1) (1) (1) (1) (1) Slicer status byte 0 (read only) 60 − FC8V FC7V VPSV PPV CCV − − Slicer status byte 1 (read only) 61 − − F21_N LN8 LN7 LN6 LN5 LN4 62 LN3 LN2 LN1 LN0 DT3 DT2 DT1 DT0 63 to 7F (1) (1) (1) (1) (1) (1) (1) (1) Slicer status byte 2 (read only) Reserved Philips Semiconductors D7 HD-CODEC 2004 Jun 29 SUB ADDR. (HEX) REGISTER FUNCTION X port, I port and the scaler part: registers 80H to EFH 140 TASK INDEPENDENT GLOBAL SETTINGS: 80H TO 8FH SMOD TEB TEA ICKS3 ICKS2 ICKS1 ICKS0 81 and 82 (1) (1) (1) (1) (1) (1) (1) (1) X port I/O enable and output clock phase control 83 (1) (1) XPCK1 XPCK0 (1) XRQT XPE1 XPE0 I port signal definitions 84 IDG01 IDG00 IDG11 IDG10 IDV1 IDV0 IDH1 IDH0 I port signal polarities 85 ISWP1 ISWP0 ILLV IG0P IG1P IRVP IRHP IDQP I port FIFO flag control and arbitration 86 VITX1 VITX0 IDG02 IDG12 FFL1 FFL0 FEL1 FEL0 I port I/O enable, output clock and gated clock phase control 87 IPCK3 IPCK2 IPCK1 IPCK0 (1) (1) IPE1 IPE0 Power save control 88 CH4EN CH2EN SWRST DPROG SLM3 (1) SLM1 SLM0 89 to 8E (1) (1) (1) (1) (1) (1) (1) (1) 8F XTRI ITRI FFIL FFOV PRDON ERROF FIDSCI FIDSCO Reserved Reserved Status information scaler part Product specification (1) SAA7108AE; SAA7109AE 80 Global control 1 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... D7 D6 D5 D4 D3 D2 D1 D0 90 CONLH OFIDC FSKP2 FSKP1 FSKP0 RPTSK STRC1 STRC0 X port formats and configuration 91 CONLV HLDFV SCSRC1 SCSRC0 SCRQE FSC2 FSC1 FSC0 X port input reference signal definitions 92 XFDV XFDH XDV1 XDV0 XCODE XDH XDQ XCKS I port output formats and configuration 93 ICODE I8_16 FYSK FOI1 FOI0 FSI2 FSI1 FSI0 TASK A DEFINITION: REGISTERS 90H TO BFH Basic settings and acquisition window definition Task handling control Horizontal input window start Horizontal input window length Vertical input window start 141 Vertical input window length 94 XO7 XO6 XO5 XO4 XO3 XO2 XO1 XO0 95 (1) (1) (1) (1) XO11 XO10 XO9 XO8 96 XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0 97 (1) (1) (1) (1) XS11 XS10 XS9 XS8 98 YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0 99 (1) (1) (1) (1) YO11 YO10 YO9 YO8 YS6 YS5 YS4 YS3 YS2 YS1 YS0 (1) (1) (1) (1) YS11 YS10 YS9 YS8 9C XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 9D (1) (1) (1) (1) XD11 XD10 XD9 XD8 9E YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0 9F (1) (1) (1) (1) YD11 YD10 YD9 YD8 A0 (1) (1) XPSC5 XPSC4 XPSC3 XPSC2 XPSC1 XPSC0 Accumulation length A1 (1) (1) XACL5 XACL4 XACL3 XACL2 XACL1 XACL0 Prescaler DC gain and FIR prefilter control A2 PFUV1 PFUV0 PFY1 PFY0 XC2_1 XDCG2 XDCG1 XDCG0 Reserved A3 (1) (1) (1) (1) (1) (1) (1) (1) Luminance brightness control A4 BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0 Luminance contrast control A5 CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0 Chrominance saturation control A6 SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0 A7 (1) (1) (1) (1) (1) (1) (1) (1) Horizontal output window length Vertical output window length FIR filtering and prescaling Horizontal prescaling Reserved Product specification YS7 SAA7108AE; SAA7109AE 9A 9B Philips Semiconductors SUB ADDR. (HEX) HD-CODEC 2004 Jun 29 REGISTER FUNCTION This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... D6 D5 D4 D3 D2 D1 D0 Horizontal luminance scaling increment A8 XSCY7 XSCY6 XSCY5 XSCY4 XSCY3 XSCY2 XSCY1 XSCY0 A9 (1) (1) (1) XSCY12 XSCY11 XSCY10 XSCY9 XSCY8 Horizontal luminance phase offset AA XPHY7 XPHY6 XPHY5 XPHY4 XPHY3 XPHY2 XPHY1 XPHY0 Reserved AB (1) (1) (1) (1) (1) (1) (1) (1) Horizontal chrominance scaling increment AC XSCC7 XSCC6 XSCC5 XSCC4 XSCC3 XSCC2 XSCC1 XSCC0 AD (1) (1) (1) XSCC12 XSCC11 XSCC10 XSCC9 XSCC8 Horizontal chrominance phase offset AE XPHC7 XPHC6 XPHC5 XPHC4 XPHC3 XPHC2 XPHC1 XPHC0 Reserved AF (1) (1) (1) (1) (1) (1) (1) (1) Vertical luminance scaling increment B0 YSCY7 YSCY6 YSCY5 YSCY4 YSCY3 YSCY2 YSCY1 YSCY0 B1 YSCY15 YSCY14 YSCY13 YSCY12 YSCY11 YSCY10 YSCY9 YSCY8 Vertical chrominance scaling increment B2 YSCC7 YSCC6 YSCC5 YSCC4 YSCC3 YSCC2 YSCC1 YSCC0 B3 YSCC15 YSCC14 YSCC13 YSCC12 YSCC11 YSCC10 YSCC9 YSCC8 B4 (1) (1) (1) YMIR (1) (1) (1) YMODE B5 to B7 (1) (1) (1) (1) (1) (1) (1) (1) Vertical chrominance phase offset ‘00’ B8 YPC07 YPC06 YPC05 YPC04 YPC03 YPC02 YPC01 YPC00 Vertical chrominance phase offset ‘01’ B9 YPC17 YPC16 YPC15 YPC14 YPC13 YPC12 YPC11 YPC10 Vertical chrominance phase offset ‘10’ BA YPC27 YPC26 YPC25 YPC24 YPC23 YPC22 YPC21 YPC20 Vertical chrominance phase offset ‘11’ BB YPC37 YPC36 YPC35 YPC34 YPC33 YPC32 YPC31 YPC30 Vertical luminance phase offset ‘00’ BC YPY07 YPY06 YPY05 YPY04 YPY03 YPY02 YPY01 YPY00 Vertical luminance phase offset ‘01’ BD YPY17 YPY16 YPY15 YPY14 YPY13 YPY12 YPY11 YPY10 Vertical luminance phase offset ‘10’ BE YPY27 YPY26 YPY25 YPY24 YPY23 YPY22 YPY21 YPY20 Horizontal phase scaling Philips Semiconductors D7 HD-CODEC 2004 Jun 29 SUB ADDR. (HEX) REGISTER FUNCTION Vertical scaling 142 Vertical scaling mode control Reserved Product specification SAA7108AE; SAA7109AE This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... D7 D6 D5 D4 D3 D2 D1 D0 BF YPY37 YPY36 YPY35 YPY34 YPY33 YPY32 YPY31 YPY30 TASK B DEFINITION REGISTERS C0H TO EFH Basic settings and acquisition window definition Task handling control C0 CONLH OFIDC FSKP2 FSKP1 FSKP0 RPTSK STRC1 STRC0 X port formats and configuration C1 CONLV HLDFV SCSRC1 SCSRC0 SCRQE FSC2 FSC1 FSC0 Input reference signal definition C2 XFDV XFDH XDV1 XDV0 XCODE XDH XDQ XCKS I port formats and configuration C3 ICODE I8_16 FYSK FOI1 FOI0 FSI2 FSI1 FSI0 Horizontal input window start C4 XO7 XO6 XO5 XO4 XO3 XO2 XO1 XO0 C5 (1) (1) (1) (1) XO11 XO10 XO9 XO8 Horizontal input window length Vertical input window start 143 Vertical input window length Horizontal output window length C6 XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0 C7 (1) (1) (1) (1) XS11 XS10 XS9 XS8 C8 YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0 C9 (1) (1) (1) (1) YO11 YO10 YO9 YO8 CA YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0 CB (1) (1) (1) (1) YS11 YS10 YS9 YS8 XD6 XD5 XD4 XD3 XD2 XD1 XD0 (1) (1) (1) (1) XD11 XD10 XD9 XD8 CE YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0 CF (1) (1) (1) (1) YD11 YD10 YD9 YD8 D0 (1) (1) XPSC5 XPSC4 XPSC3 XPSC2 XPSC1 XPSC0 Accumulation length D1 (1) (1) XACL5 XACL4 XACL3 XACL2 XACL1 XACL0 Prescaler DC gain and FIR prefilter control D2 PFUV1 PFUV0 PFY1 PFY0 XC2_1 XDCG2 XDCG1 XDCG0 Reserved D3 (1) (1) (1) (1) (1) (1) (1) (1) Luminance brightness control D4 BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0 Luminance contrast control D5 CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0 Chrominance saturation control D6 SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0 D7 (1) (1) (1) (1) (1) (1) (1) (1) Vertical output window length FIR filtering and prescaling Horizontal prescaling Reserved Product specification XD7 SAA7108AE; SAA7109AE CC CD Philips Semiconductors Vertical luminance phase offset ‘11’ SUB ADDR. (HEX) HD-CODEC 2004 Jun 29 REGISTER FUNCTION This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... D6 D5 D4 D3 D2 D1 D0 Horizontal luminance scaling increment D8 XSCY7 XSCY6 XSCY5 XSCY4 XSCY3 XSCY2 XSCY1 XSCY0 D9 (1) (1) (1) XSCY12 XSCY11 XSCY10 XSCY9 XSCY8 Horizontal luminance phase offset DA XPHY7 XPHY6 XPHY5 XPHY4 XPHY3 XPHY2 XPHY1 XPHY0 Reserved DB (1) (1) (1) (1) (1) (1) (1) (1) Horizontal chrominance scaling increment DC XSCC7 XSCC6 XSCC5 XSCC4 XSCC3 XSCC2 XSCC1 XSCC0 DD (1) (1) (1) XSCC12 XSCC11 XSCC10 XSCC9 XSCC8 Horizontal chrominance phase offset DE XPHC7 XPHC6 XPHC5 XPHC4 XPHC3 XPHC2 XPHC1 XPHC0 Reserved DF (1) (1) (1) (1) (1) (1) (1) (1) Vertical luminance scaling increment E0 YSCY7 YSCY6 YSCY5 YSCY4 YSCY3 YSCY2 YSCY1 YSCY0 E1 YSCY15 YSCY14 YSCY13 YSCY12 YSCY11 YSCY10 YSCY9 YSCY8 Vertical chrominance scaling increment E2 YSCC7 YSCC6 YSCC5 YSCC4 YSCC3 YSCC2 YSCC1 YSCC0 E3 YSCC15 YSCC14 YSCC13 YSCC12 YSCC11 YSCC10 YSCC9 YSCC8 E4 (1) (1) (1) YMIR (1) (1) (1) YMODE E5 to E7 (1) (1) (1) (1) (1) (1) (1) (1) Vertical chrominance phase offset ‘00’ E8 YPC07 YPC06 YPC05 YPC04 YPC03 YPC02 YPC01 YPC00 Vertical chrominance phase offset ‘01’ E9 YPC17 YPC16 YPC15 YPC14 YPC13 YPC12 YPC11 YPC10 Vertical chrominance phase offset ‘10’ EA YPC27 YPC26 YPC25 YPC24 YPC23 YPC22 YPC21 YPC20 Vertical chrominance phase offset ‘11’ EB YPC37 YPC36 YPC35 YPC34 YPC33 YPC32 YPC31 YPC30 Vertical luminance phase offset ‘00’ EC YPY07 YPY06 YPY05 YPY04 YPY03 YPY02 YPY01 YPY00 Horizontal phase scaling Philips Semiconductors D7 HD-CODEC 2004 Jun 29 SUB ADDR. (HEX) REGISTER FUNCTION Vertical scaling 144 Vertical scaling mode control Reserved Product specification SAA7108AE; SAA7109AE This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... D6 D5 D4 D3 D2 D1 D0 Vertical luminance phase offset ‘01’ ED YPY17 YPY16 YPY15 YPY14 YPY13 YPY12 YPY11 YPY10 Vertical luminance phase offset ‘10’ EE YPY27 YPY26 YPY25 YPY24 YPY23 YPY22 YPY21 YPY20 Vertical luminance phase offset ‘11’ EF YPY37 YPY36 YPY35 YPY34 YPY33 YPY32 YPY31 YPY30 Philips Semiconductors D7 HD-CODEC 2004 Jun 29 SUB ADDR. (HEX) REGISTER FUNCTION Note 1. All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements. 18.2.2 18.2.2.1 I2C-BUS DETAIL Subaddress 00H Table 153 Chip version (CV) identification; 00H[7:4]; read only register LOGIC LEVELS 145 FUNCTION Chip Version (CV) 18.2.2.2 ID7 ID6 ID5 ID4 CV3 CV2 CV1 CV0 Subaddress 01H The programming of the horizontal increment delay is used to match internal processing delays to the delay of the ADC. Use recommended position only. FUNCTION IDEL2 IDEL1 IDEL0 No update 1 1 1 1 Minimum delay 1 1 1 0 Recommended position 1 0 0 0 Maximum delay 0 0 0 0 Product specification IDEL3 SAA7108AE; SAA7109AE Table 154 Horizontal increment delay; 01H[3:0] Philips Semiconductors Product specification HD-CODEC 18.2.2.3 SAA7108AE; SAA7109AE Subaddress 02H Table 155 Analog input control 1 (AICO1); 02H[7:0] BIT DESCRIPTION 7 and 6 analog function select; see Fig.15 5 and 4 update hysteresis for 9-bit gain; see Fig.16 SYMBOL FUSE[1:0] VALUE 00 mode selection amplifier plus anti-alias filter bypassed 01 GUDL[1:0] 10 amplifier active 11 amplifier plus anti-alias filter active 00 off 01 ±1 LSB 10 ±2 LSB 11 3 to 0 FUNCTION MODE[3:0] ±3 LSB 0000 Mode 0: CVBS (automatic gain) from AI11 (pin P13); see Fig.59 0001 Mode 1: CVBS (automatic gain) from AI12 (pin P11); see Fig.60 0010 Mode 2: CVBS (automatic gain) from AI21 (pin P10); see Fig.61 0011 Mode 3: CVBS (automatic gain) from AI22 (pin P9); see Fig.62 0100 Mode 4: CVBS (automatic gain) from AI23 (pin P7); see Fig.63 0101 Mode 5: CVBS (automatic gain) from AI24 (pin P6); see Fig.64 0110 Mode 6: Y (automatic gain) from AI11 (pin P13) + C (gain adjustable via GAI28 to GAI20) from AI21 (pin P10); note 1; see Fig.65 0111 Mode 7: Y (automatic gain) from AI12 (pin P11) + C (gain adjustable via GAI28 to GAI20) from AI22 (pin P9); note 1; see Fig.66 1000 Mode 8: Y (automatic gain) from AI11 (pin P13) + C (gain adapted to Y gain) from AI21 (pin P10); note 1; see Fig.67 1001 Mode 9: Y (automatic gain) from AI12 (pin P11) + C (gain adapted to Y gain) from AI22 (pin P9); note 1; see Fig.68 1010 to 1111 Modes 10 to 15: reserved Note 1. To take full advantage of the Y/C modes 6 to 9 the I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth). 2004 Jun 29 146 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE AI24 AI23 AI22 AI21 AD2 AI12 AI11 AD1 CHROMA LUMA MHB559 AD2 AI12 AI11 AD1 AD2 AI12 AI11 AD1 CHROMA LUMA AI24 AI23 AI22 AI21 AD2 AI12 AI11 AD1 AI12 AI11 AD1 LUMA Fig.62 Mode 3; CVBS (automatic gain). CHROMA LUMA MHB563 AI24 AI23 AI22 AI21 AD2 AI12 AI11 AD1 CHROMA LUMA MHB564 Fig.63 Mode 4; CVBS (automatic gain). 2004 Jun 29 CHROMA MHB562 Fig.61 Mode 2; CVBS (automatic gain). AD2 LUMA Fig.60 Mode 1; CVBS (automatic gain). MHB561 AI24 AI23 AI22 AI21 CHROMA MHB560 Fig.59 Mode 0; CVBS (automatic gain). AI24 AI23 AI22 AI21 AI24 AI23 AI22 AI21 Fig.64 Mode 5; CVBS (automatic gain). 147 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE AI24 AI23 AI22 AI21 AD2 AI12 AI11 AD1 CHROMA LUMA MHB565 AI24 AI23 AI22 AI21 AD2 AI12 AI11 AD1 CHROMA LUMA MHB566 I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth). I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth). Fig.65 Mode 6; Y + C (gain channel 2 adjusted via GAI2). Fig.66 Mode 7; Y + C (gain channel 2 adjusted via GAI2). AI24 AI23 AI22 AI21 AD2 AI12 AI11 AD1 CHROMA LUMA MHB567 AI24 AI23 AI22 AI21 AD2 AI12 AI11 AD1 CHROMA LUMA MHB568 I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth). I2C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth). Fig.67 Mode 8; Y + C (gain channel 2 adapted to Y gain). Fig.68 Mode 9; Y + C (gain channel 2 adapted to Y gain). 2004 Jun 29 148 Philips Semiconductors Product specification HD-CODEC 18.2.2.4 SAA7108AE; SAA7109AE Subaddress 03H Table 156 Analog input control 2 (AICO2); 03H[6:0] BIT 6 DESCRIPTION SYMBOL VALUE HL not reference select 5 HLNRS AGC hold during vertical blanking period 4 VBSL white peak control off 3 WPOFF FUNCTION 0 normal clamping if decoder is in unlocked state 1(1) reference select if decoder is in unlocked state 0 short vertical blanking (AGC disabled during equalization and serration pulses) 1 long vertical blanking (AGC disabled from start of pre-equalization pulses until start of active video (line 22 for 60 Hz, line 24 for 50 Hz) 0(1) white peak control active 1 white peak control off 0 AGC active 1 AGC integration hold (freeze) 0 automatic gain controlled by MODE3 to MODE0 1 gain is user programmable via GAI[17:10] and GAI[27:20] automatic gain control integration HOLDG 2 gain control fix GAFIX 1 static gain control channel 2 sign bit GAI28 see Table 158 0 static gain control channel 1 sign bit GAI18 see Table 157 Note 1. HLNRS = 1 should not be used in combination with WPOFF = 0. 18.2.2.5 Subaddress 04H Table 157 Analog input control 3 (AICO3); static gain control channel 1; 03H[0] and 04H[7:0] DECIMAL VALUE GAIN (dB) SIGN BIT 03H[0] CONTROL BITS 7 TO 0 GAI18 GAI17 GAI16 GAI15 GAI14 GAI13 GAI12 GAI11 GAI10 0... −3 0 0 0 0 0 0 0 0 0 ...144 0 0 1 0 0 1 0 0 0 0 145... 0 0 1 0 0 1 0 0 0 1 ...511 +6 1 1 1 1 1 1 1 1 1 18.2.2.6 Subaddress 05H Table 158 Analog input control 4 (AICO4); static gain control channel 2; 03H[1] and 05H[7:0] DECIMAL VALUE GAIN (dB) SIGN BIT 03H[1] CONTROL BITS 7 TO 0 GAI28 GAI27 GAI26 GAI25 GAI24 GAI23 GAI22 GAI21 GAI20 0... −3 0 0 0 0 0 0 0 0 0 ...144 0 0 1 0 0 1 0 0 0 0 145... 0 0 1 0 0 1 0 0 0 1 ...511 +6 1 1 1 1 1 1 1 1 1 2004 Jun 29 149 Philips Semiconductors Product specification HD-CODEC 18.2.2.7 SAA7108AE; SAA7109AE Subaddress 06H Table 159 Horizontal sync start; 06H[7:0] DELAY TIME (STEP SIZE = 8/LLC) CONTROL BITS 7 TO 0 HSB7 HSB6 −128...−109 (50 Hz) HSB5 HSB4 HSB3 HSB2 HSB1 HSB0 forbidden (outside available central counter range) −128...−108 (60 Hz) −108 (50 Hz)... 1 0 0 1 0 1 0 0 −107 (60 Hz)... 1 0 0 1 0 1 0 1 ...108 (50 Hz) 0 1 1 0 1 1 0 0 ...107 (60 Hz) 0 1 1 0 1 0 1 1 HSS1 HSS0 109...127 (50 Hz) forbidden (outside available central counter range) 108...127 (60 Hz) 18.2.2.8 Subaddress 07H Table 160 Horizontal sync stop; 07H[7:0] DELAY TIME (STEP SIZE = 8/LLC) CONTROL BITS 7 TO 0 HSS7 HSS6 −128...−109 (50 Hz) HSS5 HSS4 HSS3 HSS2 forbidden (outside available central counter range) −128...−108 (60 Hz) −108 (50 Hz)... 1 0 0 1 0 1 0 0 −107 (60 Hz)... 1 0 0 1 0 1 0 1 ...108 (50 Hz) 0 1 1 0 1 1 0 0 ...107 (60 Hz) 0 1 1 0 1 0 1 1 109...127 (50 Hz) forbidden (outside available central counter range) 108...127 (60 Hz) 2004 Jun 29 150 Philips Semiconductors Product specification HD-CODEC 18.2.2.9 SAA7108AE; SAA7109AE Subaddress 08H Table 161 Sync control; 08H[7:0] BIT DESCRIPTION 7 automatic field detection SYMBOL VALUE AUFD 6 field selection FSEL 5 forced ODD/EVEN toggle FOET 4 and 3 horizontal time constant selection 2 horizontal PLL 1 and 0 vertical noise reduction 2004 Jun 29 HTC[1:0] HPLL VNOI[1:0] FUNCTION 0 field state directly controlled via FSEL 1 automatic field detection; recommended setting 0 50 Hz, 625 lines 1 60 Hz, 525 lines 0 ODD/EVEN signal toggles only with interlaced source 1 ODD/EVEN signal toggles fieldwise even if source is non-interlaced 00 TV mode, recommended for poor quality TV signals only; do not use for new applications 01 VTR mode, recommended if a deflection control circuit is directly connected to the SAA7108AE; SAA7109AE 10 reserved 11 fast locking mode; recommended setting 0 PLL closed 1 PLL open; horizontal frequency fixed 00 normal mode; recommended setting 01 fast mode, applicable for stable sources only; automatic field detection (AUFD) must be disabled 10 free running mode 11 vertical noise reduction bypassed 151 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE 18.2.2.10 Subaddress 09H Table 162 Luminance control; 09H[7:0] BIT DESCRIPTION 7 chrominance trap/comb filter bypass SYMBOL VALUE BYPS 0 chrominance trap or luminance comb filter active; default for CVBS mode 1 chrominance trap or luminance comb filter bypassed; default for S-video mode 0 disabled (= chrominance trap enabled, if BYPS = 0) 1 active, if BYPS = 0 0 processing delay is equal to internal pipelining delay 1 one (NTSC standards) or two (PAL standards) video lines additional processing delay 0 small remodulation bandwidth (narrow chrominance notch ⇒ higher luminance bandwidth) 1 large remodulation bandwidth (wider chrominance notch ⇒ smaller luminance bandwidth) 6 adaptive luminance comb filter 5 processing delay in non comb filter mode LDEL remodulation bandwidth for luminance; see Figs 21 to 24 LUBW sharpness control, luminance filter characteristic; see Fig.25 LUFI[3:0] 4 3 to 0 YCOMB FUNCTION 0001 resolution enhancement filter; 8.0 dB at 4.1 MHz 0010 resolution enhancement filter; 6.8 dB at 4.1 MHz 0011 resolution enhancement filter; 5.1 dB at 4.1 MHz 0100 resolution enhancement filter; 4.1 dB at 4.1 MHz 0101 resolution enhancement filter; 3.0 dB at 4.1 MHz 0110 resolution enhancement filter; 2.3 dB at 4.1 MHz 0111 resolution enhancement filter; 1.6 dB at 4.1 MHz 0000 plain 1000 low-pass filter; 2 dB at 4.1 MHz 1001 low-pass filter; 3 dB at 4.1 MHz 1010 low-pass filter; 3 dB at 3.3 MHz; 4 dB at 4.1 MHz 1011 low-pass filter; 3 dB at 2.6 MHz; 8 dB at 4.1 MHz 1100 low-pass filter; 3 dB at 2.4 MHz; 14 dB at 4.1 MHz 1101 low-pass filter; 3 dB at 2.2 MHz; notch at 3.4 MHz 1110 low-pass filter; 3 dB at 1.9 MHz; notch at 3.0 MHz 1111 low-pass filter; 3 dB at 1.7 MHz; notch at 2.5 MHz 18.2.2.11 Subaddress 0AH Table 163 Luminance brightness control: decoder part; 0AH[7:0] CONTROL BITS 7 TO 0 OFFSET DBRI7 DBRI6 DBRI5 DBRI4 DBRI3 DBRI2 DBRI1 DBRI0 255 (bright) 1 1 1 1 1 1 1 1 128 (ITU level) 1 0 0 0 0 0 0 0 0 (dark) 0 0 0 0 0 0 0 0 2004 Jun 29 152 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE 18.2.2.12 Subaddress 0BH Table 164 Luminance contrast control: decoder part; 0BH[7:0] CONTROL BITS 7 TO 0 GAIN DCON7 DCON6 DCON5 DCON4 DCON3 DCON2 DCON1 DCON0 1.984 (maximum) 0 1 1 1 1 1 1 1 1.063 (ITU level) 0 1 0 0 0 1 0 0 1.0 0 1 0 0 0 0 0 0 0 (luminance off) 0 0 0 0 0 0 0 0 −1 (inverse luminance) 1 1 0 0 0 0 0 0 −2 (inverse luminance) 1 0 0 0 0 0 0 0 18.2.2.13 Subaddress 0CH Table 165 Chrominance saturation control: decoder part; 0CH[7:0] CONTROL BITS 7 TO 0 GAIN DSAT7 DSAT6 DSAT5 DSAT4 DSAT3 DSAT2 DSAT1 DSAT0 1.984 (maximum) 0 1 1 1 1 1 1 1 1.0 (ITU level) 0 1 0 0 0 0 0 0 0 (colour off) 0 0 0 0 0 0 0 0 −1 (inverse chrominance) 1 1 0 0 0 0 0 0 −2 (inverse chrominance) 1 0 0 0 0 0 0 0 18.2.2.14 Subaddress 0DH Table 166 Chrominance hue control: 0DH[7:0] CONTROL BITS 7 TO 0 HUE PHASE (DEG) HUEC7 HUEC6 HUEC5 HUEC4 HUEC3 HUEC2 HUEC1 HUEC0 +178.6... 0 1 1 1 1 1 1 1 ...0... 0 0 0 0 0 0 0 0 ...−180 1 0 0 0 0 0 0 0 2004 Jun 29 153 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE 18.2.2.15 Subaddress 0EH Table 167 Chrominance control 1; 0EH[7:0] FUNCTION BIT DESCRIPTION SYMBOL VALUE 50 Hz/625 LINES 7 clear DTO 6 to 4 colour standard selection 3 CDTO CSTD[2:0] disable chrominance vertical filter and PAL phase error correction DCVF 2 fast colour time constant FCTC 0 adaptive chrominance comb filter CCOMB 60 Hz/525 LINES 0 disabled 1 Every time CDTO is set, the internal subcarrier DTO phase is reset to 0° and the RTCO output generates a logic 0 at time slot 68 (see document “RTC Functional Description”, available on request). So an identical subcarrier phase can be generated by an external device (e.g. an encoder). 000 PAL BGDHI (4.43 MHz) NTSC M (3.58 MHz) 001 NTSC 4.43 (50 Hz) PAL 4.43 (60 Hz) 010 Combination-PAL N (3.58 MHz) NTSC 4.43 (60 Hz) 011 NTSC N (3.58 MHz) PAL M (3.58 MHz) 100 reserved NTSC-Japan (3.58 MHz) 101 SECAM reserved 110 reserved; do not use 111 reserved; do not use 0 chrominance vertical filter and PAL phase error correction on (during active video lines) 1 chrominance vertical filter and PAL phase error correction permanently off 0 nominal time constant 1 fast time constant for special applications 0 disabled 1 active 18.2.2.16 Subaddress 0FH Table 168 Chrominance gain control; 0FH[7:0] BIT 7 DESCRIPTION automatic chrominance gain control 6 to 0 chrominance gain value (if ACGC is set to logic 1) SYMBOL VALUE FUNCTION ACGC 0 on 1 programmable gain via CGAIN6 to CGAIN0; need to be set for SECAM standard CGAIN[6:0] 000 0000 minimum gain (0.5) 010 0100 nominal gain (1.125) 111 1111 maximum gain (7.5) 2004 Jun 29 154 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE 18.2.2.17 Subaddress 10H Table 169 Chrominance control 2; 10H[7:0] BIT 7 and 6 5 and 4 3 2 to 0 DESCRIPTION fine offset adjustment B − Y component fine offset adjustment R − Y component chrominance bandwidth; see Figs 19 and 20 combined luminance/chrominance bandwidth adjustment; see Figs 19 to 25 SYMBOL OFFU[1:0] OFFV[1:0] CHBW LCBW[2:0] VALUE FUNCTION 00 0 LSB 01 1⁄ 4 LSB 10 1⁄ 2 LSB 11 3⁄ 4 LSB 00 0 LSB 01 1⁄ 4 LSB 10 1⁄ 2 LSB 11 3⁄ 4 LSB 0 small 1 wide 000 ... 111 smallest chrominance bandwidth or largest luminance bandwidth ... to ... largest chrominance bandwidth or smallest luminance bandwidth 18.2.2.18 Subaddress 11H Table 170 Mode/delay control; 11H[7:0] BIT 7 6 5 and 4 3 2 to 0 2004 Jun 29 DESCRIPTION colour on polarity of RTS1 output signal fine position of HS (steps in 2/LLC) polarity of RTS0 output signal luminance delay compensation (steps in 2/LLC) SYMBOL VALUE COLO 0 automatic colour killer enabled 1 colour forced on RTP1 HDEL[1:0] RTP0 YDEL[2:0] 155 FUNCTION 0 non inverted 1 inverted 00 0 01 1 10 2 11 3 0 non inverted 1 inverted 100 −4... 000 ...0... 011 ...3 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE 18.2.2.19 Subaddress 12H Table 171 RT signal control: RTS0 output; 12H[3:0] The polarity of any signal on RTS0 can be inverted via RTP0[11H[3]]. RTS0 OUTPUT RTSE03 RTSE02 RTSE01 RTSE00 3-state 0 0 0 0 Constant LOW 0 0 0 1 CREF (13.5 MHz toggling pulse; see Fig.32) 0 0 1 0 CREF2 (6.75 MHz toggling pulse; see Fig.32) 0 0 1 1 HL; horizontal lock indicator (note 1): 0 1 0 0 0 1 0 1 0 1 1 0 Reserved 0 1 1 1 HREF, horizontal reference signal; indicates 720 pixels valid data on the expansion port. The positive slope marks the beginning of a new active line. HREF is also generated during the vertical blanking interval; see Fig.32. 1 0 0 0 HS: 1 0 0 1 HQ; HREF gated with VGATE 1 0 1 0 Reserved 1 0 1 1 V123; vertical sync; see vertical timing diagrams Figs 30 and 31 1 1 0 0 VGATE; programmable via VSTA[8:0] 17H[0] 15H[7:0], VSTO[8:0] 17H[1] 16H[7:0] and VGPS[17H[2]] 1 1 0 1 LSBs of the 9-bit ADC’s 1 1 1 0 FID; position programmable via VSTA[8:0] 17H[0] 15H[7:0]; see vertical timing diagrams Figs 30 and 31 1 1 1 1 HL = 0: unlocked HL = 1: locked VL; vertical and horizontal lock: VL = 0: unlocked VL = 1: locked DL; vertical and horizontal lock and colour detected: DL = 0: unlocked DL = 1: locked programmable width in LLC8 steps via HSB[7:0] 06H[7:0] and HSS[7:0] 07H[7:0] fine position adjustment in LLC2 steps via HDEL[1:0] 11H[5:4]; see Fig.32 Note 1. Function of HL is selectable via HLSEL[13H[3]]: a) HLSEL = 0: HL is standard horizontal lock indicator. b) HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g. VCRs). 2004 Jun 29 156 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 172 RT signal control: RTS1 output; 12H[7:4] The polarity of any signal on RTS1 can be inverted via RTP1[11H[6]]. RTS1 OUTPUT CONTROL RTSE13 RTSE12 RTSE11 RTSE10 3-state 0 0 0 0 Constant LOW 0 0 0 1 CREF (13.5 MHz toggling pulse; see Fig.32) 0 0 1 0 CREF2 (6.75 MHz toggling pulse; see Fig.32) 0 0 1 1 HL; horizontal lock indicator (note 1): 0 1 0 0 0 1 0 1 0 1 1 0 Reserved 0 1 1 1 HREF, horizontal reference signal: indicates 720 pixels valid data on the expansion port. The positive slope marks the beginning of a new active line. HREF is also generated during the vertical blanking interval; see Fig.32. 1 0 0 0 HS: 1 0 0 1 HQ; HREF gated with VGATE 1 0 1 0 Reserved 1 0 1 1 V123; vertical sync; see vertical timing diagrams Figs 30 and 31 1 1 0 0 VGATE; programmable via VSTA[8:0] 17H[0] 15H[7:0], VSTO[8:0] 17H[1] 16H[7:0] and VGPS[17H[2]] 1 1 0 1 Reserved 1 1 1 0 FID; position programmable via VSTA[8:0] 17H[0] 15H[7:0]; see vertical timing diagrams Figs 30 and 31 1 1 1 1 HL = 0: unlocked HL = 1: locked VL; vertical and horizontal lock: VL = 0: unlocked VL = 1: locked DL; vertical and horizontal lock and colour detected: DL = 0: unlocked DL = 1: locked programmable width in LLC8 steps via HSB[7:0] 06H[7:0] and HSS[7:0] 07H[7:0] fine position adjustment in LLC2 steps via HDEL[1:0] 11H[5:4]; see Fig.32 Note 1. Function of HL is selectable via HLSEL[13H[3]]: a) HLSEL = 0: HL is standard horizontal lock indicator. b) HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g. VCRs). 2004 Jun 29 157 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE 18.2.2.20 Subaddress 13H Table 173 RT/X port output control; 13H[7:0] BIT 7 6 DESCRIPTION RTCO output enable X port XRH output selection SYMBOL VALUE RTCE 0 3-state 1 enabled 0 HREF; see Fig.32 1 HS: XRHS FUNCTION programmable width in LLC8 steps via HSB[7:0] 06H[7:0] and HSS[7:0] 07H[7:0] fine position adjustment in LLC2 steps via HDEL[1:0] 11H[5:4]; see Fig.32 5 and 4 X port XRV output selection 3 2 to 0 horizontal lock indicator selection XRVS[1:0] HLSEL XPD7 to XPD0 (port OFTS[2:0] output format selection); see Section 10.4 2004 Jun 29 00 V123; see Figs 30 and 31 01 ITU 656 related field ID; see Figs 30 and 31 10 inverted V123 11 inverted ITU 656 related field ID 0 copy of inverted HLCK status bit (default) 1 fast horizontal lock indicator (for special applications only) 000 ITU 656 001 ITU 656 like format with modified field blanking according to VGATE position (programmable via VSTA[8:0] 17H[0] 15H[7:0], VSTO[8:0] 17H[1] 16H[7:0] and VGPS[17H[2]]) 010 Y-CB-CR 4 : 2 : 2 8-bit format (no SAV/EAV codes inserted) 011 reserved 100 multiplexed AD2/AD1 bypass (bits 8 to 1) dependent on mode settings; if both ADCs are selected AD2 is output at CREF = 1 and AD1 is output at CREF = 0 101 multiplexed AD2/AD1 bypass (bits 7 to 0) dependent on mode settings; if both ADCs are selected AD2 is output at CREF = 1 and AD1 is output at CREF = 0 110 reserved 111 multiplexed ADC MSB/LSB bypass dependent on mode settings; only one ADC should be selected at a time; ADx8 to ADx1 are outputs at CREF = 1 and ADx7 to ADx0 are outputs at CREF = 0 158 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE 18.2.2.21 Subaddress 14H Table 174 Analog/ADC/compatibility control; 14H[7:0] BIT 7 6 DESCRIPTION compatibility bit for SAA7199 update time interval for AGC value 5 and 4 analog test select 3 2 XTOUTd output enable decoder status byte selection; see Table 180 1 and 0 ADC sample clock phase delay SYMBOL CM99 VALUE FUNCTION 0 off (default) 1 on (to be set only if SAA7199 is used for re-encoding in conjunction with RTCO active) UPTCV 0 horizontal update (once per line) 1 vertical update (once per field) AOSL[1:0] 00 AOUT connected to internal test point 1 01 AOUT connected to input AD1 10 AOUT connected to input AD2 11 AOUT connected to internal test point 2 0 pin P4 (XTOUTd) 3-stated 1 pin P4 (XTOUTd) enabled XTOUTE OLDSB APCK[1:0] 0 standard 1 backward compatibility to SAA7112 00 application dependent 01 10 11 2004 Jun 29 159 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... FRAME LINE COUNTING FIELD 50 Hz 60 Hz 1st 1 2nd 314 1st 2 2nd 315 1st 312 2nd 625 1st 4 2nd 267 160 1st 5 2nd 268 1st 265 2nd 3 DECIMAL VALUE MSB 17H[0] CONTROL BITS 7 TO 0 VSTA8 VSTA7 VSTA6 VSTA5 VSTA4 VSTA3 VSTA2 VSTA1 VSTA0 312 1 0 0 1 1 1 0 0 0 0... 0 0 0 0 0 0 0 0 0 ...310 1 0 0 1 1 0 1 1 1 262 1 0 0 0 0 0 1 1 0 0... 0 0 0 0 0 0 0 0 0 ...260 1 0 0 0 0 0 1 0 1 Philips Semiconductors Table 175 VGATE start; FID polarity change; 17H[0] and 15H[7:0] Start of VGATE pulse (LOW-to-HIGH transition) and polarity change of FID pulse, VGPS = 0; see Figs 30 and 31. HD-CODEC 2004 Jun 29 18.2.2.22 Subaddress 15H Product specification SAA7108AE; SAA7109AE This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... FRAME LINE COUNTING FIELD 50 Hz 60 Hz 1st 1 2nd 314 1st 2 2nd 315 1st 312 2nd 625 1st 4 2nd 267 161 1st 5 2nd 268 1st 265 2nd 3 DECIMAL VALUE MSB 17H[1] CONTROL BITS 7 TO 0 VSTO8 VSTO7 VSTO6 VSTO5 VSTO4 VSTO3 VSTO2 VSTO1 VSTO0 312 1 0 0 1 1 1 0 0 0 0... 0 0 0 0 0 0 0 0 0 ...310 1 0 0 1 1 0 1 1 1 262 1 0 0 0 0 0 1 1 0 0... 0 0 0 0 0 0 0 0 0 ...260 1 0 0 0 0 0 1 0 1 Philips Semiconductors Table 176 VGATE stop; 17H[1] and 16H[7:0] Stop of VGATE pulse (HIGH-to-LOW transition), VGPS = 0; see Figs 30 and 31. HD-CODEC 2004 Jun 29 18.2.2.23 Subaddress 16H Product specification SAA7108AE; SAA7109AE Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE 18.2.2.24 Subaddress 17H Table 177 Miscellaneous/VGATE MSBs; 17H[7:6] and 17H[2:0] BIT DESCRIPTION 7 LLC output enable SYMBOL LLCE VALUE FUNCTION 0 enable 1 3-state 0 enable 1 3-state 0 VGATE position according to Tables 175 and 176 1 VGATE occurs one line earlier during field 2 6 LLC2 output enable LLC2E 2 alternative VGATE position VGPS 1 MSB VGATE stop VSTO8 see Table 176 0 MSB VGATE start VSTA8 see Table 175 18.2.2.25 Subaddress 18H Table 178 Raw data gain control; RAWG[7:0] 18H[7:0]; see Fig.27 CONTROL BITS 7 TO 0 GAIN RAWG7 RAWG6 RAWG5 RAWG4 RAWG3 RAWG2 RAWG1 RAWG0 255 (double amplitude) 0 1 1 1 1 1 1 1 128 (nominal level) 0 1 0 0 0 0 0 0 0 (off) 0 0 0 0 0 0 0 0 18.2.2.26 Subaddress 19H Table 179 Raw data offset control; RAWO[7:0] 19H[7:0]; see Fig.27 CONTROL BITS 7 TO 0 OFFSET RAWO7 RAWO6 RAWO5 RAWO4 RAWO3 RAWO2 RAWO1 RAWO0 −128 LSB 0 0 0 0 0 0 0 0 0 LSB 1 0 0 0 0 0 0 0 +128 LSB 1 1 1 1 1 1 1 1 2004 Jun 29 162 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE 18.2.2.27 Subaddress 1FH Table 180 Status byte video decoder; 1FH[7:0]; read only register BIT DESCRIPTION 7 I2C-BUS CONTROL BIT OLDSB 14H[2] VALUE INTL − 0 non-interlaced 1 interlaced 0 both loops locked 1 unlocked 0 locked 1 unlocked 0 50 Hz 1 60 Hz not active status bit for interlace detection 6 5 status bit for horizontal and vertical loop HLVLN 0 status bit for locked horizontal frequency HLCK 1 identification bit for detected field frequency − FIDT FUNCTION 4 gain value for active luminance channel is limited; maximum (top) GLIMT − 0 1 active 3 gain value for active luminance channel is limited; minimum (bottom) GLIMB − 0 not active 1 active not active WIPA − 0 1 active copy protected source detected according to Macrovision version up to 7.01 COPRO 0 0 not active 1 active slow time constant active in WIPA mode SLTCA 2 white peak loop is activated 1 0 ready for capture (all internal loops locked) 0 not active 1 active not active RDCAP 0 0 1 active CODE 1 0 not active 1 active colour signal in accordance with selected standard has been detected 18.2.3 1 PROGRAMMING REGISTER AUDIO CLOCK GENERATION See equations in Section 9.6 and examples in Tables 35 and 36. 18.2.3.1 Subaddresses 30H to 32H Table 181 Audio master clock (AMCLK) cycles per field SUBADDRESS CONTROL BITS 7 TO 0 30H ACPF7 ACPF6 ACPF5 ACPF4 ACPF3 ACPF2 ACPF1 ACPF0 31H ACPF15 ACPF14 ACPF13 ACPF12 ACPF11 ACPF10 ACPF9 ACPF8 32H − − − − − − ACPF17 ACPF16 2004 Jun 29 163 Philips Semiconductors Product specification HD-CODEC 18.2.3.2 SAA7108AE; SAA7109AE Subaddresses 34H to 36H Table 182 Audio master clock (AMCLK) nominal increment SUBADDRESS CONTROL BITS 7 TO 0 34H ACNI7 ACNI ACNI5 ACNI4 ACNI3 ACNI2 ACNI1 ACNI0 35H ACNI15 ACNI14 ACNI13 ACNI12 ACNI11 ACNI10 ACNI9 ACNI8 36H − − ACNI21 ACNI20 ACNI19 ACNI18 ACNI17 ACNI16 SDIV2 SDIV1 SDIV0 LRDIV2 LRDIV1 LRDIV0 18.2.3.3 Subaddress 38H Table 183 Clock ratio audio master clock (AMXCLK) to serial bit clock (ASCLK) SUBADDRESS − 38H 18.2.3.4 CONTROL BITS 7 TO 0 − SDIV5 SDIV4 SDIV3 Subaddress 39H Table 184 Clock ratio serial bit clock (ASCLK) to channel select clock (ALRCLK) SUBADDRESS 39H 18.2.3.5 CONTROL BITS 7 TO 0 − − LRDIV5 LRDIV4 LRDIV3 Subaddress 3AH Table 185 Audio clock control; 3AH[3:0] BIT DESCRIPTION 3 audio PLL modes 2 SYMBOL VALUE APLL 0 PLL active, AMCLK is field-locked 1 PLL open, AMCLK is free-running 0 vertical reference pulse is taken from internal decoder 1 vertical reference is taken from XRV input (expansion port) 0 ALRCLK edges triggered by falling edges of ASCLK 1 ALRCLK edges triggered by rising edges of ASCLK 0 ASCLK edges triggered by falling edges of AMCLK 1 ASCLK edges triggered by rising edges of AMCLK audio master clock vertical reference AMVR 1 ALRCLK phase LRPH 0 ASCLK phase SCPH 18.2.4 18.2.4.1 FUNCTION PROGRAMMING REGISTER VBI DATA SLICER Subaddress 40H Table 186 Slicer control 1; 40H[6:4] BIT 6 5 4 2004 Jun 29 DESCRIPTION Hamming check framing code error amplitude searching SYMBOL VALUE HAM_N 0 Hamming check for 2 bytes after framing code, dependent on data type (default) 1 no Hamming check 0 one framing code error allowed 1 no framing code errors allowed 0 amplitude searching active (default) 1 amplitude searching stopped FCE HUNT_N 164 FUNCTION Philips Semiconductors Product specification HD-CODEC 18.2.4.2 SAA7108AE; SAA7109AE Subaddresses 41H to 57H Table 187 Line control register; LCR2 to LCR24 (41H to 57H); see Sections 9.2 and 9.4 NAME DESCRIPTION BITS 7 TO 4 (41H TO 57H) BITS 3 TO 0 (41H TO 57H) DT[3:0] 62H[3:0] (FIELD 1) DT[3:0] 62H[3:0] (FIELD 2) 27H 0000 0000 FRAMING CODE WST625 teletext EuroWST, CCST CC625 European Closed Caption 001 0001 0001 VPS video programming service 9951H 0010 0010 WSS wide screen signalling bits 1E3C1FH 0011 0011 WST525 US teletext (WST) 27H 0100 0100 CC525 US Closed Caption (line 21) 001 0101 0101 Test line video component signal, VBI region − 0110 0110 Intercast raw data − 0111 0111 General text teletext programmable 1000 1000 VITC625 VITC/EBU time codes (Europe) programmable 1001 1001 VITC525 VITC/SMPTE time codes (USA) programmable 1010 1010 Reserved reserved − 1011 1011 NABTS US NABTS − 1100 1100 Japtext MOJI (Japanese) programmable (A7H) 1101 1101 JFS Japanese format switch (L20/22) programmable 1110 1110 − 1111 1111 Active video video component signal, active video region (default) 18.2.4.3 Subaddress 58H Table 188 Programmable framing code; slicer set 58H[7:0]; see Tables 28 and 187 FRAMING CODE FOR PROGRAMMABLE DATA TYPES Default value 18.2.4.4 CONTROL BITS 7 TO 0 FC[7:0] = 40H Subaddress 59H Table 189 Horizontal offset for slicer; slicer set 59H and 5BH HORIZONTAL OFFSET Recommended value 2004 Jun 29 CONTROL BITS 5BH[2:0] CONTROL BITS 59H[7:0] HOFF[10:8] = 3H HOFF[7:0] = 47H 165 Philips Semiconductors Product specification HD-CODEC 18.2.4.5 SAA7108AE; SAA7109AE Subaddress 5AH Table 190 Vertical offset for slicer; slicer set 5AH and 5BH CONTROL BIT 5BH[4] VOFF8 CONTROL BITS 5AH[7:0] VOFF[7:0] Minimum value 0 0 00H Maximum value 312 1 38H Value for 50 Hz 625 lines input 0 03H Value for 60 Hz 525 lines input 0 06H VERTICAL OFFSET 18.2.4.6 Subaddress 5BH Table 191 Field offset, and MSBs for horizontal and vertical offsets; slicer set 5BH[7:6] See Sections 18.2.4.4 and 18.2.4.5 for HOFF[10:8] 5BH[2:0] and VOFF8[5BH[4]]. BIT DESCRIPTION SYMBOL 7 field offset 6 18.2.4.7 recode FOFF RECODE VALUE FUNCTION 0 no modification of internal field indicator (default for 50 Hz 625 lines input sources) 1 invert field indicator (default for 60 Hz 525 lines input sources) 0 let data unchanged (default) 1 convert 00H and FFH data bytes into 03H and FCH Subaddress 5DH Table 192 Header and data identification (DID; ITU 656) code control; slicer set 5DH[7:0] BIT DESCRIPTION 7 5 to 0 SYMBOL field ID and V-blank selection for text output (F and V reference selection) FVREF default; DID[5:0] = 00H DID[5:0] special cases of DID programming 18.2.4.8 VALUE FUNCTION 0 F and V output of slicer is LCR table dependent 1 F and V output is taken from decoder real time signals EVEN_ITU and VBLNK_ITU 00 0000 ANC header framing; see Fig.39 and Table 34 11 1110 DID[5:0] = 3EH SAV/EAV framing, with FVREF = 1 11 1111 DID[5:0] = 3FH SAV/EAV framing, with FVREF = 0 Subaddress 5EH Table 193 Sliced data identification (SDID) code; slicer set 5EH[5:0] BIT 5 to 0 2004 Jun 29 DESCRIPTION SDID codes SYMBOL VALUE SDID[5:0] 00H 166 FUNCTION default Philips Semiconductors Product specification HD-CODEC 18.2.4.9 SAA7108AE; SAA7109AE Subaddress 60H Table 194 Slicer status byte 0; 60H[6:2]; read only register BIT DESCRIPTION 6 framing code valid SYMBOL VALUE FC8V 5 framing code valid FC7V 4 VPS valid VPSV 3 PALplus valid PPV 2 Closed Caption valid CCV FUNCTION 0 no framing code (0 error) in the last frame detected 1 framing code with 0 error detected 0 no framing code (1 error) in the last frame detected 1 framing code with 1 error detected 0 no VPS in the last frame 1 VPS detected 0 no PALplus in the last frame 1 PALplus detected 0 no Closed Caption in the last frame 1 Closed Caption detected 18.2.4.10 Subaddresses 61H and 62H Table 195 Slicer status byte 1; 61H[5:0] and slicer status byte 2; 62H[7:0]; read only registers SUBADDRESS BIT SYMBOL DESCRIPTION 61H 5 F21_N field ID as seen by the VBI slicer; for field 1: bit 5 = 0 4 to 0 LN[8:4] line number 62H 18.2.5 18.2.5.1 7 to 4 LN[3:0] 3 to 0 DT[3:0] data type; according to Table 28 PROGRAMMING REGISTER INTERFACES AND SCALER PART Subaddress 80H Table 196 Global control 1; global set 80H[6:4] SWRST moved to subaddress 88H[5]; note 1. CONTROL BITS 6 TO 4 TASK ENABLE CONTROL SMOD TEB TEA Task of register set A is disabled X X 0 Task of register set A is enabled X X 1 Task of register set B is disabled X 0 X Task of register set B is enabled X 1 X The scaler window defines the F and V timing of the scaler output 0 X X VBI data slicer defines the F and V timing of the scaler output 1 X X Note 1. X = don’t care. 2004 Jun 29 167 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 197 Global control 1; global set 80H[3:0]; note 1 CONTROL BITS 3 TO 0 I PORT AND SCALER BACK-END CLOCK SELECTION ICKS3 ICKS2 ICKS1 ICKS0 ICLK output and back-end clock is line-locked clock LLC from decoder X X 0 0 ICLK output and back-end clock is XCLK from X port X X 0 1 ICLK output is LLC and back-end clock is LLC2 clock X X(2) 1 0 Back-end clock is the ICLK input X X 1 1 IDQ pin carries the data qualifier X 0 X X IDQ pin carries a gated back-end clock (IDQ AND CLK) X 1 X X IDQ generation only for valid data 0 X X X IDQ qualifies valid data inside the scaling region and all data outside the scaling region 1 X X X Notes 1. Although the ICLKO I/O is independent of ICKS2 and ICKS3, this selection can only be used if ICKS2 = 1. 2. X = don’t care. 18.2.5.2 Subaddresses 83H to 87H Table 198 X port I/O enable and output clock phase control; global set 83H[5:4] CONTROL BITS 5 AND 4 OUTPUT CLOCK PHASE CONTROL XPCK1 XPCK0 XCLK default output phase, recommended value 0 0 XCLK output inverted 0 1 XCLK phase shifted by about 3 ns 1 0 XCLK output inverted and shifted by about 3 ns 1 1 Table 199 X port I/O enable and output clock phase control; global set 83H[2:0] CONTROL BITS 2 TO 0 X PORT I/O ENABLE XRQT XPE1 XPE0 X port output is disabled by software X(1) 0 0 X port output is enabled by software X 0 1 X port output is enabled by pin XTRI at logic 0 X 1 0 X port output is enabled by pin XTRI at logic 1 X 1 1 XRDY output signal is A/B task flag from event handler (A = 1) 0 X X XRDY output signal is ready signal from scaler path (XRDY = 1 means SAA7108AE; SAA7109AE is ready to receive data) 1 X X Note 1. X = don’t care 2004 Jun 29 168 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 200 I port signal definitions; global set 84H[7:6] and 86H[5] CONTROL BITS I PORT SIGNAL DEFINITIONS 86H[5] 84H[7:6] IDG02 IDG01 IDG00 IGP0 is output field ID, as defined by OFIDC[90H[6]] 0 0 0 IGP0 is A/B task flag, as defined by CONLH[90H[7]] 0 0 1 IGP0 is sliced data flag, framing the sliced VBI data at the I port 0 1 0 IGP0 is set to logic 0 (default polarity) 0 1 1 IGP0 is the output FIFO almost filled flag 1 0 0 IGP0 is the output FIFO overflow flag 1 0 1 IGP0 is the output FIFO almost full flag, level to be programmed in subaddress 86H 1 1 0 IGP0 is the output FIFO almost empty flag, level to be programmed in subaddress 86H 1 1 1 Table 201 I port signal definitions; global set 84H[5:4] and 86H[4] CONTROL BITS I PORT SIGNAL DEFINITIONS 86H[4] 84H[5:4] IDG12 IDG11 IDG10 IGP1 is output field ID, as defined by OFIDC[90H[6]] 0 0 0 IGP1 is A/B task flag, as defined by CONLH[90H[7]] 0 0 1 IGP1 is sliced data flag, framing the sliced VBI data at the I port 0 1 0 IGP1 is set to logic 0 (default polarity) 0 1 1 IGP1 is the output FIFO almost filled flag 1 0 0 IGP1 is the output FIFO overflow flag 1 0 1 IGP1 is the output FIFO almost full flag, level to be programmed in subaddress 86H 1 1 0 IGP1 is the output FIFO almost empty flag, level to be programmed in subaddress 86H 1 1 1 Table 202 I port output signal definitions; global set 84H[3:0]; note 1 CONTROL BITS 3 TO 0 I PORT OUTPUT SIGNAL DEFINITIONS IDV1 IDV0 IDH1 IDH0 IGPH is a H gate signal, framing the scaler output X X 0 0 IGPH is an extended H gate (framing H gate during scaler output and scaler input H reference outside the scaler window) X X 0 1 IGPH is a horizontal trigger pulse, on active going edge of H gate X X 1 0 IGPH is a horizontal trigger pulse, on active going edge of extended H gate X X 1 1 IGPV is a V gate signal, framing scaled output lines 0 0 X X IGPV is the V reference signal from scaler input 0 1 X X IGPV is a vertical trigger pulse, derived from V gate 1 0 X X IGPV is a vertical trigger pulse derived from input V reference 1 1 X X Note 1. X = don’t care. 2004 Jun 29 169 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 203 X port signal definitions text slicer; global set 85H[7:5]; note 1 CONTROL BITS 7 TO 5 X PORT SIGNAL DEFINITIONS TEXT SLICER ISWP1 ISWP0 ILLV Video data limited to range 1 to 254 X X 0 Video data limited to range 8 to 247 X X 1 Dword byte swap, influences serial output timing D0 D1 D2 D3 ⇒ FF 00 00 SAV CB0 Y0 CR0 Y1 0 0 X D1 D0 D3 D2 ⇒ 00 FF SAV 00 Y0 CB0 Y1 CR0 0 1 X D2 D3 D0 D1 ⇒ 00 SAV FF 00 CR0 Y1 CB0 Y0 1 0 X D3 D2 D1 D0 ⇒ SAV 00 00 FF Y1 CR0 Y0 CB0 1 1 X Note 1. X = don’t care. Table 204 I port reference signal polarities; global set 85H[4:0]; note 1 CONTROL BITS 4 TO 0 I PORT REFERENCE SIGNAL POLARITIES IG0P IG1P IRVP IRHP IDQP IDQ at default polarity (1 = active) X X X X 0 IDQ is inverted X X X X 1 IGPH at default polarity (1 = active) X X X 0 X IGPH is inverted X X X 1 X IGPV at default polarity (1 = active) X X 0 X X IGPV is inverted X X 1 X X IGP1 at default polarity X 0 X X X IGP1 is inverted X 1 X X X IGP0 at default polarity 0 X X X X IGP0 is inverted 1 X X X X Note 1. X = don’t care. 2004 Jun 29 170 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 205 I port FIFO flag control and arbitration; global set 86H[7:4]; note 1 CONTROL BITS 7 TO 4 FUNCTION VITX1 See subaddress 84H: IDG11 and IDG10 VITX0 IDG02 IDG12 X X X 0 X X X 1 X X 0 X X X 1 X I port data output inhibited 0 0 X X Only video data are transferred 0 1 X X Only text data are transferred (no EAV, SAV will occur) 1 0 X X Text and video data are transferred, text has priority 1 1 X X See subaddress 84H: IDG01 and IDG00 I port signal definitions Note 1. X = don’t care. Table 206 I port FIFO flag control and arbitration; global set 86H[3:0]; note 1 CONTROL BITS 3 TO 0 I PORT FIFO FLAG CONTROL AND ARBITRATION FFL1 FFL0 FEL1 FEL0 <16 Dwords X X 0 0 <8 Dwords X X 0 1 <4 Dwords X X 1 0 0 Dwords X X 1 1 ≥16 Dwords 0 0 X X ≥24 Dwords 0 1 X X ≥28 Dwords 1 0 X X 32 Dwords 1 1 X X FAE FIFO flag almost empty level FAF FIFO flag almost full level Note 1. X = don’t care. 2004 Jun 29 171 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 207 I port I/O enable, output clock and gated clock phase control; global set 87H[7:4]; note 1 CONTROL BITS 7 TO 4 OUTPUT CLOCK AND GATED CLOCK PHASE CONTROL IPCK3(2) IPCK2(2) IPCK1 IPCK0 ICLK default output phase X X 0 0 ICLK phase shifted by 1⁄2 clock cycle ⇒ recommended for ICKS1 = 1 and ICKS0 = 0 (subaddress 80H) X X 0 1 ICLK phase shifted by about 3 ns X X 1 0 ICLK phase shifted by 2 clock cycle + approximately 3 ns ⇒ alternatively to setting ‘01’ X X 1 1 IDQ = gated clock default output phase 0 0 X X 0 1 X X 1⁄ IDQ = gated clock phase shifted by for gated clock output 1⁄ 2 clock cycle ⇒ recommended IDQ = gated clock phase shifted by approximately 3 ns 1 0 X X IDQ = gated clock phase shifted by 1⁄2 clock cycle + approximately 3 ns ⇒ alternatively to setting ‘01’ 1 1 X X Notes 1. X = don’t care. 2. IPCK3 and IPCK2 only affects the gated clock (subaddress 80H, bit ICKS2 = 1). Table 208 I port I/O enable, output clock and gated clock phase control; global set 87H[1:0] CONTROL BITS 1 AND 0 I PORT I/O ENABLE IPE1 IPE0 I port output is disabled by software 0 0 I port output is enabled by software 0 1 I port output is enabled by pin ITRI at logic 0 1 0 I port output is enabled by pin ITRI at logic 1 1 1 2004 Jun 29 172 Philips Semiconductors Product specification HD-CODEC 18.2.5.3 SAA7108AE; SAA7109AE Subaddress 88H Table 209 Power save control; global set 88H[7:4]; note 1 CONTROL BITS 7 TO 4 POWER SAVE CONTROL CH4EN CH2EN SWRST(2) DPROG DPROG = 0 after reset X X X 0 DPROG = 1 can be used to assign that the device has been programmed; this bit can be monitored in the scalers status byte, bit PRDON; if DPROG was set to logic 1 and PRDON status bit shows a logic 0, a power-up or start-up fail has occurred X X X 1 Scaler path is reset to its idle state, software reset X X 0 X Scaler is switched back to operation X X 1 X AD1x analog channel is in Power-down mode X 0 X X AD1x analog channel is active X 1 X X AD2x analog channel is in Power-down mode 0 X X X AD2x analog channel is active 1 X X X Notes 1. X = don’t care. 2. Bit SWRST is now located here. Table 210 Power save control; global set 88H[3] and 88H[1:0]; note 1 CONTROL BITS 3, 1 AND 0 POWER SAVE CONTROL SLM3 SLM1 SLM0 Decoder and VBI slicer are in operational mode X X 0 Decoder and VBI slicer are in Power-down mode; scaler only operates, if scaler input and ICLK source is the X port (refer to subaddresses 80H and 91H/C1H) X X 1 Scaler is in operational mode X 0 X Scaler is in Power-down mode; scaler in power-down stops I port output X 1 X Audio clock generation active 0 X X Audio clock generation in power-down and output disabled 1 X X Note 1. X = don’t care. 2004 Jun 29 173 Philips Semiconductors Product specification HD-CODEC 18.2.5.4 SAA7108AE; SAA7109AE Subaddress 8FH Table 211 Status information scaler part; 8FH[7:0]; read only register BIT I2C-BUS STATUS BIT 7 XTRI status on input pin XTRI, if not used for 3-state control, usable as hardware flag for software use 6 ITRI status on input pin ITRI, if not used for 3-state control, usable as hardware flag for software use 5 FFIL status of the internal ‘FIFO almost filled’ flag 4 FFOV status of the internal ‘FIFO overflow’ flag 3 PRDON copy of bit DPROG, can be used to detect power-up and start-up fails 2 ERROF error flag of scalers output formatter, normally set, if the output processing needs to be interrupted, due to input/output data rate conflicts, e.g. if output data rate is much too low and all internal FIFO capacity used FUNCTION(1) 1 FIDSCI status of the field sequence ID at the scalers input 0 FIDSCO status of the field sequence ID at the scalers output, scaler processing dependent Note 1. Status information is unsynchronized and shows the actual status at the time of I2C-bus read. 18.2.5.5 Subaddresses 90H and C0H Table 212 Task handing control; register set A [90H[7:6]] and B [C0H[7:6]]; note 1 CONTROL BITS 7 AND 6 EVENT HANDLER CONTROL CONLH OFIDC Output field ID is field ID from scaler input X 0 Output field ID is task status flag, which changes every time an selected task is activated (not synchronized to input field ID) X 1 Scaler SAV/EAV byte bit 7 and task flag = 1, default 0 X Scaler SAV/EAV byte bit 7 and task flag = 0 1 X Note 1. X = don’t care. Table 213 Task handling control; register set A [90H[5:3]] and B [C0H[5:3]] CONTROL BITS 5 TO 3 EVENT HANDLER CONTROL FSKP2 FSKP1 FSKP0 Active task is carried out directly 0 0 0 1 field is skipped before active task is carried out 0 0 1 ... fields are skipped before active task is carried out ... ... ... 6 fields are skipped before active task is carried out 1 1 0 7 fields are skipped before active task is carried out 1 1 1 2004 Jun 29 174 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 214 Task handling control; register set A [90H[2:0]] and B [C0H[2:0]]; note 1 CONTROL BITS 2 TO 0 EVENT HANDLER CONTROL RPTSK STRC1 STRC0 Event handler triggers immediately after finishing a task X 0 0 Event handler triggers with next V-sync X 0 1 Event handler triggers with field ID = 0 X 1 0 Event handler triggers with field ID = 1 X 1 1 If active task is finished, handling is taken over by the next task 0 X X Active task is repeated once, before handling is taken over by the next task 1 X X Note 1. X = don’t care. 18.2.5.6 Subaddresses 91H to 93H Table 215 X port formats and configuration; register set A [91H[7:3]] and B [C1H[7:3]]; note 1 SCALER INPUT FORMAT AND CONFIGURATION SOURCE SELECTION CONTROL BITS 7 TO 3 CONLV HLDFV SCSRC1 SCSRC0 SCRQE Only if XRQT[83H[2]] = 1: scaler input source reacts on SAA7108AE; SAA7109AE request X X X X 0 Scaler input source is a continuous data stream, which cannot be interrupted (must be logic 1 if SAA7108AE; SAA7109AE decoder part is source of scaler or XRQT[83H[2]] = 0) X X X X 1 Scaler input source is data from decoder, data type is provided according to Table 28 X X 0 0 X Scaler input source is Y-CB-CR data from X port X X 0 1 X Scaler input source is raw digital CVBS from selected analog channel, for backward compatibility only, further use is not recommended X X 1 0 X Scaler input source is raw digital CVBS (or 16-bit Y + CB-CR, if no 16-bit output are active) from X port X X 1 1 X SAV/EAV code bits 6 and 5 (F and V) may change between SAV and EAV X 0 X X X SAV/EAV code bits 6 and 5 (F and V) are synchronized to scalers output line start X 1 X X X SAV/EAV code bit 5 (V) and V gate on pin IGPV as generated by the internal processing; see Fig.45 0 X X X X SAV/EAV code bit 5 (V) and V gate are inverted 1 X X X X Note 1. X = don’t care. 2004 Jun 29 175 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 216 X port formats and configuration; register set A [91H[2:0]] and B [C1H[2:0]]; note 1 SCALER INPUT FORMAT AND CONFIGURATION FORMAT CONTROL CONTROL BITS 2 TO 0 FSC2(2) FSC1(2) FSC0 Input is Y-CB-CR 4 : 2 : 2 like sampling scheme X X 0 Input is Y-CB-CR 4 : 1 : 1 like sampling scheme X X 1 Chroma is provided every line, default 0 0 X Chroma is provided every 2nd line 0 1 X Chroma is provided every 3rd line 1 0 X Chroma is provided every 4th line 1 1 X Notes 1. X = don’t care. 2. FSC2 and FSC1 only to be used, if X port input source don’t provide chroma information for every input line. X port input stream must contain dummy chroma bytes. Table 217 X port input reference signal definitions; register set A [92H[7:4]] and B [C2H[7:4]]; note 1 CONTROL BITS 7 TO 4 X PORT INPUT REFERENCE SIGNAL DEFINITIONS Rising edge of XRV input and decoder V123 is vertical reference XFDV XFDH XDV1 XDV0 X X X 0 Falling edge of XRV input and decoder V123 is vertical reference X X X 1 XRV is a V-sync or V gate signal X X 0 X XRV is a frame sync, V pulses are generated internally on both edges of FS input X X 1 X X port field ID is state of XRH at reference edge on XRV (defined by XFDV) X 0 X X Field ID (decoder and X port field ID) is inverted X 1 X X Reference edge for field detection is falling edge of XRV 0 X X X Reference edge for field detection is rising edge of XRV 1 X X X Note 1. X = don’t care. 2004 Jun 29 176 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 218 X port input reference signal definitions; register set A [92H[3:0]] and B [C2H[3:0]]; note 1 CONTROL BITS 3 TO 0 X PORT INPUT REFERENCE SIGNAL DEFINITIONS XCODE XDH XDQ XCKS XCLK input clock and XDQ input qualifier are needed X X X 0 Data rate is defined by XCLK only, no XDQ signal used X X X 1 Data are qualified at XDQ input at logic 1 X X 0 X Data are qualified at XDQ input at logic 0 X X 1 X Rising edge of XRH input is horizontal reference X 0 X X Falling edge of XRH input is horizontal reference X 1 X X Reference signals are taken from XRH and XRV 0 X X X Reference signals are decoded from EAV and SAV 1 X X X Note 1. X = don’t care. Table 219 I port output format and configuration; register set A [93H[7:5]] and B [C3H[7:5]]; note 1 CONTROL BITS 7 TO 5 I PORT OUTPUT FORMATS AND CONFIGURATION ICODE I8_16 FYSK All lines will be output X X 0 Skip the number of leading Y only lines, as defined by FOI1 and FOI0 X X 1 Dwords are transferred byte wise, see subaddress 85H bits ISWP1 and ISWP0 X 0 X Dwords are transferred 16-bit word wise via IPD and HPD, see subaddress 85H bits ISWP1 and ISWP0 X 1 X No ITU 656 like SAV/EAV codes are available 0 X X ITU 656 like SAV/EAV codes are inserted in the output data stream, framed by a qualifier 1 X X Note 1. X = don’t care. 2004 Jun 29 177 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 220 I port output format and configuration; register set A [93H[4:0]] and B [C3H[4:0]]; note 1 CONTROL BITS 4 TO 0 I PORT OUTPUT FORMATS AND CONFIGURATION FOI1 FOI0 FSI2 FSI1 FSI0 4 : 2 : 2 Dword formatting X X 0 0 0 4 : 1 : 1 Dword formatting X X 0 0 1 4 : 2 : 0, only every 2nd line Y + CB-CR output, in between Y only output X X 0 1 0 4 : 1 : 0, only every 4th line Y + CB-CR output, in between Y only output X X 0 1 1 Y only X X 1 0 0 Not defined X X 1 0 1 Not defined X X 1 1 0 Not defined X X 1 1 1 No leading Y only line, before 1st Y + CB-CR line is output 0 0 X X X 1 leading Y only line, before 1st Y + CB-CR line is output 0 1 X X X 2 leading Y only lines, before 1st Y + CB-CR line is output 1 0 X X X 3 leading Y only lines, before 1st Y + CB-CR line is output 1 1 X X X Note 1. X = don’t care. 18.2.5.7 Subaddresses 94H to 9BH Table 221 Horizontal input window start; register set A [94H[7:0]; 95H[3:0]] and B [C4H[7:0]; C5H[3:0]] HORIZONTAL INPUT ACQUISITION WINDOW DEFINITION OFFSET IN X (HORIZONTAL) DIRECTION(1) CONTROL BITS A [95H[3:0]] B [C5H[3:0]] A [94H[7:0]] B [C4H[7:0]] XO11 XO10 XO9 XO8 XO7 XO6 XO5 XO4 XO3 XO2 XO1 XO0 A minimum of 2 should be kept, due to a line counting mismatch 0 0 0 0 0 0 0 0 0 0 1 0 Odd offsets are changing the CB-CR sequence in the output stream to CR-CB sequence 0 0 0 0 0 0 0 0 0 0 1 1 Maximum possible pixel offset = 4095 1 1 1 1 1 1 1 1 1 1 1 1 Note 1. Reference for counting are luminance samples. 2004 Jun 29 178 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 222 Horizontal input window length; register set A [96H[7:0]; 97H[3:0]] and B [C6H[7:0]; C7H[3:0]] HORIZONTAL INPUT ACQUISITION WINDOW DEFINITION INPUT WINDOW LENGTH IN X (HORIZONTAL) DIRECTION(1) CONTROL BITS A [97H[3:0]] B [C7H[3:0]] A [96H[7:0]] B [C6H[7:0]] XS11 XS10 XS9 XS8 XS7 XS6 XS5 XS4 XS3 XS2 XS1 XS0 No output 0 0 0 0 0 0 0 0 0 0 0 0 Odd lengths are allowed, but will be rounded up to even lengths 0 0 0 0 0 0 0 0 0 0 0 1 Maximum possible number of input pixels = 4095 1 1 1 1 1 1 1 1 1 1 1 1 Note 1. Reference for counting are luminance samples. Table 223 Vertical input window start; register set A [98H[7:0]; 99H[3:0]] and B [C8H[7:0]; C9H[3:0]] CONTROL BITS VERTICAL INPUT ACQUISITION WINDOW DEFINITION OFFSET IN Y (VERTICAL) DIRECTION(1) A [99H[3:0]] B [C9H[3:0]] A [98H[7:0]] B [C8H[7:0]] YO11 YO10 YO9 YO8 YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0 Line offset = 0 0 0 0 0 0 0 0 0 0 0 0 0 Line offset = 1 0 0 0 0 0 0 0 0 0 0 0 1 Maximum line offset = 4095 1 1 1 1 1 1 1 1 1 1 1 1 Note 1. For trigger condition: STRC[1:0] 90H[1:0] = 00; YO + YS > (number of input lines per field − 2), will result in field dropping. Other trigger conditions: YO > (number of input lines per field − 2), will result in field dropping. Table 224 Vertical input window length; register set A [9AH[7:0]; 9BH[3:0]] and B [CAH[7:0]; CBH[3:0]] VERTICAL INPUT ACQUISITION WINDOW DEFINITION INPUT WINDOW LENGTH IN Y (VERTICAL) DIRECTION(1) CONTROL BITS A [9BH[3:0]] B [CBH[3:0]] A [9AH[7:0]] B [CAH[7:0]] YS11 YS10 YS9 YS8 YS7 YS6 YS5 YS4 YS3 YS2 YS1 YS0 No input lines 0 0 0 0 0 0 0 0 0 0 0 0 1 input line 0 0 0 0 0 0 0 0 0 0 0 1 Maximum possible number of input lines = 4095 1 1 1 1 1 1 1 1 1 1 1 1 Note 1. For trigger condition: STRC[1:0] 90H[1:0] = 00; YO + YS > (number of input lines per field − 2), will result in field dropping. Other trigger conditions: YS > (number of input lines per field − 2), will result in field dropping. 2004 Jun 29 179 Philips Semiconductors Product specification HD-CODEC 18.2.5.8 SAA7108AE; SAA7109AE Subaddresses 9CH to 9FH Table 225 Horizontal output window length; register set A [9CH[7:0]; 9DH[3:0]] and B [CCH[7:0]; CDH[3:0]] HORIZONTAL OUTPUT ACQUISITION WINDOW DEFINITION NUMBER OF DESIRED OUTPUT PIXEL IN X (HORIZONTAL) DIRECTION(1) CONTROL BITS A [9DH[3:0]] B [CDH[3:0]] A [9CH[7:0]] B [CCH[7:0]] XD11 XD10 XD9 XD8 XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0 No output 0 0 0 0 0 0 0 0 0 0 0 0 Odd lengths are allowed, but will be filled up to even lengths 0 0 0 0 0 0 0 0 0 0 0 1 Maximum possible number of input pixels = 4095; note 2 1 1 1 1 1 1 1 1 1 1 1 1 Notes 1. Reference for counting are luminance samples. 2. If the desired output length is greater than the number of scaled output pixels, the last scaled pixel is repeated. Table 226 Vertical output window length; register set A [9EH[7:0]; 9FH[3:0]] and B [CEH[7:0]; CFH[3:0]] VERTICAL OUTPUT ACQUISITION WINDOW DEFINITION NUMBER OF DESIRED OUTPUT LINES IN Y (VERTICAL) DIRECTION CONTROL BITS A [9FH[3:0]] B [CFH[3:0]] A [9EH[7:0]] B [CEH[7:0]] YD11 YD10 YD9 YD8 YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0 No output 0 0 0 0 0 0 0 0 0 0 0 0 1 pixel 0 0 0 0 0 0 0 0 0 0 0 1 Maximum possible number of output lines = 4095; note 1 1 1 1 1 1 1 1 1 1 1 1 1 Note 1. If the desired output length is greater than the number of scaled output lines, the processing is cut. 18.2.5.9 Subaddresses A0H to A2H Table 227 Horizontal prescaling; register set A [A0H[5:0]] and B [D0H[5:0]] CONTROL BITS 5 TO 0 HORIZONTAL INTEGER PRESCALING RATIO (XPSC) XPSC5 XPSC4 XPSC3 XPSC2 XPSC1 XPSC0 Not allowed 0 0 0 0 0 0 Downscale = 1 0 0 0 0 0 1 Downscale = 1⁄2 0 0 0 0 1 0 ... ... ... ... ... ... ... 1 1 1 1 1 1 Downscale = 2004 Jun 29 1⁄ 63 180 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 228 Accumulation length; register set A [A1H[5:0]] and B [D1H[5:0]] CONTROL BITS 5 TO 0 HORIZONTAL PRESCALER ACCUMULATION SEQUENCE LENGTH (XACL) XACL5 XACL4 XACL3 XACL2 XACL1 XACL0 Accumulation length = 1 0 0 0 0 0 0 Accumulation length = 2 0 0 0 0 0 1 ... ... ... ... ... ... ... Accumulation length = 64 1 1 1 1 1 1 Table 229 Prescaler DC gain and FIR prefilter control; register set A [A2H[7:4]] and B [D2H[7:4]]; note 1 CONTROL BITS 7 TO 4 FIR PREFILTER CONTROL PFUV1 PFUV0 PFY1 PFY0 X X 0 0 (1 2 1) X X 0 1 (−1 1 1.75 4.5 1.75 1 −1) X X 1 0 (1 2 2 2 1) X X 1 1 0 0 X X Luminance FIR filter bypassed H_y(z) = H_y(z) = H_y(z) = 1⁄ 4 1⁄ 8 1⁄ 8 Chrominance FIR filter bypassed H_uv(z) = 1⁄ 0 1 X X H_uv(z) = 1⁄32 (3 8 10 8 3) 1 0 X X H_uv(z) = 1⁄8 (1 2 2 2 1) 1 1 X X 4 (1 2 1) Note 1. X = don’t care. Table 230 Prescaler DC gain and FIR prefilter control; register set A [A2H[3:0]] and B [D2H[3:0]]; note 1 CONTROL BITS 3 TO 0 PRESCALER DC GAIN XC2_1 XDCG2 XDCG1 XDCG0 X 0 0 0 2 X 0 0 1 Prescaler output is renormalized by gain factor = 1⁄4 X 0 1 0 Prescaler output is renormalized by gain factor = 1 Prescaler output is renormalized by gain factor = 1⁄ Prescaler output is renormalized by gain factor = 1⁄ 8 X 0 1 1 Prescaler output is renormalized by gain factor = 1⁄ 16 X 1 0 0 Prescaler output is renormalized by gain factor = 1⁄ 32 X 1 0 1 Prescaler output is renormalized by gain factor = 1⁄64 X 1 1 0 X 1 1 1 Weighting of all accumulated samples is factor 1; e.g. XACL = 4 ⇒ sequence 1 + 1 + 1 + 1 + 1 0 X X X Weighting of samples inside sequence is factor 2; e.g. XACL = 4 ⇒ sequence 1 + 2 + 2 + 2 + 1 1 X X X Prescaler output is renormalized by gain factor = 1⁄ 128 Note 1. X = don’t care. 2004 Jun 29 181 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE 18.2.5.10 Subaddresses A4H to A6H Table 231 Luminance brightness control; register set A [A4H[7:0]] and B [D4H[7:0]] LUMINANCE BRIGHTNESS CONTROL CONTROL BITS 7 TO 0 BRIG7 BRIG6 BRIG5 BRIG4 BRIG3 BRIG2 BRIG1 BRIG0 Value = 0 0 0 0 0 0 0 0 0 Nominal value = 128 1 0 0 0 0 0 0 0 Value = 255 1 1 1 1 1 1 1 1 Table 232 Luminance contrast control; register set A [A5H[7:0]] and B [D5H[7:0]] LUMINANCE CONTRAST CONTROL Gain = 0 Gain = 1⁄ CONTROL BITS 7 TO 0 CONT7 CONT6 CONT5 CONT4 CONT3 CONT2 CONT1 CONT0 0 0 0 0 0 0 0 0 64 0 0 0 0 0 0 0 1 Nominal gain = 64 0 1 0 0 0 0 0 0 127⁄ 0 1 1 1 1 1 1 1 Gain = 64 Table 233 Chrominance saturation control; register set A [A6H[7:0]] and B [D6H[7:0]] CHROMINANCE SATURATION CONTROL CONTROL BITS 7 TO 0 SATN7 SATN6 SATN5 SATN4 SATN3 SATN2 SATN1 SATN0 Gain = 0 0 0 0 0 0 0 0 0 Gain = 1⁄64 0 0 0 0 0 0 0 1 Nominal gain = 64 0 1 0 0 0 0 0 0 127⁄ 0 1 1 1 1 1 1 1 Gain = 64 18.2.5.11 Subaddresses A8H to AEH Table 234 Horizontal luminance scaling increment; register set A [A8H[7:0]; A9H[7:0]] and B [D8H[7:0]; D9H[7:0]] CONTROL BITS HORIZONTAL LUMINANCE SCALING INCREMENT A [A9H[7:4]] B [D9H[7:4]] A [A9H[3:0]] B [D9H[3:0]] A [A8H[7:4]] B [D8H[7:4]] A [A8H[3:0]] B [D8H[3:0]] XSCY[15:12](1) XSCY[11:8] XSCY[7:4] XSCY[3:0] 0000 0000 0000 0000 0000 0001 0010 0110 Scale = 1024⁄1023 zoom 0000 0011 1111 1111 Scale = 1, equals 1024 0000 0100 0000 0000 downscale 0000 0100 0000 0001 downscale 0001 1111 1111 1111 Scale = 1024⁄ (theoretical) zoom 1 1024⁄ 294, lower limit defined Scale = data path structure Scale = Scale = 1024⁄ 1025 1024⁄ 8191 by Note 1. Bits XSCY[15:13] are reserved and are set to logic 0. 2004 Jun 29 182 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 235 Horizontal luminance phase offset; register set A [AAH[7:0]] and B [DAH[7:0]] HORIZONTAL LUMINANCE PHASE OFFSET CONTROL BITS 7 TO 0 XPHY7 XPHY6 XPHY5 XPHY4 XPHY3 XPHY2 XPHY1 XPHY0 Offset = 0 0 0 0 0 0 0 0 0 Offset = 1⁄32 pixel 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 Offset = Offset = 32⁄ 32 = 1 pixel 255⁄ pixel 32 Table 236 Horizontal chrominance scaling increment; register set A [ACH[7:0]; ADH[7:0]] and B [DCH[7:0]; DDH[7:0]] CONTROL BITS HORIZONTAL CHROMINANCE SCALING INCREMENT A [ADH[7:4]] B [DDH[7:4]] A [ADH[3:0]] B [DDH[3:0]] A [ACH[7:4]] B [DCH[7:4]] A [ACH[3:0]] B [DCH[3:0]] XSCC[15:12](1) XSCC[11:8] XSCC[7:4] XSCC[3:0] 0000 0000 0000 0000 0000 0000 0000 0001 0001 1111 1111 1111 This value must be set to the luminance value 1⁄2XSCY[15:0] Note 1. Bits XSCC[15:13] are reserved and are set to logic 0. Table 237 Horizontal chrominance phase offset; register set A [AEH[7:0]] and B [DEH[7:0]] HORIZONTAL CHROMINANCE PHASE OFFSET This value must be set to 1⁄ XPHY[7:0] 2 CONTROL BITS 7 TO 0 XPHC7 XPHC6 XPHC5 XPHC4 XPHC3 XPHC2 XPHC1 XPHC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 18.2.5.12 Subaddresses B0H to BFH Table 238 Vertical luminance scaling increment; register set A [B0H[7:0]; B1H[7:0]] and B [E0H[7:0]; E1H[7:0]] CONTROL BITS VERTICAL LUMINANCE SCALING INCREMENT Scale = Scale = 1024⁄ (theoretical) 1 1024⁄ 1023 zoom zoom Scale = 1, equals 1024 Scale = Scale = 1024⁄ 1025 downscale 1⁄ 63.999 downscale 2004 Jun 29 A [B1H[7:4]] B [E1H[7:4]] A [B1H[3:0]] B [E1H[3:0]] A [B0H[7:4]] B [E0H[7:4]] A [B0H[3:0]] B [E0H[3:0]] YSCY[15:12] YSCY[11:8] YSCY[7:4] YSCY[3:0] 0000 0000 0000 0001 0000 0011 1111 1111 0000 0100 0000 0000 0000 0100 0000 0001 1111 1111 1111 1111 183 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 239 Vertical chrominance scaling increment; register set A [B2H[7:0]; B3H[7:0]] and B [E2H[7:0]; E3H[7:0]] CONTROL BITS VERTICAL CHROMINANCE SCALING INCREMENT A [B3H[7:4]] B [E3H[7:4]] A [B3H[3:0]] B [E3H[3:0]] A [B2H[7:4]] B [E2H[7:4]] A [B2H[3:0]] B [E2H[3:0]] YSCC[15:12] YSCC[11:8] YSCC[7:4] YSCC[3:0] 0000 0000 0000 0001 1111 1111 1111 1111 This value must be set to the luminance value YSCY[15:0] Table 240 Vertical scaling mode control; register set A [B4H[4 and 0]] and B [E4H[4 and 0]]; note 1 CONTROL BITS 4 AND 0 VERTICAL SCALING MODE CONTROL YMIR YMODE Vertical scaling performs linear interpolation between lines X 0 Vertical scaling performs higher order accumulating interpolation, better alias suppression X 1 No mirroring 0 X Lines are mirrored 1 X Note 1. X = don’t care. Table 241 Vertical chrominance phase offset ‘00’; register set A [B8H[7:0]] and B [E8H[7:0]] VERTICAL CHROMINANCE PHASE OFFSET Offset = 0 Offset = Offset = 32⁄ 32 = 1 line 255⁄ lines 32 CONTROL BITS 7 TO 0 YPC07 YPC06 YPC05 YPC04 YPC03 YPC02 YPC01 YPC00 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 Table 242 Vertical luminance phase offset ‘00’; register set A [BCH[7:0]] and B [ECH[7:0]] VERTICAL LUMINANCE PHASE OFFSET Offset = 0 Offset = Offset = 32⁄ 32 = 1 line 255⁄ lines 32 2004 Jun 29 CONTROL BITS 7 TO 0 YPY07 YPY06 YPY05 YPY04 YPY03 YPY02 YPY01 YPY00 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 184 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE 19 PROGRAMMING START SET-UP OF DIGITAL VIDEO DECODER PART 19.1 Decoder part The given values force the following behaviour of the SAA7108AE; SAA7109AE decoder part: • The analog input AI11 expects an NTSC M, PAL B, D, G, H and I or SECAM signal in CVBS format; analog anti-alias filter and AGC active • Automatic field detection enabled • Standard ITU 656 output format enabled on the expansion port • Contrast, brightness and saturation control in accordance with ITU standards • Adaptive comb filter for luminance and chrominance activated • Pins LLC, LLC2, XTOUTd, RTS0, RTS1 and RTCO are set to 3-state. Table 243 Decoder part start set-up values for the three main standards SUB ADDRESS (HEX) VALUES (HEX) REGISTER FUNCTION BIT NAME(1) NTSC M PAL B, D, G, H AND I SECAM 00 chip version ID7 to ID4 01 increment delay X, X, X, X, IDEL3 to IDEL0 08 08 08 02 analog input control 1 FUSE1, FUSE0, GUDL1, GUDL0 and MODE3 to MODE0 C0 C0 C0 03 analog input control 2 X, HLNRS, VBSL, WPOFF, HOLDG, GAFIX, GAI28 and GAI18 10 10 10 04 analog input control 3 GAI17 to GAI10 90 90 90 05 analog input control 4 GAI27 to GAI20 90 90 90 06 horizontal sync start HSB7 to HSB0 EB EB EB 07 horizontal sync stop HSS7 to HSS0 E0 E0 E0 08 sync control AUFD, FSEL, FOET, HTC1, HTC0, HPLL, VNOI1 and VNOI0 98 98 98 09 luminance control BYPS, YCOMB, LDEL, LUBW and LUFI3 to LUFI0 40 40 1B 0A luminance brightness control DBRI7 to DBRI0 80 80 80 0B luminance contrast control DCON7 to DCON0 44 44 44 0C chrominance saturation control DSAT7 to DSAT0 40 40 40 0D chrominance hue control HUEC7 to HUEC0 00 00 00 0E chrominance control 1 CDTO, CSTD2 to CSTD0, DCVF, FCTC, X and CCOMB 89 81 D0 0F chrominance gain control ACGC and CGAIN6 to CGAIN0 2A 2A 80 10 chrominance control 2 OFFU1, OFFU0, OFFV1, OFFV0, CHBW and LCBW2 to LCBW0 0E 06 00 11 mode/delay control COLO, RTP1, HDEL1, HDEL0, RTP0 and YDEL2 to YDEL0 00 00 00 2004 Jun 29 read only 185 Philips Semiconductors Product specification HD-CODEC SUB ADDRESS (HEX) SAA7108AE; SAA7109AE VALUES (HEX) REGISTER FUNCTION BIT NAME(1) NTSC M PAL B, D, G, H AND I SECAM 12 RT signal control RTSE13 to RTSE10 and RTSE03 to RTSE00 00 00 00 13 RT/X port output control RTCE, XRHS, XRVS1, XRVS0, HLSEL and OFTS2 to OFTS0 00 00 00 14 analog/ADC/compatibility control CM99, UPTCV, AOSL1, AOSL0, XTOUTE, OLDSB, APCK1 and APCK0 00 00 00 15 VGATE start, FID change VSTA7 to VSTA0 11 11 11 16 VGATE stop VSTO7 to VSTO0 FE FE FE 17 miscellaneous, VGATE configuration and MSBs LLCE, LLC2E, X, X, X, VGPS, VSTO8 and VSTA8 40 40 40 18 raw data gain control RAWG7 to RAWG0 40 40 40 19 raw data offset control RAWO7 to RAWO0 80 80 80 reserved X, X, X, X, X, X, X, X 00 00 00 1A to 1E 1F status byte video decoder INTL, HLVLN, FIDT, GLIMT, GLIMB, (OLDSB = 0) WIPA, COPRO and RDCAP Note 1. All X values must be set to logic 0. 2004 Jun 29 186 read only Philips Semiconductors Product specification HD-CODEC 19.2 SAA7108AE; SAA7109AE Audio clock generation part The given values force the following behaviour of the SAA7108AE; SAA7109AE audio clock generation part: • Used crystal is 24.576 MHz • Expected field frequency is 59.94 Hz (e.g. NTSC M standard) • Generated audio master clock frequency at pin AMCLK is 256 × 44.1 kHz = 11.2896 MHz • AMCLK is externally connected to AMXCLK (short-cut between pins K12 and J12) • ASCLK = 32 × 44.1 kHz = 1.4112 MHz • ALRCLK is 44.1 kHz. Table 244 Audio clock part set-up values SUB ADDRESS (HEX) START VALUES REGISTER FUNCTION BIT NAME(1) 7 6 5 4 3 2 1 0 HEX 30 audio master clock cycles per field; bits 7 to 0 ACPF7 to ACPF0 1 0 1 1 1 1 0 0 BC 31 audio master clock cycles per field; bits 15 to 8 ACPF15 to ACPF8 1 1 0 1 1 1 1 1 DF 32 audio master clock cycles per field; bits 17 and 16 X, X, X, X, X, X, ACPF17 and ACPF16 0 0 0 0 0 0 1 0 02 33 reserved X, X, X, X, X, X, X, X 0 0 0 0 0 0 0 0 00 34 audio master clock nominal increment; bits 7 to 0 ACNI7 to ACNI0 1 1 0 0 1 1 0 1 CD 35 audio master clock nominal increment; bits 15 to 8 ACNI15 to ACNI8 1 1 0 0 1 1 0 0 CC 36 audio master clock nominal increment; bits 21 to 16 X, X, ACNI21 to ACNI16 0 0 1 1 1 0 1 0 3A 37 reserved X, X, X, X, X, X, X, X 0 0 0 0 0 0 0 0 00 38 clock ratio AMXCLK to ASCLK X, X, SDIV5 to SDIV0 0 0 0 0 0 0 1 1 03 39 clock ratio ASCLK to ALRCLK X, X, LRDIV5 to LRDIV0 0 0 0 1 0 0 0 0 10 3A audio clock generator basic set-up X, X, X, X, APLL, AMVR, LRPH, SCPH 0 0 0 0 0 0 0 0 00 reserved X, X, X, X, X, X, X, X 0 0 0 0 0 0 0 0 00 3B to 3F Note 1. All X values must be set to logic 0. 2004 Jun 29 187 Philips Semiconductors Product specification HD-CODEC 19.3 SAA7108AE; SAA7109AE Data slicer and data type control part The given values force the following behaviour of the SAA7108AE; SAA7109AE VBI data slicer part: • Closed captioning data is expected at line 21 of field 1 (60 Hz/525 line system) • All other lines are processed as active video • Sliced data are framed by ITU 656 like SAV/EAV sequence (DID[5:0] = 3EH ⇒ MSB of SAV/EAV = 1). Table 245 Data slicer start set-up values SUB ADDRESS (HEX) 40 41 to 53 START VALUES REGISTER FUNCTION slicer control 1 BIT NAME(1) 7 6 5 4 3 2 1 0 HEX X, HAM_N, FCE, HUNT_N, X, X, X, X 0 1 0 0 0 0 0 0 40 line control register 2 to 20 LCRn_7 to LCRn_0 (n = 2 to 20) 1 1 1 1 1 1 1 1 FF line control register 21 LCR21_7 to LCR21_0 0 1 0 1 1 1 1 1 5F 55 to 57 line control register 22 to 24 LCRn_7 to LCRn_0 (n = 22 to 24) 1 1 1 1 1 1 1 1 FF 58 programmable framing code FC7 to FC0 0 0 0 0 0 0 0 0 00 59 horizontal offset for slicer HOFF7 to HOFF0 0 1 0 0 0 1 1 1 47 5A vertical offset for slicer VOFF7 to VOFF0 0 0 0 0 0 1 1 0 06(2) 5B field offset and MSBs for horizontal and vertical offset FOFF, RECODE, X, VOFF8, X, HOFF10 to HOFF8 1 0 0 0 0 0 1 1 83(2) 5C reserved X, X, X, X, X, X, X, X 0 0 0 0 0 0 0 0 00 5D header and data identification code control FVREF, X, DID5 to DID0 0 0 1 1 1 1 1 0 3E 5E sliced data identification code X, X, SDID5 to SDID0 0 0 0 0 0 0 0 0 00 5F reserved X, X, X, X, X, X, X, X 0 0 0 0 0 0 0 0 00 60 slicer status byte 0 −, FC8V, FC7V, VPSV, PPV, CCV, −, − read-only register 61 slicer status byte 1 −, −, F21_N, LN8 to LN4 read-only register 62 slicer status byte 2 LN3 to LN0, DT3 to DT0 read-only register 54 Notes 1. All X values must be set to logic 0. 2. Changes for 50 Hz/625 line systems: subaddress 5AH = 03H and subaddress 5BH = 03H. 2004 Jun 29 188 Philips Semiconductors Product specification HD-CODEC 19.4 SAA7108AE; SAA7109AE Scaler and interfaces Table 246 shows some examples for the scaler programming where: • prsc = prescale ratio • fisc = fine scale ratio • vsc = vertical scale ratio. number of input pixel The ratio is defined as: ----------------------------------------------------------number of output pixel In the following settings the VBI data slicer is inactive. To activate the VBI data slicer, VITX[1:0] 86H[7:6] has to be set to ‘11’. Depending on the VBI data slicer settings, the sliced VBI data is inserted after the end of the scaled video lines, if the regions of the VBI data slicer and scaler overlap. To compensate for the running-in of the vertical scaler, the vertical input window lengths are extended by 2 to 290 lines, respectively 242 lines for XS, but the scaler increment calculations are done with 288, respectively 240 lines. 19.4.3 19.4.1 TRIGGER CONDITION For trigger condition STRC[1:0] 90H[1:0] not equal ‘00’. If the value of (YO + YS) is ≥262 (NTSC), and 312 (PAL) the output field rate is reduced to 30 Hz and 25 Hz respectively. Horizontal and vertical offsets (XO and YO) have to be used to adjust the displayed video in the display window. As this adjustment is application dependent, the listed values are only dummy values. 19.4.2 MAXIMUM ZOOM FACTOR The maximum zoom factor is dependent on the back-end data rate and is therefore back-end clock and data format dependent (8 or 16-bit output). The maximum horizontal zoom is limited to approximately 3.5, due to internal data path restrictions. EXAMPLES Table 246 Example of configurations EXAMPLE NUMBER SCALER SOURCE AND REFERENCE EVENTS INPUT OUTPUT WINDOW WINDOW SCALE RATIOS 720 × 240 720 × 240 prsc = 1; fisc = 1; vsc = 1 1 analog input to 8-bit I port output, with SAV/EAV codes, 8-bit serial byte stream decoder output at X port; acquisition trigger at falling edge vertical and rising edge horizontal reference signal; H and V gates on IGPH and IGPV, IGP0 = VBI sliced data flag, IGP1 = FIFO almost full, level ≥24, IDQ qualifier logic 1 active 2 analog input to 16-bit output, without SAV/EAV codes, Y on 704 × 288 768 × 288 prsc = 1; I port, CB-CR on H port and decoder output at X port; fisc = 0.91667; acquisition trigger at falling edge vertical and rising edge vsc = 1 horizontal reference signal; H and V pulses on IGPH and IGPV, output FID on IGP0, IGP1 fixed to logic 1, IDQ qualifier logic 0 active 3 X port input 8 bit with SAV/EAV codes, no reference signals on XRH and XRV, XCLK as gated clock; field detection and acquisition trigger on different events; acquisition triggers at rising edge vertical and rising edge horizontal; I port output 8-bit with SAV/EAV codes like example number 1; see Table 247 4 X port and H port for 16-bit Y-CB-CR 4 : 2 : 2 input (if no 16-bit 720 × 288 200 × 80 output selected); XRH and XRV as references; field detection and acquisition trigger at falling edge of vertical and rising edge of horizontal; I port output 8-bit with SAV/EAV codes, but Y only output 2004 Jun 29 189 720 × 240 352 × 288 prsc = 2; fisc = 1.022; vsc = 0.8333 prsc = 2; fisc = 1.8; vsc = 3.6 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE Table 247 Scaler and interface configuration examples I2C-BUS ADDRESS (HEX) EXAMPLE 1 EXAMPLE 2 EXAMPLE 3 EXAMPLE 4 MAIN FUNCTION HEX DEC HEX DEC HEX DEC HEX DEC Global settings 80 task enable, IDQ and back-end clock definition 10 − 10 − 10 − 10 − 83 XCLK output phase and X port output enable 01 − 01 − 00 − 00 − 84 IGPH, IGPV, IGP0 and IGP1 output definition A0 − C5 − A0 − A0 − 85 signal polarity control and I port byte swapping 10 − 09 − 10 − 10 − 86 FIFO flag thresholds and video/text arbitration 45 − 40 − 45 − 45 − 87 ICLK and IDQ output phase and I port enable 01 − 01 − 01 − 01 − 88 power save control and software reset F0 − F0 − F0 − F0 − 00 − 00 − 00 − 00 − Task A: scaler input configuration and output format settings 90 task handling 91 scaler input source and format definition 08 − 08 − 18 − 38 − 92 reference signal definition at scaler input 10 − 10 − 10 − 10 − 93 I port output formats and configuration 80 − 40 − 80 − 84 − horizontal input offset (XO) 10 16 10 16 10 16 10 16 00 − 00 − 00 − 00 − horizontal input (source) window length (XS) D0 720 C0 704 D0 720 D0 720 02 − 02 − 02 − 02 − vertical input offset (YO) 0A 10 0A 10 0A 10 0A 10 00 − 00 − 00 − 00 − vertical input (source) window length (YS) F2 242 22 290 F2 242 22 290 00 − 01 − 00 − 01 − horizontal output (destination) window length (XD) D0 720 00 768 60 352 C8 200 02 − 03 − 01 − 00 − vertical output (destination) window length (YD) F0 240 20 288 20 288 50 80 00 − 01 − 01 − 00 − Input and output window definition 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F Prefiltering and prescaling A0 integer prescale (value ‘00’ not allowed) 01 − 01 − 02 − 02 − A1 accumulation length for prescaler 00 − 00 − 02 − 03 − A2 FIR prefilter and prescaler DC normalization 00 − 00 − AA − F2 − A4 scaler brightness control 80 128 80 128 80 128 80 128 A5 scaler contrast control 40 64 40 64 40 64 11 17 A6 scaler saturation control 40 64 40 64 40 64 11 17 2004 Jun 29 190 Philips Semiconductors Product specification HD-CODEC I2C-BUS ADDRESS (HEX) SAA7108AE; SAA7109AE EXAMPLE 1 EXAMPLE 2 EXAMPLE 3 EXAMPLE 4 MAIN FUNCTION HEX DEC HEX DEC HEX DEC HEX DEC 00 1024 AA 938 18 1048 34 1844 04 − 03 − 04 − 07 − 00 − 00 − 00 − 00 − Horizontal phase scaling A8 horizontal scaling increment for luminance A9 AA horizontal phase offset luminance AC horizontal scaling increment for chrominance AD AE horizontal phase offset chrominance 00 512 D5 469 0C 524 9A 922 02 − 01 − 02 − 03 − 00 − 00 − 00 − 00 − 00 1024 00 1024 55 853 66 3686 04 − 04 − 03 − 0E − 00 1024 00 1024 55 853 66 3686 04 − 04 − 03 − 0E − 00 − 00 − 00 − 01 − Vertical scaling B0 vertical scaling increment for luminance B1 B2 vertical scaling increment for chrominance B3 B4 B8 to BF 2004 Jun 29 vertical scaling mode control vertical phase offsets luminance and chrominance (needs to be used for interlace correct scaled output) start with B8 to BF at 00H, if there are no problems with the interlaced scaled output optimize according to Section 9.3.3.2 191 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE 20 PACKAGE OUTLINE BGA156: plastic ball grid array package; 156 balls; body 15 x 15 x 1.15 mm SOT472-1 B D A D1 ball A1 index area A2 A E1 E A1 detail X C e1 y1 C ∅v M C A B b 1/2 e e y ∅w M C P N M L K J H G F E D C B A e e2 1/2 e shape optional (4x) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 X 10 mm 5 scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 b D D1 E E1 e e1 e2 v w y y1 mm 1.75 0.5 0.3 1.25 1.05 0.6 0.4 15.2 14.8 13.7 13.0 15.2 14.8 13.7 13.0 1 13 13 0.3 0.1 0.15 0.35 REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT472-1 144E MS-034 --- 2004 Jun 29 192 EUROPEAN PROJECTION ISSUE DATE 00-03-04 03-01-22 Philips Semiconductors Product specification HD-CODEC 21 SOLDERING 21.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 21.2 SAA7108AE; SAA7109AE To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. • below 225 °C (SnPb process) or below 245 °C (Pb-free process) A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. – for all BGA, HTSSON-T and SSOP-T packages – for packages with a thickness ≥ 2.5 mm – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. • below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 21.3 21.4 Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. 2004 Jun 29 Manual soldering 193 Philips Semiconductors Product specification HD-CODEC 21.5 SAA7108AE; SAA7109AE Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE REFLOW(2) BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA, USON, VFBGA not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable(4) suitable PLCC(5), SO, SOJ suitable suitable not recommended(5)(6) suitable SSOP, TSSOP, VSO, VSSOP not recommended(7) suitable CWQCCN..L(8), PMFP(9), WQCCN..L(8) not suitable LQFP, QFP, TQFP not suitable Notes 1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. 9. Hot bar or manual soldering is suitable for PMFP packages. 2004 Jun 29 194 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE 22 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 23 DEFINITIONS 24 DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2004 Jun 29 Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 195 Philips Semiconductors Product specification HD-CODEC SAA7108AE; SAA7109AE 25 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2004 Jun 29 196 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA76 © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R21/02/pp197 Date of release: 2004 Jun 29 Document order number: 9397 750 13425