PHILIPS PC2119VU/2

INTEGRATED CIRCUITS
DATA SHEET
PCF2119x
LCD controllers/drivers
Product specification
Supersedes data of 1997 Nov 21
File under Integrated Circuits, IC12
1999 Mar 02
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
CONTENTS
9
EXTENDED FUNCTION SET
INSTRUCTIONS AND FEATURES
New instructions
Icon control
IM
IB
Normal/icon mode operation
Screen configuration
Display configuration
TC1 and TC2
Set VLCD
Reducing current consumption
1
FEATURES
1.1
Note
2
APPLICATIONS
3
GENERAL DESCRIPTION
4
ORDERING INFORMATION
5
BLOCK DIAGRAM
6
PAD INFORMATION
6.1
Pad functions
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
7
FUNCTIONAL DESCRIPTION
10
INTERFACES TO MPU
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
LCD supply voltage generator
Programming ranges
LCD bias voltage generator
Oscillator
External clock
Power-on reset
Power-down mode
Registers
Busy flag
Address Counter (AC)
Display Data RAM (DDRAM)
Character Generator ROM (CGROM)
Character Generator RAM (CGRAM)
Cursor control circuit
Timing generator
LCD row and column drivers
Reset function
10.1
10.2
Parallel interface
I2C-bus interface
11
LIMITING VALUES
12
HANDLING
13
DC CHARACTERISTICS
14
AC CHARACTERISTICS
15
TIMING CHARACTERISTICS
16
APPLICATION INFORMATION
16.1
16.3
16.4
8-bit operation, 1-line display using external
reset
4-bit operation, 1-line display using external
reset
8-bit operation, 2-line display
I2C-bus operation, 1-line display
8
INSTRUCTIONS
17
BONDING PAD LOCATIONS
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
Clear display
Return home
Entry mode set
Display control (and partial power-down mode)
Cursor or display shift
Function set
Set CGRAM address
Set DDRAM address
Read busy flag and read address
Write data to CGRAM or DDRAM
Read data from CGRAM or DDRAM
18
DEFINITIONS
19
LIFE SUPPORT APPLICATIONS
20
PURCHASE OF PHILIPS I2C COMPONENTS
1999 Mar 02
16.2
2
Philips Semiconductors
Product specification
LCD controllers/drivers
1
PCF2119x
FEATURES
• Single-chip LCD controller/driver
• 2-line display of up to 16 characters + 160 icons, or
1-line display of up to 32 characters + 160 icons
• 5 × 7 character format plus cursor; 5 × 8 for kana
(Japanese) and user defined symbols
• Very low current consumption (20 to 200 µA):
• Icon mode: reduced current consumption while
displaying icons only
– Icon mode: <25 µA
– Power-down mode: <2 µA.
• Icon blink function
• On-chip:
1.1
– Generation of LCD supply voltage, independent of
VDD, programmable by instruction (external supply
also possible)
Icon mode is used to save current. When only icons are
displayed, a much lower operating voltage VLCD can be
used and the switching frequency of the LCD outputs is
reduced. In most applications it is possible to use VDD as
VLCD.
– Temperature compensation of on-chip generated
VLCD: −8 to −12 mV/K at 5.0 V (programmable by
instruction)
– Generation of intermediate LCD bias voltages
2
– Oscillator requires no external components
(external clock also possible).
• Telecom equipment
APPLICATIONS
• Portable instruments
• Display Data RAM: 80 characters
• Point-of-sale terminals.
• Character Generator ROM: 240, 5 × 8 characters
• Character Generator RAM: 16, 5 × 8 characters;
4 characters used to drive 160 icons, 8 characters used
if icon blink feature is used in application
3
GENERAL DESCRIPTION
The PCF2119x is a low power CMOS LCD controller and
driver, designed to drive a dot matrix LCD display of 2-line
by 16 or 1-line by 32 characters with 5 × 8 dot format.
All necessary functions for the display are provided in a
single chip, including on-chip generation of LCD bias
voltages, resulting in a minimum of external components
and lower system current consumption. The PCF2119x
interfaces to most microcontrollers via a 4 or 8-bit bus or
via the 2-wire I2C-bus. The chip contains a character
generator and displays alphanumeric and kana
(Japanese) characters. The letter ‘x’ in PCF2119x
characterizes the built-in character set. Various character
sets can be manufactured on request.
• 4 or 8-bit parallel bus and 2-wire I2C-bus interface
• CMOS compatible
• 18 row and 80 column outputs
• Multiplex rates 1 : 18 (for normal operation), 1 : 9 (for
single line operation) and 1 : 2 (for icon only mode)
• Uses common 11 code instruction set (extended)
• Logic supply voltage range, VDD − VSS = 2.2 to 4.0 V
(up to 5.5 V if external VLCD is used); chip may be driven
with two battery cells
• Display supply voltage range, VLCD − VSS = 2.2 to 6.5 V
4
Note
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME
DESCRIPTION
VERSION
PC2119RU/2
−
chip with bumps in tray
−
PC2119SU/2
−
chip with bumps in tray
−
PC2119VU/2
−
chip with bumps in tray
−
1999 Mar 02
3
Philips Semiconductors
Product specification
LCD controllers/drivers
5
PCF2119x
BLOCK DIAGRAM
handbook, full pagewidth
C1 to C80
R17DUP
118 to 127, 106 to 92
87 to 73, 71 to 57,
52 to 38, 16 to 25
R1 to R18
27 to 34,
116 to 109,
26, 117
72
18
80
VLCD1
12, 13
COLUMN DRIVERS
BIAS
VOLTAGE
GENERATOR
ROW DRIVERS
80
18
DATA LATCHES
VLCD2
14, 15
SHIFT REGISTER 18-BIT
80
VLCD
GENERATOR
SHIFT REGISTER 5 × 12 BIT
5
OSCILLATOR
144
OSC
CURSOR AND DATA CONTROL
5
VDD1
VDD2
1, 2
CHARACTER
GENERATOR
RAM (128 × 5)
(CGRAM)
16 CHARACTERS
3, 4
VSS1
8, 9
VSS2
10, 11
T1
T2
T3
CHARACTER
GENERATOR
ROM
(CGROM)
240 CHARACTERS
TIMING
GENERATOR
8
6
DISPLAY DATA RAM
(DDRAM)
80 CHARACTERS/BYTES
7
7
131
PD
129
7
7
DISPLAY
ADDRESS
COUNTER
ADDRESS COUNTER
(AC)
7
7
INSTRUCTION
DECODER
8
DATA
REGISTER
(DR)
INSTRUCTION
REGISTER
BUSY
FLAG
8
PCF2119x
130
8
136
DB0/SA0
I/O BUFFER
137 to 139
140 to 143
5
134
135
128
132, 133
MGK891
DB1 to DB3
DB4 to DB7
E
R/W
RS
SCL
SDA
Fig.1 Block diagram.
1999 Mar 02
4
POR
Philips Semiconductors
Product specification
LCD controllers/drivers
6
PCF2119x
PAD INFORMATION
The identification of each pad and its location is given in Chapter 17.
6.1
Pad functions
Table 1
Pad function description
SYMBOL
DESCRIPTION
VDD1
Supply voltage for all except the high voltage generator.
VDD2
Supply voltage for the high voltage generator.
VSS1
This is the ground pad for all except the high voltage generator.
VSS2
This is the ground pad for the high voltage generator.
VLCD1
This input is used for the generation of the LCD bias levels.
VLCD2
This is the VLCD output pad if VLCD is generated internally. This pad must be connected to VLCD1.
E
The data bus clock input is set HIGH to signal the start of a read or write operation; data is clocked in
or out of the chip on the negative edge of the clock; note 1.
T1
These are three test pads. T1 and T2 must be connected to VSS1; T3 is left open-circuit and is not user
accessible.
T2
T3
R1 to R18;
R17DUP
LCD row driver outputs R1 to R18; these pads output the row select waveforms to the display;
R17 and R18 drive the icons. R17 has two pads R17 and R17DUP.
C1 to C80
LCD column driver outputs C1 to C80.
SCL
I2C-bus serial clock input; note 1.
POR
External power-on reset input.
PD
PD selects the chip power-down mode; for normal operation PD = 0.
SDA
I2C-bus serial data input/output; note 1.
R/W
This is the read/write input. R/W selects either the read (R/W = 1) or write (R/W = 0) operation. This
pad has an internal pull-up resistor.
RS
The RS input selects the register to be accessed for read and write. RS = 0, selects the instruction
register for write and the busy flag and address counter for read. RS = 1, selects the data register for
both read and write. This pad has an internal pull-up resistor.
DB0 to DB7
The 8-bit bidirectional data bus (3-state) transfers data between the system controller and the
PCF2119x. DB7 may be used as the busy flag, signalling that internal operations are not yet
completed. In 4-bit operations the 4 higher order lines DB7 to DB4 are used; DB3 to DB0 must be left
open-circuit. Data bus line DB3 has an alternative function (SA0), when selected this is the I2C-bus
address pad. Each data line has its own internal pull-up resistor; note 1.
OSC
Oscillator or external clock input. When the on-chip oscillator is used this pad must be connected to
VDD1.
Note
1. When the I2C-bus is used, the parallel interface pad E must be at logic 0. In the I2C-bus read mode DB7 to DB0
should be connected to VDD1 or left open-circuit.
a) When the parallel bus is used, pads SCL and SDA must be connected to VSS1 or VDD1; they must not be left
open-circuit.
b) If the 4-bit interface is used without reading out from the PCF2119x (i.e. R/W is set permanently to logic 0), the
unused ports DB0 to DB4 can either be set to VSS1 or VDD1 instead of leaving them open-circuit.
1999 Mar 02
5
Philips Semiconductors
Product specification
LCD controllers/drivers
7
PCF2119x
When VLCD is generated on-chip the VLCD pads should be
decoupled to VSS with a suitable capacitor. The generated
VLCD is independent of VDD and is temperature
compensated. When the generator is switched off an
external voltage may be supplied at connected pads
VLCD1,2. VLCD1,2 may be higher or lower than VDD.
FUNCTIONAL DESCRIPTION
7.1
LCD supply voltage generator
The LCD supply voltage may be generated on-chip.
The voltage generator is controlled by two internal 6-bit
registers: VA and VB. The nominal LCD operating voltage
at room temperature is given by the relationship:
The LCD supply voltage generator ensures that, as long as
VDD is in the valid range (2.2 to 4 V), the required peak
voltage VOP = 5.2 V can be generated at any time.
V OP(nom) = ( integer value of register × 0.08 2 ) + 1.82
7.2
Programming ranges
7.3
Programmed value: 1 to 63. Voltage: 1.902 to 6.986 V.
Tref = 27 °C.
LCD bias voltage generator
The intermediate bias voltages for the LCD display are
also generated on-chip. This removes the need for an
external resistive bias chain and significantly reduces the
system current consumption. The optimum value of VLCD
depends on the multiplex rate, the LCD threshold voltage
(Vth) and the number of bias levels. Using a 5-level bias
scheme for 1 : 18 maximum rate allows VLCD < 5 V for
most LCD liquids. The intermediate bias levels for the
different multiplex rates are shown in Table 2. These bias
levels are automatically set to the given values when
switching to the corresponding multiplex rate.
Values producing more than 6.5 V at operating
temperature are not allowed. Operation above this
voltage may damage the device. When programming the
operating voltage the VLCD temperature coefficient must
be taken into account.
Values below 2.2 V are below the specified operating
range of the chip and are therefore not allowed.
Value 0 for VA and VB switches the generator off
(i.e. VA = 0 in character mode, VB = 0 in icon mode).
Usually register VA is programmed with the voltage for
character mode and register VB with the voltage for icon
mode.
Table 2
Bias levels as a function of multiplex rate
MULTIPLEX
NUMBER
RATE
OF LEVELS
V1
V2
V3
V4
V5
V6
1 : 18
5
Vop
3/4(1)
1/2
1/2
1/4
Vss
1:9
5
Vop
3/4
1/2
1/2
1/4
Vss
1:2
4
Vop
2/3
2/3
1/3
1/3
Vss
Note
1. The values in the above table are given relative to Vop − Vss, e.g. 3/4 means 3/4 × (Vop − Vss).
7.4
Oscillator
The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC
pad must be connected to VDD.
1999 Mar 02
6
Philips Semiconductors
Product specification
LCD controllers/drivers
7.5
PCF2119x
When reading, data from the DDRAM or CGRAM
corresponding to the address in the instruction register is
written to the data register prior to being read by the ‘read
data’ instruction.
External clock
If an external clock is to be used this is input at the OSC
pad. The resulting display frame frequency is given by:
f OSC
f frame = ------------3 072
7.9
The busy flag indicates the internal status of the
PCF2119x. A logic 1 indicates that the chip is busy and
further instructions will not be accepted. The busy flag is
output to pad DB7 when RS = 0 and R/W = 1. Instructions
should only be written after checking that the busy flag is
at logic 0 or waiting for the required number of cycles.
Only in the power-down state is the clock allowed to be
stopped (OSC connected to VSS), otherwise the LCD is
frozen in a DC state.
7.6
Power-on reset
The PC2119x must be reset externally. This is an internal
synchronous reset that requires 3 OSC cycles to be
executed after release of the external reset signal. If no
external reset is performed, the chip might start-up in an
unwanted state. The external reset is active HIGH.
7.7
7.10
Power-down mode
7.11
During power-down, information in the RAMs and the chip
state are preserved. Instruction execution during
power-down is possible when pad OSC is externally
clocked.
Display Data RAM (DDRAM)
The DDRAM stores up to 80 characters of display data
represented by 8-bit character codes. RAM locations
which are not used for storing display data can be used as
general purpose RAM. The basic RAM to display
addressing scheme is shown in Fig.2. With no display shift
the characters represented by the codes in the first
32 RAM locations starting at address 00H in line 1 are
displayed. Figures 3 and 4 show the display mapping for
right and left shift respectively.
Registers
The PCF2119x has two 8-bit registers, an Instruction
Register (IR) and a Data Register (DR). The Register
Select signal (RS) determines which register will be
accessed. The instruction register stores instruction codes
such as ‘display clear’ and ‘cursor shift’, and address
information for the Display Data RAM (DDRAM) and
Character Generator RAM (CGRAM).
When data is written to or read from the DDRAM
wrap-around occurs from the end of one line to the start of
the next line. When the display is shifted each line wraps
around within itself, independently of the others. Thus all
lines are shifted and wrapped around together.
The address ranges and wrap-around operations for the
various modes are shown in Table 3.
The instruction register can be written to but not read from
by the system controller. The data register temporarily
stores data to be read from the DDRAM and CGRAM.
Table 3
Address Counter (AC)
The address counter assigns addresses to the DDRAM
and CGRAM for reading and writing and is set by the
commands ‘set CGRAM address’ and ‘set DDRAM
address’. After a read/write operation the address counter
is automatically incremented or decremented by 1.
The address counter contents are output to the bus
(DB6 to DB0) when RS = 0 and R/W = 1.
The chip can be put into power-down mode where all static
currents are switched off (no internal oscillator, no bias
level generation and all LCD outputs are internally
connected to VSS) when PD = 1.
7.8
Busy flag
Address space and wrap-around operation
1 × 32
2 × 16
1×9
Address space
00 to 4F
00 to 27; 40 to 67
00 to 27
Read/write wrap-around (moves to
next line)
4F to 00
27 to 40; 67 to 00
27 to 00
27 to 00; 67 to 40
27 to 00
MODE
Display shift wrap-around (stays within Do not use (make sure, that 4F and 00
line)
are not displayed at the same time.)
1999 Mar 02
7
Philips Semiconductors
Product specification
LCD controllers/drivers
handbook, full pagewidth
display
position
DDRAM
address
PCF2119x
non-displayed DDRAM addresses
1 2 3 4 5
30 31 32
00 01 02 03 04
1D 1E 1F 20 21
4C 4D 4E 4F
1-line display
non-displayed DDRAM address
DDRAM
address
1 2 3 4 5
14 15 16
00 01 02 03 04
0D 0E 0F 10 11
1 2 3 4 5
14 15 16
40 41 42 43 44
4D 4E 4F 50 51
24 25 26 27
line 1
64 65 66 67
line 2
MGK892
2-line display/MUX 1 : 9 mode
Fig.2 DDRAM to display mapping: no shift.
handbook, halfpage
DDRAM
address
5
14 15 16
27 00 01 02 03
1
2 3
0C 0D 0E
1
5
10 11 12
67 40 41 42 43
4C 4D 4E
2 3
4
4
2-line display/MUX 1 : 9 mode
Fig.3
line 1
line 2
MGL536
DDRAM to display mapping: right shift: (For 1 × 32 only as long as 4F and 00 positions are not on display
simultaneously).
handbook,display
halfpage
position
DDRAM
address
5
30 31 32
01 02 03 04 05
1
2 3
4
1E 1F 20
1-line display
1
DDRAM
address
5
14 15 16
01 02 03 04 05
2 3
0E 0F 10
1
5
14 15 16
41 42 43 44 45
4E 4F 50
2 3
4
4
2-line display/MUX 1 : 9 mode
Fig.4
line 1
line 2
MGK894
DDRAM to display mapping; left shift: (For 1 × 32 only as long as 4F and 00 positions are not on display
simultaneously).
1999 Mar 02
8
Philips Semiconductors
Product specification
LCD controllers/drivers
7.12
PCF2119x
7.15
Character Generator ROM (CGROM)
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the data buses.
The Character Generator ROM generates 240 character
patterns in a 5 × 8 dot format from 8-bit character codes.
Figure 6 shows the character set that is currently
implemented.
7.16
7.13
Character Generator RAM (CGRAM)
LCD row and column drivers
The PCF2119x contains 18 row and 80 column drivers,
which connect the appropriate LCD bias voltages in
sequence to the display in accordance with the data to be
displayed. R17 and R18 drive the icon rows.
Up to 16 user defined characters may be stored in the
Character Generator RAM. Some CGRAM characters
(see Fig.17) are also used to drive icons (6 if icons blink
and both icon rows are used in the application; 3 if no blink
but both icon rows are used in the application; 0 if no icons
are driven by the icon rows). The CGROM and CGRAM
use a common address space, of which the first column is
reserved for the CGRAM (see Fig.6). Figure 9 shows the
addressing principle for the CGRAM.
7.14
Timing generator
The bias voltages and the timing are selected
automatically when the number of lines in the display is
selected. Figures 10 to 13 show typical waveforms.
Unused outputs should be left unconnected.
Cursor control circuit
The cursor control circuit generates the cursor (underline
and/or cursor blink as shown in Fig.5) at the DDRAM
address contained in the address counter.
When the address counter contains the CGRAM address
the cursor will be inhibited.
cursor
MGA801
5 x 7 dot character font
alternating display
cursor display example
blink display example
Fig.5 Cursor and blink display examples.
1999 Mar 02
9
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
handbook, full pagewidth
upper
4 bits
0000
xxxx
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
lower
4 bits
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
MGL535
Fig.6 Character set ‘R’ in CGROM.
1999 Mar 02
10
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
handbook, full pagewidth
upper
4 bits
0000
xxxx
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
lower
4 bits
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
MGL534
Fig.7 Character set ‘S’ in CGROM.
1999 Mar 02
11
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
handbook, full pagewidth
upper
4 bits
0000
xxxx
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
lower
4 bits
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
MGL597
Fig.8 Character set ‘V’ in CGROM.
1999 Mar 02
12
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
character codes
handbook, full pagewidth
CGRAM
address
(DDRAM data)
7
6
5
4
3
2
higher
order
bits
0
0
0
0
0
0
1
0
6
lower
order
bits
0
0
0
0
0
0
0
0
5
4
3
2
higher
order
bits
0
1
0
0
0
0
0
0
character patterns
(CGRAM data)
1
0
4
lower
order
bits
0
1
3
higher
order
bits
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
2
1
character code
(CGRAM data)
0
4
3
2
1
0
0
1
1
1
1
1
1
1
0
1
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
1
0
0
1
0
1
0
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
1
1
1
0
0
1
1
0
1
0
0
0
1
0
1
0
1
0
0
0
lower
order
bits
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
cursor
position
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
character
pattern
example 1
character
pattern
example 2
MGE995
Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6.
CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logical OR with
the cursor. Data in the 8th position will appear in the cursor position.
Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in Fig.6.
As shown in Figs 6 and 7, CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds
to selection for display.
Only bits 0 to 5 of the CGRAM address are set by the ‘set CGRAM address’ command. Bit 6 can be set using the ‘set DDRAM address’ command in
the valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘read busy flag and address
counter’ command.
Fig.9 Relationship between CGRAM addresses, data and display patterns.
1999 Mar 02
13
Philips Semiconductors
Product specification
LCD controllers/drivers
frame n
handbook, full pagewidth
ROW 1
PCF2119x
frame n + 1
state 1 (ON)
state 2 (OFF)
VLCD
V2
V3/V4
V5
VSS
R1
R2
R3
R4
R5
ROW 9
R6
VLCD
V2
V3/V4
V5
VSS
ROW 2
VLCD
V2
V3/V4
V5
VSS
COL1
VLCD
V2
V3/V4
V5
VSS
COL2
VLCD
V2
V3/V4
V5
VSS
R7
R8
R9
VOP
0.5VOP
0.25VOP
state 1 0 V
−0.25VOP
−0.5VOP
−VOP
VOP
0.5VOP
0.25VOP
state 2 0 V
−0.25VOP
−0.5VOP
−VOP
MGE996
1 2 3
18 1 2 3
18
Fig.10 MUX 1 : 18 LCD waveforms; character mode.
1999 Mar 02
14
Philips Semiconductors
Product specification
LCD controllers/drivers
frame n + 1
frame n
handbook, full pagewidth
ROW 1
PCF2119x
state 1 (ON)
state 2 (OFF)
VLCD
V2
V3/V4
V5
VSS
R1
R2
R3
R4
R5
ROW 2
R6
VLCD
V2
V3/V4
V5
VSS
ROW 3
VLCD
V2
V3/V4
V5
VSS
COL1
VLCD
V2
V3/V4
V5
VSS
COL2
VLCD
V2
V3/V4
V5
VSS
R7
R8
R9
VOP
0.5VOP
0.25VOP
state 1 0 V
−0.25VOP
−0.5VOP
−VOP
VOP
0.5VOP
0.25VOP
state 2 0 V
−0.25VOP
−0.5VOP
−VOP
1
9
1
9
MGK900
Fig.11 MUX 1 : 9 LCD waveforms; character mode. R10 to 18 to be left open.
1999 Mar 02
15
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
frame n + 1
frame n
handbook, full pagewidth
only icons are
driven (MUX 1 : 2)
VLCD
ROW 17
2/3
1/3
VSS
VLCD
ROW 18
2/3
1/3
VSS
VLCD
ROW 1 to 16
2/3
1/3
VSS
VLCD
COL 1 ON/OFF
2/3
1/3
VSS
VLCD
COL 2 OFF/ON
2/3
1/3
VSS
VLCD
COL 3 ON/ON
2/3
1/3
VSS
VLCD
COL 4 OFF/OFF
2/3
1/3
VSS
MGE997
Fig.12 MUX 1 : 2 LCD waveforms; icon mode.
1999 Mar 02
16
Philips Semiconductors
Product specification
LCD controllers/drivers
handbook, full pagewidth V
PIXEL
PCF2119x
frame n + 1
frame n
state 1 (ON)
state 1
COL 1 ROW 17
state 2
COL 2 ROW 17
VOP
2/3 VOP
1/3 VOP
state 2 (OFF)
R17
R18
0
R1-16
−1/3 VOP
−2/3 VOP
−VOP
state 3 (OFF)
VOP
2/3 VOP
1/3 VOP
0
−1/3 VOP
−2/3 VOP
−VOP
VOP
2/3 VOP
1/3 VOP
state 3
COL 1 0
ROW 1 to 16 −1/3 VOP
−2/3 VOP
−VOP
MGE998
VON(rms) = 0.745VOP
VOFF(rms) = 0.333VOP
V ON
= 2.23
D = ------------V OFF
Fig.13 MUX 1 : 2 LCD waveforms; icon mode.
1999 Mar 02
17
Philips Semiconductors
Product specification
LCD controllers/drivers
7.17
PCF2119x
Reset function
The PCF2119x must be reset externally when power is turned on. The reset executes a ‘clear display’, requiring
165 oscillator cycles. After the reset the chip has the state shown in Table 4.
Table 4
State after reset
STEP
FUNCTION
1
clear display
2
entry mode set
3
4
display control
function set
CONTROL BIT STATE
CONDITION
I/D = 1
+1 (increment)
S=0
no shift
D=0
display off
C=0
cursor off
B=0
cursor character blink off
DL = 1
8-bit interface
M=0
1-line display
H=0
normal instruction set
SL = 0
MUX 1 : 18 mode
5
default address pointer to DDRAM; the Busy Flag (BF) indicates the busy state (BF = 1) until
initialization ends; the busy state lasts 2 ms; the chip may also be initialized by software; see
Tables 17 and 18
6
icon control
IM, IB = 00
icons/icon blink disabled
7
display/screen configuration
L = 0; P = 0; Q = 0
default configurations
8
VLCD temperature coefficient
TC1 = 0; TC2 = 0
default temperature coefficient
9
set VLCD
VA = 0; VB = 0 (VLCD generator off)
10
I2C-bus interface reset
1999 Mar 02
18
Philips Semiconductors
Product specification
LCD controllers/drivers
8
PCF2119x
In normal use, category 3 instructions are used most
frequently. However, automatic incrementing by 1
(or decrementing by 1) of internal RAM addresses after
each data write lessens the MPU program load.
The display shift in particular can be performed
concurrently with display data write, enabling the designer
to develop systems in minimum time with maximum
programming efficiency.
INSTRUCTIONS
Only two PCF2119x registers, the Instruction Register (IR)
and the Data Register (DR) can be directly controlled by
the MPU. Before internal operation, control information is
stored temporarily in these registers, to allow interfacing to
various types of MPUs which operate at different speeds
or to allow interface to peripheral control ICs.
The PCF2119x operation is controlled by the instructions
shown in Table 6 together with their execution time.
Details are explained in subsequent sections.
During internal operation, no instructions other than the
‘read busy flag’ and ‘read address’ instructions will be
executed. Because the busy flag is set to a logic 1 while an
instruction is being executed, check to ensure it is a logic 0
before sending the next instruction or wait for the
maximum instruction execution time, as given in Table 6.
An instruction sent while the busy flag is logic 1 will not be
executed.
Instructions are of 4 types, those that:
1. Designate PCF2119x functions such as display
format, data length, etc.
2. Set internal RAM addresses
3. Perform data transfer with internal RAM
4. Others.
Table 5
Instruction set for I2C-bus commands
CONTROL BYTE
Co RS 0
0
0
0
COMMAND BYTE
0
0
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 note 1
Note
1. R/W is set together with the slave address.
1999 Mar 02
I2C-BUS COMMANDS
19
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INSTRUCTION
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DESCRIPTION
REQUIRED
CLOCK
CYCLES
H = 0 or 1
NOP
0
0
0
0
0
0
0
0
0
0
no operation
3
Function set
0
0
0
0
1
DL
0
M
SL
H
sets interface Data Length (DL) and number of
display lines (M); single line/MUX 1 : 9 (SL),
extended instruction set control (H)
3
Read busy flag
and address
counter
0
1
BF
reads the Busy Flag (BF) indicating internal
operating is being performed and reads address
counter contents
0
Read data
1
1
read data
reads data from CGRAM or DDRAM
3
Write data
1
0
write data
writes data from CGRAM or DDRAM
3
Clear display
0
0
0
0
0
0
0
0
0
1
clears entire display and sets DDRAM address 0
in address counter
165
Return home
0
0
0
0
0
0
0
0
1
0
sets DDRAM address 0 in address counter; also
returns shifted display to original position; DDRAM
contents remain unchanged
3
Entry mode set
0
0
0
0
0
0
0
1
I/D
S
sets cursor move direction and specifies shift of
display; these operations are performed during
data write and read
3
Display control
0
0
0
0
0
0
1
D
C
B
sets entire display on/off (D), cursor on/off (C) and
blink of cursor position character (B); D = 0
(display off) puts chip into the power-down mode
3
Cursor/display
shift
0
0
0
0
0
1
S/C
R/L
0
0
moves cursor and shifts display without changing
DDRAM contents
3
Set CGRAM
address
0
0
0
1
sets CGRAM address; bit 6 is to be set by the
command ‘set DDRAM address’; look at the
description of the commands
3
Set DDRAM
address
0
0
1
sets DDRAM address
3
AC
Philips Semiconductors
Instruction set with parallel bus commands; note 1
LCD controllers/drivers
1999 Mar 02
Table 6
H=0
20
ACG
Product specification
PCF2119x
ADD
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R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DESCRIPTION
REQUIRED
CLOCK
CYCLES
H=1
Reserved
0
0
0
0
0
0
0
0
0
1
do not use
−
Screen
configuration
0
0
0
0
0
0
0
0
1
L
set screen configuration
3
Display
configuration
0
0
0
0
0
0
0
1
P
Q
set display configuration
3
IB
0
set icon mode (IM), icon blink (IB)
Icon control
0
0
0
0
0
0
1
IM
Temperature
control
0
0
0
0
0
1
0
0
Reserved
0
0
0
1
X
X
X
X
Set VLCD
0
0
1
V
voltage
TC1 TC2 set temperature coefficient (TCx)
X
X
3
3
do not use
−
store VLCD in register VA or VB (V)
3
Philips Semiconductors
RS
LCD controllers/drivers
1999 Mar 02
INSTRUCTION
Note
1. X = don’t care.
21
Product specification
PCF2119x
Philips Semiconductors
Product specification
LCD controllers/drivers
Table 7
PCF2119x
Explanations of symbols used in Table 6
STATE
BIT
LOGIC 0
LOGIC 1
I/D
decrement
S
display freeze
display shift
D
display off
display on
C
cursor off
cursor on
B
cursor character blink off: character at cursor
position does not blink
cursor character blink on: character at cursor
position blinks
S/C
cursor move
display shift
R/L
left shift
right shift
DL
4 bits
8 bits
H
use basic instruction set
use extended instruction set
L (no impact, if
M = 1 or SL = 1)
left/right screen: standard connection (as in
PCF2114)
left/right screen: mirrored connection (as in
PCF2116)
1st 16 characters of 32: columns are from
1 to 80
1st 16 characters of 32: columns are from
1 to 80
2nd 16 characters of 32: columns are from
1 to 80
2nd 16 characters of 32: columns are from
80 to 1
P
column data: left to right (as in PCF2116);
column data is displayed from 1 to 80
column data: right to left; column data is
displayed from 80 to 1
Q
row data: top to bottom (as in PCF2116); row
data is displayed from 1 to 16 and icon row data
is in 17 and 18
row data: bottom to top; row data is displayed
from 16 to 1 and icon row data is in 18 and 17
IM
character mode; full display
icon mode; only icons displayed
IB
icon blink disabled
icon blink enabled
V
set VA
set VB
M (no impact, if
SL = 1)
1-line by 32 display
2-line by 16 display
SL
MUX 1 : 18 (1 × 32 or 2 × 16 character display)
MUX 1 : 9 (1 × 16 character display)
C0
last control byte; see Table 5
another control byte follows after data/command
Table 8
increment
Explanation of TC1 and TC2 used in Table 6
TC1
TC2
0
0
VLCD temperature coefficient 0
1
0
VLCD temperature coefficient 1
0
1
VLCD temperature coefficient 2
1
1
VLCD temperature coefficient 3; for ranges for TC see Chapter 13
1999 Mar 02
DESCRIPTION
22
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
RS
R/W
E
DB7
IR7
IR3
BF
AC3
DR7
DR3
DB6
IR6
IR2
AC6
AC2
DR6
DR2
DB5
IR5
IR1
AC5
AC1
DR5
DR1
DB4
IR4
IR0
AC4
AC0
DR4
DR0
busy flag and
address counter read
instruction
write
data register
read
MGA804
Fig.14 4-bit transfer example.
RS
R/W
E
internal
DB7
internal operation
IR7
IR3
instruction
write
busy
AC3
busy flag
check
not
busy
AC3
busy flag
check
D7
instruction
write
IR7, IR3: instruction 7th, 3rd bit.
AC3: address counter 3rd bit.
D7, D3: data 7th, 3rd bit.
Fig.15 An example of 4-bit data transfer timing sequence.
1999 Mar 02
23
D3
MGA805
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
RS
R/W
E
internal
DB7
internal operation
data
instruction
write
busy
busy flag
check
not
busy
busy
busy flag
check
busy flag
check
data
instruction
write
MGA806
Fig.16 Example of busy flag checking timing sequence.
8.1
Clear display
8.3
‘Clear display’ writes character code 20H into all DDRAM
addresses (the character pattern for character code 20H
must be a blank pattern), sets the DDRAM address
counter to logic 0 and returns the display to its original
position, if it was shifted. Thus, the display disappears and
the cursor or blink position goes to the left edge of the
display. Sets entry mode I/D = 1 (increment mode). S of
entry mode does not change.
8.3.1
8.3.2
S
When S = 1, the entire display shifts either to the right
(I/D = 0) or to the left (I/D = 1) during a DDRAM write. Thus
it appears as if the cursor stands still and the display
moves. The display does not shift when reading from the
DDRAM, or when writing to or reading from the CGRAM.
When S = 0, the display does not shift.
Return home
‘Return home’ sets the DDRAM address counter to logic 0
and returns the display to its original position if it was
shifted. DDRAM contents do not change. The cursor or
blink position goes to the left of the first display line.
I/D and S of entry mode do not change.
1999 Mar 02
I/D
When I/D = 1 (0) the DDRAM or CGRAM address
increments (decrements) by 1 when data is written into or
read from the DDRAM or CGRAM. The cursor or blink
position moves to the right when incremented and to the
left when decremented. The cursor underline and cursor
character blink are inhibited when the CGRAM is
accessed.
The instruction ‘clear display’ requires extra execution
time. This may be allowed by checking the Busy Flag (BF)
or by waiting until the 165 clock cycles have elapsed.
The latter must be applied where no read-back options are
foreseen, as in some Chip-On-Glass (COG) applications.
8.2
Entry mode set
24
Philips Semiconductors
Product specification
LCD controllers/drivers
8.4
8.4.1
PCF2119x
Display control (and partial power-down mode)
8.5
‘Cursor/display shift’ moves the cursor position or the
display to the right or left without writing or reading display
data. This function is used to correct a character or move
the cursor through the display. In 2-line displays, the
cursor moves to the next line when it passes the last
position (40) of the line. When the displayed data is shifted
repeatedly all lines shift at the same time; displayed
characters do not shift into the next line.
D
The display is on when D = 1 and off when D = 0. Display
data in the DDRAM is not affected and can be displayed
immediately by setting D to a logic 1.
When the display is off (D = 0) the chip is in partial
power-down mode:
• The LCD outputs are connected to VSS
• The LCD generator and bias generator are turned off.
The Address Counter (AC) content does not change if the
only action performed is shift display, but increments or
decrements with the ‘cursor shift’.
Three oscillator cycles are required after sending the
‘display off’ instruction to ensure all outputs are at VSS,
afterwards OSC can be stopped. If the oscillator is running
during partial power-down mode (‘display off’) the chip can
still execute instructions. Even lower current consumption
is obtained by inhibiting the oscillator (OSC = VSS).
8.6
8.6.1
C
The cursor is displayed when C = 1 and inhibited when
C = 0. Even if the cursor disappears, the display functions
I/D, etc. remain in operation during display data write.
The cursor is displayed using 5 dots in the 8th line
(see Fig.5).
8.4.3
DL (PARALLEL MODE ONLY)
‘Function set’ from the I2C-bus interface sets the DL bit to
logic 1.
8.6.2
M
Selects either 1-line by 32 display (M = 0) or 2-line by
16 display (M = 1).
B
The character indicated by the cursor blinks when B = 1.
The cursor character blink is displayed by switching
between display characters and all dots on with a period of
f OSC
approximately 1 second, with f blink = ---------------52 224
8.6.3
SL
Selects MUX 1 : 9, 1-line by 16 display (independent of
M and L). Only rows 1 to 8 and 17 are to be used. All other
rows must be left open-circuit. The DDRAM map is the
same as in the 2-line by 16 display mode, however, the
second line is not displayable.
The cursor underline and the cursor character blink can be
set to display simultaneously.
1999 Mar 02
Function set
Sets interface data width. Data is sent or received in bytes
(DB7 to DB0) when DL = 1 or in two nibbles (DB7 to DB4)
when DL = 0. When 4-bit width is selected, data is
transmitted in two cycles using the parallel bus. In a 4-bit
application DB3 to DB0 should be left open-circuit (internal
pull-ups). Hence in the first ‘function set’ instruction after
power-on, N and H are set to logic 1. A second ‘function
set’ must then be sent (2 nibbles) to set N and H to their
required values.
To ensure IDD <1 µA, the parallel bus pads DB7 to DB0
should be connected to VDD; RS and R/W to VDD or left
open-circuit and PD to VDD. Recovery from power-down
mode: PD back to logic 0, if necessary OSC back to VDD
and send a ‘display control’ instruction with D = 1.
8.4.2
Cursor or display shift
25
Philips Semiconductors
Product specification
LCD controllers/drivers
8.6.4
PCF2119x
At the same time, the value of the address counter
expressed in binary A6 to A0 is read out. The address
counter is used by both CGRAM and DDRAM, and its
value is determined by the previous instruction.
H
When H = 0 the chip can be programmed via the standard
11 instruction codes used in the PCF2116 and other LCD
controllers.
When H = 1 the extended range of instructions will be
used. These are mainly for controlling the display
configuration and the icons.
8.10
8.7
Whether the CGRAM or DDRAM is to be written into is
determined by the previous ‘set CGRAM address’ or ‘set
DDRAM address’ command. After writing, the address
automatically increments or decrements by 1, in
accordance with the entry mode. Only bits D4 to D0 of
CGRAM data are valid, bits D7 to D5 are ‘don’t care’.
‘Write data’ writes binary 8-bit data D7 to D0 to the
CGRAM or the DDRAM.
Set CGRAM address
‘Set CGRAM address’ sets bits 5 to 0 of the CGRAM
address ACG into the address counter (binary A5 to A0).
Data can then be written to or read from the CGRAM.
Attention: the CGRAM address uses the same address
register as the DDRAM address and consists of 7 bits
(binary A6 to A0). With the ‘set CGRAM address’
command, only bits 5 to 0 are set. Bit 6 can be set using
the ‘set DDRAM address’ command first, or by using the
auto-increment feature during CGRAM write. All bits 6 to 0
can be read using the ‘read busy flag’ and ‘read address’
command.
8.11
The most recent ‘set address’ command determines
whether the CGRAM or DDRAM is to be read.
The ‘read data’ instruction gates the content of the Data
Register (DR) to the bus while E is HIGH. After E goes
LOW again, internal operation increments (or decrements)
the AC and stores RAM data corresponding to the new AC
into the DR.
Set DDRAM address
There are only three instructions that update the data
register:
‘Set DDRAM address’ sets the DDRAM address ADD into
the address counter (binary A6 to A0). Data can then be
written to or read from the DDRAM.
8.9
• ‘set CGRAM address’
• ‘set DDRAM address’
Read busy flag and read address
• ‘read data’ from CGRAM or DDRAM.
‘Read busy flag’ and ‘read address’ read the Busy Flag
(BF) and Address Counter (AC). BF = 1 indicates that an
internal operation is in progress. The next instruction will
not be executed until BF = 0. It is recommended that the
BF status is checked before the next write operation is
executed.
1999 Mar 02
Read data from CGRAM or DDRAM
‘Read data’ reads binary 8-bit data D7 to D0 from the
CGRAM or DDRAM.
When writing to the lower part of the CGRAM, ensure that
bit 6 of the address is not set (e.g. by an earlier DDRAM
write or read action).
8.8
Write data to CGRAM or DDRAM
Other instructions (e.g. ‘write data’, ‘cursor/display shift’,
‘clear display’ and ‘return home’) do not modify the data
register content.
26
Philips Semiconductors
Product specification
LCD controllers/drivers
9
PCF2119x
9.4
EXTENDED FUNCTION SET INSTRUCTIONS AND
FEATURES
9.1
Icon blink control is independent of the cursor/character
blink function.
New instructions
When IB = 0, icon blink is disabled. Icon data is stored in
CGRAM character 0 to 3 (4 × 8 × 5 = 160 bits for
160 icons).
H = 1, sets the chip into alternate instruction set mode.
9.2
Icon control
When IB = 1, icon blink is enabled. In this case each icon
is controlled by two bits. Blink consists of two half phases
(corresponding to the cursor on and off phases called even
and odd phases hereafter).
The PCF2119x can drive up to 160 icons. See Fig.17 for
CGRAM to icon mapping.
9.3
IB
IM
When IM = 0, the chip is in character mode. In the
character mode characters and icons are driven
(MUX 1 : 18). The VLCD generator, if used, produces the
VLCD voltage programmed in register VA.
Icon states for the even phase are stored in CGRAM
characters 0 to 3 (4 × 8 × 5 = 160 bits for 160 icons).
These bits also define icon state when icon blink is not
used.
When IM = 1, the chip is in icon mode. In the icon mode
only the icons are driven (MUX 1 : 2) and the VLCD voltage
generator, if used, produces the VLCD voltage as
programmed in register VB.
Icon states for the odd phase are stored in CGRAM
character 4 to 7 (another 160 bits for the 160 icons). When
icon blink is disabled CGRAM characters 4 to 6 may be
used as normal CGRAM characters.
Table 9
Blink effect for icons and cursor character blink
PARAMETER
Cursor underline
EVEN PHASE
ODD PHASE
on
off
Cursor character blink
block (all on)
normal (display character)
Icons
state 1: CGRAM character 0 to 2
state 2: CGRAM character 4 to 6
1999 Mar 02
27
Philips Semiconductors
Product specification
LCD controllers/drivers
handbook, full pagewidth
display:
PCF2119x
COL 1 to 5
COL 6 to 10
COL 76 to 80
ROW 17 –
1
2
3
4
5
6
7
8
9
10
ROW 18 –
81
82
83
84
85
86
87
88
89
90
76
77
78
79
80
156 157 158 159 160
MGL249
block of 5 columns
icon
no.
handbook, full
pagewidth
phase
ROW/COL
character codes
7
6
5
4
3
2
CGRAM address
1
MSB
0
6
LSB
MSB
5
4
3
2
1
CGRAM data
0
4
3
2
1
LSB MSB
icon view
0
LSB
1-5
even
17/1-5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
6-10
even
17/6-10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
11-15
even
17/11-15
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
0
76-80
even
17/76-80
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
81-85
even
18/1-5
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
0
156-160
even
18/76-80
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
0
1
1-5
odd (blink)
17/1-5
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
156-160
odd (blink)
18/76-80
0
0
0
0
0
1
1
1
0
1
1
1
1
1
1
0
0
1
1
0
MGK999
CGRAM data bit = logic 1 turns the icon on, data bit = logic 0 turns the icon off.
Data in character codes 0 to 2 define the icon state when icon blink is disabled or during the even phase when icon blink is enabled.
Data in character codes 4 to 6 define the icon state during the odd phase when icon blink is enabled (not used for icons when icon blink is disabled).
Fig.17 CGRAM to icon mapping.
1999 Mar 02
28
Philips Semiconductors
Product specification
LCD controllers/drivers
9.5
Normal/icon mode operation
IM
9.6
PCF2119x
CONDITION
9.10
Reducing current consumption can be achieved by one of
the options given in Table 10.
VLCD
0
character mode
generates VA
1
icon mode
generates VB
When VLCD lies outside the VDD range and must be
generated, it is usually more efficient to use the on-chip
generator than an external regulator.
Screen configuration
L: default is L = 0.
Table 10 Reducing current consumption
L = 0: the two halves of a split screen are connected in a
standard way i.e. column 1/81, 2/82 to 80/160.
ORIGINAL MODE
L = 1: the two halves of a split screen are connected in a
mirrored way i.e. column 1/160, 2/159 to 80/81. This
allows single layer PCB or glass layout.
9.7
icon mode (control bit IM)
Display on
display off (control bit D)
Any mode
power-down (PD pad)
VA
Normal operation VLCD character
mode
Q = 1: mirrors the row data.
TC1 and TC2
Default is TC1 and TC2 = 0. This selects the default
temperature coefficient for the internally generated VLCD.
TC1 and TC2 = 10, 01 and 11 selects alternative
temperature coefficients 1, 2 and 3 respectively.
Set VLCD
The VLCD value is programmed by instruction. Two on-chip
registers hold VLCD values for the character mode and the
icon mode respectively (VA and VB). The generated VLCD
value is independent of VDD, allowing battery operation of
the chip.
VLCD programming:
1. Send ‘function set’ instruction with H = 1
2. Send ‘set VLCD’ instruction to write to voltage register:
a) DB7, DB6 = 10: DB5 to DB0 are VLCD of character
mode (VA)
b) DB7, DB6 = 11: DB5 to DB0 are VLCD of icon mode
(VB)
c) DB5 to DB0 = 000000 switches VLCD generator off
(when selected)
d) During ‘display off’ and power-down the VLCD
generator is also disabled.
3. Send ‘function set’ instruction with H = 0 to resume
normal programming.
1999 Mar 02
Character mode
MODE
P = 1: mirrors the column data.
9.9
ALTERNATIVE MODE
Table 11 Use of the VA and VB registers
Display configuration
P, Q: default is P, Q = 0.
9.8
Reducing current consumption
29
VB
VLCD icon mode
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
The device that acknowledges must pull-down the SDA
line during the acknowledge clock pulse, so that the SDA
line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration).
10 INTERFACES TO MPU
10.1
Parallel interface
The PCF2119x can send data in either two 4-bit operations
or one 8-bit operation and can thus interface to 4-bit or
8-bit microcontrollers.
A master receiver must signal an end of data to the
transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event
the transmitter must leave the data line HIGH to enable the
master to generate a STOP condition.
In 8-bit mode data is transferred as 8-bit bytes using the
8 data lines DB7 to DB0. Three further control lines
E, RS and R/W are required; see Section 6.1.
In 4-bit mode data is transferred in two cycles of 4 bits
each using pads DB7 to DB4 for the transaction.
The higher order bits (corresponding to DB7 to DB4 in
8-bit mode) are sent in the first cycle and the lower order
bits (DB3 to DB0 in 8-bit mode) in the second. Data
transfer is complete after two 4-bit data transfers. It should
be noted that two cycles are also required for the busy flag
check. 4-bit operation is selected by instruction,
see Figs 14 to 16 for examples of bus protocol.
10.2.1
Before any data is transmitted on the I2C-bus, the device
which should respond is addressed first. The addressing is
always carried out with the first byte transmitted after the
START procedure. The I2C-bus configuration for the
different PCF2119x read and write cycles is shown in
Figs 22 to 24. The slow down feature of the I2C-bus
protocol (receiver holds SCL LOW during internal
operations) is not used in the PCF2119x.
In 4-bit mode, pads DB3 to DB0 must be left open-circuit.
They are pulled up to VDD internally.
10.2
I2C-BUS PROTOCOL
10.2.2
I2C-bus interface
DEFINITIONS
• Transmitter: the device which sends the data to the bus
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are the
Serial Data line (SDA) and the Serial Clock Line (SCL).
Both lines must be connected to a positive supply via
pull-up resistors. Data transfer may be initiated only when
the bus is not busy.
• Receiver: the device which receives the data from the
bus
• Master: the device which initiates a transfer, generates
clock signals and terminates a transfer
• Slave: the device addressed by a master
Each byte of eight bits is followed by an acknowledge bit.
The acknowledge bit is a HIGH level signal put on the bus
by the transmitter during which time the master generates
an extra acknowledge related clock pulse. A slave receiver
which is addressed must generate an acknowledge after
the reception of each byte.
• Multi-master: more than one master can attempt to
control the bus at the same time without corrupting the
message
Also a master receiver must generate an acknowledge
after the reception of each byte that has been clocked out
of the slave transmitter.
• Synchronization: procedure to synchronize the clock
signals of two or more devices.
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
• Arbitration: procedure to ensure that, if more than one
master simultaneously tries to control the bus, only one
is allowed to do so and the message is not corrupted
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
MGA807
Fig.18 System configuration.
1999 Mar 02
30
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
handbook, full pagewidth
SDA
SCL
data line
stable;
data valid
change
of data
allowed
MBC621
Fig.19 Bit transfer.
handbook, full pagewidth
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
MBC622
Fig.20 Definition of START and STOP conditions.
handbook, full pagewidth
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
MBC602
Fig.21 Acknowledgement on the I2C-bus.
1999 Mar 02
31
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Philips Semiconductors
LCD controllers/drivers
handbook, full pagewidth
1999 Mar 02
acknowledgement
from PCF2119x
S
S 0 1 1 1 0 1 A 0 A 1 RS CONTROL BYTE A
DATA BYTE
A 0 RS CONTROL BYTE A
DATA BYTE
A P
0
slave address
R/W
Co
2n ≥ 0 bytes
1 byte
Co
n ≥ 0 bytes
update
data pointer
32
MGK899
S
0 1 1 1 0 1 A 0
0
PCF2119x
slave address
R/W
Product specification
PCF2119x
Fig.22 Master transmits to slave receiver; write mode.
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DATA BYTE
A 0 RS CONTROL BYTE A
DATA BYTE(1)
0
slave address
2n
R/W
0 bytes
Co
acknowledgement
33
S
n ≥ 0 bytes
1 byte
Co
A
LCD controllers/drivers
S
S 0 1 1 1 0 1 A 0 A 1 RS CONTROL BYTE A
Philips Semiconductors
th
1999 Mar 02
acknowledgement
SLAVE
ADDRESS
S
A 1 A
0
acknowledgement
DATA BYTE
A
n bytes
R/W
Co
no acknowledgement
DATA BYTE
1 P
last byte
update
data pointer
update
data pointer
MGG003
Product specification
Fig.23 Master reads after setting word address; writes word address, set RS; ‘read data’.
PCF2119x
(1) Last data byte is a dummy byte (may be omitted).
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
acknowledgement
from PCF2113x
dbook, full pagewidth
S
SLAVE
ADDRESS
S
A 1 A
0
acknowledgement
from master
DATA BYTE
A
no acknowledgement
from master
DATA BYTE
n bytes
R/W
Co
1 P
last byte
update
data pointer
update
data pointer
MGG004
Fig.24 Master reads slave immediately after first byte; read mode (RS previously defined).
dbook, full pagewidth
SDA
t BUF
tf
t LOW
SCL
t HD;STA
t HD;DAT
tr
t HIGH
t SU;DAT
SDA
MGA728
t SU;STA
Fig.25 I2C-bus timing diagram.
1999 Mar 02
34
t SU;STO
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
11 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage
−0.5
+6.5
V
VLCD
LCD supply voltage
−0.5
+7.5
V
VI
input voltage pads OSC, RS, R/W, E and DB7 to DB0
−0.5
VDD + 0.5
V
VO
output voltage pads R1 to R18, C1 to C80 and VLCD
−0.5
VLCD + 0.5
V
II
DC input current
−10
+10
mA
IO
DC output current
−10
+10
mA
IDD, ISS and ILCD VDD, VSS or VLCD current
−50
+50
mA
Ptot
total power dissipation
−
400
mW
PO
power dissipation per output
−
100
mW
Tstg
storage temperature
−65
+150
°C
12 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”).
1999 Mar 02
35
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
13 DC CHARACTERISTICS
VDD = 2.2 to 4.0 V (external VLCD: VDD = 2.2 to 5.5 V); VSS = 0 V; VLCD = 2.2 to 6.5 V; Tamb = −30 to +85 °C;
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD1
supply voltage
VDD2
high voltage generator supply
voltage
VLCD
LCD supply voltage
ISS
ground supply current
internal VLCD generation
2.2
−
4.0
V
external VLCD generation
2.2
−
5.5
V
internal VLCD generation
2.2
−
4.0
2.2
−
6.5
V
external VLCD; note 1
internal VLCD; notes 1 and 3
ISS1
ground supply current 1
−
70
120
µA
ISS3
ground supply current 3
VDD = 3 V; VLCD = 5 V; note 2
−
45
80
µA
ISS4
ground supply current 4
icon mode; VDD = 3 V;
VLCD = 2.5 V; note 2
−
25
45
µA
ISS5
ground supply current 5
power-down mode; VDD = 3 V; −
VLCD = 2.5 V; DB7 to DB0,
RS and R/W = 1; OSC = 0;
PD = 1
2
5
µA
ISS6
ground supply current 6
−
190
400
µA
ISS8
ground supply current 8
VDD = 3 V; VLCD = 5 V; note 2
−
160
400
µA
ISS9
ground supply current 9
icon mode; VDD = 3 V;
VLCD = 2.5 V; note 2
−
120
−
µA
Logic
VIL1
LOW-level input voltage pads T1, E,
RS, R/W, DB7 to DB0 and SA0
0
−
0.3VDD
V
VIH1
HIGH-level input voltage pads T1,
E, RS, R/W, DB7 to DB0 and SA0
0.7VDD
−
VDD
V
VIL(PD)
LOW-level input voltage pad PD
0
−
0.2VDD
V
VIH(PD)
HIGH-level input voltage pad PD
0.8VDD
−
VDD
V
−
VDD − 1.5 V
VIL(osc)
LOW-level input voltage pad OSC
0
VIH(osc)
HIGH-level voltage pad OSC
VDD − 0.1 −
VDD
V
IOL(DB)
LOW-level output current
pads DB7 to DB0
VOL = 0.4 V; VDD = 5 V
1.6
4
−
mA
IOH(DB)
HIGH-level output current
pads DB7 to DB0
VOH = 4 V; VDD = 5 V
−1
−8
−
mA
Ipu
pull-up current pads DB7 to DB0
VI = VSS
0.04
0.15
1
µA
IL
leakage current pads OSC, E, RS,
R/W, DB7 to DB0 and SA0
VI = VDD or VSS
−1
−
+1
µA
1999 Mar 02
36
Philips Semiconductors
Product specification
LCD controllers/drivers
SYMBOL
PCF2119x
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I2C-bus
SDA AND SCL
VIL2
LOW-level input voltage
0
−
0.3VDD
V
VIH2
HIGH-level input voltage
0.7VDD
−
5.5
V
ILI
input leakage current
VI = VDD or VSS
−1
−
+1
µA
Ci
input capacitance
note 4
−
−
10
pF
IOL(SDA)
LOW-level output current SDA
VOL = 0.4 V; VDD = 5 V
3
−
−
mA
LCD outputs
RO(ROW)
row output resistance
pads R1 to R18
note 5
−
10
30
kΩ
RO(COL)
column output resistance
pads C1 to C80
note 5
−
15
40
kΩ
Vbias(tol)
bias tolerance pads R1 to R18 and
C1 to C80
note 6
−
20
130
mV
VVLCD(tol)
VLCD tolerance
Tamb = 25 °C; note 3
VLCD < 3 V
−
−
220
mV
VLCD < 4 V
−
−
270
mV
VLCD < 5 V
−
−
340
mV
VLCD < 6 V
−
−
440
mV
VLCD = 5.018 V
(VA/B = 27H)
−
−
340
mV
TC0
VLCD temperature coefficient 0
note 7
−
−8.0
−
mV/K
TC1
VLCD temperature coefficient 1
note 7
−
−9.0
−
mV/K
TC2
VLCD temperature coefficient 2
note 7
−
−10.5 −
mV/K
TC3
VLCD temperature coefficient 3
note 7
−
−11.8 −
mV/K
Notes
1. LCD outputs are open-circuit; inputs at VDD or VSS; bus inactive.
2. Tamb = 25 °C; fOSC = 200 kHz.
3. LCD outputs are open-circuit; HV generator is on; load current IVLCD (at VLCD) = 5 µA.
4. Tested on sample basis.
5. Resistance of output terminals (R1 to R18 and C1 to C80) with a load current of 20 µA; outputs measured one at a
time; external VLCD.
6. LCD outputs open-circuit; external VLCD.
7. Temperature coefficient at VOP = 5.0 V. Typical range ±2 mV/K.
1999 Mar 02
37
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
14 AC CHARACTERISTICS
VDD = 2.2 to 5.5 V; VSS = 0 V; VLCD = 2.2 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
fFR
LCD frame frequency (internal clock)
fOSC
oscillator frequency (not available at any pad)
140
250
450
kHz
fOSC(ext)
external clock frequency
140
−
450
kHz
tOSCST
oscillator start-up time after power-down
−
200
300
µs
VDD = 5.0 V
45
95
147
Hz
Bus timing characteristics: parallel interface; note 1
WRITE OPERATION (WRITING DATA FROM MPU TO PCF2119X)
Tcy(en)
enable cycle time
500
−
−
ns
tW(en)
enable pulse width
220
−
−
ns
tsu(A)
address set-up time
50
−
−
ns
th(A)
address hold time
25
−
−
ns
tsu(D)
data set-up time
60
−
−
ns
th(D)
data hold time
25
−
−
ns
READ OPERATION (READING DATA FROM PCF2119X TO MPU)
Tcy(en)
enable cycle time
500
−
−
ns
tW(en)
enable pulse width
220
−
−
ns
tsu(A)
address set-up time
50
−
−
ns
th(A)
address hold time
25
−
−
ns
td(D)
data delay time
−
−
150
ns
th(D)
data hold time
20
−
100
ns
Timing characteristics: I2C-bus interface; note 1
fSCL
SCL clock frequency
−
−
400
kHz
tLOW
SCL clock low period
1.3
−
−
µs
tHIGH
SCL clock high period
0.6
−
−
µs
tSU;DAT
data set-up time
100
−
−
ns
tHD;DAT
data hold time
0
−
−
ns
tr
SCL, SDA rise time
−
−
300
ns
tf
SCL, SDA fall time
−
−
300
ns
CB
capacitive bus line load
−
−
400
pF
tSU;STA
set-up time for a repeated START condition
0.6
−
−
µs
tHD;STA
START condition hold time
0.6
−
−
µs
tSU;STO
set-up time for STOP condition
0.6
−
−
µs
tSW
tolerable spike width on bus
−
−
50
ns
Note
1. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
VIL and VIH with an input voltage swing of VSS to VDD.
1999 Mar 02
38
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
15 TIMING CHARACTERISTICS
handbook, full pagewidth
RS
VIH1
V IL1
VIH1
VIL1
t su(A)
R/W
t h(A)
V IL1
VIL1
t h(A)
tW(en)
VIH1
VIH1
VIL1
E
VIL1
VIL1
t h(D)
t su(D)
VIH1
valid data
VIL1
DB0 to DB7
VIH1
VIL1
MBK474
Tcy(en)
Fig.26 Parallel bus write operation sequence; writing data from MPU to PCF2119x.
handbook, full pagewidth
RS
VIH1
V IL1
VIH1
VIL1
tsu(A)
R/W
t h(A)
VIH1
VIH1
tW(en)
E
VIL1
VIH1
t h(A)
VIH1
VIL1
t d(D)
DB0 to DB7
VIL1
t h(D)
VOH1
VOL1
VOH1
VOL1
Tcy(en)
MBK475
Fig.27 Parallel bus read operation sequence; reading data from PCF2119x to MPU.
1999 Mar 02
39
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
16 APPLICATION INFORMATION
handbook, full pagewidth
P80CL51
P20
RS
P21
R/W
P22
E
P17 to P10
2
R1 to R16
2 × 16 CHARACTER
LCD DISPLAY
PLUS 160 ICONS
PCF2119x
16
C1 to C80
DB7 to DB0
8
R17, R18
80
MGK895
Fig.28 Direct connection to 8-bit MPU; 8-bit bus.
handbook, full pagewidth
P80CL51
P10
RS
P11
R/W
P12
E
P17 to P14
2
R1 to R16
2 × 16 CHARACTER
LCD DISPLAY
PLUS 160 ICONS
PCF2119x
16
C1 to C80
DB7 to DB4
4
R17, R18
80
MGK896
Fig.29 Direct connection to 8-bit MPU; 4-bit bus.
handbook, full pagewidth
OSC
VDD
R17, R18
2
R1 to R16
2 × 16 CHARACTER
LCD DISPLAY
PLUS 160 ICONS
VDD
PCF2119x
100
nF
VSS
16
VLCD
100
nF
C1 to C80
80
VSS
8
DB7 to DB0 E
MGK897
RS R/W
Fig.30 Typical application using parallel interface.
1999 Mar 02
40
Philips Semiconductors
Product specification
LCD controllers/drivers
handbook, full pagewidth
PCF2119x
VDD VDD
VDD
OSC
VDD
DB3/SAO
2
R1 to R16
2 × 16 CHARACTER
LCD DISPLAY
PLUS 160 ICONS
VDD
PCF2119x
100
nF
R17, R18
16
VLCD
100
nF
VSS
VSS
C1 to C80
80
R17, R18
2
R1 to R16
1 × 32 CHARACTER
LCD DISPLAY
PLUS 160 ICONS
SCL SDA
VSS
OSC
VDD
DB3/SAO
VDD
PCF2119x
100
nF
VSS
SCL SDA
16
VLCD
100
nF
C1 to C80
VSS
80
SCL SDA
MASTER TRANSMITTER
PCF84C81A; P80CL410
MGK898
Fig.31 Application using I2C-bus interface.
1999 Mar 02
41
Philips Semiconductors
Product specification
LCD controllers/drivers
16.1
PCF2119x
16.3
8-bit operation, 1-line display using external
reset
For a 2-line display, the cursor automatically moves from
the first to the second line after the 40th digit of the first line
has been written. Thus, if there are only 8 characters in the
first line, the DDRAM address must be set after the 8th
character is completed (see Table 6). It should be noted
that both lines of the display are always shifted together;
data does not shift from one line to the other.
Table 13 shows an example of a 1-line display in 8-bit
operation. The PCF2119x functions must be set by the
‘function set’ instruction prior to display. Since the DDRAM
can store data for 80 characters, the RAM can be used for
advertising displays when combined with display shift
operation. Since the display shift operation changes
display position only and the DDRAM contents remain
unchanged, display data entered first can be displayed
when the ‘return home’ operation is performed.
16.2
8-bit operation, 2-line display
16.4
I2C-bus operation, 1-line display
A control byte is required with most commands
(see Table 16).
4-bit operation, 1-line display using external
reset
The program must set functions prior to a 4-bit operation,
see Table 12. When power is turned on, 8-bit operation is
automatically selected and the PCF2119x attempts to
perform the first write as an 8-bit operation. Since nothing
is connected to DB0 to DB3, a rewrite is then required.
However, since one operation is completed in two
accesses of 4-bit operation, a rewrite is required to set the
functions (see Table 12 step 3). Thus, DB4 to DB7 of the
‘function set’ are written twice.
Table 12 4-bit operation, 1-line display example; using external reset
STEP
INSTRUCTION
1
power supply on (PCF2119x is initialized by
the external reset)
2
function set
3
4
5
6
DISPLAY
RS
R/W
DB7
DB6
DB5
DB4
0
0
0
0
1
0
OPERATION
initialized; no display appears
sets to 4-bit operation; in this instance operation
is handled as 8-bits by initialization and only this
instruction completes with one write
function set
0
0
0
0
1
0
0
0
0
0
0
0
sets to 4-bit operation, selects 1-line display and
VLCD = V0; 4-bit operation starts from this point
and resetting is needed
display on/off control
0
0
0
0
0
0
0
0
1
1
1
0
_
turns on display and cursor; entire display is
blank after initialization
_
sets mode to increment the address by 1 and to
shift the cursor to the right at the time of write to
the DD/CGRAM; display is not shifted
P_
writes ‘P’; the DDRAM has already been selected
by initialization at power-on; the cursor is
incremented by 1 and shifted to the right
entry mode set
0
0
0
0
0
0
0
0
0
1
1
0
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
1
1
0
0
0
0
0
1999 Mar 02
42
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INSTRUCTION
DISPLAY
1
power supply on (PCF2119x is initialized by the external
reset)
2
function set
3
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
1
0
0
0
0
sets to 8-bit operation, selects 1-line display and
VLCD = V0
0
0
0
0
0
1
1
1
0
_
turns on display and cursor; entire display is blank after
initialization
0
0
0
0
1
1
0
_
sets mode to increment the address by 1 and to shift the
cursor to the right at the time of the write to the
DD/CGRAM; display is not shifted
0
0
0
0
P_
writes ‘P’; the DDRAM has already been selected by
initialization at power-on; the cursor is incremented by 1
and shifted to the right
1
0
0
0
PH_
entry mode set
0
5
0
display mode on/off control
0
4
initialized; no display appears
0
0
0
0
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
1
43
6
OPERATION
Philips Semiconductors
STEP
LCD controllers/drivers
1999 Mar 02
Table 13 8-bit operation, 1-line display example; using external reset (character set ‘A’)
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
0
7 to 11
writes ‘H’
|
|
12
‘write data’ to CGRAM/DDRAM
1
13
0
1
0
0
1
1
PHILIPS_
writes ‘S’
0
0
0
0
0
0
1
1
1
PHILIPS_
sets mode for display shift at the time of write
0
0
0
0
0
0
HILIPS _
writes space
1
1
0
1
ILIPS
writes ‘M’
0
1
0
0
1
0
0
M_
|
|
|
PCF2119x
0
Product specification
‘write data’ to CGRAM/DDRAM
1
16
1
‘write data’ to CGRAM/DDRAM
1
15
0
entry mode set
0
14
0
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17
‘write data’ to CGRAM/DDRAM
18
cursor/display shift
1
0
19
0
1
1
1
1
MICROKO
writes ‘O’
0
0
1
0
0
0
0
MICROKO
shifts only the cursor position to the left
0
0
0
0
1
0
0
0
0
MICROKO
shifts only the cursor position to the left
0
0
1
0
0
0
0
1
1
ICROCO
writes ‘C’ correction; the display moves to the left
0
0
0
0
1
1
1
0
0
MICROCO
shifts the display and cursor to the right
0
0
1
0
1
0
0
MICROCO_
shifts only the cursor to the right
1
1
0
1
ICROCOM_
writes ‘M’
cursor/display shift
0
23
0
cursor/display shift
0
22
0
1
‘write data’ to CGRAM/DDRAM
1
21
0
0
OPERATION
cursor/display shift
0
20
0
DISPLAY
Philips Semiconductors
INSTRUCTION
LCD controllers/drivers
1999 Mar 02
STEP
0
0
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
0
24
|
44
|
|
25
return home
0
0
0
0
0
0
0
0
1
0
PHILIPS M
returns both display and cursor to the original position
(address 0)
Product specification
PCF2119x
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INTRODUCTION
DISPLAY
1
power supply on (PCF2119x is initialized by the external
reset)
2
function set
3
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
1
0
0
0
0
sets to 8-bit operation, selects 1-line display and
VLCD = V0
0
0
45
0
0
0
1
1
1
0
_
turns on display and cursor; entire display is blank after
initialization
0
0
0
0
0
0
1
1
0
_
sets mode to increment the address by 1 and to shift the
cursor to the right at the time of the write to the
DD/CGRAM; display is not shifted
0
0
0
0
0
0
_
sets the CGRAM address to position of character 0; the
CGRAM is selected
1
0
1
0
_
set CGRAM address
0
6
1
entry mode set
0
5
0
display mode on/off control
0
4
initialized; no display appears
0
0
OPERATION
Philips Semiconductors
STEP
LCD controllers/drivers
1999 Mar 02
Table 14 8-bit operation, 1-line display and icon example; using external reset (character set ‘A’)
0
0
1
‘write data’ to CGRAM/DDRAM
1
0
0
0
0
0
7
writes data to CGRAM for icon even phase; icons appears
|
|
8
set CGRAM address
0
9
0
0
1
1
1
0
0
0
0
_
1
0
1
0
_
sets the CGRAM address to position of character 4; the
CGRAM is selected
‘write data’ to CGRAM/DDRAM
1
0
0
0
0
0
10
writes data to CGRAM for icon odd phase
|
|
function set
12
0
0
1
1
0
0
0
1
_
sets H = 1
0
0
0
0
1
0
1
0
_
icons blink
0
0
1
1
0
0
0
1
_
sets H = 0
icon control
0
13
0
0
function set
0
0
PCF2119x
0
Product specification
11
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0
1
0
0
0
0
0
0
0
sets the DDRAM address to the first position; DDRAM is
selected
0
0
0
0
P_
writes ‘P’; the cursor is incremented by 1 and shifted to the
right
1
0
0
0
PH_
writes ‘H’
‘write data’ to CGRAM/DDRAM
1
16
OPERATION
set DDRAM address
0
15
DISPLAY
0
0
1
0
1
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
0
17 to 20
|
|
21
Philips Semiconductors
14
INTRODUCTION
LCD controllers/drivers
1999 Mar 02
STEP
return home
0
0
0
0
0
0
0
0
1
0
PHILIPS
returns both display and cursor to the original position
(address 0)
46
Product specification
PCF2119x
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INTRODUCTION
DISPLAY
1
power supply on (PCF2119x is initialized by the external
reset)
2
function set
3
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
sets to 8-bit operation; selects 2-line display and voltage
generator off
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
_
turns on display and cursor; entire display is blank after
initialization
0
0
0
0
1
1
0
_
sets mode to increment the address by 1 and to shift the
cursor to the right at the time of write to the CG/DDRAM;
display is not shifted
0
0
0
0
P_
writes ‘P’; the DDRAM has already been selected by
initialization at power-on; the cursor is incremented by 1
and shifted to the right
entry mode set
0
5
0
display on/off control
0
4
initialized; no display appears
0
0
OPERATION
0
0
Philips Semiconductors
STEP
LCD controllers/drivers
1999 Mar 02
Table 15 8-bit operation, 2-line display example; using external reset
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
1
47
6 to 10
|
|
|
11
‘write data’ to CGRAM/DDRAM
1
12
1
0
1
0
0
1
1
PHILIPS_
writes ‘S’
0
1
1
0
0
0
0
0
0
PHILIPS
_
sets DDRAM address to position the cursor at the head of
the 2nd line
1
1
0
1
PHILIPS
M_
writes ‘M’
‘write data’ to CGRAM/ DDRAM
1
0
0
1
0
0
|
|
Product specification
|
PCF2119x
14 to 19
0
set DDRAM address
0
13
0
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0
0
1
0
0
1
1
1
1
PHILIPS
MICROCO_
writes ‘O’
0
1
1
1
PHILIPS
MICROCO_
sets mode for display shift at the time of write
1
1
0
1
HILIPS
ICROCOM_
writes ‘M’; display is shifted to the left; the first and second
lines shift together
‘write data’ to CGRAM/DDRAM
0
22
OPERATION
‘write data’ to CGRAM/DDRAM
1
21
DISPLAY
0
0
0
0
0
‘write data’ to CGRAM/DDRAM
1
0
0
1
0
0
23
|
Philips Semiconductors
20
INTRODUCTION
LCD controllers/drivers
1999 Mar 02
STEP
|
|
24
return home
0
0
0
0
0
0
0
0
1
0
PHILIPS
MICROCOM
returns both display and cursor to the original position
(address 0)
48
Product specification
PCF2119x
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1
I2C-bus
2
slave address for write
DISPLAY
start
initialized; no display appears
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack
0
3
4
1
1
1
0
1
0
0
1
during the acknowledge cycle SDA will be pulled-down by the
PCF2119x
control byte sets RS for following data bytes
send a control byte for ‘function set’
Co
RS
0
0
0
0
0
0
Ack
0
0
0
0
0
0
0
0
1
function set
selects 1-line display and VLCD = V0; SCL pulse during
acknowledge cycle starts execution of instruction
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
5
0
1
X
0
0
0
0
1
display on/off control
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
6
0
0
0
1
1
1
0
49
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
0
0
7
I2C start
8
slave address for write
0
1
1
0
0
_
sets mode to increment the address by 1 and to shift the cursor
to the right at the time of write to the DDRAM or CGRAM; display
is not shifted
_
for writing data to DDRAM, RS must be set to 1; therefore a
control byte is needed
1
1
1
0
1
0
0
1
_
send a control byte for ‘write data’
Co
RS
0
0
0
0
0
0
Ack
0
1
0
0
0
0
0
0
1
_
‘write data’ to DDRAM
0
1
0
0
0
0
P_
writes ‘P’; the DDRAM has been selected at power-up; the
cursor is incremented by 1 and shifted to the right
PH_
writes ‘H’
1
‘write data’ to DDRAM
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
1
0
0
1
0
0
0
1
Product specification
1
PCF2119x
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
11
turns on display and cursor; entire display shows character 20H
(blank in ASCII-like character sets)
1
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack
10
_
1
entry mode set
0
9
OPERATION
Philips Semiconductors
I2C BYTE
STEP
LCD controllers/drivers
1999 Mar 02
Table 16 Example of I2C-bus operation; 1-line display (using external reset, assuming SA0 = VSS; note 1)
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12 to 15
OPERATION
|
|
|
|
16
‘write data’ to DDRAM
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
1
0
1
0
0
1
1
17
(optional I2C stop) I2C start + slave address for write
(as step 8)
18
control byte
19
Co
RS
0
0
0
0
0
0
Ack
1
0
0
0
0
0
0
0
1
50
0
0
0
0
20
I2C start
21
slave address for read
0
0
1
0
PHILIPS_
PHILIPS_
0
1
PHILIPS
1
sets DDRAM address 0 in address counter (also returns shifted
display to original position; DDRAM contents unchanged); this
instruction does not update the Data Register (DR)
PHILIPS
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack
23
writes ‘S’
return home
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
22
PHILIPS_
1
Philips Semiconductors
DISPLAY
LCD controllers/drivers
1999 Mar 02
I2C BYTE
STEP
1
1
0
1
0
1
1
PHILIPS
during the acknowledge cycle the content of the DR is loaded
into the internal I2C-bus interface to be shifted out; in the
previous instruction neither a ‘set address’ nor a ‘read data’ has
been performed; therefore the content of the DR was unknown;
the R/W has to be set to 1 while still in I2C-write mode
PHILIPS
DDRAM content will be read from following instructions
PHILIPS
8 × SCL; content loaded into interface during previous
acknowledge cycle is shifted out over SDA; MSB is DB7; during
master acknowledge content of DDRAM address 01 is loaded
into the I2C-bus interface
control byte for read
Co
RS
0
0
0
0
0
0
Ack
0
1
1
0
0
0
0
0
1
‘read data’: 8 × SCL + master acknowledge; note 2
X
X
X
X
X
X
X
0
PCF2119x
X
Product specification
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
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‘read data’: 8 × SCL + master acknowledge; note 2
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
25
1
0
0
1
0
0
0
PHILIPS
8 × SCL; code of letter ‘H’ is read first; during master
acknowledge code of ‘I’ is loaded into the I2C interface
PHILIPS
no master acknowledge; after the content of the I2C-bus
interface register is shifted out no internal action is performed;
no new data is loaded to the interface register, data register is
not updated, address counter is not incremented and cursor is
not shifted
0
‘read data’: 8 × SCL + no master acknowledge; note 2
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
0
26
OPERATION
1
I2C stop
0
0
1
0
0
1
1
PHILIPS
Philips Semiconductors
24
DISPLAY
LCD controllers/drivers
1999 Mar 02
I2C BYTE
STEP
Notes
1. X = don’t care.
2. SDA is left at high-impedance by the microcontroller during the read acknowledge.
51
Product specification
PCF2119x
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DESCRIPTION
power-on or unknown state
|
wait 2 ms after external reset has been applied
|
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
BF cannot be checked before this instruction
0
0
0
0
1
1
X
X
X
X
function set (interface is 8 bits long)
|
wait 2 ms
|
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
BF cannot be checked before this instruction
0
0
0
0
1
1
X
X
X
X
function set (interface is 8 bits long)
DB4
DB3
DB2
DB1
DB0
BF cannot be checked before this instruction
1
X
X
X
X
Philips Semiconductors
STEP
LCD controllers/drivers
1999 Mar 02
Table 17 Initialization by instruction, 8-bit interface (note 1)
|
wait more than 40 µs
|
52
RS
R/W
DB7
DB6
DB5
0
0
0
0
1
|
|
RS
function set (interface is 8 bits long)
BF can be checked after the following instructions; when BF is not checked,
the waiting time between instructions is the specified instruction time
(see Table 3)
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
1
1
0
M
0
H
0
0
0
0
0
0
1
0
0
0
display off
0
0
0
0
0
0
0
0
0
1
clear display
0
0
0
0
0
0
0
1
I/D
S
entry mode set
function set (interface is 8 bits long); specify the number of display lines
|
Initialization ends
Product specification
1. X = don’t care.
PCF2119x
Note
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DESCRIPTION
power-on or unknown state
|
Wait 2 ms after external reset has been applied
|
RS
R/W
DB7
DB6
DB5
DB4
0
0
0
0
1
1
DB6
DB5
DB4
0
1
1
BF cannot be checked before this instruction
function set (interface is 8 bits long)
|
Wait 2 ms
|
RS
R/W
DB7
0
0
0
Philips Semiconductors
STEP
LCD controllers/drivers
1999 Mar 02
Table 18 Initialization by instruction, 4-bit interface; not applicable for I2C-bus operation
BF cannot be checked before this instruction
function set (interface is 8 bits long)
|
Wait 40 µs
|
53
RS
R/W
DB7
DB6
DB5
DB4
0
0
0
0
1
1
|
BF cannot be checked before this instruction
function set (interface is 8 bits long)
BF can be checked after the following instructions; when BF is not checked, the waiting time
between instructions is the specified instruction time (see Table 3)
RS
R/W
DB7
DB6
DB5
DB4
0
0
0
0
1
0
0
0
0
0
1
0
function set (interface is 4 bits long)
0
0
0
M
0
H
specify number of display lines
0
0
0
0
0
0
0
0
1
0
0
0
display off
0
0
0
0
0
0
clear display
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
I/D
S
entry mode set
Product specification
Initialization ends
interface is 8 bits long
PCF2119x
|
function set (set interface to 4 bits long)
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
17 BONDING PAD LOCATIONS
handbook, full pagewidth
8.64
mm
dummy (VSS1)
R16
R15
R14
R13
R12
R11
R10
R9
R18
108
109
110
111
112
113
114
115
116
117
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
118
119
120
121
122
123
124
125
126
127
SCL
T3
POR
PD
SDA
SDA
128
129
130
131
132
133
R/W
RS
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
OSC
VDD1
VDD1
134
135
136
137
138
139
140
141
142
143
144
1
2
VDD2
VDD2
3
4
E
T1
T2
VSS1
VSS1
5
6
7
8
9
VSS2
VSS2
10
11
VLCD1
VLCD1
12
13
VLCD2
VLCD2
14
15
C71
C72
C73
C74
C75
C76
C77
C78
C79
C80
16
17
18
19
20
21
22
23
24
25
R17
R1
R2
R3
R4
R5
R6
R7
R8
dummy (VSS1)
26
27
28
29
30
31
32
33
34
35
Y
X
PC2119-1
ROM010
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
dummy (VSS1)
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
dummy (VSS1)
dummy (VSS1)
dummy (VSS1)
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
dummy (VSS1)
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
C38
C39
C40
R17DUP
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
dummy (VSS1)
dummy (VSS1)
dummy (VSS1)
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
dummy (VSS1)
C56
C57
C58
C59
C60
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70
dummy (VSS1)
dummy (VSS1)
MGK890
1.91 mm
Fig.32 Bonding pad locations.
1999 Mar 02
54
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
x
handbook, full pagewidth
A
y
1,1
2,1
1,2
2,2
3,1
x,1
D
B
1,3
F
x,y
1,y
E
MGR977
Fig.33 Tray details.
Table 19 Dimensions for Fig.33
DIM.
PCF2119-1
handbook, halfpage
MGR978
The orientation of the IC in a pocket is indicated by the position of the
IC type name on the die surface with respect to the chamfer on the
upper left corner of the tray. Refer to the bonding pad location
diagram for the orientating and position of the type name on the die
surface.
Fig.34 Tray alignment.
1999 Mar 02
55
DESCRIPTION
VALUE
A
pocket pitch, x direction
10.89 mm
B
pocket pitch, y direction
4.34 mm
C
pocket width, x direction
8.74 mm
D
pocket width, y direction
2.01 mm
E
tray width, x direction
50.67 mm
F
tray width, y direction
50.67 mm
x
number of pockets in x
direction
4
y
number of pockets in y
direction
10
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
Table 20 Bonding pad locations
Dimensions in µm; all x/y coordinates are referenced to
centre of chip; see Fig.32
SYMBOL
PAD
VDD1
VDD1
VDD2
VDD2
E
T1
T2
VSS1
VSS1
VSS2
VSS2
VLCD1
VLCD1
VLCD2
VLCD2
C71
C72
C73
C74
C75
C76
C77
C78
C79
C80
R17
R1
R2
R3
R4
R5
R6
R7
R8
Dummy (VSS1)
Dummy (VSS1)
Dummy (VSS1)
C70
C69
C68
C67
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
1999 Mar 02
x
−117
−16
+185
+286
+486
+587
+688
+789
+889
+1090
+1191
+1393
+1493
+1695
+1795
+1996
+2097
+2198
+2298
+2399
+2499
+2600
+2701
+2801
+2902
+3103
+3204
+3304
+3405
+3505
+3606
+3707
+3807
+3908
+4008
3957
3856
3756
3655
3555
3454
y
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
779
779
779
779
779
779
56
SYMBOL
PAD
C66
C65
C64
C63
C62
C61
C60
C59
C58
C57
C56
Dummy (VSS1)
Dummy (VSS1)
Dummy (VSS1)
Dummy (VSS1)
C55
C54
C53
C52
C51
C50
C49
C48
C47
C46
C45
C44
C43
C42
C41
R17DUP
C40
C39
C38
C37
C36
C35
C34
C33
C32
C31
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
x
3353
3253
3152
3052
2951
2850
2750
2649
2549
2448
2347
2247
1744
1643
1543
1442
1341
1241
1140
1040
939
838
738
637
537
436
335
235
134
34
−67
−168
−268
−369
−469
−570
−671
−771
−872
−972
−1073
y
779
779
779
779
779
779
779
779
779
779
779
779
779
779
779
779
779
779
779
779
779
779
779
779
779
779
779
779
779
779
+779
+779
+779
+779
+779
+779
+779
+779
+779
+779
+779
Philips Semiconductors
Product specification
LCD controllers/drivers
SYMBOL
PAD
C30
C29
C28
C27
C26
Dummy (VSS1)
Dummy (VSS1)
Dummy (VSS1)
Dummy (VSS1)
C25
C24
C23
C22
C21
C20
C19
C18
C17
C16
C15
C14
C13
C12
C11
Dummy (VSS1)
Dummy (VSS1)
R16
R15
R14
R13
R12
R11
R10
R9
R18
C1
C2
C3
C4
C5
C6
C7
C8
C9
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
1999 Mar 02
PCF2119x
x
−1174
−1274
−1375
−1475
−1576
−1677
−2180
−2280
−2381
−2481
−2582
−2683
−2783
−2884
−2984
−3085
−3186
−3286
−3387
−3487
−3588
−3689
−3789
−3890
−3990
−4141
−4041
−3940
−3840
−3739
−3638
−3538
−3437
−3337
−3236
−3035
−2934
−2834
−2733
−2633
−2532
−2431
−2331
−2230
y
+779
+779
+779
+779
+779
+779
+779
+779
+779
+779
+779
+779
+779
+779
+779
+779
+779
+779
+779
+779
+779
+779
+779
+779
+779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
SYMBOL
PAD
C10
SCL
T3
POR
PD
SDA
SDA
R/W
RS
DB0/SA0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
OSC
Rec. Pat. C1
Rec. Pat. C2
Rec. Pat. +
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
−
−
−
x
−2129
−1928
−1827
−1726
−1626
−1525
−1425
−1223
−1123
−1022
−922
−821
−720
−620
−519
−419
−318
−217
+4125
−4125
4095
y
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−779
−762
+762
762
Table 21 Bump size
57
PARAMETER
VALUE
Type
Bump width
Bump length
Bump height
Height difference in one die
Convex deformation
Pad size, aluminium
Passivation opening CBB
Wafer thickness
galvanic pure Au
70 ±6
90 ±6
17.5 ±5
<2
<5
85 × 100
58 × 78
380 ±25
UNIT
−
µm
µm
µm
µm
µm
µm
µm
µm
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
18 DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
19 LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
20 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1999 Mar 02
58
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2119x
NOTES
1999 Mar 02
59
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© Philips Electronics N.V. 1999
SCA62
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Printed in The Netherlands
465006/00/02/pp60
Date of release: 1999 Mar 02
Document order number:
9397 750 04653