Features • • • • • • • • Single Power Supply Read and Write Voltage, 5 V ± 5% High Performance 200 ns Maximum Access Time 6 ms Typical Sector Write CMOS Low Power Consumption 25 mA Typical Active Current (Byte Mode) 400 µA Typical Standby Current Fully MS-DOS Compatible Flash Driver and Formatter Virtual-Disk Flash Driver with 512 Bytes/Sector Random Read/Write to any Sector No Erase Operation Required Prior to any Write Zero Data Retention Power Batteries not Required for Data Storage PCMCIA/JEIDA 68-Pin Standard Selectable Byte- or Word-Wide Configuration High Re-programmable Endurance Built-in Redundancy for Sector Replacement Minimum 100,000 Write Cycles Five Levels of Write Protection Prevent Accidental Data Loss 8-Megabyte Flash Memory PCMCIA Card AT5FC008 Preliminary Block Diagram PCMCIA JEIDA 68 PINS 23 ADDRESS BUFFERS 16 DATA TRANSCEIVERS 5 BUS CONTROL Pin Configuration Pin Name Function A0-A22 Addresses D0-D15 Data CE1, CE2, WE, OE, REG Control Signals CD, WP BVD1, BVD2 Card Status A1-A19 19 8-MBYTE FLASH MEMORY ARRAY 16 A0, A20, A21, A22 CEX, WE, OE, REG GND D3 D4 D5 D6 D7 CE1 A10 OE A11 A9 A8 A13 A14 WE NC VCC NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 GND CD1 D11 D12 D13 D14 D15 CE2 NC RFU RFU A17 A18 A19 A20 A21 VCC NC A22 NC NC NC NC NC NC NC REG BVD2 BVD1 D8 D9 D10 CD2 GND Description The Card Information Structure (CIS) can be written by the OEM or by Atmel at the attribute memory address space using a format utility. The CIS appears at the beginning of the card’s attribute memory space and defines the low-level organization of data on the PC card. The AT5FC008 contains a separate 2K byte EEPROM memory for the card’s attribute memory space. The third party software solutions such as AWARD Software’s CardWare system and the SCM’s Flash File System (FFS), enables Atmel’s Flash Memory Card to emulate the function of essentially all the major brand personal computers that are DOS/Windows compatible. For some unique portable computers, such as the HP200/100/95LX series, the software Driver and Formatter are also available. The Atmel Driver and Formatter utilizes a selfcontained spare sector replacement algorithm, enabled by Atmel’s small 512-byte sectors, to achieve long term card reliability and endurance. Atmel’s Flash Memory Card provides the highest system level performance for data and file storage solutions to the portable PC market segment. Data files and applications programs can be stored on the AT5FC008. This allows OEM manufacturers of portable system to eliminate the weight, power consumption and reliability issues associated with electro-mechanical disk-based systems. The AT5FC008 requires a single voltage power supply for total system operation. No batteries are needed for data retention due to its Flash-based technology. Since no high voltage (12 V) is required to perform any write operation, the AT5FC008 is suitable for the emerging "mobile" personal systems. The AT5FC008 is compatible with the 68-pin PCMCIA/JEIDA international standard. Atmel’s Flash Memory Cards can be read in either a byte-wide or word-wide mode which allows for flexible integration into various system platforms. It can be read like any typical PCMCIA SRAM or ROM card. Block Diagram VCC D0-D15 R R WE OE WP D8-D15 I/O TRANSCEIVERS AND BUFFERS WP D0-D7 WE OE VCC WRITE PROTECT SWITCH DEVICE A0-A18 SYSTEM A0 A1-A22 ADDRESS BUFFERS AND DECODERS CE2 CE1 CEH0CEH7 CEL0CEL7 REG AT29C040 A0-A18 CE R R OE WE ATTRIBUTE MEMORY R D0-D7 VCC CE WE OE D0-D7 AT29C040 CE S0 VSS VCC D8-D15 A0-A18 WE OE S1 VSS VCC A0-A10 CD1 CD2 A0-A18 CE CARD DETECT WE OE D0-D7 A0-A18 CE WE S2 VSS VCC OE D8-D15 S3 VSS VCC BVD1 BVD2 A0-A18 VCC BATTERY VOLTAGE DETECT GND VCC 2 AT5FC008 CE WE OE D0-D7 S14 VSS VCC A0-A18 CE WE OE D8-D15 S15 VSS VCC AT5FC008 Absolute Maximum Ratings* Storage Temperature........................ -30°C to +70°C Ambient Temperature with Power Applied................................... -10°C to +70°C Voltage with Respect to Ground, All pins(1).......... -2.0 V to +7.0 V VCC(1) ............................................... -2.0 V to +7.0 V Output Short Circuit Current (2) .................... -200 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the card. This is a stress rating only and functional operation of the card at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transients, inputs may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins is VCC+0.5 V. During voltage transitions, outputs may overshoot to VCC+2.0 V for periods up to 20 ns. 2. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. Conditions equal VOUT = 0.5 V or 5.0 V, VCC = Max. D.C. and A.C. Operating Range AT5FC008-20 Operating Temperature (Case) 0oC - 70oC Com. 5 V ± 5% VCC Power Supply Pin Capacitance (f = 1 MHz, T = 25°C) (1) Symbol Parameter Conditions CIN1 Address Capacitance COUT Max Units VIN = 0 V 20 pF Output Capacitance VOUT = 0 V 20 pF CIN2 Control Capacitance VIN = 0 (CE) 45 pF CI/O I/O Capacitance VI/O = 0 V 20 pF Note: Typ 1. This parameter is characterized and is not 100% tested. 3 PC Card Pin Assignments I = Input, O = Output, I/O = Bi-directional, NC = No Connect Pin Signal 1 GND 2 D3 3 I/O Function Pin Signal Ground 35 GND I/O Data Bit 3 36 CD1 O Card Detect 1 (1) D4 I/O Data Bit 4 37 D11 I/O Data Bit 11 4 D5 I/O Data Bit 5 38 D12 I/O Data Bit 12 5 D6 I/O Data Bit 6 39 D13 I/O Data Bit 13 6 D7 I/O Data Bit 7 40 D14 I/O Data Bit 14 41 D15 I/O Data Bit 15 I (1) Function Ground 7 CE1 I Card Enable 1 8 A10 I Address Bit 10 42 CE2 9 OE I Output Enable 43 NC No Connect 10 A11 I Address Bit 11 44 RFU Reserved 11 A9 I Address Bit 9 45 RFU Reserved 12 A8 I Address Bit 8 46 A17 I Address Bit 17 13 A13 I Address Bit 13 47 A18 I Address Bit 18 14 A14 I Address Bit 14 48 A19 I Address Bit 19 15 WE I Write Enable 49 A20 I Address Bit 20 16 NC No Connect 50 A21 I Address Bit 21 17 VCC Power Supply 51 VCC Power Supply 18 NC No Connect 52 NC No Connect 19 A16 I Address Bit 16 53 A22 20 A15 I Address Bit 15 54 NC No Connect 21 A12 I Address Bit 12 55 NC No Connect 22 A7 I Address Bit 7 56 NC No Connect 23 A6 I Address Bit 6 57 NC No Connect 24 A5 I Address Bit 5 58 NC No Connect 25 A4 I Address Bit 4 59 NC No Connect 26 A3 I Address Bit 3 60 NC No Connect 27 A2 I Address Bit 2 61 REG I Register Select 28 A1 I Address Bit 1 62 BVD2 O Battery Voltage Detect 2 (2) 29 A0 I Address Bit 0 63 BVD1 O Battery Voltage Detect 1 (2) 30 D0 I/O Data Bit 0 64 D8 I/O Data Bit 8 31 D1 I/O Data Bit 1 65 D9 I/O Data Bit 9 32 D2 I/O Data Bit 2 66 D10 I/O Data Bit 10 67 CD2 O Card Detect 2 (1) 68 GND 33 WP 34 GND O Write Protect (1) Ground Notes: 1. Signal must not be connected between cards. 2. BVD = Internally pulled up. 4 I/O AT5FC008 I Card Enable 2 (1) Address Bit 22 Ground AT5FC008 Pin Description Symbol Name Type Function A0-A22 Address Inputs Input Address Inputs are internally latched during write cycles. D0-D15 Data Input/Output Input/Output Data Input/Outputs are internally latched on write cycles. Data outputs are latched during read cycles. Data pins are active high. When the memory card is de-selected or the outputs are disabled the outputs float to tri-state. CE1, CE2 Card Enable Input Card Enable is active low. The memory card is de-selected and power consumption is reduced to standby levels when CE is high. CE activates the internal memory card circuitry that controls the high and low byte control logic of the card, input buffers, segment decoders, and associated memory devices. OE Output Enable Input Output Enable is active low and enables the data buffers through the card outputs during read cycles. Input Write Enable is active low and controls the write function to the memory array. The target address is latched on the falling edge of the WE pulse and the appropriate data is latched on the rising edge of the pulse. WE Write Enable VCC PC Card Power Supply PC Card Power Supply for device operation (5.0 V ± 5%) GND Ground Ground CD1, CD2 Card Detect Output When Card Detect 1 and 2 = Ground the system detects the card. WP Write Protect Output Write Protect is active high and indicates that all card write operations are disabled by the write protect switch. NC No Connect BVD1, BVD2 Battery Voltage Detect Output Internally pulled up. (There is no battery in the card.) REG Register Select Input Provide access to Card Information Structure in the Attribute Memory Device Corresponding pin is not connected internally. 5 Memory Card Operations The AT5FC008 Flash Memory Card is organized as an array of 16 individual AT29C040 devices. They are logically defined as contiguous sectors of 512 bytes. Each sector can be read and written randomly as designated by the host. There is NO need to erase any sector prior to any write operation. Also, there is NO high voltage (12 V) required to perform any write operations. The common memory space data contents are altered in a similar manner as writing to individual Flash memory devices. Oncard address and data buffers activate the appropriate Flash device in the memory array. Each device internally latches address and data during write cycles. Refer to the Common Memory Operations table. falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Each byte pair to be programmed must have its high-to-low transition on WE (or CE) within 150 µs of the low-to- high transition of WE (or CE) of the preceding byte pair. If a high-to-low transition is not detected within 150 µs of the last low-to-high transition, the data load period will end and the internal programming period will start. All the bytes of a sector are simultaneously programmed during the internal programming period. A maximum write time of 10 ms per sector is self-controlled by the Flash devices. Refer to A.C. Write Waveforms drawings. Write Protection Byte-Wide Operations The AT5FC008 provides the flexibility to operate on data in byte-wide or word-wide operations. Byte-wide data is available on D0-D7 for read and write operations (CE1 = low, CE2 = high). Even and odd bytes are stored in a pair of memory chip segments (i.e., S0 and S1) and are accessed when A0 is low and high respectively. Word-Wide Operations The 16-bit words are accessed when both CE1 and CE2 are forced low, A0 = don’t care. D0-D15 are used for word-wide operations Read Enable/Output Disable Data outputs from the card are disabled when OE is at a logichigh level. Under this condition, outputs are in the high-impedance state. The A20, A21 and A22 select the paired memory chip segments, while A0 decides the upper or lower bank. The CE1/CE2 pins determine either byte or word mode operation. The Output Enable (OE) is forced low to activate all outputs of the memory chip segments. The on-card I/O transceiver is set in the output mode. The AT5FC008 sends data to the host. Refer to A.C. Read Waveforms drawing. Standby Operations When both CE1 and CE2 are at logic-high level, the AT5FC008 is in Standby mode; i.e., all memory chip segments as well as the decoder/transceiver are completely de-selected at minimum power consumption. Even in the byte-mode read operation, only one memory chip segment (even or odd) is active at any time. The other seven memory chip segments remain in standby. In the word-mode there are two memory chip segments in active and six in standby. Write Operations The AT5FC008 is written on a sector basis. Each sector of 512 bytes can be selected randomly and written independently without any prior erase cycle. A9 to A19 specify the sector address, while A20, A21 and A22 specify the Flash chip segment pair. Within each sector, the individual byte address is latched on the 6 AT5FC008 The AT5FC008 has five types of write protection. The PCMCIA/JEIDA socket itself provides the first type of write protection. Power supply and control pins have specific pin lengths in order to protect the card with proper power supply sequencing in the case of hot insertion and removal. A mechanical write protection switch provides a second type of write protection. When this switch is activated, WE is internally forced high. The Flash memory arrays are therefore write-disabled. The third type of write protection is achieved with the built-in low VCC sensing circuit within each Flash device. If the external VCC is below 3.8 V (typical), the write function is inhibited. The fourth type of write protection is a noise filter circuit within each Flash device. Any pulse of less than 15 ns (typical) on the WE, CE1 or CE2 inputs will not initiate a program cycle. The last type of write protection is based on the Software Data Protection (SDP) scheme of the AT29C040 devices. Each of the sixteen devices needs to enable and disable the SDP individually. Refer to the Software Data Protected Programming/Disable Algorithm tables for descriptions of enable and disable SDP operations. Card Detection Each CD (output) pin should be read by the host system to determine if the memory card is properly seated in the socket. CD1 and CD2 are internally tied to the ground. If both bits are not detected, the system should indicate that the card must be re-inserted. CIS Data The Card Information Structure (CIS) describes the capabilities and specifications of a card. The CIS of the AT5FC008 can be written either by the OEM or by Atmel at the attribute memory space beginning at address 00000H by using a format utility. The AT5FC008 contains a separate 2K byte EEPROM memory for the card’s attribute memory space. The attribute is active when the REG pin is driven low. D0-D7 are active during attribute memory access. D8-D15 should be ignored. Odd order bytes present invalid data. Refer to the Attribute Memory Operations table. AT5FC008 Common Memory Operations X = Don’t Care, where Don’t Care is either VIL or VIH levels. Pins REG CE2 CE1 OE WE A0 D8-D15 D0-D7 Read (x8) (1) VIH VIH VIL VIL VIH VIL High Z Data Out-Even Read (x8) (2) VIH VIH VIL VIL VIH VIH High Z Data Out-Odd Read (x8) (3) VIH VIL VIH VIL VIH X Data Out-Odd High Z VIH VIL VIL VIL VIH X Data Out-Odd Data Out-Even VIH X X VIH VIH X High Z High Z X VIH VIH X X X High Z High Z Write (x8) (1) VIH VIH VIL VIH VIL VIL High Z Data In-Even Write (x8) (2) VIH VIH VIL VIH VIL VIH High Z Data In-Odd (3) VIH VIL VIH VIH VIL X Data In-Odd High Z VIH VIL VIL VIH VIL X Data In-Odd Data In-Even VIH X X VIH VIL X High Z High Z Read-Only Read (x16) (4) Output Disable Standby Write-Only Write (x8) Write (x16) (4) Output Disable Notes: 1. Byte access - Even. In this x8 mode, D0-D7 contain the "even" byte (low byte) of the x16 word. D8-D15 are inactive. 2. Byte access - Odd. In this x8 mode, D0-D7 contain the "odd" byte (high byte) of the x16 word. This is accomplished internal to the card by transposing D8-D15 to D0-D7. D8-D15 are inactive. 3. Odd byte only access. In this x8 mode, D8-D15 contain the "odd" byte (high byte) of the x16 word. D0-D7 are inactive. A0 = X. 4. Word access. In this mode D0-D7 contain the "even" byte while D8-D15 contain the "odd" byte. A0 = X Memory Card Program Routine Memory Card Program Routine Byte Mode Word Mode BEGIN BEGIN SELECT SECTOR SELECT SECTOR LOAD ADDRESS/DATA OF 512 BYTES INTERLEAVING LOW 256 BYTES AND HIGH 256 BYTES LOAD ADDRESS/DATA OF 256 WORDS WAIT FOR A MAXIMUM OF 10 ms WAIT FOR A MAXIMUM OF 10 ms SECTOR PROGRAM COMPLETE SECTOR PROGRAM COMPLETE LOW AND HIGH BYTES SIMULTANEOUSLY 7 Attribute Memory Operations X = Don’t Care, where Don’t Care is either VIL or VIH levels. Pins REG CE2 CE1 OE WE A0 D8-D15 D0-D7 Read (x8) (1) VIL VIH VIL VIL VIH VIL High Z Data Out-Even Read (x8) VIL VIH VIL VIL VIH VIH High Z Not Valid Read (x8) VIL VIL VIH VIL VIH X Not Valid High Z Read (x16) VIL VIL VIL VIL VIH X Not Valid Data Out-Even Output Disable VIL X X VIH VIH X High Z High Z X VIH VIH X X X High Z High Z Write (x8) (1) VIL VIH VIL VIH VIL VIL High Z Data In-Even Write (x8) VIL VIH VIL VIH VIL VIH High Z Not Valid Write (x8) VIL VIL VIH VIH VIL X Not Valid High Z Write (x16) VIL VIL VIL VIH VIL X Not Valid Data In-Even Output Disable VIL X X VIH VIL X High Z High Z Read-Only Standby Write-Only Note: 8 1. Byte access - Even. In this x8 mode, D0-D7 contain the "even" byte (low byte) of the x16 word. D8-D15 are inactive. AT5FC008 AT5FC008 D.C. Characteristics, Byte-Wide Operation Symbol Parameter Condition ILI Input LeakageCurrent ILO Min Typ Max Units VCC = VCC Max, VIN = VCC or VSS 1.0 ±20 µA Output Leakage Current VCC = VCC Max, VOUT = VCC or VSS 1.0 20 µA ISB VCC Standby Current VCC = VCC Max, CE = VCC ± 0.2 V 0.6 1.2 mA ICC1 (1) VCC Active Read Current VCC = VCC Max, CE = VIL, OE = VIH, IOUT = 0 mA, at 5 MHz 25 40 mA ICC2 VCC Active Write Current CE = VIL,WE = VIL, Programming in Progress 25 40 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage VOL Output Low Voltage IOL = 3.2 mA VOH Output High Voltage IOH = -2.0 mA 2.4 V 0.40 3.8 V V Notes: 1. One Flash device active, 15 in standby. D.C. Characteristics, Word-Wide Operation Symbol Parameter Condition ILI Input LeakageCurrent ILO Min Typ Max Units VCC = VCC Max, VIN = VCC or VSS 1.0 ±20 µA Output Leakage Current VCC = VCC Max, VOUT = VCC or VSS 1.0 20 µA ISB VCC Standby Current VCC = VCC Max, CE = VCC ± 0.2 V 0.6 1.2 mA ICC1 (1) VCC Active Read Current VCC = VCC Max, CE = VIL, OE = VIH, IOUT = 0 mA, at 5 MHz 50 80 mA ICC2 VCC Active Write Current CE = VIL, WE = VIL, Programming in Progress 50 80 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage VOL Output Low Voltage IOL = 3.2 mA VOH Output High Voltage IOH = -2.0 mA 2.4 V 0.40 3.8 V V Notes: 1. Two Flash devices active, 14 in standby. 9 A.C. Read Characteristics Symbol Parameter Min Max 200 Units tRC Read Cycle Time tCE Chip Enable Access Time 200 ns tACC Address Access Time 200 ns tOE Output Enable Access Time 100 ns tLz Chip Enable to Output in Low Z tDF Chip Disable to Output in High Z tOLZ Output Enable to Output in Low Z tDF Output Disable to Output in High Z tOH Output Hold Time from First of Address, CE, or OE Change tWC Write Recovery Time Before Read 5 5 5 ns ns 10 ms Output Test Load 5.0V 1.8K AC MEASUREMENT LEVEL 0.0V ns ns 60 3.0V 1.5V ns 60 Input test Waveforms and Measurement Level AC DRIVING LEVELS ns OUTPUT PIN 100pF 1.3K tR, tF < 5 ns A.C. Read Waveforms (1) DEVICE AND ADDRESS SELECTION POWER-UP, STANDBY ADDRESS OUTPUT DATA ENABLED VALID STANDBY, POWER-DOWN ADDRESSES STABLE tRC CE tDF OE tDF tWC WE tOE tCE tOLZ tLZ DATA tACC VCC 5.0 V 0V Note: 1. CE refers to CE1, and/or CE2 10 AT5FC008 tOH OUTPUT VALID HIGH Z AT5FC008 Write Cycle Characteristics Symbol Parameter Min Max Units tWC Write Cycle Time 10 ms tAS Address Set-up Time 10 ns tAH Address Hold Time 60 ns tDS Data Set-up Time 60 ns tDH Data Hold Time 10 ns tWP Write Pulse Width 100 ns tBLC Byte Load Cycle Time tWPH Write Pulse Width High µs 150 100 ns A.C. Write Waveforms (Byte Mode) OE CE2 CE1 tWP tWPH WE tAS A0 tWC tBLC tAH tDH A1-A8 BYTE ADDRESS A9-A19 SECTOR ADDRESS tDS DATA BYTE 0 BYTE 1 BYTE 2 Notes: 1. A20, A21 and A22 specify the pair of AT29C040 devices to be written, while A0 controls the selection of even and odd bytes. A0, A20, A21 and A22 must be valid throughout the entire WE low pulse. 2. A9 through A19 must specify the sector address during each high to low transition of WE (or CE). BYTE 510 BYTE 511 3. OE must be high when WE and CE are both low. 4. All bytes that are not loaded within the sector being pro- grammed will be erased to FF. 11 A.C. Write Waveforms (Word Mode) OE CE1,2 tWP tWPH WE tAS tAH A1-A8 BYTE ADDRESS A9-A19 SECTOR ADDRESS tDH tWC tBLC tDS DATA WORD 0 WORD 1 WORD 2 1. A20, A21 and A22 specify the pair of AT29C040 devices to be written; they must be valid throughout the entire WE low pulse. A0 is don’t care. 2. A9 through A19 must specify the sector address during each high to low transition of WE (or CE). 12 AT5FC008 WORD 254 WORD 255 3. OE must be high when WE and CE are both low. 4. All bytes that are not loaded within the sector being pro- grammed will be erased to FF. AT5FC008 Software Data Protected Programming Algorithm (1) Device 0 1 2 3 4 5 6 7 Data Address AA 00AAAA AA 00AAAB AA 10AAAA AA 10AAAB AA 20AAAA AA 20AAAB AA 30AAAA AA 30AAAB Data Address 55 005554 55 005555 55 105554 55 105555 55 205554 55 205555 55 305554 55 305555 Data Address A0 00AAAA A0 00AAAB A0 10AAAA A0 10AAAB A0 20AAAA A0 20AAAB A0 30AAAA A0 30AAAB Writes Enabled Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Device 8 9 10 11 12 13 14 15 Data Address AA 40AAAA AA 40AAAB AA 50AAAA AA 50AAAB AA 60AAAA AA 60AAAB AA 70AAAA AA 70AAAB Data Address 55 405554 55 405555 55 505554 55 505555 55 605554 55 605555 55 705554 55 705555 Data Address A0 40AAAA A0 40AAAB A0 50AAAA A0 50AAAB A0 60AAAA A0 60AAAB A0 70AAAA A0 70AAAB Writes Enabled Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Note: 1. Load 3 bytes to corresponding Flash chip segment individually to enable software data protection. 13 Software Data Protected Disable Algorithm (1) Device 0 1 2 3 4 5 6 7 Data Address AA 00AAAA AA 00AAAB AA 10AAAA AA 10AAAB AA 20AAAA AA 20AAAB AA 30AAAA AA 30AAAB Data Address 55 005554 55 005555 55 105554 55 105555 55 205554 55 205555 55 305554 55 305555 Data Address 80 00AAAA 80 00AAAB 80 10AAAA 80 10AAAB 80 20AAAA 80 20AAAB 80 30AAAA 80 30AAAB Data Address AA 00AAAA AA 00AAAB AA 10AAAA AA 10AAAB AA 20AAAA AA 20AAAB AA 30AAAA AA 30AAAB Data Address 55 005554 55 005555 55 105554 55 105555 55 205554 55 205555 55 305554 55 305555 Data Address 20 00AAAA 20 00AAAB 20 10AAAA 20 10AAAB 20 20AAAA 20 20AAAB 20 30AAAA 20 30AAAB Writes Enabled Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Device 8 9 10 11 12 13 14 15 Data Address AA 40AAAA AA 40AAAB AA 50AAAA AA 50AAAB AA 60AAAA AA 60AAAB AA 70AAAA AA 70AAAB Data Address 55 405554 55 405555 55 505554 55 505555 55 605554 55 605555 55 705554 55 705555 Data Address 80 40AAAA 80 40AAAB 80 50AAAA 80 50AAAB 80 60AAAA 80 60AAAB 80 70AAAA 80 70AAAB Data Address AA 40AAAA AA 40AAAB AA 50AAAA AA 50AAAB AA 60AAAA AA 60AAAB AA 70AAAA AA 70AAAB Data Address 55 405554 55 405555 55 505554 55 505555 55 605554 55 605555 55 705554 55 705555 Data Address 20 40AAAA 20 40AAAB 20 50AAAA 20 50AAAB 20 60AAAA 20 60AAAB 20 70AAAA 20 70AAAB Writes Enabled Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Write Bytes Note: 14 1. Load 6 bytes to corresponding Flash chip segment individually to disable software data protection. AT5FC008 AT5FC008 Ordering Information tACC (ns) Ordering Code Package 200 AT5FC008-20 PCMCIA Type 1 Operation Range Commercial (0°C to 70°C) Packaging Information PCMCIA, Type 1 PC Memory Card Dimensions in millimeters 85.6 0.2 mm 10.0 MIN. (mm) 54.0 0.1 mm 10.0 MIN. (mm) 3.3 0.1 mm 34 68 FRONT SIDE BACK SIDE 1 35 CardWare may be trademarks of others. 15