ATMEL U2739M-BFC

U2739M-B
DAB One-Chip Channel- and Source Decoder
Description
The U2739M-B is an integrated circuit in advanced
CMOS technology for demodulation and decoding of a
DAB signal according to ETS 300 401. The channel
decoder part includes the main features OFDM
demodulation & decoding and time & frequency synchronization algorithms, using the embedded OAK DSP core.
The source decoder consists of an audio and a data
decoder part. The audio source decoder supports
ISO MPEG 1,2 layer 2 and the data decoder offers
2 independent packet mode decoders.
Several standard interfaces, like I2C/L3, I2S, SPDIF or
RDI are implemented to offer a flexible utilization.
Moreover the U2739M-B includes a mechanism to
replace respectively extend certain software modules by
using a special boot mode (so-called USE). For example,
the time & frequency synchronization modules can be
replaced by down-loading the corresponding user
software algorithms to the OAK DSP core.
Electrostatic sensitive device.
Observe precautions for handling.
Block Diagram
RAM
U2739M–A
SLI, WAGC
I2S
Tuner
Channel
decoder
ADC
DAC
Audio
decoder
SPDIF
Data
decoder
ROM
MC
interface
MCU
RDI
interface
SFCO
V24/RS232
HSSO
RDI
Figure 1. Block diagram
Ordering Information
Extended Type Number
Package
Remarks
U2739M-BFT
T–PQFP–G100
Tray
U2739M-BFC
CQFP144
Tray
Rev. A1, 22-May-01
1 (69)
U2739M-B
Table of Contents
1
2
3
4
5
6
2 (69)
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Channel Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Audio Source Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Data Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Strap Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2
ADC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.1
ADC Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.2
ADC Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.3
ADC Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.4
ADC Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3
Tuner Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.1
Tuner Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.2
Tuner Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4
MC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.1
MC Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.2
MC Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.3
L3 Bus Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.4
L3 Bus Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.5
I2C Bus Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.6
I2C Bus Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5
C-Bus / BOOT Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.1
C-Bus Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.2
C-Bus / BOOT Bus Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.3
BOOT Bus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.4
BOOT Bus Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6
SRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.1
SRAM Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.2
SRAM Interface Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.3
SRAM Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.4
SRAM Interface Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7
VCXO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.1
VCXO Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.2
VCXO Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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5
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Rev. A1, 22-May-01
U2739M-B
Table of Contents (continued)
6.8
7
8
Audio Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8.1
I2S Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8.2
I2S Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8.3
I2S Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8.4
I2S Interface Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8.5
SP-DIF Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8.6
SP-DIF Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8.7
SP-DIF Interface Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8.8
SP-DIF Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9
RDI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9.1
RDI Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9.2
RDI Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9.3
RDI Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9.4
RDI Interface Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10
SFCO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.1
SFCO Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.2
SFCO Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.3
SFCO Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.4
Detailed SFCO Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10.5
SFCO Interface Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11
RS232 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11.1
RS232 Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11.2
RS232 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11.3
RS232 Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11.4
RS232 Interface Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12
HSSO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.1
HSSO Interface Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.2
HSSO Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.3
HSSO Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12.4
HSSO Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MC Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1
’Set System’ Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.1
Set DAB System Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.2
Set ASD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.3
Set DD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.4
Set DD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.5
Set CIF Counter and Occurrence Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.6
Set Current SBCHID Long Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.7
Set Next SBCHID Long Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.1.8
Set Current SBCHID Short Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. A1, 22-May-01
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3 (69)
U2739M-B
Table of Contents (continued)
8.2
9
4 (69)
’Set Configuration’ Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.1
Set Global Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.2
Set TS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.3
Set FS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.4
Set XO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.5
Set HSSO / RS232 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.6
Set WAGC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.7
Set RCC Slot Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2.8
Set RFU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3
’Read Status’ Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.1
Read Global Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.2
Read Synchronization Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3.3
Read CIR Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4
’Read Data’ Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.1
Read ASD Header Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.2
Read X–PAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.3
Read F–PAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.4
Read AIC Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.5
Read TII Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.6
Read EFC Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.7
Read FIC Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.8
Read RCC Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.9
Read Slot Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.10
Read RFU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Rev. A1, 22-May-01
U2739M-B
1
1.1
Features
General
D Support of mode I, II, III and IV acc. to ETS 300 401
D Time & frequency synchronization with a wide-range
parameter set
D Optional implementation of user-defined synchronization strategy by using USE boot mode
D Digital AGC with a wide gain control range
D Off-chip de-interleaver memory for full 1.8 Mbit/s
decoding data rate
D Time & frequency synchronization on DSP OAK core
D Support of TII decoding and corresponding RDI
insertion (set 2)
D Flexible software configuration:
set 1 – (temic kernel), set 2 – (user extension) concept
D Automatic mode detection (AMD)
1.3
D FIC on-chip memory, access via MC interface
D Supports MPEG1 layer II streams according to ISO/
IEC 11172/3
D Generation of receiver status information
D Generation of tuner control signals
D Generation of pulse width modulated VCXO control
signal
D Power supply 3.3 V, master clock 24.576 MHz
D Plastic TQFP100 package or
D Ceramic QFP144 package for software development
Audio Source Decoder
D Supports MPEG2 layer II (half sampling rate) streams
according to ISO/IEC 13818–3
D Supports all bit rates defined in the ETS 300 401
standard
D I2S and SPDIF output interfaces
D Programmable fader
D Programmable DRC
D PAD extraction
1.2
Channel Decoder
D Demodulation and decoding of up to 64 UEP/EEP
sub-channels
1.4
D Support of dynamic multiplex reconfiguration
(DMR) without mute state
D Flexible configuration via MC commands
Data Decoder
D 2 independent packet mode decoder
D Digital Null-Symbol detection (FSYNCH generation)
D Data group length limited to ~1 kbyte each
D Channel filtering (48 dB)
D Output via HSSO or V24
D Optional SAW filter equalization
D DD1 option: FIDC decoder
D Digital AFC (freq. tolerance < 0.5 Hz for mode I)
D Support of AIC decoding (set 2)
Rev. A1, 22-May-01
5 (69)
U2739M-B
1.5
Interfaces
D Source decoder output interface: I2S and SPDIF
D 10-bit ADC interface:
D Data decoder output interface: V24 or HSSO
– ADC sampling clock generation
D Channel decoder output interface: RDI and SFCO
– ADC binary or 2’s complement format selection
D Microcontroller interface:
– support of several intermediate frequencies
I2C/L3
D RDI:
D DSP OAK core bootstrap ROM interface
– Extended high capacity mode
– IEC 958 format
– RDI control channel (RCC)
D Voltage controlled reference oscillator (VCXO)
interface
D SFCO simple full capacity output:
– window-, serial sub-channel identifier (SbChId)-,
data-, error- and clock line
– 3.072 MHz burst mode interface
2
D Time de-interleaver SRAM (4 Mbit) interface
D High speed serial output HSSO (PAD, DD1, DD2,
CIR) interface, 3-line serial burst mode interface
Functional Block Diagram
SRAM
I2S
ADC
IQ splitting
filtering
Demodulation
AFC
AGC
Deinterleaving
Audio
source
decoding
Decodeing
DAC
SPDIF
FS_IN
SLI
TUNER
W_AGC
FSYNC
generation
PWM
FSYNC
dF
AMD
Time
synchro–
nization
TII decoding
(USE)
Frequency
synchro–
nization
Status
generation
PAD
extraction
Source decoder
Data
decoder 1
(FIDC)
Channel
decoder
V24/RS232
Data
decoder 2
(AIC (USE))
VCXO
tank
XO
UNIT
ROM
BOOT
UNIT
Data decoder
MC
interface
MC
RDI
controller
memory
MC interface
U2739M-B
RDI_TX
RDI_RX
RDI interface
SFCO
HSSO
MC
Figure 2. Functional block diagram
6 (69)
Rev. A1, 22-May-01
U2739M-B
3
Pin Description
QFP144
QFP100
1
1
Pin Name
Signal Description
Pad Type
Dir.
5 V Tol.
ADC_CLK
ADC sampling clock output 8.192 MHz
PDO04T
out
2
TIN0
Test input 0 (pull down)
PDDZ
in
x
3
TIN1
Test input 1 (pull down)
PDDZ
in
x
4
2
ADC_DATA9
ADC data input, bit 9 (MSB)
PDIZ
in
x
5
3
ADC_DATA8
ADC data input, bit 8
PDIZ
in
x
6
4
ADC_DATA7
ADC data input, bit 7
PDIZ
in
x
7
5
ADC_DATA6
ADC data input, bit 6
PDIZ
in
x
TIN2
Test input 2 (pull down)
PDDZ
in
x
8
DVSSE
Ground
PVSS1Z, PVSS2Z
gnd
x
10
9
6
ADC_DATA5
ADC data input, bit 5
PDIZ
in
x
11
7
ADC_DATA4
ADC data input, bit 4
PDIZ
in
x
12
8
ADC_DATA3
ADC data input, bit 3
PDIZ
in
x
13
9
ADC_DATA2
ADC data input, bit 2
PDIZ
in
x
TIN3
Test input 3 (pull down)
PDDZ
in
x
14
15
TIN4
Test input 4 (pull down)
PDDZ
in
x
16
10
ADC_DATA1
ADC data input, bit 1
PDIZ
in
x
17
11
ADC_DATA0
ADC data input, bit 0 (LSB)
PDIZ
in
x
18
12
DVSS1
Digital ground
PVSS1Z, PVSS2Z
gnd
x
19
13
AVSS1
Analog ground
PVSS3Z
gnd
x
20
14
XIN
Oscillator input
PDX02
osc
21
15
XOUT
Oscillator output
(PDX02)
osc
22
16
AVDD1
Analog power supply
PVDD3Z
pwr
/C_DR
C-bus data read enable
PRO04T
out
23
24
17
/RS
Low active reset
PDIZ
in
25
18
PWM
Pulse width modulated control output
PRO04T
out
/C_DW
C-bus data write enable
PRO04T
out
26
27
19
W_AGC
Window AGC
PRO04T
out
28
20
SLI
Synchronization lock indicator
PRO04T
out
/C_PR
C-bus program read enable
PRO04T
out
HSSO_WIN
HSSO window signal
PRO04T
out
/C_PW
C-bus program write enable
PRO04T
out
HSSO _CLK
HSSO clock signal
PRO04T
out
/ABORT
Low active ABORT signal (pull up)
PDUZ
in
29
30
21
31
32
22
33
34
23
HSSO _DAT
HSSO data signal
PRO04T
out
35
24
C_ADD0
C-bus address bit 0 (LSB)
PRO04T
out
36
25
C_ADD1
C-bus address bit 1
PRO04T
out
37
26
/BOOT_RE
BOOT read enable
PRO04T
out
38
27
C_ADD2
C-bus address bit 2
PRO04T
out
39
28
C_ADD3
C-bus address bit 3
PRO04T
out
40
29
C_ADD4
C-bus address bit 4
PRO04T
out
41
30
C_ADD5
C-bus address bit 5
PRO04T
out
42
31
C_ADD6
C-bus address bit 6
PRO04T
out
TOUT0
Test output bit 0
PRO02T
out
C_ADD7
C-bus address bit 7
PRO04T
out
43
44
32
Rev. A1, 22-May-01
x
x
7 (69)
U2739M-B
QFP144
QFP100
45
33
C_ADD8
C-bus address bit 8
PRO04T
out
46
34
C_ADD9
C-bus address bit 9
PRO04T
out
47
35
C_ADD10
C-bus address bit 10
PRO04T
out
48
36
C_ADD11
C-bus address bit 11
PRO04T
out
49
37
C_ADD12
C-bus address bit 12
PRO04T
out
50
38
DVDD1
Digital power supply
PVDD1Z, PVDD2Z
pwr
51
39
C_ADD13
C-bus address bit 13
PRO04T
out
C_ADD14
C-bus address bit 14
PRO04T
out
52
53
Pin Name
Signal Description
Pad Type
Dir.
5 V Tol.
x
C_ADD15
C-bus address bit 15
PRO04T
54
40
C_DATA0/DBG
C-bus data bit 0 (pull down)
PRD04TZ
inout
out
x
55
41
C_DATA1/BOOT
C-bus data bit 1 (pull down)
PRD04TZ
inout
x
56
C_DATA8
C-bus data bit 8 (pull down)
PRD04TZ
inout
x
57
C_DATA9
C-bus data bit 9 (pull down)
PRD04TZ
inout
x
58
42
DVSS2
Digital ground
PVSS1Z, PVSS2Z
gnd
x
59
43
C_DATA2/URST
C-bus data bit 2 (pull down)
PRD04TZ
inout
x
60
44
C_DATA3/XUSE
C-bus data bit 3 (pull down)
PRD04TZ
inout
x
61
C_DATA10
C-bus data bit 10 (pull down)
PRD04TZ
inout
x
62
C_DATA11
C-bus data bit 11 (pull down)
PRD04TZ
inout
x
63
45
C_DATA4/PSPC
C-bus data bit 4 (pull down)
PRD04TZ
inout
x
64
46
C_DATA5/RDI_VBIT
C-bus data bit 5 (pull down)
PRD04TZ
inout
x
65
C_DATA12
C-bus data bit 12 (pull down)
PRD04TZ
inout
x
66
C_DATA13
C-bus data bit 13 (pull down)
PRD04TZ
inout
x
67
47
C_DATA6/XO12
C-bus data bit 6 (pull down)
PRD04TZ
inout
x
68
48
C_DATA7/ADE
C-bus data bit 7 (pull down)
PRD04TZ
inout
x
C_DATA14
C-bus data bit 14 (pull down)
PRD04TZ
inout
x
69
70
C_DATA15
C-bus data bit 15 (pull down)
PRD04TZ
inout
x
71
49
TEST_MODE/BYPP
Test mode selection (pull down)
PDDZ
in
x
72
50
MCM_TRIGGER
MCM trigger signal
PRO04T
out
73
51
MC_MODE
Microcontroller mode signal
PDIZ
in
x
74
52
MC_CLK
Microcontroller clock signal
PDIZ
in
x
75
53
MC_DAT
Microcontroller data signal
PRB04TZ
inout
x
x
76
DVDDE
Digital power supply
PVDD1Z, PVDD2Z
pwr
77
54
SPDIF
SPDIF output
PRO04T
out
78
55
RS232
RS232 output
PRO04T
out
79
56
I2S_CLK
I2S clock output
PRO04T
out
80
57
I2S_DAT
I2S data output
PRO04T
out
TOUT1
Test output bit 1
PRO02T
out
I2S_WIN
I2S win output
PRO04T
out
TOUT2
Test output bit 2
PRO02T
out
out
81
82
58
83
84
59
TOUT3
Test output bit 3
PRO02T
85
60
RDI_RX
RDI receive data
PDIZ
in
86
61
RDI_TX
RDI transmit data
PRO04T
out
87
62
DVSS3
Digital ground
PVSS1Z, PVSS2Z
gnd
TOUT4
Test output bit 4
PRO02T
out
88
8 (69)
x
x
Rev. A1, 22-May-01
U2739M-B
QFP144
QFP100
89
Pin Name
Signal Description
Pad Type
Dir.
TOUT5
Test output bit 5
PRO02T
out
90
63
SFCO_SID
SFCO sub-channel ID
PRO04T
out
91
64
SFCO_ERR
SFCO errorflag
PRO04T
out
92
65
SFCO_DAT
SFCO data
PRO04T
out
TOUT6
Test output bit 6
PRO02T
out
93
94
66
SFCO_CLK
SFCO clock
PRO04T
out
95
67
SFCO_WIN
SFCO window
PRO04T
out
96
TOUT7
Test output bit 7
PRO02T
out
97
68
DVDD2
Digital power supply
PVDD1Z, PVDD2Z
pwr
98
69
TOUT8
Test output bit 8
PRO02T
out
99
5 V Tol.
x
TOUT9
Test output bit 9
PRO02T
out
100
70
SRAM_D7
SRAM data bit 7
PRB04TZ
inout
x
101
71
SRAM_D6
SRAM data bit 6
PRB04TZ
inout
x
TOUT10
Test output bit 10
PRO02T
out
102
103
72
SRAM_D5
SRAM data bit 5
PRB04TZ
inout
x
104
73
SRAM_D4
SRAM data bit 4
PRB04TZ
inout
x
105
TOUT11
Test output bit 11
PRO02T
out
106
74
SRAM_D3
SRAM data bit 3
PRB04TZ
inout
x
107
75
SRAM_D2
SRAM data bit 2
PRB04TZ
inout
x
TOUT12
Test output bit 12
PRO02T
out
108
109
76
SRAM_D1
SRAM data bit 1
PRB04TZ
inout
x
110
77
SRAM_D0
SRAM data bit 0
PRB04TZ
inout
x
x
TIN5
Test input 5 (pull down)
PDDZ
in
112
111
78
SRAM_WR
SRAM write signal
PRO04T
out
113
79
SRAM_OE
SRAM output enable
PRO04T
out
114
80
SRAM_A18
SRAM address bit 18
PRO04T
out
115
TIN6
Test input 6 (pull down)
PDDZ
in
116
81
SRAM_A17
SRAM address bit 17
PRO04T
out
117
82
SRAM_A16
SRAM address bit 16
PRO04T
out
TOUT13
Test output bit 13
PRO02T
out
118
x
119
83
SRAM_A15
SRAM address bit 15
PRO04T
out
120
84
SRAM_A14
SRAM address bit 14
PRO04T
out
121
85
DVSS4
Digital ground
PVSS1Z, PVSS2Z
gnd
x
TIN7
Test input 7 (pull down)
PDDZ
in
x
122
123
86
SRAM_A13
SRAM address bit 13
PRO04T
out
124
87
SRAM_A12
SRAM address bit 12
PRO04T
out
125
TOUT14
Test output bit 14
PRO02T
out
126
88
SRAM_A11
SRAM address bit 11
PRO04T
out
127
89
SRAM_A10
SRAM address bit 10
PRO04T
out
TOUT15
Test output bit 15
PRO02T
out
128
129
90
SRAM_A9
SRAM address bit 9
PRO04T
out
130
91
SRAM_A8
SRAM address bit 8
PRO04T
out
Rev. A1, 22-May-01
9 (69)
U2739M-B
QFP144
QFP100
131
Pin Name
Signal Description
Pad Type
Dir.
TOUT16
Test output bit 16
PRO02T
out
132
92
SRAM_A7
SRAM address bit 7
PRO04T
out
133
93
SRAM_A6
SRAM address bit 6
PRO04T
out
134
94
DVDD3
Digital power supply
PVDD1Z, PVDD2Z
pwr
TOUT17
Test output bit 17
PRO02T
out
135
136
95
SRAM_A5
SRAM address bit 5
PRO04T
out
137
96
SRAM_A4
SRAM address bit 4
PRO04T
out
TMUX0
Test mux in bit 0 (LSB) (pull down)
PDDZ
in
138
139
97
SRAM_A3
SRAM address bit 3
PRO04T
out
140
98
SRAM_A2
SRAM address bit 2
PRO04T
out
TMUX1
Test mix in bit 1 (pull down)
PDDZ
in
141
142
99
SRAM_A1
SRAM address bit 1
PRO04T
out
143
100
SRAM_A0
SRAM address bit 0
PRO04T
out
TMUX2
Test mux in bit 2 (pull down)
PDDZ
in
144
4
5 V Tol.
x
x
x
Strap Pins
QFP144
QFP100
16
10
ADC_DATA1
ADC data input, bit 1
PDIZ
in
Strap pin OCSEL 1
17
11
ADC_DATA0
ADC data input, bit 0
PDIZ
in
Strap pin OCSEL 0
54
40
C_DATA0/DBG
C-bus data bit 0
PRD04TZ
inout
Strap pin C_DATA0/DBG
55
41
C_DATA1/BOOT
C-bus data bit 1
PRD04TZ
inout
Strap pin C_DATA1/BOOT
59
43
C_DATA2/URST
C-bus data bit 2
PRD04TZ
inout
Strap pin C_DATA2/URST
60
44
C_DATA3/XUSE
C-bus data bit 3
PRD04TZ
inout
Strap pin C_DATA3/XUSE
63
45
C_DATA4/PSPC
C-bus data bit 4
PRD04TZ
inout
Strap pin C_DATA4/PSPC
64
46
C_DATA5/
RDI_VBIT
C-bus data bit 5
PRD04TZ
inout
Strap pin C_DATA5/RDI_VBIT
0 RDI spec.: validity bit 1
1 IEC958 spec.: validity bit 0
67
47
C_DATA6/XO12
C-bus data bit 6
PRD04TZ
inout
Strap pin C_DATA6/XO12
0 external oscillator 24.576 MHz
1 external oscillator 12.288 MHz
68
48
C_DATA7/ADE
C-bus data bit 7
ADC_DATA strap pin
function enable
PRD04TZ
inout
Strap pin C_DATA7/ADE
0 ADC_DATA strap pin function disabled
1 ADC_DATA strap pin function enabled
71
49
TEST_MODE/BYPP Test mode selection
PDDZ
in
Strap pin TEST_MODE/BYPP
0 PLL activated
1 PLL bypassed
73
51
MC_MODE
PDIZ
in
Strap pin I2C/L3
0 I2C
1 L3
10 (69)
Pin Name
Signal Description
Microcontroller mode
signal
Pad Type
Dir
Comment
Rev. A1, 22-May-01
U2739M-B
Pin Configuration
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
SRAM_A0
SRAM_A1
SRAM_A2
SRAM_A3
SRAM_A4
SRAM_A5
DVDD3
SRAM_A6
SRAM_A7
SRAM_A8
SRAM_A9
SRAM_A10
SRAM_A11
SRAM_A12
SRAM_A13
DVSS4
SRAM_A14
SRAM_A15
SRAM_A16
SRAM_A17
SRAM_A18
SRAM_OE
SRAM_WR
SRAM_D0
SRAM_D1
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
QFP100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SRAM_D2
SRAM_D3
SRAM_D4
SRAM_D5
SRAM_D6
SRAM_D7
TOUT8
DVDD2
SFCO_WIN
SFCO_CLK
SFCO_DAT
SFCO_ERR
SFCO_SID
DVSS3
RDI_TX
RDI_RX
TOUT3
I2S_WIN
I2S_DAT
I2S_CLK
RS232
SPDIF
MC_DAT
MC_CLK
MC_MODE
/BOOT_RE
C_ADD2
C_ADD3
C_ADD4
C_ADD5
C_ADD6
C_ADD7
C_ADD8
C_ADD9
C_ADD10
C_ADD11
C_ADD12
DVDD1
C_ADD13
C_DATA0
C_DATA1
DVSS2
C_DATA2
C_DATA3
C_DATA4
C_DATA5
C_DATA6
C_DATA7
TEST_MODE
MCM_TRIGGER
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
ADC_CLK
ADC_D9
ADC_D8
ADC_D7
ADC_D6
ADC_D5
ADC_D4
ADC_D3
ADC_D2
ADC_D1
ADC_D0
DVSS1
AVSS1
XOUT
XIN
AVDD1
/RS
PWM
W_AGC
SLI
HSSO_WIN
HSSO_CLK
HSSO_DAT
C_ADD0
C_ADD1
Figure 3. Production version QFP100
Rev. A1, 22-May-01
11 (69)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
/ABORT
HSSO_CLK
/C_PW
HSSO_WIN
/C_PR
SLI
W_AGC
/C_DW
PWM
/RS
/C_DR
AVDD1
XIN
XOUT
AVSS1
DVSS1
ADC_D0
ADC_D1
TIN4
TIN3
ADC_D2
ADC_D3
ADC_D4
ADC_D5
DVSSE
TIN2
ADC_D6
ADC_D7
ADC_D8
ADC_D9
TIN1
TIN0
ADC_CLK
TMUX2
143
SRAM_A0
39
142
SRAM_A1
40
141
TMUX1
41
140
SRAM_A2
C_ADD6
42
139
SRAM_A3
TOUT0
43
138
TMUX0
C_ADD7
44
137
SRAM_A4
C_ADD8
45
136
SRAM_A5
C_ADD9
46
135
TOUT17
C_ADD10
47
134
DVDD3
C_ADD11
48
133
SRAM_A6
C_ADD12
49
132
SRAM_A7
DVDD1
50
131 TOUT16
C_ADD13
51
130
C_ADD14
52
129
SRAM_A9
C_ADD15
53
128
TOUT15
C_DATA0
54
C_DATA1
55
C_DATA8
56
C_DATA9
DVSS2
CQFP 144
Figure 4. Software development version QFP144
144
SRAM_A8
127 SRAM_A10
126
SRAM_A11
125
TOUT14
57
124
SRAM_A12
58
123
SRAM_A13
122
TIN7
SRAM_D4
TOUT11
SRAM_D3
SRAM_D2
TOUT12
102
103
104
105
106
107
108
98
SRAM_D5
97
101
TOUT8
96
TOUT10
DVDD2
95
SRAM_D6
TOUT7
94
99
SFCO_WIN
93
100
SFCO_CLK
92
SRAM_D7
TOUT6
91
TOUT9
SFCO_DAT
90
SRAM_D1
SFCO_ERR
SRAM_D0
109
89
110
72
SFCO_SID
71
88
TEST_MODE
MCM_TRIGGER
TOUT5
TIN5
87
111
TOUT4
70
86
SRAM_WR
C_DATA15
DVSS3
112
85
69
RDI_TX
SRAM_OE
C_DATA14
84
C_DATA7
113
RDI_RX
SRAM_A18
68
83
114
TOUT3
67
82
TIN6
C_DATA6
TOUT2
115
81
66
I2S_WIN
SRAM_A17
C_DATA13
80
116
TOUT1
SRAM_A16
65
79
C_DATA5
C_DATA12
I2S_DAT
TOUT13
117
78
118
64
I2S_CLK
63
77
C_DATA4
RS232
SRAM_A15
76
119
SPDIF
62
75
SRAM_A14
C_DATA11
DVDDE
120
74
61
MC_DAT
121 DVSS4
C_DATA10
73
60
MC_CLK
59
C_DATA3
MC_MODE
Rev. A1, 22-May-01
C_DATA2
U2739M-B
33
HSSO_DAT
C_ADD5
34
C_ADD4
C_ADD0
C_ADD3
C_ADD1
38
35
37
C_ADD2
36
12 (69)
/BOOT_RE
1
2
141
C_ADD5
41
140
SRAM_A2
C_ADD6
42
139
SRAM_A3
43
138
C_ADD7
44
137
SRAM_A4
C_ADD8
45
136
SRAM_A5
C_ADD9
46
135
C_ADD10
47
134
DVDD3
C_ADD11
48
133
SRAM_A6
C_ADD12
49
132
SRAM_A7
DVDD1
50
131
C_ADD13
51
130
SRAM_A8
52
129
SRAM_A9
6
5
4
ADC_D7
ADC_D8
ADC_D9
12
11
10
ADC_D2
ADC_D3
ADC_D4
ADC_D5
21
20
19
18
17
16
AVDD1
XIN
XOUT
AVSS1
DVSS1
ADC_D0
ADC_D1
24
PWM
/RS
27
SLI
W_AGC
29
30
31
32
34
C_ADD1
C_ADD0
HSSO_DAT
HSSO_CLK
35
33
HSSO_WIN
28
26
25
23
22
15
14
13
9
8
ADC_D6
ADC_CLK
142
40
7
3
39
C_ADD4
CQFP 144
C_ADD3
36
125
56
SRAM_A1
38
124
SRAM_A12
58
123
SRAM_A13
C_DATA2
59
122
C_DATA3
60
121
DVSS4
61
120
SRAM_A14
62
119
SRAM_A15
C_DATA4
63
118
C_DATA5
64
117
SRAM_A16
65
116
SRAM_A17
66
115
C_DATA6
67
114
SRAM_A18
C_DATA7
68
113
SRAM_OE
69
112
SRAM_WR
70
111
106
107
108
SRAM_D2
SRAM_D4
103
104
TOUT8
SRAM_D7
SRAM_D6
97
98
100
101
SFCO_WIN
94
95
SFCO_ERR
SFCO_DAT
90
91
92
RDI_RX
RDI_TX
DVSS3
84
85
86
87
83
82
I2S_CLK
I2S_DAT
77
78
79
80
81
RS232
MC_CLK
MC_DAT
73
74
75
13 (69)
MC_MODE
76
SPDIF
I2S_WIN
TOUT3
88
89
SFCO_SID
93
SFCO_CLK
96
99
DVDD2
102
SRAM_D5
105
SRAM_D3
SRAM_D1
U2739M-B
57
DVSS2
Figure 5. Version QFP144 used as production version
55
SRAM_A0
143
37
C_ADD2
Rev. A1, 22-May-01
SRAM_A11
C_DATA1
SRAM_D0
72
SRAM_A10
126
54
109
71
128
53
110
TEST_MODE
MCM_TRIGGER
127
C_DATA0
144
/BOOT_RE
U2739M-B
6
Interface Description
6.1
Overview
The interface description explains the purpose, the
utilization and the meaning of every interface and every
signal. It is divided into twelve sections, which are related
to the different interfaces. An overview of all interfaces
is shown in the functional block diagram below. Several
standard output interfaces like I2S or SPDIF are used to
offer a flexible usage of the U2739M-B.
SRAM
I2S
IQ splitting
filtering
ADC
Demodulation
AFC
AGC
Deinterleaving
Audio
source
decoding
Decodeing
DAC
SPDIF
FS_IN
SLI
TUNER
W_AGC
FSYNC
generation
FSYNC
PWM
dF
AMD
Time
synchro–
nization
TII decoding
(USE)
Frequency
synchro–
nization
Status
generation
PAD
extraction
Source decoder
Data
decoder 1
(FIDC)
Channel
decoder
V24/RS232
Data
decoder 2
(AIC (USE))
VCXO
tank
XO
UNIT
ROM
BOOT
UNIT
Data decoder
MC
interface
MC
MC interface
U2739M-B
RDI_TX
RDI
controller
memory
RDI_RX
RDI interface
SFCO
HSSO
MC
Figure 6. Functional block diagram
6.2
ADC Interface
6.2.1
ADC Interface Signal Description
QFP144
QFP100
1
1
ADC_CLK
ADC sampling clock output 8.192 MHz
PDO04T
out
4
2
ADC_DATA9
ADC data input, bit 9 (MSB)
PDIZ
in
x
5
3
ADC_DATA8
ADC data input, bit 8
PDIZ
in
x
6
4
ADC_DATA7
ADC data input, bit 7
PDIZ
in
x
7
5
ADC_DATA6
ADC data input, bit 6
PDIZ
in
x
10
6
ADC_DATA5
ADC data input, bit 5
PDIZ
in
x
11
7
ADC_DATA4
ADC data input, bit 4
PDIZ
in
x
12
8
ADC_DATA3
ADC data input, bit 3
PDIZ
in
x
13
9
ADC_DATA2
ADC data input, bit 2
PDIZ
in
x
16
10
ADC_DATA1
ADC data input, bit 1
PDIZ
in
x
17
11
ADC_DATA0
ADC data input, bit 0 (LSB)
PDIZ
in
x
14 (69)
Pin Name
Signal Description
Pad Type
Dir.
5 V Tol.
Rev. A1, 22-May-01
U2739M-B
6.2.2
ADC Interface Description
The ADC interface as shown in figure 6 consists of the
ADC data input signal ADC_DATA(9:0) and the ADC
sampling clock output signal ADC_CLK. The
U2739M-B can be connected to every standard AD with
either binary or 2’s complement output format. The
sampling frequency is 8.192 MHz and a bandwidth of
2 MHz is necessary. The possible IF’s, which are
supported in conjunction with the IF input signal mode
(parameter IFM) are given by the formula.
fif = 2.048 MHz + n
4.096 MHz, with n = 0, 1, 2, 3 ....
Thus possible IFs are 2.048 MHz, 6.144 MHz, ...
38.912 MHz. The parameter IFM is defined by the
MC command ‘set global configuration’ [Atmel Wireless
& Microcontrollers U2739M documentation set –
“U2739M_MC_Command_set_vxxx.pdf”]. The analog
input bandwidth of the A/D converter must be chosen
accordingly. The ADC_DATA input is 10 bit wide. The
6.2.3
typical output delay (td3 in figure 7) of the AD converter
related to the falling edge of the sampling clock CLK8192
should be 20 ns. The generated 8.192 MHz output clock
take over the ADC_DATA with his rising edge of
ADC_CLK. The format ‘binary offset’ or ‘2’s
complement’ of the A/D converter can be selected by the
parameter ADCF. This parameter is also defined by the
‘set global configuration’ MC command [Atmel Wireless
& Microcontrollers U2739M documentation set –
“U2739M_MC_Command_set_vxxx.pdf”].
Furthermore, the sampling clock generation is performed
by the U2739M-B. The input data appearing at the
ADC_DATA port are assumed to be generated by an A/D
converter. The effective resolution of this converter
should be greater than 9 bit in order to use the full
dynamic range implemented in the U2739M-B. The
sampling clock required for the external A/D converter is
derived inside U2739M-B. It has to be 8.192 MHz.
ADC Interface Timing Diagram
tclk
tH
tL
XIN
td1
tc8
td1
tc8 H
tc8 L
ADC_CLK
ADC_D[9:0]
ts1
Figure 7. ADC interface timing diagram
6.2.4
ADC Interface Timing Parameters
Parameter
Symbol
Min.
Typ.
Max.
40.7
Unit
XIN clock period
tclk
XIN clock high
tH
15.0
20.35
25.0
ns
XIN clock low
tL
15.0
20.35
25.0
ns
ADC_CLK clock period
tc8
3 × 40.7
ns
ADC_CLK clock high
tc8H
1 × 40.7
ns
ADC_CLK clock low
tc8L
2 × 40.7
ns
Setup time ADC_D(9:0)
ts1
5.0
Output delay of ADC_CLK
td1
12.0
Rev. A1, 22-May-01
ns
ns
20.0
28.0
ns
15 (69)
U2739M-B
6.3
Tuner Interface
6.3.1
Tuner Interface Signal Description
QFP144
QFP100
Pin Name
27
19
W_AGC
28
20
SLI
6.3.2
Signal Description
Dir.
Window AGC
0 during COFDM symbols
1 during the NULL symbol
PRO04T
out
Synchronization lock indicator
0 receiver synchronization not locked
1 receiver synchronization locked
PRO04T
out
5 V Tol.
Tuner Interface Description
In order to implement a flexible AGC concept of a DAB
receiver the signals W_AGC and SLI can be used to
control the tuner IC U2731B. The influence of W_AGC
and SLI to the RF AGC voltage generation block is
described in the U2731B preliminary datasheet.
The WAGC signal must be controlled by the MC by using
6.4
Pad Type
the set WAGC configuration MC command. The WAGC
signal does not follow the moving FFT window. The
rising and falling edge can be adjusted by the MC. The
MC can use the differential dT, which correspond to the
FFT window shift, from the read synchronization status
command to adjust the WAGC rising and falling edge.
MC Interface
6.4.1
MC Interface Signal Description
QFP144
QFP100
72
50
MCM_TRIGGER
MCM trigger signal
PRO04T
out
73
51
MC_MODE
Microcontroller mode signal
0 I2C bus protocol
1 L3 bus protocol
PDIZ
in
x
74
52
MC_CLK
Microcontroller clock signal
PDIZ
in
x
75
53
MC_DAT
Microcontroller data signal
PRB04TZ
inout
x
6.4.2
Pin Name
Signal Description
Dir.
5 V Tol.
MC Interface Description
The MC interface is used for data transmission between
the U2739M-B (slave) and an external microcontroller
(master). It can be configured for L3- or I2C protocol
depending on the status of the MC_MODE line during
reset (/RS = LOW):
MC_MODE = HIGH
V
L3 bus selected
MC_MODE = LOW
V
I2C bus selected
The MCM_TRIGGER line indicates the status of the
internal interface controller.
16 (69)
Pad Type
The external MCU is able to communicate with the
U2739M-B during LOW phases of MCM_TRIGGER
only !
Further the MCM trigger signal indicates the synchronization status. If the MCM trigger has period of 8 ms,
then the U2739M-B is not locked. In the synchronized
(‘locked’) state the MCM trigger period correspond to the
CIF frame, which is provided every 24 ms. The complete
FIC is processed at the beginning of the transmission
frame.
Rev. A1, 22-May-01
U2739M-B
6.4.3
L3 Bus Interface Timing Diagram
1
Address mode
ts2
th2
MC_MODE
tLC
tHC
MC_CLK
MC_DAT
0
ts1
1
6
7
th1
2
Data mode
ts2
th2
MC_MODE
tLC
tHC
MC_CLK
MC_DAT
(MCU
0
U2739M)
ts
6
7
th1
MC_DAT
(U2739M
1
0
MCU)
1
6
7
td1
3
Halt mode
tL
MC_MODE
th2
ts2
MC_CLK
td3
td2
MC_DAT
(U2739M
high Z
MCU)
Figure 8. MC L3 bus interface timing diagram
Rev. A1, 22-May-01
17 (69)
U2739M-B
6.4.4
L3 Bus Timing Parameter
Parameter
Symbol
Min.
MC_CLK low phase
tLC
61
ns
MC_CLK high phase
tHC
61
ns
MC_DAT input setup time
ts1
61
ns
MC_DAT input hold time
th1
61
ns
MC_MODE hold time
th2
61
ns
MC_MODE setup time
ts2
61
ns
MC_CLK(h/l) / MC_DAT delay
td1
20
100
ns
MC_MODE(l/h) / MC_DAT (output driven)
td2
110
130
ns
MC_CLK(l/h) / MC_DAT(high Z)
td3
120
160
ns
6.4.5
Typ.
Max.
Unit
I2C Bus Interface Timing Diagram
tBF
thS
tsS
7
MC_DATA
tsD
tLC
thS
0
tsS
7
0
thD
tHC
MC_CLK
S
p
r
S
t
S
t
S
p
Figure 9. MC I2C bus timing diagram
6.4.6
I2C Bus Timing Parameter
Parameter
Symbol
Min.
Bus free time between STOP and START
condition
tBF
400
ns
Hold time (repeated) START condition
thS
200
ns
Setup time data
tsD
120
ns
Hold time data
thD
320
ns
Low period clock
tLC
300
ns
High period clock
tHC
200
ns
Setup time:
repeated START condition, STOP condition
tsS
240
ns
18 (69)
Typ.
Max.
Unit
Rev. A1, 22-May-01
U2739M-B
6.5
C-Bus / BOOT Bus Interface
6.5.1
QFP144
C-Bus Signal Description
QFP100
Pin Name
Signal Description
Pad Type
Dir.
23
/C_DR
C-bus data read enable
PRO04T
out
26
/C_DW
C-bus data write enable
PRO04T
out
29
/C_PR
C-bus program read enable
PRO04T
out
31
/C_PW
C-bus program write enable
PRO04T
out
35
24
C_ADD0
C-bus address bit 0 (LSB)
PRO04T
out
36
25
C_ADD1
C-bus address bit 1
PRO04T
out
37
26
/BOOT_RE
BOOT read enable
PRO04T
out
38
27
C_ADD2
C-bus address bit 2
PRO04T
out
39
28
C_ADD3
C-bus address bit 3
PRO04T
out
40
29
C_ADD4
C-bus address bit 4
PRO04T
out
41
30
C_ADD5
C-bus address bit 5
PRO04T
out
42
31
C_ADD6
C-bus address bit 6
PRO04T
out
44
32
C_ADD7
C-bus address bit 7
PRO04T
out
45
33
C_ADD8
C-bus address bit 8
PRO04T
out
46
34
C_ADD9
C-bus address bit 9
PRO04T
out
47
35
C_ADD10
C-bus address bit 10
PRO04T
out
48
36
C_ADD11
C-bus address bit 11
PRO04T
out
49
37
C_ADD12
C-bus address bit 12
PRO04T
out
51
39
C_ADD13
C-bus address bit 13
PRO04T
out
52
C_ADD14
C-bus address bit 14
PRO04T
out
53
C_ADD15
C-bus address bit 15
PRO04T
out
5 V Tol.
54
40
C_DATA0/DBG
C-bus data bit 0 (pull down)
PRD04TZ
inout
x
55
41
C_DATA1/BOOT
C-bus data bit 1 (pull down)
PRD04TZ
inout
x
56
C_DATA8
C-bus data bit 8 (pull down)
PRD04TZ
inout
x
57
C_DATA9
C-bus data bit 9 (pull down)
PRD04TZ
inout
x
59
43
C_DATA2/URST
C-bus data bit 2 (pull down)
PRD04TZ
inout
x
60
44
C_DATA3/XUSE
C-bus data bit 3 (pull down)
PRD04TZ
inout
x
61
C_DATA10
C-bus data bit 10 (pull down)
PRD04TZ
inout
x
62
C_DATA11
C-bus data bit 11 (pull down)
PRD04TZ
inout
x
63
45
C_DATA4/PSPC
C-bus data bit 4 (pull down)
PRD04TZ
inout
x
64
46
C_DATA5/RDI_VBIT
C-bus data bit 5 (pull down)
PRD04TZ
inout
x
65
C_DATA12
C-bus data bit 12 (pull down)
PRD04TZ
inout
x
66
C_DATA13
C-bus data bit 13 (pull down)
PRD04TZ
inout
x
67
47
C_DATA6/XO12
C-bus data bit 6 (pull down)
PRD04TZ
inout
x
68
48
C_DATA7/BYPP
C-bus data bit 7 (pull down)
PRD04TZ
inout
x
69
C_DATA14
C-bus data bit 14 (pull down)
PRD04TZ
inout
x
70
C_DATA15
C–-bus data bit 15 (pull down)
PRD04TZ
inout
x
Rev. A1, 22-May-01
19 (69)
U2739M-B
6.5.2
C-Bus / BOOT Bus Interface Description
The C-Bus is a multiplexed program as well as data bus
system to communicate with external components. The
complete bus system is available only in the QFP144
package version and needed for debugging the internal
OAK DSP core.
Atmel Wireless & Microcontrollers firmware. The
BOOT bus is a standard ROM interface (address/ data
buses, read enable line) and the read access is always with
16 wait states (referring the OAK internal 49.152 MHz
clock) to support slow devices.
The BOOT bus covers a subset of the C-Bus signals. The
user is able to download his own so-called ’User Software
Extensions’ using this bus system to replace or extend the
The BOOT bus is available in both package versions. The
timing diagram refers to the BOOT bus signals only.
6.5.3
BOOT Bus Timing Diagram
/BOOT_RE
C_ADD (13..0)
valid address
C_DATA (7..0)
valid address
valid data
valid data
tacc
Figure 10. C-bus interface timing diagram
6.5.4
BOOT Bus Timing Parameter
Parameter
BOOT ROM access time
20 (69)
Symbol
tacc
Min.
Typ.
Max.
Unit
120
ns
Rev. A1, 22-May-01
U2739M-B
6.6
SRAM Interface
6.6.1
SRAM Interface Signal Description
QFP144
QFP100
Dir.
5 V Tol.
100
70
SRAM_D7
SRAM data bit 7
PRB04TZ
inout
x
101
71
SRAM_D6
SRAM data bit 6
PRB04TZ
inout
x
103
72
SRAM_D5
SRAM data bit 5
PRB04TZ
inout
x
104
73
SRAM_D4
SRAM data bit 4
PRB04TZ
inout
x
106
74
SRAM_D3
SRAM data bit 3
PRB04TZ
inout
x
107
75
SRAM_D2
SRAM data bit 2
PRB04TZ
inout
x
109
76
SRAM_D1
SRAM data bit 1
PRB04TZ
inout
x
110
77
SRAM_D0
SRAM data bit 0
PRB04TZ
inout
x
112
78
SRAM_WR
SRAM write signal
PRO04T
out
113
79
SRAM_OE
SRAM output enable
PRO04T
out
114
80
SRAM_A18
SRAM address bit 18
PRO04T
out
116
81
SRAM_A17
SRAM address bit 17
PRO04T
out
117
82
SRAM_A16
SRAM address bit 16
PRO04T
out
119
83
SRAM_A15
SRAM address bit 15
PRO04T
out
120
84
SRAM_A14
SRAM address bit 14
PRO04T
out
123
86
SRAM_A13
SRAM address bit 13
PRO04T
out
124
87
SRAM_A12
SRAM address bit 12
PRO04T
out
126
88
SRAM_A11
SRAM address bit 11
PRO04T
out
127
89
SRAM_A10
SRAM address bit 10
PRO04T
out
129
90
SRAM_A9
SRAM address bit 9
PRO04T
out
130
91
SRAM_A8
SRAM address bit 8
PRO04T
out
132
92
SRAM_A7
SRAM address bit 7
PRO04T
out
133
93
SRAM_A6
SRAM address bit 6
PRO04T
out
136
95
SRAM_A5
SRAM address bit 5
PRO04T
out
137
96
SRAM_A4
SRAM address bit 4
PRO04T
out
139
97
SRAM_A3
SRAM address bit 3
PRO04T
out
140
98
SRAM_A2
SRAM address bit 2
PRO04T
out
142
99
SRAM_A1
SRAM address bit 1
PRO04T
out
143
100
SRAM_A0
SRAM address bit 0
PRO04T
out
6.6.2
Pin Name
Signal Description
Pad Type
SRAM Interface Descriptions
For time de-interleaving and further task an external
static random access memory of 4 MB is necessary. The
organization of the SRAM is 512 k × 8 bit.
Rev. A1, 22-May-01
Due to the high data rates a fast SRAM with a access time
of 18 ns or below is necessary.
21 (69)
U2739M-B
6.6.3
SRAM Interface Timing Diagram
READ CYCLE
XIN
td1
tavav
SRAM_A(18:0)
valid address
td2
SRAM_WR
SRAM_OE
td3
HIGH–Z
SRAM_D(7:0)
data valid
tsdata
WRITE CYCLE
XIN
tavav
td1
SRAM_A(18:0)
valid address
td2
SRAM_WR
twleh
td3
SRAM_OE
SRAM_D(7:0)
data valid
tddata
tdvwh
Figure 11. SRAM interface timing diagram
22 (69)
Rev. A1, 22-May-01
U2739M-B
6.6.4
SRAM Interface Timing Parameter
Parameter
Symbol
Read/ write cycle time
Min.
tavav
Typ.
Max.
Unit
40.7
ns
Output delay SRAM_A(18:0)
td1
15.0
25.0
35.0
ns
Output delay SRAM_WR
td2
12.0
20.0
28.0
ns
Output delay SRAM_OE
td3
16.0
24.0
32.0
ns
Setup time SRAM_D(7:0)
tsdata
2.0
Write pulse with
twleh
33.0
40.7
48.0
ns
Output delay SRAM_D(7:0)
tddata
15.0
23.0
31.0
ns
Data valid to end of write
tdvwh
33.0
40.7
48.0
ns
6.7
ns
VCXO Interface
6.7.1
VCXO Interface Signal Description
QFP144
QFP100
19
13
AVSS1
Analog ground
20
14
XIN
21
15
22
25
6.7.2
Pin Name
Signal Description
Pad Type
Dir.
5 V Tol.
PVSS3Z
gnd
x
Oscillator input
PDX02
osc
XOUT
Oscillator output
(PDX02)
osc
16
AVDD1
Analog power supply
PVDD3Z
pwr
18
PWM
Pulse width modulated control output
PRO04T
out
VCXO Interface Description
U2739M-B
PLL
49.192 MHz
PWM
PAD
XIN
PAD
XOUT
PAD
VCXO 24.576 MHz
fPWM = fclk2457 / 2n
n = 11 –> fPWM = 12 kHz
Figure 12. VCXO application circuit
The U2739M-B master clock should be derived from a voltage-controlled reference oscillator. The pulse width modulated output signal PWM of the U2739M-B can be used to control the VCXO frequency of 24.576 MHz.
Rev. A1, 22-May-01
23 (69)
U2739M-B
6.8
Audio Interfaces
6.8.1
I2S Interface Signal Description
QFP144
QFP100
79
56
I2S_CLK
I2S clock line
PRO04T
out
80
57
I2S_DAT
I2S data line
PRO04T
out
82
58
I2S_WIN
I2S window line
PRO04T
out
6.8.2
Pin Name
Signal Description
Dir.
5 V Tol.
I2S Interface Description
The I2S interface is a standard continuous audio interface
consisting of bit clock (_CLK), word select (_WIN) and
data (_DAT) lines. The word select line indicates the
transmitted channel: LOW for left, HIGH for right. Please
be aware of the 1 cycle delay of the data word MSB
corresponding to the I2S_WIN edge !
6.8.3
Pad Type
As in the DAB system the I2S_WIN clock is fixed as
48 kHz (MPEG1) or 24 kHz (MPEG2) the bit clock
depends on the data word length. The standard word
length is 16 bit, hence the bit clock is fixed at 1.536 MHz
resp. 768 kHz.
I2S Interface Timing Diagram
tclk
tH
tL
I2S_CLK
I2S_WIN
td1
I2S_DAT
0
15
14
13
12
3
2
1
0
15
14
13
12
3
2
1
0
15
14
13
12
td2
left sample
right sample
Figure 13. I2S interface timing diagram
6.8.4
I2S Interface Timing Parameter
Parameter
Symbol
Min.
Typ.
Max.
Unit
I2S clock period
tclk
16.28
us
I2S clock high
tH
14.28
us
I2S clock low
tL
14.28
us
I2S_WIN output delay
td1
–5.0
0.0
5.0
ns
I2S_DAT output delay
td2
–5.0
0.0
5.0
ns
6.8.5
SP-DIF Interface Signal Description
QFP144
QFP100
77
54
24 (69)
Pin Name
SPDIF
Signal Description
SPDIF output
Pad Type
PRO04T
Dir.
5 V Tol.
out
Rev. A1, 22-May-01
U2739M-B
6.8.6
SP-DIF Interface Description
The SP-DIF format is frame based, which means one
frame represents one audio sampling period. Every frame
comprises 2 subframes a 32 bit referring to the left and
right sample. The data is transmitted in bi-phase coded
format. The frame synchronization pattern are based on
biphase violations and indicate whether a left or right
subframe follows.
The last 4 bi-phase coded bits of each subframe represent
the V (validity flag), U (user channel data), C (channel
status data) and P (parity) information as described in the
SP-DIF specification.
6.8.8
Complete frames (left and right sample according to
64
2 bit due to bi-phase coding) are transmitted at the
audio sampling rate (48 resp. 24 kHz).
6.8.7
SP-DIF Interface Timing
Parameter
The SP-DIF interface was designed according the digital
audio interface IEC958 specification [CEI/ISO 958
Digital Audio Interface Standard].
SP-DIF Interface Timing Diagram
SPDIF
S3
S2
S1
A0
Frame sync. pattern
8 Zero’s (bi–phase coded)
A1
A2
A14
A15
V
Audio data bits (bi–phase coded)
U
C
P
Flag bits (bi–phase coded)
SP–DIF subframe (left or right audio sample)
Figure 14. SP-DIF interface timing diagram
6.9
RDI Interface
6.9.1
RDI Interface Signal Description
QFP144
QFP100
64
46
C_DATA5/RDI_VBIT
C–bus data bit 5 (pull down)
PRD04TZ
85
60
RDI_RX
RDI receive data
86
61
RDI_TX
RDI transmit data
6.9.2
Pin Name
Signal Description
Dir.
5 V Tol.
inout
x
PDIZ
in
x
PRO04T
out
RDI Interface Description
The RDI interface is designed according to the ‘Digital
Audio Broadcasting System: Specification of the
Receiver Data Interface (RDI)’ [Digital Audio
Broadcasting System: Specification of the Receiver Data
Interface (RDI), Issue 1.4]. The RDI frames are
embedded into the IEC 958 interface. The RDI output
6.9.3
Pad Type
data is provided in the extended format of the high
capacity mode. Further the RDI Control Channel (RCC)
can be implemented according to the preliminary specification [Digital Audio Broadcasting System: Preliminary
Specification of the RDI Control Channel], [Proposal of
DAB Command Set for Receiver (DCSR)].
RDI Interface Timing Diagram
tH
tL
2 * tH
2 * tL
3 * tH
3 * tL
RDI_TX/RX
Figure 15. RDI interface timing diagram
Rev. A1, 22-May-01
25 (69)
U2739M-B
6.9.4
RDI Interface Timing Parameter
The RDI interface is realized according to the digital audio interface IEC958 specification [CEI/ISO 958 Digital Audio
Interface Standard].
Parameter
Symbol
Min.
Typ.
Max.
Unit
Data high period
TH
160
ns
Data low period
TL
160
ns
6.10 SFCO Interface
6.10.1
SFCO Interface Signal Description
QFP144
QFP100
90
63
SFCO_SID
SFCO sub-channel ID
PRO04T
out
91
64
SFCO_ERR
SFCO error flag
PRO04T
out
92
65
SFCO_DAT
SFCO data
PRO04T
out
94
66
SFCO_CLK
SFCO clock
PRO04T
out
95
67
SFCO_WIN
SFCO window
PRO04T
out
6.10.2
Pin Name
Signal Description
Dir.
5 V Tol.
SFCO Interface Description
The simple full capacity output interface (SFCO) is a
3.072 MHz burst mode interface. It consists of a window,
data, errorflag and clock line. Furthermore, a serial subchannel identifier information is provided. The interface
carries fast information channel (FIC) and main service
information (MSC) at the output of the COFDM channel
26 (69)
Pad Type
decoder. The window line can be used to distinguish
between FIC and MSC data. Via the MC interface the
provided sub-channel can be selected. Only these
selected sub-channels are processed by the channel
decoder.
Rev. A1, 22-May-01
U2739M-B
6.10.3
SFCO Interface Timing Diagram
2 * 32 * clk
FIC
48*clk
32*clk
SFCO_win
32 * clk
3 * 32 * clk
16*clk
20*clk
80*clk
12*clk
16 *clk
SFCO_clk
FIB1
1
SFCO_data
FIB1
12
FIB1
CRC
FIB2
1
FIBn
12
FIBn
CRC
0
SFCO_SubChId
SFCO_ErrFl
MSC
32*clk
1*clk
SFCO_win
32*clk
22*clk
10 *clk
SFCO_clk
MSC
1
SFCO_data
MSC
n–1
MSC
n
6*clk
SFCO_SubChId
ID
SFCO_ErrFl
Figure 16. SFCO interface timing diagram
Rev. A1, 22-May-01
27 (69)
U2739M-B
6.10.4
Detailed SFCO Interface Timing Diagram
FIC
td1
td2
SFCO_win
tHC
tLC
SFCO_clk
SFCO_data
0
ts
1
n
th
0
SFCO_SubChId
SFCO_ErrFl
MSC
tHW
th
SFCO_win
tHC
tLC
SFCO_clk
SFCO_data
0
ts
SFCO_SubChId
1
6
5
0
n
th
6
SFCO_ErrFl
Figure 17. Detailed SFCO interface timing diagram
28 (69)
Rev. A1, 22-May-01
U2739M-B
6.10.5
SFCO Interface Timing Parameter
Parameter
Symbol
Min.
Typ.
Max.
Unit
Clock high period
tHC
160
ns
Clock low period
tLC
160
ns
Data setup time
ts
160
ns
Data hold time
th
160
ns
tHW
10.56
us
Delay data valid
td1
10.24
us
Delay window FIC low
td2
10.24
us
Window MSC high period
6.11 RS232 Interface
6.11.1
RS232 Interface Signal Description
QFP144
QFP100
78
55
6.11.2
Pin Name
Signal Description
RS232
Pad Type
RS232 output
PRO04T
out
RS232-ID
(Burst Identifier)
bit
D Data decoder 2
D Programme Associated Data (PAD)
Each RS232 burst consists of a header word followed by
n data words (as indicated in the header):
D Data decoder 1
Length
(Number of Transmitted Data Words n Without Header Word)
15
14
13
12
DD1
0
0
0
1
Number of DD1 words
DD2
0
0
1
0
Number of DD2 words
PAD
0
0
1
1
Number of PAD words
11
10
9
The RS232 output can be configured using the ’set HSSO/
RS232 configuration’ MC command [Atmel Wireless &
Microcontrollers U2739M documentation set –
“U2739M_MC_Command_set_vxxx.pdf”]. Using this
command the user can select the application to be given
RS232
5 V Tol.
RS232 Interface Description
The RS232 interface is an standard serial output used for
transferring data directly to a PC COM port. One of 3
applications can be given out:
6.11.3
Dir.
8
7
6
5
4
3
2
1
0
out and the baud rate.
Please notice the byte order: first the high byte is transmitted followed by the low byte (LSB first both).
RS232 Interface Timing Diagram
8
9
10
14
15
0
1
2
6
7
8
9
10
11
12
Figure 18. RS232 interface timing diagram
6.11.4
RS232 Interface Timing Parameter
The RS232 timing is related to the defined baud rate of the interface.
Rev. A1, 22-May-01
29 (69)
U2739M-B
6.12 HSSO Interface
6.12.1
HSSO Interface Signal Description
QFP144
QFP100
30
21
HSSO_WIN
HSSO window signal
PRO04T
out
32
22
HSSO _CLK
HSSO clock signal
PRO04T
out
34
23
HSSO _DAT
HSSO data signal
PRO04T
out
6.12.2
Pin Name
Signal Description
Pad Type
5 V Tol.
HSSO Interface Description
The High Speed Serial Output (HSSO) is a standard 3-line
output interface implemented to give out data bursts in a
multiplexed way. Up to 4 applications can be given out
simultaneously:
D Channel Impulse Response (CIR)
D Data decoder 1
HSSO-ID
(Burst Identifier)
bit
D Data decoder 2
D Programme Associated Data (PAD)
The HSSO can be configured using the ’set HSSO / RS232
configuration’ MC command (see section 8). Each HSSO
burst consists of a header word followed by n data words
(as indicated in the header).
Length
(Number of Transmitted Data Words n Without Header Word)
15
14
13
12
CIR
0
0
0
0
Number of CIR words
DD1
0
0
0
1
Number of DD1 words
DD2
0
0
1
0
Number of DD2 words
PAD
0
0
1
1
Number of PAD words
6.12.3
Dir.
11
10
9
8
7
6
5
4
3
2
1
0
HSSO Interface Timing Diagram
tclk
tH
tL
HSSO_CLK
HSSO_WIN
td1
HSSO_DAT
15
14
13
1
0
15
14
13
1
0
15
0
15
14
1
0
td2
header
Data 0
Data n–1
Figure 19. HSSO interface timing diagram
6.12.4
HSSO Interface Timing Parameters
Parameter
Symbol
Min.
Typ.
Max.
Unit
HSSO clock period
tclk
4.07
us
HSSO clock high
tH
2.035
us
HSSO clock low
tL
2.035
us
HSSO_WIN output delay
td1
–5.0
0.0
5.0
ns
HSSO_DAT output delay
td2
–5.0
0.0
5.0
ns
30 (69)
Rev. A1, 22-May-01
U2739M-B
7
7.1
Electrical Characteristics
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Unit
VDD
–0.5
VDD + 0.5
V
Input / output voltage
Vin/Vout
–0.5
VDD + 0.5
V
Storage temperature
Tstg
–65
125
°C
Supply voltage
7.2
Operating Range
Parameter
Symbol
Min.
Typ.
Max.
Unit
VDD
3.0
3.3
3.6
V
Input / output voltage
Vin/Vout
0
VDD
V
Ambient temperature
Tamb
–40
+85
°C
Power dissipation
Pstat
20
mW
Power dissipation
Pdyn
860
mW
Supply voltage
7.3
DC Characteristics
Parameter
Test Conditions
Pad Type
Input HIGH voltage
VIH
Input LOW voltage
VIL
Threshold
VT
Output HIGH voltage
IOH= –2 mA
VOH
IOH= –4 mA
Output LOW voltage
IOL= 2 mA
IOL= 4 mA
Rev. A1, 22-May-01
VOL
Symbol
Min.
Typ.
Max.
2.0
Unit
V
0.8
1.4
V
V
Pxx02x
2.4
VDD
V
Pxx04x
2.4
VDD
V
Pxx02x
0.2
0.4
V
Pxx04x
0.2
0.4
V
31 (69)
U2739M-B
8
MC Command Set
8.1
’Set System’ Commands
8.1.1
Set DAB System Mode
Command Settings Overview:
D Set system mode
D Set FSLI control loops
Command
sequence:
Address Mode
7
0
6
5
4
1
1
0
DAB
3
2
1
1
U2739M-B
1
0
1
0
Write Command
$6E
Data Mode
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
$00
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
0
DAB
U2739M-B
Write Command
$6C
Data Mode
7
6
SMODE
5
4
3
2
1
0
NSM
0
0
0
0
0
$XX
Command Parameters:
Parameter
Meaning
Description
SMODE(1..0)
New DAB system mode
00:
01:
10:
11:
DAB system mode 4
DAB system mode 1
DAB system mode 2
DAB system mode 3
NSM
New system mode valid
0:
1:
SMODE not valid
SMODE indicates new system mode
32 (69)
Rev. A1, 22-May-01
U2739M-B
8.1.2
Set ASD
Command Settings Overview:
D Set ASD on/off
D Set ASD dynamic range control fixed value
D Set ASD mute state
D Set ASD ScF–CRC on/off
D Set ASD sub–channel ID
D Set ASD dual channel configuration
D Set ASD dynamic range control on/off
D Set ASD fader value
Command
sequence:
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
1
0
DAB
U2739M-B
Write Command
$6E
Data Mode
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
0
$10
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
0
DAB
U2739M-B
Write Command
$6C
Data Mode
Rev. A1, 22-May-01
7
6
5
4
3
2
ASDE
MUTE
IDV
DCCV
FADV
DRCON
1
0
DRCFIX SCFON
$XX
FADD
SBCHID
$XX
DCC
DRCFV
$XX
33 (69)
U2739M-B
Command Parameters:
Parameter
Meaning
Description
ASDE
ASD enable
0:
1:
ASD disabled
ASD enabled
MUTE
ASD mute state
0:
1:
ASD output active
ASD output muted
IDV
ASD SBCHID valid
0:
1:
Last set ASD SBCHID remains valid
Following ASD SBCHID valid
DCCV
DCC setting valid
0:
1:
Last set DCC remains valid
Following DCC valid
FADV
Fader setting valid
0:
1:
Last set FAD remains valid
Following FAD valid
DRCON
DRC on/off switch
0:
1:
DRC off
DRC on
DRCFIX
DRC additional fixed gain 0:
value valid
1:
DRC additional fixed gain + 6 dB (default)
DRC additional fixed gain according to DRCFV
SCFON
ScF–CRC on/off switch
0:
1:
ScF–CRC off
ScF–CRC on
FAD
Fader value
00:
01:
10:
11:
Fade In / Fade out over 0 frames each
Fade In / Fade out over 30 frames each
Fade In / Fade out over 60 frames each
Fade In / Fade out over 90 frames each
SBCHID(5..0)
Sub–channel identifier
n:
ASD sub–channel ID
DCC(1..0)
Dual channel
configuration
00/10: Left channel on both ASD output channels
01:
Right channel on both ASD output channels
11:
Both channels on ASD output
DRCFV(5..0)
DRC additional fixed gain 000000:
Fixed gain 0 dB
value
000001:
Fixed gain + 0.25 dB
... (continuous steps of +0.25 dB)
111111:
fixed gain + 15.75 dB
34 (69)
Rev. A1, 22-May-01
U2739M-B
8.1.3
Set DD1
DD configuration for transmission in packet mode
Command Settings Overview:
D Set DD1 on/off
D Set DD1 sub–channel ID
D Set DD1 packet address
Command
sequence:
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
1
0
DAB
U2739M-B
Write Command
$6E
Data Mode
7
6
5
4
3
2
1
0
0
0
0
1
0
0
0
1
$11
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
0
DAB
U2739M-B
Write Command
$6C
Data Mode
7
6
5
4
DD1E
FIDC
PA1V
ID1V
3
2
1
0
0
PA(9/8)
PA(7..0)
0
$XX
$XX
SBCHID
$XX
Command Parameters:
Parameter
Meaning
Description
DD1E
DD1 enable
0:
1:
DD1 disabled
DD1 enabled
FIDC
FIDC decoding switch
0:
1:
DD1 decodes MSC
DD1 decodes FIDC 1)
PA1V
PA valid
0:
1:
Last set DD1 PA remains valid
Following DD1 PA valid
ID1V
DD1 SBCHID valid
0:
1:
Last set DD1 SBCHID remains valid
Following DD1 SBCHID valid
PA(9..0)
Packet address
n:
DD1 packet address
SBCHID(5..0)
Sub–channel identifier
n:
DD1 sub–channel ID
1)
in this case PA and SBCHID parameters are ignored (regardless of whether PA1V/ID1V have been set or not)
Rev. A1, 22-May-01
35 (69)
U2739M-B
8.1.4
Set DD2
DD configuration for transmission in packet mode
Command Settings Overview:
D Set DD2 on/off
D Set DD2 sub–channel ID
D Set DD2 AIC on/off
D Set DD2 packet address
Command
sequence:
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
1
0
DAB
U2739M-B
Write Command
$6E
Data Mode
7
6
5
4
3
2
1
0
0
0
0
1
0
0
1
0
$12
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
0
DAB
U2739M-B
Write Command
$6C
Data Mode
7
6
5
4
DD2E
AIC
PA2V
ID2V
3
2
1
0
0
PA(9/8)
PA(7..0)
0
$0X
$XX
SBCHID
$XX
Command Parameters:
Parameter
Meaning
Description
DD2E
DD2 enable
0:
1:
DD2 disabled
DD2 enabled
AIC
AIC decoding switch
0:
1:
DD2 decodes MSC
DD2 decodes AIC 2)
PA2V
DD2 PA valid
0:
1:
Last set DD2 PA remains valid
Following DD2 PA valid
ID2V
DD2 SBCHID valid
0:
1:
Last set DD2 SBCHID remains valid
Following DD2 SBCHID valid
PA(9..0)
Packet address
n:
DD2 packet address
SBCHID(5..0)
Sub–channel identifier
n:
DD2 sub–channel ID
1)
in this case PA and SBCHID parameters are ignored (regardless of whether PA2V/ID2V have been set or not)
and the default values for AIC decoding (PA = 1023, SBCHID = 63) are used instead
36 (69)
Rev. A1, 22-May-01
U2739M-B
8.1.5
Set CIF Counter and Occurrence Change
Command Settings Overview:
D Set channel decoder CIF counter
D Set channel decoder occurrence change
Command
sequence:
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
1
0
DAB
U2739M-B
Write Command
$6E
Data Mode
7
6
5
4
3
2
1
0
0
0
0
1
0
0
1
1
3
2
1
0
1
1
0
0
$13
Address Mode
7
0
6
5
4
1
1
0
DAB
U2739M-B
Write Command
$6C
Data Mode
7
6
5
CF
4
3
AF
2
1
0
CIFCH(4..0)
$XX
CIFCL(7..0)
$XX
OC(7..0)
$XX
Command Parameters:
Parameter
Meaning
Description
CF(1..0)
Change flags
00:
01:
10:
11:
No change
Sub–channel organization change
Service organization change
Sub–channel & service organization change
AF
Alarm flag
0:
1:
Alarm messages not accessible
Alarm messages accessible
CIFCH(4..0)
CIF counter (higher part)
n:
CIF counter higher part (modulo 20)
CIFCL(7..0)
CIF counter (lower part)
n:
CIF counter lower part (modulo 250)
OC(7..0)
Occurrence change
n:
Value for CIFCL, from which the new
configuration is valid
Rev. A1, 22-May-01
37 (69)
U2739M-B
8.1.6
Set Current SBCHID Long Form
Command Settings Overview:
D Set current sub–channel parameters (long form)
Command
sequence:
Address Mode
7
0
6
5
4
1
1
0
DAB
3
2
1
1
U2739M-B
1
0
1
0
Write Command
$6E
Data Mode
7
6
5
4
3
2
1
0
0
0
0
1
0
1
0
0
$14
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
0
DAB
U2739M-B
Write Command
$6C
Data Mode
7
6
ON
SCEFC
5
4
3
2
1
0
SBCHID
$XX
SCU(9..2)
SCU(1..0)
EP
EPPAR
CU(7..0)
38 (69)
$XX
CU(9..8)
$XX
$XX
Rev. A1, 22-May-01
U2739M-B
Command Parameters:
Parameter
Meaning
Description
ON
Sub–channel on/off switch 0:
1:
Switch sub–channel off
Switch sub–channel on
SCEFC
Single sub–channel for
EFC
0:
1:
Single sub–channel for EFC remains unchanged
Set SBCHID as single sub–channel for EFC
SBCHID(5..0)
sub–channel identifier
n:
Sub–channel ID
SCU(9..0)
Start CU for SBCHID
n:
Start CU address (0..863)
EP
Error Protection
0:
1:
UEP
EEP
EPPAR(2..0)
Error Protection
parameters
If EP = 0 (UEP):
000: Protection level P 1
001: Protection level P 2
010: Protection level P 3
011: Protection level P 4
100: Protection level P 5
If EP = 1 (EEP):
0xx: EEP long form option 0 (protection level xx–A)
00:
Protection level 1–A (code rate 2/8)
01:
Protection level 2–A (code rate 3/8)
10:
Protection level 3–A (code rate 4/8)
11:
Protection level 4–A (code rate 6/8)
CU(9..0)
Rev. A1, 22-May-01
Sub–channel size
(number of CU’s)
1xx:
EEP long form option 1 (protection level xx–B)
00:
Protection level 1–B (code rate 4/9)
01:
Protection level 2–B (code rate 4/7)
10:
Protection level 3–B (code rate 4/6)
11:
Protection level 4–B (code rate 4/5)
n:
Sub–channel size in CU’s (4..864)
39 (69)
U2739M-B
8.1.7
Set Next SBCHID Long Form
Command Settings Overview:
D Set next sub–channel parameters
Command
sequence:
Address Mode
7
0
6
5
4
1
1
0
DAB
3
2
1
1
U2739M-B
1
0
1
0
Write Command
$6E
Data Mode
7
6
5
4
3
2
1
0
0
0
0
1
0
1
0
1
$15
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
0
DAB
U2739M-B
Write Command
$6C
Data Mode
7
6
ON
SCEFC
5
4
3
2
1
0
SBCHID
$XX
SCU(9..2)
SCU(1..0)
EP
EPPAR
CU(7..0)
40 (69)
$XX
CU(9..8)
$XX
$XX
Rev. A1, 22-May-01
U2739M-B
Command Parameters:
Parameter
Meaning
Description
ON
Sub–channel on/off switch 0:
1:
Switch sub–channel off
Switch sub–channel on
SCEFC
Single sub–channel for
EFC
0:
1:
Single sub–channel for EFC remains unchanged
Set SBCHID as single sub–channel for EFC
SBCHID(5..0)
Sub–channel identifier
n:
Sub–channel ID
SCU(9..0)
Start CU for SBCHID
n:
Start CU address (0..863)
EP
Error Protection
0:
1:
UEP
EEP
EPPAR(2..0)
Error Protection
parameters
If EP = 0 (UEP):
000: Protection level P 1
001: Protection level P 2
010: Protection level P 3
011: Protection level P 4
100: Protection level P 5
If EP = 1 (EEP):
0xx: EEP long form option 0 (protection level xx–A)
00:
Protection level 1–A (code rate 2/8)
01:
Protection level 2–A (code rate 3/8)
10:
Protection level 3–A (code rate 4/8)
11:
Protection level 4–A (code rate 6/8)
CU(9..0)
Rev. A1, 22-May-01
Sub–channel size
(number of CU’s)
1xx:
EEP long form option 1 (protection level xx–B)
00:
Protection level 1–B (code rate 4/9)
01:
Protection level 2–B (code rate 4/7)
10:
Protection level 3–B (code rate 4/6)
11:
Protection level 4–B (code rate 4/5)
n:
Sub–channel size in CU’s (4..864)
41 (69)
U2739M-B
8.1.8
Set Current SBCHID Short Form
Command Settings Overview:
D Set current sub–channel parameters (short form)
Command
sequence:
Address Mode
7
0
6
5
4
1
1
0
DAB
3
2
1
1
U2739M-B
1
0
1
0
Write Command
$6E
Data Mode
7
6
5
4
3
2
1
0
0
0
0
1
0
1
1
0
$16
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
0
DAB
U2739M-B
Write Command
$6C
Data Mode
7
6
5
ON
SCEFC
4
3
2
1
SBCHID
0
$XX
Command Parameters:
Parameter
Meaning
Description
ON
Sub–channel on/off switch 0:
1:
Switch sub–channel off
Switch sub–channel on
SCEFC
Single sub–channel for
EFC
0:
1:
Single sub–channel for EFC remains unchanged
Set SBCHID as single sub–channel for EFC
SBCHID(5..0)
Sub–channel identifier
n:
Sub–channel ID
42 (69)
Rev. A1, 22-May-01
U2739M-B
8.2
’Set Configuration’ Commands
8.2.1
D Set channel decoder AGC values
Set Global Configuration
D Set channel decoder global parameters
Command Settings Overview:
Command
sequence:
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
1
0
DAB
U2739M-B
Write Command
$6G
Data Mode
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
$00
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
0
DAB
U2739M-B
Write Command
$6C
Data Mode
7
6
5
AGCV
0
dB3
4
3
2
DSC
1
0
PSC(10..8)
PSC(7..0)
CDPV
IFM
FSYS
SAW
$XX
$XX
ADCF
0
$XX
Command Parameters:
Parameter
Meaning
Description
Defaults
AGCV
AGC values valid
0:
1:
Following DSC/PSC values ignored
Following DSC/PSC values valid
DSC(1..0)
Input data scale
n:
Scale value
PSC(10..0)
Programmable (I)FFT scale
n:
Scale value
CDPV
Channel decoder parameters valid
0:
1:
Following global parameters ignored
Following global parameters valid
IFM
IF input signal mode
0:
1:
Common IF representation
Reverse IF representation
1
FSYS
Frame synchronization sensitivity
level
00:
01:
10:
11:
Very high
High
Low
Very low
01
SAW
SAW filter equalization switch
0:
1:
Equalization off
Equalization on
1
ADCF
ADC format
0:
1:
Binary ADC input format
2’s complement ADC input format
0
Rev. A1, 22-May-01
43 (69)
U2739M-B
8.2.2
Set TS Configuration
Command Settings Overview:
D Set TS post processing parameters
Command
sequence:
Address Mode
7
0
6
5
4
1
1
0
DAB
3
2
1
1
U2739M-B
1
0
1
0
Write Command
$6E
Data Mode
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
1
$21
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
0
DAB
U2739M-B
Write Command
$6C
Data Mode
44 (69)
7
6
PARV
COV
5
4
3
PKS
2
1
ISPCnt
0
$XX
TMIN
$XX
CIRTH
$XX
NSTH
$XX
GFCH
$XX
GFCL
$XX
Rev. A1, 22-May-01
U2739M-B
Command Parameters:
Parameter
Meaning
Description
Defaults
PARV
CIR post processing parameters valid
(PKS / AVG / CIRTH / NSTH / TMIN)
0:
1:
Parameters not valid
Following parameters valid
COV
CIR post processing filter coefficients
valid
0:
1:
Coefficients not valid
following coefficients valid
PKS
Number of peaks required for ’CIR
correct’ indication
2n :
Required peaks
0
ISPCnt
CIR post processing average
n:
CIR output average over n+1 values
0
TMIN(7..0)
CIR minimum dT output
n:
Minimum dT output after CIR post
processing (* 488 ns)
0
CIRTH(7..0)
CIR threshold
n.n:
– Threshold value for CIR peak
detection (format: 4.4 bit)
– Will be multiplied by ?
(standard deviation)
NSTH(7..0)
Noise threshold
n:
– Noise threshold value
(8 bit unsigned)
– Will be multiplied by 32
B0(15..0)
IIR filter coefficients
Coefficients for 1st order IIR filter used for
CIR post processing (Q15 format required)
Rev. A1, 22-May-01
3.0
0
0.5
0.5
0
45 (69)
U2739M-B
8.2.3
Set FS Configuration
Command Settings Overview:
D Set FS post processing parameters
Command
sequence:
Address Mode
7
0
6
5
4
1
1
0
DAB
3
2
1
1
U2739M-B
1
0
1
0
Write Command
$6E
Data Mode
7
6
5
4
3
2
1
0
0
0
1
0
0
0
1
0
$22
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
0
DAB
U2739M-B
Write Command
$6C
Data Mode
7
6
5
4
3
2
1
0
GA
$XX
THA
$XX
GB
$XX
THB
$XX
GC
$XX
F2FT
$XX
Command Parameters:
Parameter
Meaning
Description
Defaults
GA(7..0)
Area A gradient
n:
Fractional part
0.03125
THA(7..0)
Area A threshold
n:
Fractional part
0.03125
GB(7..0)
Area B gradient
n:
Fractional part
0.125
THB(7..0)
Area B threshold
n:
Fractional part
0.25
GC(7..0)
Area C gradient
n:
Fractional part
0.5
F2FT(7..0)
Max. frame–to–frame tolerance
n:
Maximum frequency shift in carriers
(format: 3.5 bit)
1.0
46 (69)
Rev. A1, 22-May-01
U2739M-B
8.2.4
Set XO Configuration
Command Settings Overview:
D Set XO control parameters
Command
sequence:
Address Mode
7
0
6
5
4
1
1
0
DAB
3
2
1
1
U2739M-B
1
0
1
0
Write Command
$6E
Data Mode
7
6
5
4
3
2
1
0
0
0
1
0
0
0
1
1
$23
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
0
DAB
U2739M-B
Write Command
$6C
Data Mode
7
6
5
4
3
2
1
0
XO_Rough line
$XX
XO_Fine line
$XX
XOAVG
0
$XX
Command Parameters:
Parameter
Meaning
Description
XO_B0(15..0)
XO_B1(15..0)
XO_B2(15..0)
XO_A1(15..0)
XO_A2(15..0)
IIR filter coefficients
Coefficients for
control
XOAVG(4..0)
XO control average
n:
Rev. A1, 22-May-01
2nd
order IIR filter used for XO
XO control average over n+1 values
Defaults
0.25
0.5
0.25
0
0
0
47 (69)
U2739M-B
8.2.5
Set HSSO / RS232 Configuration
Command Settings Overview:
D Set HSSO parameters
D Set RS232 parameters
Command
sequence:
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
1
0
DAB
U2739M-B
Write Command
$6E
Data Mode
7
6
5
4
3
2
1
0
0
0
1
0
0
1
0
0
3
2
1
0
1
1
0
0
$00
Address Mode
7
0
6
5
4
1
1
0
DAB
U2739M-B
Write Command
$6C
Data Mode
7
6
5
HCLK
4
HCIRL
RSBAUD
3
2
1
0
HPAD
HDD2
HDD1
HCIR
0
RSSEL
$XX
$XX
Command Parameters:
Parameter
Meaning
Description
HCLK(1..0)
HSSO bit clock
00: 0.768 MHz
01: 1.536 MHz
HCIRL(1..0)
HSSO CIR output length
00: N values (DAB system mode dependent)
01: N/2
1x: N/4
HPAD
HSSO PAD output switch
0: No PAD output via HSSO
1: PAD output
HDD2
HSSO DD2 output switch
0: No DD2 output via HSSO
1: DD2 output
HDD1
HSSO DD1 output switch
0: No DD1 output via HSSO
1: DD1 output
HCIR
HSSO CIR output switch
0: No CIR output via HSSO
1: CIR output
RSBAUD(1..0)
RS232 baud rate
00: 19200 baud
01: 38400 baud
RSSEL(1..0)
RS232 output selection
00:
01:
10:
11:
48 (69)
10: 3.072 MHz
11: 6.144 MHz
10: 57600 baud
11: 115200 baud
no output
DD1
DD2
PAD
Rev. A1, 22-May-01
U2739M-B
Command Parameters:
Parameter
Meaning
Description
UFS
USE FS module
0:
1:
Internal set2 XTFPR module used
External USE module used
UFSP
USE FS post processing module
0:
1:
Internal set2 module used
External USE module used
UTSP
USE TS post processing module
0:
1:
Internal set2 module used
External USE module used
UXOC
USE XO control module
0:
1:
Internal set2 module used
External USE module used
UDD1
USE DD1 module
0:
1:
Internal set2 module used
External USE module used
UDD2
USE DD2 module
0:
1:
Internal set2 module used
External USE module used
UPAD
USE PAD extraction module
0:
1:
Internal set2 module used
External USE module used
UTII
USE TII module
0:
1:
Internal set2 module used
External USE module used
UAMD ... UNMI
Reserved
Rev. A1, 22-May-01
49 (69)
U2739M-B
8.2.6
Set WAGC Configuration
Command Settings Overview:
D Set WAGC rising edge / falling edge parameters
Command
sequence:
Address Mode
7
0
6
5
4
1
1
0
DAB
3
2
1
1
U2739M-B
1
0
1
0
Write Command
$6E
Data Mode
7
6
5
4
3
2
1
0
0
0
1
0
0
1
1
0
$26
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
0
DAB
U2739M-B
Write Command
$6C
Data Mode
7
6
5
4
WRISE(3..0)
3
2
WS
1
0
0
WV
WRISE(11..4)
WFALL(1..0)
$XX
$XX
WRISE(17..12)
$XX
WFALL(9..2)
$XX
WFALL(17..10)
$XX
Command Parameters:
Parameter
Meaning
Description
WV
WAGC values valid
0:
1:
use default WAGC values
use following WAGC values
WRISE(17..0)
WAGC rising edge time marker
n:
value for WAGC rising edge
WFALL(17..0)
WAGC falling edge time marker
n:
value for WAGC falling edge
50 (69)
Rev. A1, 22-May-01
U2739M-B
8.2.7
Set RCC Slot Configuration
Command Settings Overview:
D Set RCC slot data
Command
sequence:
Address Mode
7
0
6
5
4
1
1
0
DAB
3
2
1
1
U2739M-B
1
0
1
0
Write Command
$6E
Data Mode
7
6
5
4
3
2
1
0
0
0
1
0
0
1
1
1
$27
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
0
DAB
U2739M-B
Write Command
$6C
Data Mode
7
6
5
4
3
2
1
0
RCC(7..0)
$XX
RCC(15..8)
$XX
RCC(23..16)
$XX
RCC(31..24)
$XX
RCC(39..32)
$XX
RCC(47..40)
$XX
RCC(55..48)
$XX
RCC(63..56)
$XX
Command Parameters:
Parameter
RCC(63..0)
Rev. A1, 22-May-01
Meaning
Description
RCC slot data
51 (69)
U2739M-B
8.2.8
Set RFU
Command Settings Overview:
D Set RFU parameters
Command
sequence:
Address Mode
7
0
6
5
4
1
1
0
DAB
3
2
1
1
U2739M-B
1
0
1
0
Write Command
$6E
Data Mode
7
6
5
4
3
2
1
0
0
0
1
1
0
0
0
0
$30
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
0
DAB
U2739M-B
Write Command
$6C
Data Mode
7
6
5
4
3
2
1
0
(reserved)
$XX
(reserved)
$XX
(reserved)
$XX
(reserved)
$XX
RFU4
$XX
RFU5
$XX
RFU6
$XX
...
$XX
...
$XX
RFU42
$XX
RFU43
$XX
RFU44
$XX
Command Parameters:
Parameter
Meaning
Description
(reserved)
Reserved for internal use (Atmel Wireless &
Microcontrollers will deliver default values, if necessary)
RFU4..44
Reserved for future use
52 (69)
Rev. A1, 22-May-01
U2739M-B
8.3
’Read Status’ Commands
8.3.1
Read Global Status
Command Overview:
D Get DAB system mode
D Get synchronization status
D Get OAK core operating mode
D Get AGC information
Command
sequence:
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
1
1
DAB
U2739M-B
Write Command
$6F
Data Mode
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
$40
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
1
DAB
U2739M-B
Write Command
$6D
Data Mode
7
6
DABMODE
0
0
5
4
OAKMODE
3
2
1
0
MV
FSLI
SLI
WDSP
CIRS
PSLI
CAFC
IDSL
P(7..0)
Rev. A1, 22-May-01
CCIR
P(8)
$XX
$XX
$XX
$XX
53 (69)
U2739M-B
Command Parameters:
Parameter
Meaning
Description
DABMODE(1..0)
DAB system mode
00:
01:
10:
11:
DAB system mode 4
DAB system mode 1
DAB system mode 2
DAB system mode 3
OAKMODE(1..0)
OAK operating mode
00:
01:
10:
11:
Normal stand–alone
USE boot mode
XUSE boot mode
HOST boot mode
MV
MODE_VALID line status
FSLI
FSLI line status
SLI
SLI line status
CIRS
CIR status
0:
1:
No CIR detected
CIR correct
CCIR(1..0)
Coded CIR status
00:
01:
10:
11:
|average| ? N/64
N/64 < |average| ? N/8
|average| > N/4
rfu.
CAFC(1..0)
Coded AFC status
00:
01:
10:
11:
|dFFRAME | ? TA
TA < |dFFRAME | ? TB
TB < |dFFRAME |< 16 kHz
|dFFRAME | ? 16 kHz
PSLI(3..0)
Precise signal level information
0000: Very weak signal
...
1111: Very strong signal
IDSL(1..0)
Input data signal level
00:
01:
10:
11:
P(8..0)
Calculated in–band power
WDSP
Watchdog DSP
54 (69)
Weak input signal
Typical input signal
Strong input signal
rfu.
Toggels every 24 ms from 0 to 1
Rev. A1, 22-May-01
U2739M-B
8.3.2
Read Synchronization Status
Command Overview:
D Get TS control value
D Get FS control value
Command
sequence:
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
1
1
DAB
U2739M-B
Write Command
$6F
Data Mode
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
1
3
2
1
0
1
1
0
1
$41
Address Mode
7
0
6
5
4
1
1
0
DAB
U2739M-B
Write Command
$6D
Data Mode
7
6
5
4
3
2
1
0
DT(9..2)
DT(1..0)
0
$XX
DF(19..16)
$XX
DF(15..8)
$XX
DF(7..0)
$XX
Command Parameters:
Parameter
Meaning
Description
1)
DT(9..0)
Detected time deviation
n:
Cycle count (signed, @2.048 MHz)
DF(19..0)
Detected channel
frequency deviation
n:
Deviation in carriers (signed, Q11 format)
1)
Signed values refers to virtual zero at Tguard/2
Rev. A1, 22-May-01
55 (69)
U2739M-B
8.3.3
Read CIR Status
Command Overview:
D Get CIR post processing results 1)
Command
sequence:
Address Mode
7
0
6
5
4
1
1
0
DAB
3
2
1
1
U2739M-B
1
0
1
1
Write Command
$6F
Data Mode
7
6
5
4
3
2
1
0
0
1
0
0
0
0
1
0
$42
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
1
DAB
U2739M-B
Write Command
$6D
Data Mode
7
6
5
4
3
2
1
0
P_FIRST(15..8)
$XX
P_FIRST(7..0)
$XX
P_AGV(15..8)
$XX
P_AGV(7..0)
$XX
P_LAST(15..8)
$XX
P_LAST(7..0)
$XX
Command Parameters:
Parameter
Meaning
P_FIRST(15..0)
Index of
P_AVG(15..0)
P_LAST(15..0)
1)
2)
1st
CIR peak above CIR threshold
Description
n:
Cycle count (signed, @2.048 MHz)
Index of CIR average value
n:
Cycle count (signed, @2.048 MHz)
Index of last CIR peak above CIR threshold
n:
Cycle count (signed, @2.048 MHz)
2)
If time synchronization has lost all values are set to $8000 !
Signed values refers to zero at Tguard/2
56 (69)
Rev. A1, 22-May-01
U2739M-B
8.4
’Read Data’ Commands
8.4.1
Read ASD Header Data
Command Overview:
D Get MPEG audio header
Command
sequence:
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
1
1
DAB
U2739M-B
Write Command
$6F
Data Mode
7
6
5
4
3
2
1
0
0
1
0
1
0
0
0
0
$50
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
1
DAB
U2739M-B
Write Command
$6D
Data Mode
7
6
5
4
3
2
1
0
MPG_HW1(15..8)
$XX
MPG_HW1(7..0)
$XX
MPG_HW2(15..8)
$XX
MPG_HW2(7..0)
$XX
Command Parameters:
Parameter
Meaning
Description
MPG_HW1(15..0)
1st MPEG header word
Sync. word ($FFFx) expected
MPG_HW2(15..0)
2nd
MPEG stream signature
Rev. A1, 22-May-01
MPEG header word
57 (69)
U2739M-B
8.4.2
Read X–PAD
Command Overview:
D Get MPEG ancillary data (X–PAD)
Command
sequence:
Address Mode
7
0
6
5
4
1
1
0
DAB
3
2
1
1
U2739M-B
1
0
1
1
Write Command
$6F
Data Mode
7
6
5
4
3
0
1
0
1
0
2
1
0
XPNUM
$5X
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
1
DAB
U2739M-B
Write Command
$6D
Data Mode
7
6
5
4
3
2
X–PAD0
1
0
$XX
...
X–PAD31
$XX
Command Parameters:
Parameter
Meaning
Description
XPNUM
X–PAD block number n
(n from 1..5)
The maximum X–PAD capacity supported by the U2739M-B is 64kbit/s.
The access is splitted into 6 blocks (numbered 1..5) of 32 bytes.
The blocks are time aligned, that means block 1 is the first block in an
MPEG frame after audio samples.
X–PADm
X–PAD byte m
Byte 0 is the first byte of block n, byte 31 the last one. It is followed by
the first one of block n+1.
Read RFU
Use MC command “RFU” to read block 6
58 (69)
Rev. A1, 22-May-01
U2739M-B
8.4.3
Read F–PAD
Command Overview:
D Get MPEG ancillary data (F–PAD)
Command
sequence:
Address Mode
7
0
6
5
4
1
1
0
DAB
3
2
1
1
U2739M-B
1
0
1
1
Write Command
$6F
Data Mode
7
6
5
4
3
2
1
0
0
1
0
1
1
0
0
0
$58
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
1
DAB
U2739M-B
Write Command
$6D
Data Mode
7
6
5
4
3
2
1
0
F–PAD0
$XX
F–PAD1
$XX
Command Parameters:
Parameter
Meaning
F–PAD0
F–PAD byte 0
F–PAD1
F–PAD byte 1
Rev. A1, 22-May-01
Description
59 (69)
U2739M-B
8.4.4
Read AIC Data
Command Overview:
D Get AIC data
Command
sequence:
Address Mode
7
0
6
5
4
1
1
0
DAB
3
2
1
1
U2739M-B
1
0
1
1
Write Command
$6F
Data Mode
7
6
5
4
0
1
1
0
3
2
1
0
AICNUM
$6X
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
1
DAB
U2739M-B
Write Command
$6D
Data Mode
7
6
5
4
3
2
AIC0
1
0
$XX
...
AIC31
$XX
Command Parameters:
Parameter
Meaning
Description
AICNUM
AIC block number n The maximum AIC capacity is 512 bytes.
The access is splitted into 16 blocks (numbered 0..15) of 32 bytes.
The blocks are time aligned, that means block 0 is the first filled block.
AICm
AIC byte m
60 (69)
Byte 0 is the first byte of block n, byte 31 the last one. It is followed by
the first one of block n+1.
Rev. A1, 22-May-01
U2739M-B
8.4.5
Read TII Data
Command Overview:
D Get TII data
Command
sequence:
Address Mode
7
0
6
5
4
1
1
0
DAB
3
2
1
1
U2739M-B
1
0
1
1
Write Command
$6F
Data Mode
7
6
5
4
3
2
0
1
1
1
0
0
1
0
TIINUM
$7X
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
1
DAB
U2739M-B
Write Command
$6D
Data Mode
7
6
5
4
3
2
TII0
1
0
$XX
...
TII31
$XX
Command Parameters:
Parameter
Meaning
Description
TIINUM
TII block number n
The maximum TII capacity is 128 bytes.
The access is splitted into 4 blocks (numbered 0..3) of 32 bytes.
The blocks are time aligned, that means block 0 is the first filled block.
TIIm
TII byte m
Byte 0 is the first byte of block n, byte 31 the last one. It is followed by
the first one of block n+1.
Rev. A1, 22-May-01
61 (69)
U2739M-B
8.4.6
Read EFC Data
Command Overview:
D Get EFC data
Command
sequence:
Address Mode
7
0
6
5
4
1
1
0
DAB
3
2
1
1
U2739M-B
1
0
1
1
Write Command
$6F
Data Mode
7
6
5
4
3
2
1
0
0
0
0
0
1
0
EFCSEL
$8X
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
1
DAB
U2739M-B
Write Command
$6D
Data Mode
7
6
5
4
3
2
1
0
EFC(7..0)
$XX
EFC(15..8)
$XX
Command Parameters:
Parameter
Meaning
Description
EFCSEL
EFC selection
00:
01:
EFC of FIC
EFC of all MSC applications
EFC(15..0)
EFC value for chosen
application
n:
EFC value summarized over...
... 12 FIB’s
(DAB mode 1)
... 3 FIB’s
(DAB mode 2)
... 4 FIB’s
(DAB mode 3)
... 6 FIB’s
(DAB mode 4)
62 (69)
Rev. A1, 22-May-01
U2739M-B
8.4.7
Read FIC Data
D Get FIB bytes
Command Overview:
Command
sequence:
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
1
1
DAB
U2739M-B
Write Command
$6F
Data Mode
7
6
5
4
1
0
0
1
3
2
1
0
FIBNUM
$9X
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
1
DAB
U2739M-B
Write Command
$6D
Data Mode
7
6
5
4
3
2
FIB0
1
0
$XX
...
FIB31
$XX
Command Parameters:
Parameter
Meaning
Description
FIBNUM
FIB number n
Possible FIB numbers DAB mode dependent:
0..11 (DAB mode 1)
0..2 (DAB mode 2)
0..3 (DAB mode 3)
0..5 (DAB mode 4)
FIBm
FIB byte m
Each FIB consists of 32 bytes. The order of the FIB bytes and bits corresponds
to the serial FIC processing. That means:
(1) Byte order:
The first 8 output bits after FIC processing represent FIB byte 0 of FIB number 0, the next ones FIB byte 1 of FIB number 0 and so on.
(2) Bit order:
The FIB bytes are given out MSB first. The first outgoing bit represents bit 7
of the corresponding byte, the next one bit 6 and so on. The FIB bits are numbered from bit 0 (MSB of FIB0) up to bit 255 (LSB of FIB31).
NOTE:
The last 2 bytes of an FIB represent the result of the U2739M internal CRC
check. That means, if these bytes are $00 both, the internal CRC check was
successful and the FIB data bytes are correct.
Rev. A1, 22-May-01
63 (69)
U2739M-B
8.4.8
Read RCC Slot
Command Overview:
D Get RCC slot data
Command
sequence:
Address Mode
7
0
6
5
4
1
1
0
DAB
3
2
1
1
U2739M-B
1
0
1
1
Write Command
$6F
Data Mode
7
6
5
4
3
2
1
0
1
0
1
0
0
0
0
0
$A0
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
1
DAB
U2739M-B
Write Command
$6D
Data Mode
7
6
5
4
3
2
1
0
RCC(7..0)
$XX
RCC(15..8)
$XX
RCC(23..16)
$XX
RCC(31..24)
$XX
RCC(39..32)
$XX
RCC(47..40)
$XX
RCC(55..48)
$XX
RCC(3..56)
$XX
Command Parameters:
Parameter
RCC(63..0)
64 (69)
Meaning
Description
RCC slot data
Rev. A1, 22-May-01
U2739M-B
8.4.9
Read Slot Pointer
Command Overview:
D Get RCC RX/TX slot pointer
Command
sequence:
Address Mode
7
0
6
5
4
1
1
0
DAB
3
2
1
1
U2739M-B
1
0
1
1
Write Command
$6F
Data Mode
7
6
5
4
3
2
1
0
1
0
1
0
0
0
0
1
$A1
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
1
DAB
U2739M-B
Write Command
$6D
Data Mode
7
6
5
TXPTR
4
3
2
1
RXPTR
0
$XX
Command Parameters:
Parameter
Meaning
RXPTR(3..0)
RCC RX slot pointer
TXPTR(3..0)
RCC TX slot pointer
Rev. A1, 22-May-01
Description
65 (69)
U2739M-B
8.4.10
Read RFU
Command Overview:
D Get RFU data
Command
sequence:
Address Mode
7
0
6
5
4
1
1
0
DAB
3
2
1
1
U2739M-B
1
0
1
1
Write Command
$6F
Data Mode
7
6
5
4
3
2
1
0
1
0
1
1
0
0
0
0
$9X
Address Mode
7
6
5
4
3
2
1
0
0
1
1
0
1
1
0
1
DAB
U2739M-B
Write Command
$6D
Data Mode
7
6
5
4
3
2
1
RFU0
0
$XX
...
RFU43
$XX
Command Parameters:
Parameter
XPAD0..31
RFU0..11
66 (69)
Meaning
XPAD block 6
Description
See: read XPAD command
Reserved for future use
Rev. A1, 22-May-01
U2739M-B
9
Package Information
Rev. A1, 22-May-01
67 (69)
U2739M-B
68 (69)
Rev. A1, 22-May-01
U2739M-B
Ozone Depleting Substances Policy Statement
It is the policy of Atmel Germany GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on
the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid
their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these
substances.
Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed
in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances
and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer
application by the customer. Should the buyer use Atmel Wireless & Microcontrollers products for any unintended
or unauthorized application, the buyer shall indemnify Atmel Wireless & Microcontrollers against all claims,
costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death
associated with such unintended or unauthorized use.
Data sheets can also be retrieved from the Internet:
http://www.atmel–wm.com
Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
Rev. A1, 22-May-01
69 (69)