ATMEL T87C5101XXX

Features
• 80C51 Code Compatible
•
•
•
•
•
•
•
•
•
•
•
•
•
– 8051 Instruction Compatible
– 16 I/O + 2 Outputs in 24 Pin Packages
16 I/O + 6 Outputs in 28 Pin Packages
– Three 16-bit Timer/Counters
– 256 Bytes Scratchpad RAM
Program Memory
– 8 KB ROM T83C5102
– 16 KB ROM T83C5101
– 16 KB EPROM/OTP T87C5101
High-speed Architecture
40 MHz from 2.7 to 5.5V, Commercial or Industrial Temperature Range:
– 40 MHz with a 40 MHz Crystal In Std. Mode
– 40 MHz with a 20 MHz Crystal In X2 Mode
66 MHz from 4.5 to 5.5V, Commercial Temperature Range
– 40 MHz with a 40 MHz Crystal in Std. Mode
– 66 MHz with a 33 MHz Crystal in X2 Mode
Dual Data Pointer
On-chip eXpanded RAM (XRAM) (256 bytes)
Programmable Clock Out and Up/Down Timer/Counter 2
Asynchronous Port Reset
Interrupt Structure with
– 6 Interrupt Sources,
– 4-Level Priority Interrupt System
Full-duplex Enhanced UART
– Framing Error Detection
– Automatic Address Recognition
Low EMI (no ALE)
Power Control Modes
– Idle Mode
– Power-down Mode
Packages: SO24, DIL24, SSOP24, SO28
8-bit Low Pin
Count
Microcontrollers
T83C5101
T87C5101
T83C5102
Description
The T8xC5101/02 family is a high performance CMOS ROM, OTP, EPROM derivative
of the 80C51 CMOS single chip 8-bit microcontroller.
The T8xC5101/02 family is a low pin count device where only Port 1, port 3 and 2/6
bits of a new port 4 are outputted. This prevents any external access, like external program memory access (fetch, MOVC) or external data memory (MOVX). The
T8xC5101/02 family retains all features of the 80C51 with extended capacity 8 KB
ROM (5102), 16 KB ROM (5101)/16 KB EPROM/OTP (5101), 256 bytes of internal
RAM, a 6-source, 4-level interrupt system, an on-chip oscillator and three
timer/counters.
In addition, the T8xC5101/02 family has an XRAM of 256 bytes, the X2 feature, a
more versatile serial channel that facilitates multiprocessor communication (EUART),
a dual data pointer and an improved timer 2. The fully static design of the
T8xC5101/02 family allows to reduce system power consumption by bringing the
clock frequency down to any value, even DC, without loss of data.
The T8xC5101/02 family has 2 software-selectable modes of reduced activity for further reduction in power consumption. In idle mode the CPU is frozen while the timers,
the serial port and the interrupt system are still operating. In power-down mode the
RAM is saved and all other functions are inoperative.
Rev. 4233H–8051–02/08
1
(2) (2)
(1)
XTAL1
EUART
XTAL2
PROG
TEST
RAM
256x8
ROM
/EPROM
16Kx8
XRAM
256x8
T2
T2EX
Vss
Vcc
TxD
RxD
Block Diagram
(1)
Timer2
(3)
C51
CORE
(3)
IB-bus
CPU
VPP
Timer 0
Timer 1
INT
Ctrl
Parallel I/O Ports
P3
P4
P1
INT0
INT1
(2) (2)
T1
(2) (2)
T0
RESET
Port 1 Port 4 Port 3
(1): Alternate function of Port 1
(2): Alternate function of Port 3
(3): Multiplexed function of Port 4.
2
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
SFR Mapping
The Special Function Registers (SFRs) of the T8xC5101/02 fall into the following
categories:
•
C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
•
I/O port registers: P1, P3, P4
•
Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2,
RCAP2L, RCAP2H
•
Serial I/O port registers: SADDR, SADEN, SBUF, SCON
•
Power and clock control registers: PCON
•
Interrupt system registers: IE, IP, IPH
•
Others: AUXR, CKCON
No write must be made to reserved areas. Reading a reserved area will give indeterminate results.
3
4233H–8051–02/08
Table 1. All SFRs With Their Address and Rest Values
Bit
addressable
0/8
Non Bit addressable
1/9
2/A
3/B
4/C
5/D
6/E
7/F
F8h
F0h
FFh
B
0000 0000
F7h
E8h
E0h
EFh
ACC
0000 0000
E7h
D8h
DFh
D0h
PSW
0000 0000
C8h
T2CON
0000 0000
D7h
T2MOD
XXXX XX00
RCAP2L
0000 0000
RCAP2H
0000 0000
TL2
0000 0000
TH2
0000 0000
CFh
P4
C0h
C7h
XX11 1111
IP
SADEN
XX00 000
0000 0000
B8h
BFh
P3
B0h
IPH
XX00 0000
1111 1111
IE
SADDR
0X00 0000
0000 0000
A8h
AFh
AUXR1
A0h
B7h
A7h
XXXX0XX0
SCON
SBUF
0000 0000
XXXX XXXX
98h
9Fh
P1
90h
97h
1111 1111
TCON
TMOD
TL0
TL1
TH0
TH1
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
SP
0000 0111
DPL
0000 0000
DPH
0000 0000
1/9
2/A
3/B
88h
80h
0/8
AUXR
XXXXXX00
CKCON
8Fh
XXXX XXX0
PCON
87h
00X1 0000
4/C
5/D
6/E
7/F
Reserved
4
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
T8xC5101/02 Pin Configuration
P3.4/T0
1
24
Vcc
P3.4/T0
1
28
P3.3/INT1
2
P3.5/T1
P3.3/INT1
P3.2/INT0
P3.1
3
4
23
22
P3.6
P3.7
P3.2/INT0
P3.1
2
3
27
26
25
P3.0
5
20
19
18
17
P1.7
P1.6
P3.0
4
5
VPP
21
DIL24
6
SO24
7
8
P4.0/Prog
P4.1/Test
RST
SSOP24*
9
10
XTAL2
XTAL1
11
12
Vss
P1.5
P1.4
16
P1.3
15
14
P1.2
13
P1.0/T2
P1.1/T2EX
* Check for availability
VPP 6
7
P4.3
P4.0/Prog
P4.1/Test
RST
XTAL2
XTAL1
P4.4
Vss
SO28*
8
9
10
24
23
22
21
20
19
Vcc
P4.2
P3.5/T1
P3.6
P3.7
P1.7
P1.6
P4.5
P1.5
P1.4
P1.3
12
13
18
17
16
P1.1/T2EX
14
15
P1.0/T2
11
P1.2
* Check for availability
Pin Number
24 pins
28
pins
Type
VSS
12
14
I
Ground: 0V reference
VCC
24
28
I
Power Supply: This is the power supply voltage for normal, idle and power-down operation
13-20
15-20
22-23
I/O
Mnemonic
P1.0-P1.7
Name and Function
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port
1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1
also receives the low-order address byte during memory programming and verification.
Alternate functions for Port 1 include:
I/O
I
P4.0 (Prog)-P4.1
(Test)
7
8
8
9
O (I)
O (I)
T2 (P1.0): Timer/Counter 2 external count input/Clockout
T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control
Port 4 bits 0 & 1: Except during programming and verifying, these two bits are output port driving
30 micro Amps at high level and sinking 10 mA at low level (Vol < 1V). If they have 1s written to
them, they output a high level and if they have 0 written to them, they output a low level. These 2
pins cannot be used as inputs. Users should take care to never externally drive these pins
low, especially during reset. These two pins are primarily designed to drive LEDs.
During programming and verifying, these two pins are used as input, as explained in the
corresponding chapter.
A Read or a Read/Modify/Write instruction to these bits will read the status of the output: 1 if the
output is 1, 0 if the output is 0.
P4.2-P4.5
P3.0-P3.7
NA
5-1
27
7
13
21
I/O
Port 4 bits 2 to 5: bidirectional I/O port with internal pull-ups. Port 4.2 to 4.5 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port
4.2 to 4.5 pins that are externally pulled low will source current because of the internal pull-ups.
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port
3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3
also serves the special features of the 80C51 family, as listed below.
5-1
26-24
I/O
5
5
I
RxD (P3.0): Serial input port
4
4
O
TxD (P3.1): Serial output port
3
3
I
INT0 (P3.2): External interrupt 0
2
2
I
INT1 (P3.3): External interrupt 1
23-21
5
4233H–8051–02/08
Pin Number
24 pins
28
pins
Type
1
1
I
T0 (P3.4): Timer 0 external input
23
26
I
T1 (P3.5): Timer 1 external input
22
25
I/O
No alternate function on this pin
21
24
I/O
No alternate function on this pin
Reset
9
10
I
VPP
6
6
I
XTAL1
11
12
I
XTAL2
10
11
O
Mnemonic
6
Name and Function
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device.
An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to
VCC.
Programming Supply Voltage: This pin receives the 12.75V programming supply voltage (VPP)
during EPROM programming. During normal operation, VPP pin must be tied to Vcc.
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
Crystal 2: Output from the inverting oscillator amplifier
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
Low Pin Count
Specificities
The T8xC5101/02 family is not able to perform any external memory access, such as a
code fetch, a look-up table access (using MOVC) or a data access (using MOVX)
because traditional Port ×0 and Port 2 are not implemented. It should be noted that 2
bits of a new port 4 are available, but they are pure user outputs. On the 28 pin package,
there is also a set of 4 extra I/Os, which cannot be used for external access.
This inability to perform external memory accesses has the following consequences:
•
Port 0 SFR doesn’t exist
•
Port 2 SFR doesn’t exist
•
Port 4 has six bits defined among which two are pure outputs for LED driving.
•
Security level 4 is no longer applicable
•
Code memory addresses is limited to 4000h. Accessing to any address above
3FFFh will return indeterminate value. Jumps, subroutine Calls, MOVC instructions
should be limited to a maximum address range of 3FFFh to avoid any error.
•
External data memory addresses is limited to 100h. Writing to any address above
FFh will have no effect. Reading any address above FFh will return indeterminate
value. To avoid any mistake, MOVX address should be limited to a maximum
address range of FFh.
•
In Rx devices, the user could disable the XRAM (for example, if he had shared
resource at the corresponding address range). As no external access is possible
with the T83/87C510x, it makes no sense to be able to disable accesses to XRAM.
Nevertheless, access to AUXR bit 1 will cause no error and any write to this bit will
have no effect.
•
As there is no external access, EA, ALE, PSEN, RD and WR signals are not
implemented. So, the corresponding pins or alternate functions are removed.
•
As there is no ALE, there is no need for ALE disabling. Nevertheless, access to
AUXR bit 0 will cause no error and any write to this bit will have no effect.
•
Compared to the corresponding 16 KB Rx2 device, the TS80C51RB2, the following
features are removed:
–
Port 0 & 2
–
PCA
–
Watchdog
–
ONCE mode
–
Power Off Flag (POF)
7
4233H–8051–02/08
T8xC5101/02
T8xC5101/02
Enhanced Features
X2 Feature
In comparison to the original 80C52, the T8xC5101/02 implements some new features,
which are:
•
The X2 option.
•
The Dual Data Pointer.
•
The extended RAM.
•
The 4 level interrupt priority system.
•
Some enhanced features are also located in the UART and the timer 2.
The T8xC5101/02 core needs only 6 clock periods per machine cycle. This feature
called ”X2” provides the following advantages:
•
Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
•
Save power consumption while keeping same CPU power (oscillator power saving).
•
Save power consumption by dividing dynamically operating frequency by 2 in
operating and idle modes.
•
Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by software.
Description
The clock for the whole circuit and peripheral is first divided by two before being used by
the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1
input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic
ratio between 40 to 60%. Figure 1 shows the clock generation block diagram. X2 bit is
validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD
mode. Figure 2 shows the mode switching waveforms.
Figure 1. Clock Generation Diagram
2
XTAL1
FXTAL
XTAL1:2
state machine: 6 clock cycles.
0
1
CPU control
FOSC
X2
CKCON reg
8
4233H–8051–02/08
Figure 2. Mode Switching Waveforms
XTAL1
XTAL1:2
X2 bit
CPU clock
STD Mode
X2 Mode
STD Mode
The X2 bit in the CKCON register (See Table 2.) allows to switch from 12 clock cycles
per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated
(STD mode). Setting this bit activates the X2 feature (X2 mode).
CAUTION
In order to prevent any incorrect operation while operating in X2 mode, user must be
aware that all peripherals using clock frequency as time reference (UART, timers,
PCA...) will have their time reference divided by two. For example a free running timer
generating an interrupt every 20 ms will then generate an interrupt every 10 ms. UART
with 4800 baud rate will have 9600 baud rate.
Table 2. CKCON Register
CKCON - Clock Control Register (8Fh)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
X2
Bit
Number
Bit
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0
X2
Description
CPU and peripheral clock bit
Clear to select 12 clock periods per machine cycle (STD mode,
FOSC=FXTAL/2).
Set to select 6 clock periods per machine cycle (X2 mode, FOSC=FXTAL).
Reset Value = XXXX XXX0b
Not bit addressable
9
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
The additional data pointer can be used to speed up code execution and reduce code
size in a number of ways.
Dual Data Pointer
Register (DPTR)
The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external
memory, and a single bit called DPS = AUXR1/bit0 (See Table 3.) that allows the program code to switch between them (Refer to Figure 3).
Figure 3. Use of Dual Pointer
External Data Memory
(On chip XRAM)
7
0
DPS
DPTR1
AUXR1(A2H)
DPTR0
DPH(83H) DPL(82H)
Table 3. AUXR1: Auxiliary Register 1
AUXR1
Address 0A2H
Reset value
Symbol
-
-
-
-
GF3
0
-
DPS
X
X
X
X
0
0
X
0
Function
Not implemented, reserved for future use.
DPS
Data Pointer Selection.
DPS
GF3
Notes:
-
Operating Mode(1)
0
DPTR0 Selected
1
DPTR1 Selected
This bit is a general purpose user flag(2)
1. User software should not write 1s to reserved bits. These bits may be used in future
8051 family products to invoke new feature. In that case, the reset value of the new
bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.
2. GF3 will not be available on first version of the RC devices.
10
4233H–8051–02/08
Application
Software can take advantage of the additional data pointers to both increase speed and
reduce code size, for example, block operations (copy, compare, search ...) are well
served by using one data pointer as a ’source’ pointer and the other one as a "destination" pointer.
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Destroys DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2
AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1
; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008
LOOP:
0008 05A2 INC AUXR1
; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR
; increment SOURCE address
000C 05A2 INC AUXR1
; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR
; increment DEST address
0010 70F6JNZ LOOP
; check for 0 terminator
0012 05A2 INC AUXR1
; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1
SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example,
only the fact that DPS is toggled in the proper sequence matters, not its actual value. In
other words, the block move routine works the same whether DPS is '0' or '1' on entry.
Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in
the opposite state.
11
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
Expanded RAM
(XRAM)
The T8xC5101/02 provide 256 additional Bytes of random access memory (RAM) space
for increased data parameter handling and high level language usage.
The T8xC5101/02 have internal data memory that is mapped into four separate
segments.
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly
addressable.
2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable
only.
3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly
addressable only.
4. The expanded RAM bytes are indirectly accessed by MOVX instructions.
As external accesses are not possible on the T8xC5101/02 family, it makes no sense to
have the possibility to disable accesses to XRAM. That’s why, compared to
TS80C51RB2, writing a 1 in AUXR register bit 1 will have no effect, and won’t disable
access to the XRAM.
The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper
128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy
the same address space as the SFR. That means they have the same address, but are
physically separate from SFR space.
When an instruction accesses an internal location above address 7FH, the CPU knows
whether the access is to the upper 128 bytes of data RAM or to SFR space by the
addressing mode used in the instruction.
•
Instructions that use direct addressing access SFR space. For example: MOV
0A0H, # data, accesses the SFR at location 0B0H (which is P3).
•
Instructions that use indirect addressing access the Upper 128 bytes of data RAM.
For example: MOV @R0, # data where R0 contains 0B0H, accesses the data byte
at address 0B0H, rather than P3 (which address is 0B0H).
•
The 256 XRAM bytes can be accessed by indirect addressing, with MOVX
instructions. This part of memory which is physically located on-chip, logically
occupies the first 256 bytes of external data memory.
•
The XRAM is indirectly addressed, using the MOVX instruction in combination with
any of the registers R0, R1 of the selected bank or DPTR. An access to XRAM will
not affect any ports. A write to external data memory locations higher than FFH
(i.e. 0100H to FFFFH) will have no effect. A read will return an indeterminate value.
The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and
upper RAM) internal data memory. The stack may not be located in the XRAM.
12
4233H–8051–02/08
Figure 4. Internal and External Data Memory Address
FF
FF
FF
Upper
128 bytes
Internal
Ram
indirect accesses
80
XRAM
Special
Function
Register
direct accesses
80
256 bytes
Lower
128 bytes
Internal
Ram
direct or indirect
accesses
00
00
Table 4. Auxiliary Register - AUXR
AUXR
Address 08EH
Reset value
Symbol
AO
EXTRAM
13
-
-
-
-
-
EXTRAM
AO
X
X
X
X
X
X
0
0
Function
Not implemented, reserved for future use. (1)
-
1.
-
Writing to this bit will have no effect (refer to chapter "Reduced EMI mode")
Writing to this bit will have no effect
User software should not write 1s to reserved bits. These bits may be used in future 8051
family products to invoke new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
Timer 2
The timer 2 in the T8xC5101/02 family is compatible with the timer 2 in the 80C52.
It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2
and TL2, connected in cascade. It is controlled by T2CON register (See Table 5) and
T2MOD register (See Table 6). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2
selects FOSC/12 (timer operation) or external pin T2 (counter operation) as the timer
clock input. Setting TR2 allows TL2 to be incremented by the selected input.
Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These
modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON), as
described in the Atmel 8-bit Microcontroller Hardware description.
Refer to the Atmel 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate Generator Modes.
In T8xC5101/02 Timer 2 includes the following enhancements:
Auto-Reload Mode
•
Auto-reload mode with up or down counter
•
Programmable clock-output
The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the
Atmel 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an
Up/down timer/counter as shown in Figure 5. In this mode the T2EX pin controls the
direction of count.
When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the
TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value
in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.
When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the
timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.
The underflow sets TF2 flag and reloads FFFFh into the timer registers.
The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. EXF2 does not generate any interrupt. This bit can be used to provide
17-bit resolution.
14
4233H–8051–02/08
Figure 5. Auto-Reload Mode Up/Down Counter (DCEN = 1)
(:6 in X2 mode)
:12
XTAL1
FXTAL
FOSC
0
1
T2
TR2
C/T2
T2CONreg
T2CONreg
T2EX:
(DOWN COUNTING RELOAD VALUE)
FFh
(8-bit)
FFh
(8-bit)
if DCEN=1, 1=UP
if DCEN=1, 0=DOWN
if DCEN = 0, up
counting
TOGGLE T2CONreg
EXF2
TL2
(8-bit)
TH2
(8-bit)
TF2
T2CONreg
TIMER 2
INTERRUPT
RCAP2L RCAP2H
(8-bit)
(8-bit)
(UP COUNTING RELOAD VALUE)
Programmable Clock-Output
In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 6) . The input clock increments TL2 at frequency FOSC/2. The timer
repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H
and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2 overflows do
not generate interrupts. The formula gives the clock-out frequency as a function of the
system oscillator frequency and the value in the RCAP2H and RCAP2L registers:
F
× 2 x2
osc
---------------------------------------------------------------------------------------Clock – OutFrequency =
4 × ( 65536 – RCAP2H ⁄ RCAP2L )
For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz
(FOSC/216) to 4 MHz (FOSC/4) in X1 mode. The generated clock signal is brought out to
T2 pin (P1.0).
Timer 2 is programmed for the clock-out mode as follows:
15
•
Set T2OE bit in T2MOD register.
•
Clear C/T2 bit in T2CON register.
•
Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L
registers.
•
Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the
reload value or a different one depending on the application.
•
To start the timer, set TR2 run control bit in T2CON register.
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not
independent since both functions use the values in the RCAP2H and RCAP2L registers.
Figure 6. Clock-Out Mode C/T2 = 0
XTAL1
:2
(:1 in X2 mode)
TR2
T2CON reg
TL2
(8-bit)
TH2
(8-bit)
OVERFLOW
Toggle
RCAP2L
(8-bit)
RCAP2H
(8-bit)
T2
Q
D
T2OE
T2MOD reg
T2EX
EXF2
EXEN2
T2CON reg
TIMER 2
INTERRUPT
T2CON reg
16
4233H–8051–02/08
Table 5. T2CON Register
T2CON - Timer 2 Control Register (C8h)
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit Number
Bit
Mnemonic
7
TF2
Description
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
6
EXF2
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1)
5
RCLK
Receive Clock bit
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
4
TCLK
Transmit Clock bit
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3
EXEN2
2
TR2
1
C/T2#
0
CP/RL2#
Timer 2 External Enable bit
Clear to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to clock
the serial port.
Timer 2 Run control bit
Clear to turn off timer 2.
Set to turn on timer 2.
Timer/Counter 2 select bit
Clear for timer operation (input from internal clock system: FOSC).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode.
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow.
Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
Reset Value = 0000 0000b
Bit addressable
17
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
Table 6. T2MOD Register
T2MOD - Timer 2 Mode Control Register (C9h)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
T2OE
DCEN
Bit
Number
Bit
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1
T2OE
Timer 2 Output Enable bit
Clear to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as clock output.
0
DCEN
Down Counter Enable bit
Clear to disable timer 2 as up/down counter.
Set to enable timer 2 as up/down counter.
Description
Reset Value = XXXX XX00b
Not bit addressable
18
4233H–8051–02/08
T8xC5101/02
T8xC5101/02 Serial
I/O Port
The serial I/O port in the T8xC5101/02 family is compatible with the serial I/O port in the
80C52. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three fullduplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur
simultaneously and at different baud rates.
Serial I/O port includes the following enhancements:
Framing Error Detection
•
Framing error detection
•
Automatic address recognition
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2
and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 7).
Figure 7. Framing Error Block Diagram
SM0/FE SM1
SM2
REN
TB8
RB8
TI
RI
SCON (98h)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SM0 to UART mode control (SMOD = 0)
SMOD1SMOD0
-
POF
GF1
GF0
PD
IDL
PCON (87h)
To UART framing error control
When this feature is enabled, the receiver checks each incoming data frame for a valid
stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous
transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in
SCON register (See ) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set,
only software or a reset can clear FE bit. Subsequently received frames with valid stop
bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the
last data bit (See Figure 8. and Figure 9.).
Figure 8. UART Timings in Mode 1
RXD
D0
Start
bit
D1
D2
D3
D4
Data byte
D5
D6
D7
Stop
bit
RI
SMOD0=X
FE
SMOD0=1
19
4233H–8051–02/08
Figure 9. UART Timings in Modes 2 and 3
RXD
D0
Start
bit
D1
D2
D3
D4
Data byte
D5
D6
D7
D8
Ninth Stop
bit
bit
RI
SMOD0=0
RI
SMOD0=1
FE
SMOD0=1
Automatic Address
Recognition
The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor
communication feature by allowing the serial port to examine the address of each
incoming command frame. Only when the serial port recognizes its own address, the
receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU
is not interrupted by command frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this
configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the
received command frame address matches the device’s address and is terminated by a
valid stop bit.
To support automatic address recognition, a device is identified by a given address and
a broadcast address.
Note:
Given Address
The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
Each device has an individual address that is specified in SADDR register; the SADEN
register is a mask byte that contains don’t-care bits (defined by zeros) to form the
device’s given address. The don’t-care bits provide the flexibility to address one or more
slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111
1111b.
For example:
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Given1111 0X0Xb
Slave B:SADDR1111 0011b
SADEN1111 1001b
Given1111 0XX1b
Slave C:SADDR1111 0010b
SADEN1111 1101b
Given1111 00X1b
20
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g.
1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with
slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both
set (e.g. 1111 0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0
set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b).
Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers
with zeros defined as don’t-care bits, e.g.:
SADDR 0101 0110b
SADEN 1111 1100b
Broadcast =SADDR OR SADEN1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however
in most applications, a broadcast address is FFh. The following is an example of using
broadcast addresses:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Broadcast1111 1X11b,
Slave B:SADDR1111 0011b
SADEN1111 1001b
Broadcast1111 1X11B,
Slave C:SADDR=1111 0010b
SADEN1111 1101b
Broadcast1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with
all of the slaves, the master must send an address FFh. To communicate with slaves A
and B, but not slave C, the master can send and address FBh.
Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and
broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial
port will reply to any address, and so, that it is backwards compatible with the 80C51
microcontrollers that do not support automatic address recognition.
21
4233H–8051–02/08
Table 7. SADEN Register
SADEN - Slave Address Mask Register (B9h)
7
6
5
4
3
2
1
0
3
2
1
0
Reset Value = 0000 0000b
Not bit addressable
Table 8. SAADR Register
SADDR - Slave Address Register (A9h)
7
6
5
4
Reset Value = 0000 0000b
Not bit addressable
22
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
Table 9. SCON Register
SCON - Serial Control Register (98h)
7
6
5
4
3
2
1
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit Number
7
Bit
Mnemonic
FE
Description
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
SM0
Serial port Mode bit 0
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
SM1
Serial port Mode bit 1
SM0 SM1 Mode Description
0
0
0 Shift Register
0
1
1 8-bit UART
1
0
2 9-bit UART
1
1
3 9-bit UART
5
SM2
Serial port Mode 2 bit/Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should
be cleared in mode 0.
4
REN
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
3
TB8
6
Baud Rate
FXTAL/12 (/6 in X2 mode)
Variable
FXTAL/64 or FXTAL/32 (/32, /16in X2 mode)
Variable
Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3.
2
RB8
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8/Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1
TI
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other
modes.
0
RI
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 8. and Figure 9. in the other modes.
Reset Value = 0000 0000b
Bit addressable
23
4233H–8051–02/08
Table 10. PCON Register
PCON - Power Control Register (87h)
7
6
5
4
3
2
1
0
SMOD1
SMOD0
-
POF
GF1
GF0
PD
IDL
Bit
Number
Bit
Mnemonic
7
SMOD1
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6
SMOD0
Serial port Mode bit 0
Clear to select SM0 bit in SCON register.
Set to to select FE bit in SCON register.
5
-
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
POF
Power-Off Flag
Clear to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be
set by software.
3
GF1
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
2
GF0
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
1
PD
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0
IDL
Idle mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
Reset Value = 00X1 0000b
Not bit addressable
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset
doesn’t affect the value of this bit.
24
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
Interrupt System
The T8xC5101/02 family has a total of 6 interrupt vectors: two external interrupts (INT0
and INT1), three timer interrupts (timers 0, 1 and 2) and the serial port interrupt. These
interrupts are shown in Figure 10. The addresses of the interrupt vectors are the same
as in the standard C52.
Figure 10. Interrupt Control System
High priority
interrupt
IPH, IP
INT0
3
IE0
0
3
TF0
0
INT1
Interrupt
polling
sequence, decreasing from
high to low priority
3
IE1
0
3
TF1
0
RI
TI
3
TF2
EXF2
3
0
0
Individual Enable
Low priority
interrupt
Global Disable
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (See Table 12). This register also contains a
global disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (See Table 13) and in the
Interrupt Priority High register (See Table 14). shows the bit values and priority levels
associated with each combination.
Table 11. Priority Level Bit Values
IPH.x
IP.x
Interrupt Level Priority
0
0
0 (Lowest)
0
1
1
1
0
2
1
1
3 (Highest)
25
4233H–8051–02/08
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another
low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt
source.
If two interrupt requests of different priority levels are received simultaneously, the
request of higher priority level is serviced. If interrupt requests of the same priority level
are received simultaneously, an internal polling sequence determines which request is
serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
Table 12. IE Register
IE - Interrupt Enable Register (A8h)
7
6
5
4
3
2
1
0
EA
-
ET2
ES
ET1
EX1
ET0
EX0
Bit
Number
Bit
Mnemonic
Description
Enable All interrupt bit
Clear to disable all interrupts.
Set to enable all interrupts.
If EA=1, each interrupt source is individually enabled or disabled by setting or
clearing its own interrupt enable bit.
7
EA
6
-
5
ET2
Timer 2 overflow interrupt Enable bit
Clear to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.
4
ES
Serial port Enable bit
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
3
ET1
Timer 1 overflow interrupt Enable bit
Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
2
EX1
External interrupt 1 Enable bit
Clear to disable external interrupt 1.
Set to enable external interrupt 1.
1
ET0
Timer 0 overflow interrupt Enable bit
Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0
EX0
External interrupt 0 Enable bit
Clear to disable external interrupt 0.
Set to enable external interrupt 0.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = 0X00 0000b
Bit addressable
26
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
Table 13. IP Register
IP - Interrupt Priority Register (B8h)
7
6
5
4
3
2
1
0
-
-
PT2
PS
PT1
PX1
PT0
PX0
Bit
Number
Bit
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
PT2
Timer 2 overflow interrupt Priority bit
Refer to PT2H for priority level.
4
PS
Serial port Priority bit
Refer to PSH for priority level.
3
PT1
Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
2
PX1
External interrupt 1 Priority bit
Refer to PX1H for priority level.
1
PT0
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
0
PX0
External interrupt 0 Priority bit
Refer to PX0H for priority level.
Description
Reset Value = XX00 0000b
Bit addressable
27
4233H–8051–02/08
Table 14. IPH Register
IPH - Interrupt Priority High Register (B7h)
7
6
5
4
3
2
1
0
-
-
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
Bit
Number
Bit
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
4
3
2
1
0
Description
PT2H
Timer 2 overflow interrupt Priority High bit
PT2H
PT2 Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PSH
Serial port Priority High bit
PS Priority Level
PSH
0
0
Lowest
0
1
1
0
1
1
Highest
PT1H
Timer 1 overflow interrupt Priority High bit
PT1 Priority Level
PT1H
0
0
Lowest
0
1
1
0
1
1
Highest
PX1H
External interrupt 1 Priority High bit
PX1H
PX1 Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PT0H
Timer 0 overflow interrupt Priority High bit
PT0H
PT0 Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
PX0H
External interrupt 0 Priority High bit
PX0H
PX0 Priority Level
0
0
Lowest
0
1
1
0
1
1
Highest
Reset Value = XX00 0000b
Not bit addressable
28
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
Idle Mode
An instruction that sets PCON.0 causes that to be the last instruction executed before
going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the
CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirely: the Stack Pointer, Program Counter, Program Status Word,
Accumulator and all other registers maintain their data during Idle. The port pins hold
the logical states they had at the time Idle was activated.
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause
PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to be executed will be the one following
the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured during normal operation or during an Idle. For example, an instruction that activates Idle
can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt
service routine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock
oscillator is still running, the hardware reset needs to be held active for only two
machine cycles (24 oscillator periods) to complete the reset.
Power-Down Mode
To save maximum power, a power-down mode can be invoked by software (Refer to
Table 10., PCON register).
In power-down mode, the oscillator is stopped and the instruction that invoked powerdown mode is the last instruction executed. The internal RAM and SFRs retain their
value until the power-down mode is terminated. VCC can be lowered to save further
power. Either a hardware reset or an external interrupt can cause an exit from powerdown. To properly terminate power-down, the reset or external interrupt should not be
executed before VCC is restored to its normal operating level and must be held active
long enough for the oscillator to restart and stabilize.
Only external interrupts INT0 and INT1 are useful to exit from power-down. For that,
interrupt must be enabled and configured as level or edge sensitive interrupt input.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as
detailed in Figure 11. When both interrupts are enabled, the oscillator restarts as soon
as one of the two inputs is held low and power down exit will be completed when the first
input will be released. In this case the higher priority interrupt service routine is executed.
Once the interrupt is serviced, the next instruction to be executed after RETI will be the
one following the instruction that put T8xC5101/02 into power-down mode.
Figure 11. Power-Down Exit Waveform
INT0
INT1
XTAL1
Active phase
Power-down phase
Oscillator restart phase
Active phase
Exit from power-down by reset redefines all the SFRs, exit from power-down by external
interrupt does no affect the SFRs.
29
4233H–8051–02/08
Exit from power-down by either reset or external interrupt does not affect the internal
RAM content.
Note:
If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence
is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and
idle mode is not entered.
Table 15. State of Ports During Idle and Power-down Modes
30
Mode
Program Memory
PORT1
PORT3
PORT4
Idle
Internal
Port Data
Port Data
Port Data
Power Down
Internal
Port Data
Port Data
Port Data
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
Reduced EMI Mode
As there is no Port 0 nor Port 2 outputted from this device, there is no need to output
ALE. EMI are then reduced intrinsically.
The bit which controls ALE disabling in Rx devices is A0 (bit 0) in register AUXR. As
explained earlier for bit EXTRAM, writing any value to AO will have no effect on the
device behavior.
Table 16. AUXR Register
AUXR - Auxiliary Register (8Eh)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
EXTRAM
AO
Bit Number
Bit
Mnemonic
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1
EXTRAM
EXTRAM bit
Writing to this bit will have no effect. The value read from this bit is
indeterminate.
0
AO
ALE Output bit
Writing to this bit will have no effect. The value read from this bit is
indeterminate.
Description
Reset Value = XXXX XX00b
Not bit addressable
31
4233H–8051–02/08
T8xC5101/02
T83C5101/02 ROM
ROM Structure
The T83C5101/02 ROM memory is divided in three different arrays:
•
the code array
–
T83C5101: 16 KB
–
T83C5102: 8 KB
•
the encryption array: 64 bytes
•
the signature array: 4 bytes
ROM Lock System
The program Lock system, when programmed, protects the on-chip program against
software piracy.
Encryption Array
Within the ROM array are 64 bytes of encryption array. Every time a byte is addressed
during program verify, 6 address lines are used to select a byte of the encryption array.
This byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted
verify byte. The algorithm, with the encryption array in the unprogrammed state, will
return the code in its original, unmodified form.
When using the encryption array, one important factor needs to be considered. If a byte
has the value FFh, verifying the byte will produce the encryption byte value. If a large
block (>64 bytes) of code is left unprogrammed, a verification routine will display the
content of the encryption array. For this reason all the unused code bytes should be programmed with random values.
Program Lock Bits
The lock bits when programmed according to Table 17. will provide different level of protection for the on-chip code and data.
Table 17. Program Lock Bits
Program Lock Bits
Security
level
LB1
LB2
LB3
1
U
U
U
No program lock features enabled. Code verify will still be
encrypted by the encryption array if programmed.
2
P
U
U
Not applicable as usually this protection deals with executing
MOVC from external memory (impossible) and sampling EA pin
(doesn’t exist any more)
3
U
P
U
Protection Description
Verify disable.
This security level is available because ROM integrity will be
verified thanks to another method.
U: unprogrammed
P: programmed
Signature Bytes
The T8xC5101/02 family contains 4 factory programmed signatures bytes. To read
these bytes, perform the process described in sections Section “Definition of Terms”
and Section “Signature Bytes”.
Verify Algorithm
Refer to Section “Verifying Algorithm”, page 36
32
4233H–8051–02/08
T8xC5101/02
T87C5101 EPROM
EPROM Structure
The T87C5101 EPROM is divided into two different arrays:
•
the code array: 16 KB
•
the encryption array: 64 bytes
In addition a third non programmable array is implemented:
•
the signature array: 4 bytes.
EPROM Lock System
The program Lock system, when programmed, protects the on-chip program against
software piracy.
Encryption Array
Within the EPROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time a byte is addressed during program verify, 6 address
lines are used to select a byte of the encryption array. This byte is then exclusiveNOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm,
with the encryption array in the unprogrammed state, will return the code in its original,
unmodified form.
When using the encryption array, one important factor needs to be considered. If a byte
has the value FFh, verifying the byte will produce the encryption byte value. If a large
block (>64 bytes) of code is left unprogrammed, a verification routine will display the
content of the encryption array. For this reason all the unused code bytes should be programmed with random values.
Program Lock Bits
The three lock bits, when programmed according to Table 18, will provide different level
of protection for the on-chip code and data.
Table 18. Program Lock Bits
Program Lock Bits
Security
level
LB1
LB2
LB3
1
U
U
U
No program lock features enabled. Code verify will still be
encrypted by the encryption array if programmed.
2
P
U
U
Further programming of the program memory is disabled.
3
U
P
U
Same as security level 2 + verify disabled.
4
U
U
P
Not applicable as usually this protection deals with external
execution, which is impossible with this device.
Protection Description
U: unprogrammed,
P: programmed
WARNING: Security level 2 and higher should only be programmed after EPROM
verification.
Signature Bytes
The T8xC5101/02 family contains 4 factory programmed signatures bytes. To read
these bytes, perform the process described in section and .
33
4233H–8051–02/08
EPROM Programming
In order to program and verify the EPROM or to read the signature bytes, the T87C5101
is placed in specific test modes (See Figure 12.).
Set-up Modes
Control and program signals must be held at the levels indicated in Table 19.
Address and Control Lines: RST, TEST, Port 3
Definition of Terms
Data Lines:
Port 1
Program Signals: VPP, PROG
Table 19. EPROM Set-Up Modes
Mode
RST
TEST
Program Code data
1
0/1
Verify Code data
1
0/1
Program Encryption
Array Address 0-3Fh
1
0/1
Read Signature Bytes
1
0
Program Lock bit 1
1
0/1
Program Lock bit 2
1
0/1
Program Lock bit 3
NA
NA
NA
1
0
1
Read lock bits
PROG
VPP
P3.7
P3.6
P3.3
P3.2
P3.1
1
1
1
1
0
1
1
0
0
0
1
0
1
1
0
0
0
0
0
0
1
1
1
1
1
0
0
1
1
1
NA
NA
NA
NA
NA
NA
0
1
0
0
0
0
0/
12.75V
1
0/1
0/
12.75V
1
0
0/
12.75V
0/
12.75V
NA: not applicable
Figure 12. Programming and Verifying Modes Configuration
TCODE = Test code, ADH = address high, ADL = address low
5V
’0’/’1’/VPP
’1’
’0’/’1’
TCODE
/ ADH/ADL
4 to 12 MHz
RST
VPP
PROG
TEST
RST
’0’/’1’
’1’
’0’/’1’
VPP
VCC
data
P1
PROG
TEST
P3
TCODE
/ ADH/ADL
P3
XTAL1
4 to 12 MHz
XTAL1
Programming Configuration
34
5V
’1’
VCC
data
P1
Verifying Configuration
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
EPROM Programming and
Verification Characteristics
TA = 21°C to 27°C; VSS = 0V; VCC = 5V ± 10% while programming. VCC = operating
range while verifying.
Table 20. EPROM Programming Parameters
Symbol
Parameter
Min
Max
Units
VPP
Programming Supply Voltage
12.5
13
V
IPP
Programming Supply Current
75
mA
12
MHz
Oscillator Frequency
1/TCLCL
Programming Algorithm
4
•
step 1: VPP and TEST low, present T code for programming on P3 and raise VPP to
12.75V
•
step 2: present Address High on P3 and pulse TEST high
•
step 3: present address Low on P3 and data on P1
•
step 4: pulse PROG low
•
step 5: back to step 3 if the next byte to program is in the same 256 byte page
OR
•
step 5: back to step 2 if the next byte to program is in a different page
Figure 13. Programming Signals Waveform
tCVPX
tPHCX
VPP=12.75V
tPHTX
VPP
tCVTX
tTHTX
tTLCX
TEST
tGHCX
tDVGX
tCVGX
tGLGX
tGHDX
PROG
P3
TCode prog
ADH#1
ADL #1
ADL #2
Data #1
Data #2
ADL#3
ADH#2
tPHDZ
P1
Data#3
Table 21. Programming Algorithm Parameters
12 MHz
Symbol
tOSC
tCVPX
Parameter
Oscillator period
Code input Valid to VPP rising edge setup time
Formula
Min
36 tOSC
3
Max
Unit
83.3
ns
µs
35
4233H–8051–02/08
Table 21. Programming Algorithm Parameters (Continued)
12 MHz
Symbol
Verifying Algorithm
Parameter
Formula
Min
Max
Unit
tPHCX
Code input valid from VPP High hold time
1 tOSC
83.3
ns
tPHTX
Test input valid from VPP High hold time
1 tOSC
83.3
ns
tTHTX
Test High pulse width
36 tOSC
3
µs
tCVTX
Address high Valid to Test falling edge setup time
36 tOSC
3
µs
tTLCX
Address input Valid from Test falling edge hold time
1 tOSC
83.3
ns
tPHDZ
Data output Hi-Z from VPP high delay
tGLGX
Prog Low pulse width
tCVGX
Address valid to Prog falling edge setup time
36 tOSC
3
µs
tDVGX
Data input Valid to Prog falling edge setup time
36 tOSC
3
µs
tGHCX
Address valid from Prog rising edge hold time
1 tOSC
83.3
ns
tGHDX
Data input valid from Prog rising edge hold time
1 tOSC
83.3
ns
0
90
110
µs
•
step 1: VPP and TEST low, present T code for verification on P3 and Raise VPP to
Vcc
•
step 2: present address High and pulse TEST high
•
step 3: present address Low on P3 and read data on P1
•
step 4: back to step 3 if the next byte is in the same 256 byte page
OR
•
step 4: back to step 2 if the next byte to program is in a different page
Figure 14. Verifying Signals Waveform
tCVPX
tPHCX
VPP high is 5V
tPHTX
VPP
tCVTX
tTHTX
tTLCX
TEST
PROG
P3
TCode
ADH#1*
ADL #1
tCVDV
P1
Note:
36
Data #1
ADL #2
ADH#2*
ADL#3
tCXDX
Data #2
Data#3
* ADH is egal to 0 when addressing signature bytes
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
Table 22. Verify Algorithm Parameters
12 MHz
Symbol Parameter
Programming/Verify
Algorithm
Formula
Min
Max
Unit
83.3
ns
tOSC
Oscillator period
tCVPX
Code input Valid to VPP rising edge setup time
36 tOSC
3
µs
tPHCX
Code input valid from VPP High hold time
1 tOSC
83.3
ns
tPHTX
Test input valid from VPP High hold time
1 tOSC
83.3
ns
tTHTX
Test High pulse width
36 tOSC
3
µs
tCVTX
Address high Valid to Test falling edge setup time
36 tOSC
3
µs
tTLCX
Address input Valid from Test falling edge hold time
1 tOSC
83.3
ns
tCVDV
Address Valid to Data output Valid delay
36 tOSC
tCXDX
Data valid from Address Invalid hold time
3
µs
0
•
step 1: VPP and TEST low, present T code for programming on P3 and raise VPP to
12.75V
•
step 2: present Address High on P3 and pulse TEST high
•
step 3: present address Low on P3 and data on P1
•
step 4: pulse PROG low
•
step 5: present T code for verifying on P3 and lower VPP to 0V
•
step 6: read previous data
•
step 7: present T code for programming on P3 and raise VPP to 12.75V
•
step 8: goto step 3 if the next byte to program is in the same 256 byte page
OR
•
step 8: goto step 2 if the next byte to program is in a different page
37
4233H–8051–02/08
Figure 15. Programming/Verifying Signals Waveform
VPP=12.75V
tCVPX
tPPGX
tPHTX
tGHPX
tPHCX
VPP
tCVTX
tTHTX
tTLCX
TEST
tDVGX
tGHDX
tCVGX
tGLGX
tGHCX
PROG
P3
tTVDV
TCode Prog
ADH#1
ADL#1
TCode Ver
ADL#2
TCode Prog
tPLCX
tTXDX
tPLDX
tPHDZ
Data#1 (in)
P1
Data#1 (out)
Data#2 (in)
Note: after programming, addresses high and low are already latched in the device, and
when switching to verify, the device outputs directly the last written data.
Table 23. Programming/Verifying Signnal’s Wavaform Parameters
12 MHz
Symbol
38
Parameter
Formula
Min
-
Max
Unit
83.3
ns
tOSC
Oscillator period
tCVPX
Code input Valid to VPP rising edge setup time
36 tOSC
3
µs
tPHCX
Code input valid from VPP High hold time
1 tOSC
83.3
ns
tPHTX
Test input valid from VPP High hold time
1 tOSC
83.3
ns
tTHTX
Test High pulse width
36 tOSC
3
µs
tCVTX
Address high Valid to Test falling edge setup time
36 tOSC
3
µs
tTLCX
Address input Valid from Test falling edge hold time
1 tOSC
83.3
ns
tPHDZ
Data output Hi-Z from VPP high delay
tGLGX
Prog Low pulse width
tCVGX
Address valid to Prog falling edge setup time
36 tOSC
3
µs
tDVGX
Data input Valid to Prog falling edge setup time
36 tOSC
3
µs
tGHCX
Address valid from Prog rising edge hold time
1 tOSC
83.3
ns
tGHDX
Data input valid from Prog High hold time
1 tOSC
83.3
ns
tGHPX
VPP on VPP pin from Prog High hold time
36 tOSC
3
µs
0
90
110
µs
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
Table 23. Programming/Verifying Signnal’s Wavaform Parameters (Continued)
12 MHz
Symbol
Parameter
Formula
Min
Max
Unit
3
µs
tTXDX
Data output valid from T code invalid hold time
0
tTVDV
Data output valid from T code valid delay
36 tOSC
tPLCX
Address valid from VPP falling edge hold time
36 tOSC
3
µs
tPPGX
VPP on VPP pin to Prog falling edge setup time
36 tOSC
3
µs
tPLDX
Data output from VPP Low delay
0
µs
Lock Bits Programming and
Verification
Programming:
Verification:
•
step 1: VPP and TEST low, present T code for Lock bits programming on P3 and
raise VPP to 12.75V
•
step 2: pulse PROG low
•
step 1: VPP and TEST low, present T code for Lock bits verification
•
step 2: read data
Figure 16. Lock Bits Programming Signals Waveform and Lock Bits Verifying Signals Waveform
VPP=12.75V
tCVPX
tPHCX
tPPGX
tGHPX
VPP
TEST
tGLGX
PROG
P3
tTVDV
T code
T code
tPHDZ
tPLCV
tTXDX
tPLDX
data out
P1
tPLDV
Table 24. Lock Bits Programming Signals Waveform and Lock Bits Verifying Signals
Waveform Parameters
12 MHz
Symbol
tOSC
Parameter
Oscillator period
Formula
-
Min
Max
Unit
83.3
ns
39
4233H–8051–02/08
Table 24. Lock Bits Programming Signals Waveform and Lock Bits Verifying Signals
Waveform Parameters (Continued)
12 MHz
Symbol
Parameter
Formula
Min
tCVPX
Code input valid to VPP rising edge setup time
36 tOSC
3
µs
tPHCX
Code input valid from VPP high hold time
1 tOSC
83.3
ns
tPPGX
VPP on VPP pin to PROG Low setup time
36 tOSC
3
µs
tGLGX
Prog Low pulse width
tGHPX
VPP on VPP pin from PROG High hold time
36 tOSC
tPLDV
Data Output Valid from VPP Low delay
36 tOSC
tPLDX
Data output from VPP Low delay
tTVDV
Data output valid from T code valid delay
tTXDX
Data output valid from T code invalid hold time
tPHDZ
Data output Hi-Z from VPP high delay
tPLCV
VPP low to T code valid setup time
90
Max
110
3
Unit
µs
µs
3
µs
3
µs
0
36 tOSC
0
0
36 tOSC
•
VPP pin in driven:
•
to 0V when P3 contains the test code
•
to 5V when P3 contains high order or low order addresses
•
to VPP during programming cycled
•
Test pin is driven:
•
to 5V when P3 contains high order address
•
to 0V in the other cases
3
µs
EPROM Erasure
(Windowed Packages
Only)
Erasing the EPROM erases the code array, the encryption array and the lock bits returning the parts to full functionality.
Erasure Characteristics
The recommended erasure procedure is exposure to ultraviolet light (at 2537 Å) to an
integrated dose at least 15 W-sec/cm2. Exposing the EPROM to an ultraviolet lamp of
12,000 µW/cm2 rating for 30 minutes, at a distance of about 25 mm, should be sufficient.
An exposure of 1 hour is recommended with most of standard erasers.
Erasure leaves all the EPROM cells in a 1’s state (FF).
Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately 4,000 Å. Since sunlight and fluorescent lighting have
wavelengths in this range, exposure to these light sources over an extended time (about
1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this type of exposure, it is suggested
that an opaque label be placed over the window.
40
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
Signature Bytes
Signature Bytes Content
The T8xC5101/02 has four signature bytes in location 30h, 31h, 60h and 61h. To read
these bytes follow the procedure for EPROM verify but activate the control lines provided in Table 19. for Read Signature Bytes. Table 25. shows the content of the
signature byte for the T8xC5101/02.
Table 25. Signature Bytes Content
Location
Contents
Comment
30h
58h
Manufacturer Code: Atmel
31h
57h
Family Code: C51 X2
60h
3Bh
Product name: T83C5101/02 8K or 16K ROM version
60h
BBh
Product name: T87C5101 16K OTP version
61h
EFh
Product revision number: T8xC5101/02 Rev.0
41
4233H–8051–02/08
T8xC5101/02
Electrical Characteristics
Table 26. Absolute Maximum Ratings
C = commercial......................................................0°C to 70°C
I = industrial ........................................................-40°C to 85°C
Storage Temperature .................................... -65°C to + 150°C
Voltage on VCC to VSS ........................................-0.5 V to + 7 V
Voltage on VPP to VSS ......................................-0.5 V to + 13 V
Voltage on Any Pin to VSS ........................-0.5 V to VCC + 0.5 V
*NOTICE:
Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Power Dissipation value is based on the maximum allowable die temperature and the thermal
resistance of the package.
Power Dissipation ........................................................... 1 W(2)
Power Consumption
Measurement
Since the introduction of the first C51 devices, every manufacturer made operating Icc
measurements under reset, which made sense for the designs were the CPU was running under reset. In Atmel new devices, the CPU is no more active during reset, so the
power consumption is very low but is not really representative of what will happen in the
customer system. That’s why, while keeping measurements under Reset, Atmel presents a new way to measure the operating Icc:
Using an internal test ROM, the following code is executed:
Label:
SJMP Label (80 FE)
Ports 1, 3, 4 are disconnected, RST = Vss, XTAL2 is not connected and XTAL1 is driven
by the clock.
This is much more representative of the real operating Icc.
42
4233H–8051–02/08
DC Parameters for
Standard Voltage
TA = 0°C to +70°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz.
TA = -40°C to +85°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz.
Table 27. DC Parameters in Standard Voltage
Symbol
Parameter
Min
VIL
Input Low Voltage
VIH
Input High Voltage except XTAL1, RST
VIH1
Input High Voltage, XTAL1, RST
VOL
Output Low Voltage, ports 1, 3, 4.2-4.5 (6)
VOL1
VOH
RRST
Output High Voltage, ports 1, 3, 4.2-4.5 (6)
RST Pulldown Resistor
IIL
Logical 0 Input Current ports 1, 3 and 4
ILI
Input Leakage Current
ITL
Logical 1 to 0 Transition Current, ports 1, 3
CIO
Capacitance of I/O Buffer
IPD
Power Down Current
ICC
under
RESET
ICC
operating
Max
Unit
-0.5
0.2 VCC - 0.1
V
0.2 VCC + 0.9
VCC + 0.5
V
0.7 VCC
VCC + 0.5
V
Output Low Voltage, port 4.0-4.1 (6)
Power Supply Current Maximum values, X1
mode: (7)
Typ
0.76(5)
0.3
V
IOL = 100 µA
0.45
V
IOL = 1.6 mA
1.0
V
IOL = 3.5 mA
V
IOL = 10.0 mA
0.5
V
IOL = 6.0 mA
1.0
V
IOL = 12.0 mA
VCC - 0.3
V
VCC - 0.7
V
VCC - 1.5
V
50
90 (5)
200
-50
µA
±10
µA
idle
Power Supply Current Maximum values, X1
mode: (7)
IOH = -60 µA
VCC = 5 V ± 10%
Vin = 0.45 V, port 1 & 3
Vin = 0.45 V, port 4
0.45 V < Vin < VCC
Vin = 2.0 V, port 1 & 3
µA
10
pF
Fc = 1 MHz
TA = 25°C
20 (5)
50
µA
2.0 V < VCC < 5.5 V(3)
to be
confirmed
1 + 0.4 Freq
(MHz)
@12MHz 5.8
to be
confirmed
3 + 0.6 Freq
(MHz)
@12MHz 10.2
mA
mA
@16MHz 12.6
ICC
IOH = -30 µA
TBD
@16MHz 7.4
Power Supply Current Maximum values, X1
mode: (7)
IOH = -10 µA
kΩ
TBD
-650
to be
confirmed
Test Conditions
to be
confirmed
0.25+0.3 Freq
(MHz)
@12MHz 3.9
mA
Vin = 2.0 V, port 4
VCC = 5.5 V(1)
VCC = 5.5 V(8)
VCC = 5.5 V(2)
@16MHz 5.1
43
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
DC Parameters for Low
Voltage
TA = 0°C to +70°C; VSS = 0 V; VCC = 2.7 V to 5.5 V; F = 0 to 30 MHz.
TA = -40°C to +85°C; VSS = 0 V; VCC = 2.7 V to 5.5 V; F = 0 to 30 MHz.
Table 28. DC Parameters for Low Voltage
Symbol
Parameter
Min
VIL
Input Low Voltage
VIH
Input High Voltage except XTAL1, RST
VIH1
Input High Voltage, XTAL1, RST
VOL
Output Low Voltage, ports 1, 3, 4.2-4.5 (6)
Typ
Max
Unit
-0.5
0.2 VCC - 0.1
V
0.2 VCC + 0.9
VCC + 0.5
V
0.7 VCC
VCC + 0.5
V
0.45
V
IOL = 0.8 mA
V
V
IOL = 10.0 mA
IOL = 4.8 mA
V
IOH = -10 µA
0.83(5)
(6)
VOL1
Output Low Voltage, port 4.0-4.1
VOH
Output High Voltage, ports 1, 3, 4.2-4.5 (6)
IIL
Logical 0 Input Current ports 1, 2 and 3
ILI
Input Leakage Current
ITL
Logical 1 to 0 Transition Current, ports 1, 3
RRST
RST Pulldown Resistor
CIO
Capacitance of I/O Buffer
IPD
Power Down Current
ICC
under
RESET
ICC
operating
Power Supply Current Maximum values, X1
mode: (7)
0.5
0.9 VCC
-50
TBD
µA
±10
µA
-650
50
to be
confirmed
90 (5)
TBD
µA
200
kΩ
10
pF
20 (5)
50
(5)
30
10
to be
confirmed
1 + 0.2 Freq
(MHz)
@12MHz 3.4
idle
mA
Vin = 0.45 V, port 1 & 3
Vin = 0.45 V, port 4
0.45 V < Vin < VCC
Vin = 2.0 V, port 1 & 3
Vin = 2.0 V, port 4
Fc = 1 MHz
TA = 25°C
VCC = 2.0 V to 5.5 V(3)
VCC = 2.0 V to 3.3 V(3)
VCC = 3.3 V(1)
@16MHz 4.2
Power Supply Current Maximum values, X1
mode: (7)
to be
confirmed
1 + 0.3 Freq
(MHz)
@12MHz 4.6
@16MHz 5.8
ICC
µA
Test Conditions
Power Supply Current Maximum values, X1
mode: (7)
to be
confirmed
mA
VCC = 3.3 V(8)
0.15 Freq
(MHz) + 0.2
@12MHz 2
mA
VCC = 3.3 V(2)
@16MHz 2.6
Notes:
1. ICC under reset is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 21.), VIL =
VSS + 0.5 V, VIH = VCC - 0.5V; XTAL2 N.C.; VPP = RST = VCC. ICC would be slightly higher if a crystal oscillator used.
2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC 0.5 V; XTAL2 N.C; VPP = RST = VSS (see Figure 19.).
3. Power Down ICC is measured with all output pins disconnected; VPP = VSS; XTAL2 NC.; RST = VSS (see Figure 20).
4. Not Applicable
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
44
4233H–8051–02/08
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 6 and 8-bit port:
Port 4.0 + 4.1: 20 mA
Port 4.2 to 4.5: 8 mA
Ports 1 and 3: 15 mA
Maximum total IOL for all output pins: 58 mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
7. For other values, please contact your sales office.
8. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 21.), VIL =
VSS + 0.5 V,
VIH = VCC - 0.5V; XTAL2 N.C.; VPP= VCC; RST = VSS. The internal ROM runs the code 80 FE (label: SJMP label). ICC would
be slightly higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is the
worst case.
Figure 17. ICC Test Condition, under reset
VCC
ICC
VCC
VCC
VPP
RST
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 18. Operating ICC Test Condition
VCC
ICC
VCC
Reset = Vss after a high pulse
during at least 24 clock cycles
RST
(NC)
CLOCK
SIGNAL
45
XTAL2
XTAL1
VSS
VPP
All other pins are disconnected.
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
Figure 19. ICC Test Condition, Idle Mode
VCC
ICC
VCC
Reset = Vss after a high pulse
during at least 24 clock cycles
VPP
RST
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 20. ICC Test Condition, Power-Down Mode
VCC
ICC
VCC
Reset = Vss after a high pulse
during at least 24 clock cycles
(NC)
RST
VPP
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 21. Clock Signal Waveform for ICC Tests in Active and Idle Modes
VCC-0.5V
0.45V
TCLCH
TCHCL
TCLCH = TCHCL = 5ns.
0.7VCC
0.2VCC-0.1
46
4233H–8051–02/08
AC Parameters
Explanation of the AC
Symbols
Each timing symbol has 5 characters. The first character is always a “T” (stands for
Time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and
what they stand for.
Example:TXHDV = Time from clock rising edge to input data valid.
TA = 0 to +70°C (commercial temperature range); V SS = 0 V; V CC = 5 V ± 10%; -V
ranges.
TA = 0 to +70°C (commercial temperature range); VSS = 0 V; 2.7 V < VCC < 5.5 V; -L
range.
TA = -40°C to +85°C (industrial temperature range); VSS = 0 V; 2.7 V < VCC < 5.5 V; -L
range.
Table 29. gives the maximum applicable load capacitance for Port 1, 3 and 4. Timings
will be guaranteed if these capacitances are respected. Higher capacitance values can
be used, but timings will then be degraded.
Table 29. Load Capacitance versus speed range, in pF
Port 1, 3 & 4
-V
-L
50
80
Table 31 gives the description of each AC symbols.
Table 31 gives for each range the AC parameter.
Table 32 gives the frequency derating formula of the AC parameter. To calculate each
AC symbols, take the x value corresponding to the speed grade you need (-V or -L) and
replace this value in the formula. Values of the frequency must be limited to the corresponding speed grade:
Table 30. Max frequency for derating formula regarding the speed grade
-V X1 mode
-V X2 mode
-L X1 mode
-L X2 mode
Freq (MHz)
40
33
40
20
T (ns)
25
30
25
50
Example:
TXHDV in X2 mode for a -V part at 20 MHz (T = 1/20E6 = 50 ns):
x= 133 (Table 32.)
T= 50ns
TXHDV= 5T - x = 5 x 50 - 133 = 117ns
47
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
Serial Port Timing - Shift
Register Mode
Symbol
Parameter
TXLXL
Serial port clock cycle time
TQVHX
Output data set-up to clock rising edge
TXHQX
Output data hold after clock rising edge
TXHDX
Input data hold after clock rising edge
TXHDV
Clock rising edge to input data valid
Table 31. AC Parameters for a Fix Clock
-V
-V
-L
-L
X2 mode
standard mode
40 MHz
X2 mode
standard mode
20 MHz
40 MHz
33 MHz
Speed
66 MHz equiv.
Max
40 MHz equiv.
Symbol
Min
TXLXL
180
300
300
300
ns
TQVHX
100
200
200
200
ns
TXHQX
10
30
30
30
ns
TXHDX
0
0
0
0
ns
TXHDV
Min
17
Max
Min
117
Max
Units
Min
Max
117
117
ns
Table 32. AC Parameters for a Variable Clock: derating formula
Symbol
Type
Standard
Clock
X2 Clock
TXLXL
Min
12 T
6T
TQVHX
Min
10 T - x
5T-x
50
50
ns
TXHQX
Min
2T-x
T-x
20
20
ns
TXHDX
Min
x
x
0
0
ns
TXHDV
Max
10 T - x
5 T- x
133
133
ns
-V
-L
Units
ns
48
4233H–8051–02/08
Shift Register Timing
Waveforms
Figure 22. Shift Register Timing Waveforms
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
TXLXL
CLOCK
TXHQX
TQVXH
0
OUTPUT DATA
1
2
INPUT DATA
4
5
6
7
TXHDX
TXHDV
WRITE to SBUF
3
VALID
VALID
SET TI
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
CLEAR RI
External Clock Drive
Characteristics (XTAL1)
Symbol
Max
Units
Oscillator Period
25
ns
TCHCX
High Time
5
ns
TCLCX
Low Time
5
ns
TCLCH
Rise Time
5
ns
TCHCL
Fall Time
5
ns
60
%
Cyclic ratio in X2 mode
40
Figure 23. External Clock Drive Waveforms
VCC-0.5 V
0.45 V
AC Testing Input/Output
Waveforms
Min
TCLCL
TCHCX/TCLCX
External Clock Drive
Waveforms
Parameter
0.7VCC
0.2VCC-0.1 V
TCHCL
TCLCX
TCHCX
TCLCH
TCLCL
Figure 24. AC Testing Input/Output Waveforms
VCC-0.5 V
INPUT/OUTPUT
0.45 V
0.2VCC+0.9
0.2VCC-0.1
AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”.
Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”.
49
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
Figure 25. Float Waveforms
Float Waveforms
FLOAT
VOH-0.1 V VLOAD
VLOAD+0.1 V
VLOAD-0.1 V
VOL+0.1 V
For timing purposes as port pin is no longer floating when a 100 mV change from load
voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level
occurs. IOL/IOH ≥ ± 20mA.
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2
divided by two.
Clock Waveforms
Figure 26. Clock Waveforms
INTERNAL
CLOCK
STATE4
STATE5
STATE6
STATE1
STATE2
P1P2
P1P2
P1P2
P1P2
P1P2
STATE3
P1P2
STATE4
P1P2
STATE5
P1P2
XTAL2
PORT OPERATION
OLD DATA
NEW DATA
MOV DEST PORT (P1, P3, P4)
(INCLUDES INT0, INT1, TO, T1)
P1, P3, P4 PINS SAMPLED
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
RXD SAMPLED
P1, P3, P4 PINS SAMPLED
RXD SAMPLED
This diagram indicates when signals are clocked internally. The time it takes the signals
to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is
dependent on variables such as temperature and pin loading. Propagation also varies
from output to output and component. Typically though (TA=25°C fully loaded) RD and
WR propagation delays are approximately 50ns. The other signals are typically 85 ns.
Propagation delays are incorporated in the AC specifications.
50
4233H–8051–02/08
T8xC5101/02
Ordering Information
Table 33. Maximum Clock Frequency
Code
-V
-L
Unit
Standard Mode, oscillator frequency
40
Standard Mode, internal frequency
40
40
40
MHz
33
20
66
40
X2 Mode, oscillator frequency
X2 Mode, internal equivalent
frequency
MHz
Table 34. Possible Order Entries
Part Number
Memory Size
Supply Voltage
Temperature
Range
Speed (MHz)
Package
Packing
T83C5101xxx-3ZSCL
T83C5101xxx-3ZSCV
T83C5101xxx-3ZSIL
T83C5101xxx-TDSCL
T83C5101xxx-TDSCV
T83C5101xxx-TDSIL
T83C5101xxx-TDRCL
T83C5101xxx-TDRCV
T83C5101xxx-TDRIL
T83C5101xxx-TISCL
T83C5101xxx-TISCV
OBSOLETE
T83C5101xxx-TISIL
T83C5101xxx-TIRCL
T83C5101xxx-TIRCV
T83C5101xxx-TIRIL
T83C5101xxx-ICUCL
T83C5101xxx-ICUCV
T83C5101xxx-ICUIL
T83C5101xxx-ICFCL
T83C5101xxx-ICFCV
T83C5101xxx-ICFIL
51
4233H–8051–02/08
Table 34. Possible Order Entries (Continued)
Part Number
Memory Size
Supply Voltage
Temperature
Range
Speed (MHz)
Package
Packing
T83C5102xxx-3ZSCL
T83C5102xxx-3ZSCV
T83C5102xxx-3ZSIL
T83C5102xxx-TDSCL
T83C5102xxx-TDSCV
T83C5102xxx-TDSIL
T83C5102xxx-TDRCL
T83C5102xxx-TDRCV
T83C5102xxx-TDRIL
T83C5102xxx-TISCL
T83C5102xxx-TISCV
OBSOLETE
T83C5102xxx-TISIL
T83C5102xxx-TIRCL
T83C5102xxx-TIRCV
T83C5102xxx-TIRIL
T83C5102xxx-ICUCL
T83C5102xxx-ICUCV
T83C5102xxx-ICUIL
T83C5102xxx-ICFCL
T83C5102xxx-ICFCV
T83C5102xxx-ICFIL
52
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
Table 34. Possible Order Entries (Continued)
Part Number
Memory Size
Supply Voltage
Temperature
Range
Speed (MHz)
Package
Packing
T87C5101xxx-3ZSCL
T87C5101xxx-3ZSCV
T87C5101xxx-3ZSIL
T87C5101xxx-TDSCL
T87C5101xxx-TDSCV
T87C5101xxx-TDSIL
T87C5101-TDRCL
T87C5101-TDRCV
T87C5101-TDRIL
T87C5101-TISCL
T87C5101-TISCV
OBSOLETE
T87C5101-TISIL
T87C5101-TIRCL
T87C5101-TIRCV
T87C5101-TIRIL
T87C5101-ICUCL
T87C5101-ICUCV
T87C5101-ICUIL
T87C5101-ICFCL
T87C5101-ICFCV
T87C5101-ICFIL
53
4233H–8051–02/08
Package Drawings
DIL24
54
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
SO24
55
4233H–8051–02/08
SO28
56
T8xC5101/02
4233H–8051–02/08
T8xC5101/02
SSOP24
57
4233H–8051–02/08
Atmel Headquarters
Atmel Operations
Corporate Headquarters
Memory
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 487-2600
Europe
Atmel SarL
Route des Arsenaux 41
Casa Postale 80
CH-1705 Fribourg
Switzerland
TEL (41) 26-426-5555
FAX (41) 26-426-5500
Asia
Atmel Asia, Ltd.
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimhatsui
East Kowloon
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
Japan
Atmel Japan K.K.
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Atmel Corporate
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 436-4270
FAX 1(408) 436-4314
Microcontrollers
Atmel Corporate
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 436-4270
FAX 1(408) 436-4314
Atmel Nantes
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
TEL (33) 2-40-18-18-18
FAX (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
Atmel Rousset
Zone Industrielle
13106 Rousset Cedex, France
TEL (33) 4-42-53-60-00
FAX (33) 4-42-53-60-01
RF/Automotive
Atmel Heilbronn
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
TEL (49) 71-31-67-0
FAX (49) 71-31-67-2340
Atmel Colorado Springs
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Atmel Grenoble
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex,
France
TEL (33) 4-76-58-30-00
FAX (33) 4-76-58-34-80
Atmel Colorado Springs
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Atmel Smart Card ICs
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
TEL (44) 1355-803-000
FAX (44) 1355-242-743
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
© 2008 Atmel Corporation. All rights reserved. Atmel ®, logo and combinations thereof, and others are registered trademarks or trademarks of
Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
4233H–8051–02/08
/xM