AD AD9139BCPZRL

16-Bit, 1600 MSPS, TxDAC+ Digital-toAnalog Converter
AD9139
Data Sheet
FEATURES
GENERAL DESCRIPTION
Selectable 1× or 2× interpolation filter
Support input signal bandwidth up to 575 MHz
Very small inherent latency variation: <2 DAC clock cycles
Proprietary low spurious and distortion design
6-carrier GSM ACLR = 79 dBc at 200 MHz IF
SFDR >85 dBc (bandwidth = 300 MHz) at zero IF
Flexible 16-bit LVDS interface
Supports word and byte load
Multiple chip synchronization
Fixed latency and data generator latency compensation
FIFO eases system timing and includes error detection
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
Low power: 700 mW at 1230 MSPS
72-lead LFCSP
The AD9139 is an 16-bit, high dynamic range digital-to-analog
converter (DAC) that provides a sample rate of 1600 MSPS,
permitting a multicarrier generation up to the Nyquist frequency.
The AD9139 TxDAC+® includes features optimized for wideband
communication applications, including 1× and 2× interpolation, a
delay locked loop (DLL) powered high speed interface, sample
error detection, and parity detection. A 3-wire serial port
interface provides for the programming/readback of many
internal parameters. A full-scale output current can be
programmed over a range of 9 mA up to 33 mA. The AD9139 is
available in a 72-lead LFCSP.
PRODUCT HIGHLIGHTS
1.
2.
APPLICATIONS
Wireless communications: 3G/4G and MC-GSM base stations,
wideband repeaters, software defined radios
Wideband communications: point-to-point, LMDS/MMDS
Transmit diversity/MIMO
Instrumentation
Automated test equipment
3.
4.
575 MHz achievable input signal bandwidth.
Advanced low spurious and distortion design techniques
provide high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
Very small inherent latency variation simplifies both software
and hardware design in the system. It allows easy multichip
synchronization for most applications.
Low power architecture improves power efficiency.
FUNCTIONAL BLOCK DIAGRAM
DLL
13-TAP
DCIP/DCIN
AD9139
16
HB1
2×
DACOUTP
DACOUTN
DAC_CLK
GAIN 1
INTERP
MODE CTRL
FIFO CTRL
SED CTRL
INTERFACE CTRL
FRAMEP/PARITYP
FRAMEN/PARITYN
DAC 1
16-BIT
DC OFFSET
CONTROL
GAIN CONTROL
INV SINC
FIFO
8-SAMPLE
SED
D0P/D0N
LVDS DATA
RECEIVER
D15P/D15N
10
REF
AND
BIAS
VREF
FSADJ
INTERNAL CLOCK TIMING AND CONTROL LOGIC
PROGRAMMING
REGISTERS
SERIAL
INPUT/OUTPUT
PORT
POWER-ON
RESET
MULTICHIP
SYNCHRONIZATION
DAC_CLK
CLOCK
MULTIPLIER
DACCLKP
DACCLKN
REF
RCVR
REFP/SYNCP
REFN/SYNCN
11744-001
IRQ2
RESET
TXEN
IRQ1
CS
SCLK
SDIO
SYNC
CLK
RCVR
Figure 1.
Rev. 0
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AD9139
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Multidevice Synchronization and Fixed Latency ....................... 29
Applications ....................................................................................... 1
Very Small Inherent Latency Variation ................................... 29
General Description ......................................................................... 1
Further Reducing the Latency Variation................................. 29
Product Highlights ........................................................................... 1
Synchronization Implementation ............................................ 29
Functional Block Diagram .............................................................. 1
Synchronization Procedures ..................................................... 30
Revision History ............................................................................... 3
Interrupt Request Operation ........................................................ 32
Specifications..................................................................................... 4
Interrupt Working Mechanism ................................................ 32
DC Specifications ......................................................................... 4
Interrupt Service Routine .......................................................... 32
Digital Specifications ................................................................... 5
Temperature Sensor ....................................................................... 33
Latency Variation Specifications ................................................ 6
DAC Input Clock Configurations ................................................ 34
AC Specifications.......................................................................... 6
Driving the DACCLK and REFCLK Inputs ........................... 34
Operating Speed Specifications .................................................. 6
Direct Clocking .......................................................................... 34
Absolute Maximum Ratings ....................................................... 7
Clock Multiplication .................................................................. 34
Thermal Resistance ...................................................................... 7
PLL Settings ................................................................................ 35
ESD Caution .................................................................................. 7
Configuring the VCO Tuning Band ........................................ 35
Pin Configuration and Function Descriptions ............................. 8
Automatic VCO Band Select .................................................... 35
Typical Performance Characteristics ........................................... 11
Manual VCO Band Select ......................................................... 35
Terminology .................................................................................... 15
PLL Enable Sequence ................................................................. 35
Serial Port Operation ..................................................................... 16
Analog Outputs............................................................................... 36
Data Format ................................................................................ 16
Transmit DAC Operation.......................................................... 36
Serial Port Pin Descriptions ...................................................... 16
Interfacing to Modulators ......................................................... 37
Serial Port Options ..................................................................... 16
Reducing LO Leakage and Unwanted Sidebands .................. 38
Data Interface .................................................................................. 18
Start-Up Routine ............................................................................ 39
LVDS Input Data Ports .............................................................. 18
Device Configuration Register Map and Description ............... 40
Word Interface Mode ................................................................. 18
SPI Configure Register .............................................................. 42
Byte Interface Mode ................................................................... 18
Power-Down Control Register ................................................. 42
Data Interface Configuration Options .................................... 18
Interrupt Enable 0 Register ....................................................... 42
DLL Interface Mode ................................................................... 18
Interrupt Enable 1 Register ....................................................... 42
Parity ............................................................................................ 21
Interrupt Flag 0 Register............................................................ 43
SED Operation ............................................................................ 21
Interrupt Flag 1 Register............................................................ 43
SED Example ............................................................................... 22
Interrupt Select 0 Register ......................................................... 43
Delay Line Interface Mode ........................................................ 22
Interrupt Select 1 Register ......................................................... 44
FIFO Operation .............................................................................. 24
Frame Mode Register ................................................................. 44
Resetting the FIFO ..................................................................... 25
Data Control 0 Register ............................................................. 44
Serial Port Initiated FIFO Reset ............................................... 25
Data Control 1 Register ............................................................. 44
Frame Initiated FIFO Reset ....................................................... 25
Data Control 2 Register ............................................................. 45
Digital Datapath.............................................................................. 27
Data Control 3 Register ............................................................. 45
Interpolation Filters ................................................................... 27
Data Status 0 Register ................................................................ 45
Inverse Sinc Filter ....................................................................... 28
DAC Clock Receiver Control Register .................................... 46
Digital Function Configuration................................................ 28
Reference Clock Receiver Control Register ............................ 46
Rev. 0 | Page 2 of 56
Data Sheet
AD9139
PLL Control Register ..................................................................46
Gain Step Control0 Register ...................................................... 52
PLL Control Register ..................................................................47
Gain Step Control1 Register ...................................................... 52
PLL Control Register ..................................................................47
TX Enable Control Register ...................................................... 52
PLL Status Register .....................................................................47
DAC Output Control Register .................................................. 53
PLL Status Register .....................................................................48
DLL Cell Enable 0 Register ........................................................ 53
DAC FS Adjust LSB Register .....................................................48
DLL Cell Enable 1 Register ........................................................ 53
DAC FS Adjust MSB Register ....................................................48
SED Control Register ................................................................. 53
Die Temperature Sensor Control Register ...............................48
SED Pattern S0 Low Bits Register ............................................. 54
Die Temperature LSB Register ..................................................48
SED Pattern S0 High Bits Register ............................................ 54
Die Temperature MSB Register .................................................49
SED Pattern S1 Low Bits Register ............................................. 54
Chip ID Register..........................................................................49
SED Pattern S1 High Bits Register ............................................ 54
Interrupt Configuration Register ..............................................49
SED Pattern S2 Low Bits Register ............................................. 54
Sync CTRL Register ....................................................................49
SED Pattern S2 High Bits Register ............................................ 54
Frame Reset CTRL Register .......................................................49
SED Pattern S3 Low Bits Register ............................................. 54
FIFO Level Configuration Register ..........................................50
SED Pattern S3 High Bits Register ............................................ 55
FIFO Level Readback Register ..................................................50
Parity Control Register ............................................................... 55
FIFO CTRL Register ...................................................................50
Parity Error Rising Edge Register ............................................. 55
Data Format Select Register.......................................................51
Parity Error Falling Edge Register ............................................ 55
Datapath Control Register .........................................................51
Version Register .......................................................................... 55
Interpolation Control Register ..................................................51
Packaging and Ordering Information .......................................... 56
Power-Down Data Input 0 Register..........................................51
Outline Dimensions ................................................................... 56
DAC_DC_OFFSET0 Register ...................................................51
Ordering Guide ........................................................................... 56
DAC_DC_OFFSET1 Register ...................................................51
DAC_GAIN_ADJ Register ........................................................52
REVISION HISTORY
10/13—Revision 0: Initial Version
Rev. 0 | Page 3 of 56
AD9139
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUT
Offset Error
Gain Error
Full-Scale Output Current
Output Compliance Range
Output Resistance
Gain DAC Monotonicity
Settling Time to Within ±0.5 LSB
MAIN DAC TEMPERATURE DRIFT
Offset
Gain
Reference Voltage
REFERENCE
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
AVDD33
CVDD18
DIGITAL SUPPLY VOLTAGES
DVDD18
DVDD18 Variation over Operating
Conditions 1
POWER CONSUMPTION
1× Mode
2× Mode
Phase-Locked Loop
Inverse Sinc
Reduced Power Mode (Power-Down)
AVDD33 Current
CVDD18 Current
DVDD18 Current
OPERATING RANGE
1
Test Conditions/Comments
Min
Typ
16
Max
±2.1
±3.7
With internal reference
10 kΩ external resistor between FSADJ and AVSS
−0.001
−3.2
19.06
−1.0
0
+2
19.8
LSB
LSB
+0.001
+4.7
20.6
+1.0
10
Guaranteed
20
% FSR
% FSR
mA
V
MΩ
ns
0.04
100
30
1.17
Unit
Bits
ppm/°C
ppm/°C
ppm/°C
1.19
V
kΩ
5
3.13
1.7
3.3
1.8
3.47
1.9
V
V
1.7
−2.5%
1.8
1.9
+2.5%
V
V
57.3
0.4
26.6
4.5
+85
mW
mW
mW
mW
mW
mW
mW
mA
mA
mA
°C
fDAC = 614 MSPS
fDAC = 1230 MSPS
fDAC = 800 MSPS
fDAC = 1600 MSPS
440
700
670
1150
70
60
fDAC = 1230 MSPS
−40
+25
This parameter specifies the maximum allowable variation of DVDD18 over operating conditions compared with the DVDD18 presented to the device at the time the
data interface DLL is enabled.
Rev. 0 | Page 4 of 56
Data Sheet
AD9139
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
Input
Logic High
Logic Low
CMOS OUTPUT LOGIC LEVEL
Output
Logic High
Logic Low
LVDS RECEIVER INPUTS
Input Voltage Range
Input Differential Threshold
Input Differential Hysteresis
Receiver Differential Input Impedance
DLL SPEED RANGE
DAC UPDATE RATE
DAC Adjusted Update Rate
DAC CLOCK INPUT (DACCLKP, DACCLKN)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
REFCLK/SYNCCLK INPUT (REFP/SYNCP,
REFN/SYNCN)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Input Clock Frequency
SERIAL PORT INTERFACE
Maximum Clock Rate
Minimum Pulse Width
High
Low
SDIO to SCLK Setup Time
SDIO to SCLK Hold Time
CS to SCLK Setup Time
CS to SCLK Hold Time
SDIO to SCLK Delay
Symbol
Min
DVDD18 = 1.8 V
DVDD18 = 1.8 V
1.2
DVDD18 = 1.8 V
DVDD18 = 1.8 V
Data and frame inputs
1.4
VIA or VIB
VIDTH
VIDTHH to VIDTHL
RIN
Typ
825
−175
0.6
V
V
0.4
V
V
575
1600
1150
800
500
1.25
2000
mV
V
100
500
1.25
2000
mV
V
MHz
1.03 GHz ≤ fVCO ≤ 2.07 GHz
SCLK
450
40
MHz
12.5
12.5
Wait time for valid output from
SDIO
Time for SDIO to relinquish the
output bus
1.5
0.68
2.38
9.6
11
Rev. 0 | Page 5 of 56
1.4
8.5
1.2
With 2 mA loading
With 2 mA loading
mV
mV
mV
Ω
MHz
MSPS
MSPS
MSPS
100
Self biased input, ac-coupled
VIH
VIL
IIH
IIL
Unit
20
100
1× interpolation
2× interpolation
tPWH
tPWL
tDS
tDH
tDCSB
tDCSB
tDV
Max
1675
+175
250
SDIO High-Z to CS
SDIO LOGIC LEVEL
Voltage Input High
Voltage Input Low
Voltage Output High
Voltage Output Low
Test Conditions/Comments
1.36
0
ns
ns
ns
ns
ns
ns
ns
ns
1.8
0
0.5
2
0.45
V
V
V
V
AD9139
Data Sheet
LATENCY VARIATION SPECIFICATIONS
Table 3.
Parameter
DAC LATENCY 1 VARIATION
SYNC Off
SYNC On
1
Min
Typ
Max
Unit
1
0
2
1
DAC clock cycles
DAC clock cycles
DAC latency is defined as the elapsed time from a data sample clocked at the input to the device until the analog output begins to change.
AC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted.
Table 4.
Parameter
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fDAC = 737.28 MSPS
Bandwidth (BW) = 125 MHz
BW = 270 MHz
fDAC = 983.04 MSPS
BW = 360 MHz
fDAC = 1228.8 MSPS
BW = 200 MHz
BW = 500 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDAC = 737.28 MSPS
fDAC = 983.04 MSPS
fDAC = 1228.8 MSPS
NOISE SPECTRAL DENSITY (NSD)
fDAC = 737.28 MSPS
fDAC = 983.04 MSPS
fDAC = 1228.8 MSPS
W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR)
fDAC = 983.04 MSPS
fDAC = 1228.8 MSPS
W-CDMA SECOND (ACLR)
fDAC = 983.04 MSPS
fDAC = 1228.8 MSPS
Test Conditions/Comments
−14 dBFS single tone
fOUT = 200 MHz
Min
Typ
Max
Unit
85
80
dBc
dBc
85
dBc
85
75
dBc
dBc
80
82
80
dBc
dBc
dBc
−160
−161.5
−164.5
dBm/Hz
dBm/Hz
dBm/Hz
81
83
80
dBc
dBc
dBc
85
86
86
dBc
dBc
dBc
fOUT = 200 MHz
fOUT = 280 MHz
−12 dBFS each tone
fOUT = 200 MHz
fOUT = 200 MHz
fOUT = 280 MHz
Eight-tone, 500 kHz tone spacing
fOUT = 200 MHz
fOUT = 200 MHz
fOUT = 280 MHz
Single carrier
fOUT = 200 MHz
fOUT = 20 MHz
fOUT = 280 MHz
Single carrier
fOUT = 200 MHz
fOUT = 20 MHz
fOUT = 280 MHz
OPERATING SPEED SPECIFICATIONS
Table 5.
Interpolation
Factor
1×
2×
DVDD18, CVDD18 = 1.8 V ± 5%
fDCI (MSPS) Max
fDAC (MSPS) Max
575
1150
350
1400
DVDD18, CVDD18 = 1.9 V ± 5% or 1.8 V ± 2%
fDCI (MSPS) Max
fDAC (MSPS) Max
575
1150
375
1500
Rev. 0 | Page 6 of 56
DVDD18, CVDD18 = 1.9 V ± 2%
fDCI (MSPS) Max
fDAC (MSPS) Max
575
1150
400
1600
Data Sheet
AD9139
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 6.
Parameter
AVDD33 to GND
DVDD18, CVDD18 to GND
FSADJ, VREF, DACOUTP/DACOUTN, to
GND
D15P to D0P/D15N to D0N,
FRAMEP/FRAMEN, DCIP/DCIN to
GND
DACCLKP/DACCLKN,
REFP/SYNCP/REFN/SYNCN to GND
RESET, IRQ1, IRQ2, CS, SCLK, SDIO
to GND
Junction Temperature
Storage Temperature Range
Rating
−0.3 V to +3.6 V
−0.3 V to +2.1 V
−0.3 V to AVDD33 + 0.3 V
−0.3 V to DVDD18 + 0.3 V
−0.3 V to CVDD18 + 0.3 V
The exposed pad (EPAD) must be soldered to the ground plane
(AVSS) for the 72-lead LFCSP. The EPAD provides an electrical,
thermal, and mechanical connection to the board.
Typical θJA, θJB, and θJC values are specified for a 4-layer board in
still air. Airflow increases heat dissipation, effectively reducing
θJA and θJB.
Table 7. Thermal Resistance
−0.3 V to DVDD18 + 0.3 V
Package
72-Lead LFCSP
125°C
−65°C to +150°C
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 7 of 56
θJA
20.7
θJB
10.9
θJC
1.1
Unit
°C/W
Conditions
EPAD soldered
to ground plane
AD9139
Data Sheet
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
CVDD18
CVDD18
VREF
FSADJ
AVDD33
DACOUTP
DACOUTN
AVDD33
CVDD18
CVDD18
DACCLKP
DACCLKN
CVDD18
CVDD18
AVDD33
DNC
DNC
AVDD33
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
AD9139
TOP VIEW
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
CS
SCLK
SDIO
IRQ1
IRQ2
DVDD18
DVDD18
D0N
D0P
D1N
D1P
DVDD18
D2N
D2P
D3N
D3P
D4N
D4P
11744-002
DVDD18
D11P
D11N
D10P
D10N
D9P
D9N
D8P
D8N
DCIP
DCIN
D7P
D7N
D6P
D6N
D5P
D5N
DVDD18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CVDD18
REFP/SYNCP
REFN/SYNCN
CVDD18
RESET
TXEN
DVDD18
FRAMEP/PARITYP
FRAMEN/PARITYN
D15P
D15N
DVDD18
D14P
D14N
D13P
D13N
D12P
D12N
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE (AVSS, DVSS, CVSS).
THE EPAD PROVIDES AN ELECTRICAL, THERMAL, AND MECHANICAL CONNECTION TO THE BOARD.
Figure 2. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
Mnemonic
CVDD18
REFP/SYNCP
REFN/SYNCN
CVDD18
RESET
TXEN
7
DVDD18
8
9
10
11
12
FRAMEP/PARITYP
FRAMEN/PARITYN
D15P
D15N
DVDD18
13
14
15
16
17
18
19
D14P
D14N
D13P
D13N
D12P
D12N
DVDD18
20
21
22
23
D11P
D11N
D10P
D10N
Description
1.8 V PLL Supply. CVDD18 supplies the power to the clock receivers, clock multiplier, and clock distribution.
PLL Reference Clock/Synchronization Clock Input, Positive.
PLL Reference Clock/Synchronization Clock Input, Negative.
1.8 V PLL Supply. CVDD18 supplies the power to the clock receivers, clock multiplier, and clock distribution.
Reset, Active Low. CMOS levels with respect to DVDD18. Recommended reset pulse length is 1 µs.
Active High Transmit Path Enable. CMOS levels with respect to DVDD18. A low level on this pin triggers two
selectable actions in the DAC. See Register 0x43 in Table 64 for details.
1.8 V Digital Supply. Pin 7 supplies power to the digital core, digital data ports, serial port input/output
pins, RESET, IRQ1, and IRQ2.
Frame/Parity Input, Positive.
Frame/Parity Input, Negative.
Data Bit 15 (MSB), Positive.
Data Bit 15 (MSB), Negative.
1.8 V Digital Supply. Pin 12 supplies the power to the digital core and digital data ports, serial port
input/output pins, RESET, IRQ1, and IRQ2.
Data Bit 14, Positive.
Data Bit 14, Negative.
Data Bit 13, Positive.
Data Bit 13, Negative.
Data Bit 12, Positive.
Data Bit 12, Negative.
1.8 V Digital Supply. Pin 19 supplies power to the digital core, digital data ports, serial port input/output
pins, RESET, IRQ1, and IRQ2.
Data Bit 11, Positive.
Data Bit 11, Negative.
Data Bit 10, Positive.
Data Bit 10, Negative.
Rev. 0 | Page 8 of 56
Data Sheet
Pin No.
24
25
26
27
28
29
30
31
32
33
34
35
36
Mnemonic
D9P
D9N
D8P
D8N
DCIP
DCIN
D7P
D7N
D6P
D6N
D5P
D5N
DVDD18
37
38
39
40
41
42
43
D4P
D4N
D3P
D3N
D2P
D2N
DVDD18
44
45
46
47
48
D1P
D1N
D0P
D0N
DVDD18
49
DVDD18
50
IRQ2
51
IRQ1
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
SDIO
SCLK
CS
AVDD33
DNC
DNC
AVDD33
CVDD18
CVDD18
DACCLKN
DACCLKP
CVDD18
CVDD18
AVDD33
DACOUTN
DACOUTP
AVDD33
FSADJ
VREF
CVDD18
AD9139
Description
Data Bit 9, Positive.
Data Bit 9, Negative.
Data Bit 8, Positive.
Data Bit 8, Negative.
Data Clock Input, Positive.
Data Clock Input, Negative.
Data Bit 7, Positive.
Data Bit 7, Negative.
Data Bit 6, Positive.
Data Bit 6, Negative.
Data Bit 5, Positive.
Data Bit 5, Negative.
1.8 V Digital Supply. Pin 36 supplies the power to the digital core, digital data ports, serial port input/output
pins, RESET, IRQ1, and IRQ2.
Data Bit 4, Positive.
Data Bit 4, Negative.
Data Bit 3, Positive.
Data Bit 3, Negative.
Data Bit 2, Positive.
Data Bit 2, Negative.
1.8 V Digital Supply. Pin 43 supplies the power to the digital core, digital data ports, serial port input/output
pins, RESET, IRQ1, and IRQ2.
Data Bit 1, Positive.
Data Bit 1, Negative.
Data Bit 0, Positive.
Data Bit 0, Negative.
1.8 V Digital Supply. Pin 48 supplies the power to the digital core, digital data ports, serial port input/output
pins, RESET, IRQ1, and IRQ2.
1.8 V Digital Supply. Pin 49 supplies the power to the digital core, digital data ports, serial port input/output
pins, RESET, IRQ1, and IRQ2.
Second Interrupt Request. Open-drain, active low output. Connect an external pull-up to DVDD18 through a
10 kΩ resistor.
First Interrupt Request. Open-drain, active low output. Connect an external pull-up to DVDD18 through a
10 kΩ resistor.
Serial Port Data Input/Output. CMOS levels with respect to DVDD18.
Serial Port Clock Input. CMOS levels with respect to DVDD18.
Serial Port Chip Select. Active low (CMOS levels with respect to DVDD18).
3.3 V Analog Supply.
Do No Connect. Leave this pin floating.
Do No Connect. Leave this pin floating.
3.3 V Analog Supply.
1.8 V Clock Supply. CVDD18 supplies the power to the clock receivers and clock distribution.
1.8 V Clock Supply. CVDD18 supplies the power to the clock receivers and clock distribution.
DAC Clock Input, Negative.
DAC Clock Input, Positive.
1.8 V Clock Supply. CVDD18 supplies the power to the clock receivers and clock distribution.
1.8 V Clock Supply. CVDD18 supplies the power to the clock receivers and clock distribution.
3.3 V Analog Supply.
DAC Current Output, Negative.
DAC Current Output, Positive.
3.3 V Analog Supply.
Full-Scale Current Output Adjust. Place a 10 kΩ resistor from this pin to AVSS.
Voltage Reference. Nominally 1.2 V output. Decouple VREF to AVSS.
1.8 V Clock Supply. Pin 71 supplies power to the clock receivers, clock multiplier, and clock distribution.
Rev. 0 | Page 9 of 56
AD9139
Pin No.
72
Mnemonic
CVDD18
EPAD
Data Sheet
Description
1.8 V Clock Supply. Pin 72 supplies power to the clock receivers, clock multiplier, and clock distribution.
Exposed Pad. The exposed pad (EPAD) must be soldered to the ground plane (AVSS, DVSS, CVSS). The EPAD
provides an electrical, thermal, and mechanical connection to the board.
Rev. 0 | Page 10 of 56
Data Sheet
AD9139
TYPICAL PERFORMANCE CHARACTERISTICS
–40
–40
fDAC = 737.28MHz
fDAC = 983.04MHz
fDAC = 1228.8MHz
–50
–70
–80
–80
–90
–90
–100
0
100
200
300
400
500
600
700
fOUT (MHz)
–100
Figure 3. Single-Tone (0 dBFS) SFDR vs. fOUT in the First Nyquist Zone over fDAC
0
100
150
200
250
300
350
400
fOUT (MHz)
Figure 6. Single-Tone SFDR Excluding 2nd and 3rd Harmonics vs. fOUT in the
First Nyquist Zone over fDAC and Digital Back Off
–40
–40
0dBFS
–6dBFS
–12dBFS
–16dBFS
–50
fDAC = 737.28MHz
fDAC = 983.04MHz
fDAC = 1228.8MHz
–50
–60
–70
–70
–80
–80
–90
–90
100
200
300
400
500
600
700
fOUT (MHz)
–100
11744-004
0
0
100
200
300
400
500
600
700
fOUT (MHz)
Figure 4. Single-Tone Second Harmonic vs. fOUT in the First Nyquist Zone
over Digital Back Off, fDAC = 1228.8 MHz
11744-008
IMD (dBc)
–60
–100
Figure 7. Two-Tone Third IMD vs. fOUT over fDAC
–40
–40
0dBFS
–6dBFS
–12dBFS
–16dBFS
–50
0dBFS
–6dBFS
–12dBFS
–16dBFS
–50
–60
–70
–70
–80
–80
–90
–90
–100
0
100
200
300
400
fOUT (MHz)
500
600
700
Figure 5. Single-Tone Third Harmonic vs. fOUT in the First Nyquist Zone
over Digital Back Off, fDAC = 1228.8 MHz
Rev. 0 | Page 11 of 56
–100
0
100
200
300
400
500
600
fOUT (MHz)
Figure 8. Two-Tone Third IMD vs. fOUT over Digital Back Off,
fDAC = 1228.8 MHz
700
11744-009
IMD (dBc)
–60
11744-005
THIRD HARMONIC (dBc)
50
11744-006
SFDR (dBc)
–70
11744-003
SFDR (dBc)
0dBFS
–12dBFS
–60
–60
SECOND HARMONIC (dBc)
fDAC = 800MHz
fDAC = 1600MHz
–50
AD9139
Data Sheet
–40
–150
PLL OFF
PLL ON
0dBFS
–12 dBFS
PLL OFF
PLL ON
–50
–155
NSD (dBm/Hz)
IMD (dBc)
–60
–70
–160
–80
–165
0
100
200
300
400
500
600
700
fOUT (MHz)
Figure 9. Two-Tone Third IMD vs. fOUT over PLL on and off,
fDAC = 1228.8 MHz
–145
–170
11744-010
–100
0
100
200
400
300
500
600
700
fOUT (MHz)
11744-013
–90
Figure 12. Single-Tone NSD vs. fOUT, over Digital Back Off, PLL on and off
–60
fDAC = 737.28MHz
fDAC = 983.04MHz
fDAC = 1228.8MHz
fDAC = 1228.8MHz
fDAC = 983.04MHz
–65
–150
PLL OFF
PLL ON
ACLR (dBc)
NSD (dBm/Hz)
–70
–155
–160
–75
–80
–165
0
100
200
300
400
500
600
700
fOUT (MHz)
–90
11744-011
–170
0
100
200
300
400
500
600
fOUT (MHz)
11744-014
–85
Figure 13. 1-Carrier WCDMA 1st Adjacent ACLR vs. fOUT over fDAC
PLL on and off
Figure 10. Single-Tone (0 dBFS) NSD vs. fOUT over fDAC
–150
0dBFS
–6dBFS
–12dBFS
–16dBFS
–60
PLL OFF
PLL ON
–70
ACLR (dBc)
NSD (dBm/Hz)
fDAC = 1228.8MHz
fDAC = 983.04MHz
–65
–155
–160
–75
–80
–165
100
200
300
400
fOUT (MHz)
500
600
700
–90
0
100
200
300
400
500
600
fOUT (MHz)
Figure 11. Single-Tone NSD vs. fOUT, over Digital Back Off, fDAC = 1228.8 MHz
Rev. 0 | Page 12 of 56
Figure 14. 1-Carrier WCDMA 2nd Adjacent ACLR vs. fOUT over fDAC
PLL on and off
11744-015
0
11744-012
–85
–170
AD9139
11744-017
11744-023
Data Sheet
Figure 15. Two-Tone Third IMD Performance, IF = 200 MHz,
fDAC = 1228.8 MHz, −9 dBFS
Figure 18. 4-Carrier WCDMA ACLR Performance, IF = 200 MHz,
fDAC = 1228.8 MHz
1.0
1× INTERPOLATION
2× INTERPOLATION
0.9
POWER (W)
0.8
0.7
0.6
0.5
0.4
0.2
200
400
600
11744-019
0
800
1000
1200
1400
fDAC (MHz)
11744-024
0.3
Figure 19. Total Power Consumption vs. fDAC over Interpolation
Figure 16. 1-Carrier WCDMA ACLR Performance, IF = 200 MHz,
fDAC = 1228.8 MHz
350
1× INTERPOLATION
2× INTERPOLATION
DVDD18 CURRENT (mA)
300
250
200
150
100
0
11744-021
0
Figure 17. Single-Tone Performance, IF = 200 MH, fDAC = 1228.8 MHz
200
400
600
800
1000
1200
fDAC (MHz)
Figure 20. DVDD18 Current vs. fDAC over Interpolation
Rev. 0 | Page 13 of 56
1400
11744-025
50
AD9139
Data Sheet
35
250
AVDD33 (mA)
CVDD18 (mA), PLL OFF
CVDD18 (mA), PLL ON
DIGITAL GAIN AND OFFSET
INVERSE SINC
30
SUPPLY CURRENT (mA)
25
20
15
10
150
100
50
0
0
200
400
600
800
1000
1200
1400
fDAC (MHz)
Figure 21. DVDD18 Current vs. fDAC over Digital Functions
0
0
200
400
600
800
1000
1200
fDAC (MHz)
Figure 22. CVDD18 and AVDD18 Current vs. fDAC
Rev. 0 | Page 14 of 56
1400
11744-027
5
11744-026
DVDD18 CURRENT (mA)
200
Data Sheet
AD9139
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation of the actual analog output from
the ideal output, determined by a straight line drawn from zero
scale to full scale.
Settling Time
Settling time is the time required for the output to reach and
remain within a specified error band around its final value,
measured from the start of the output transition.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the peak amplitude
of the output signal and the peak spurious signal within the dc
to Nyquist frequency of the DAC. Typically, the interpoloation
filters reject energy in this band. This specification, therefore,
defines how well the interpolation filters work and the effect of
other parasitic coupling paths on the DAC output.
Offset Error
Offset error is the deviation of the output current from the ideal
of 0 mA. For DACOUTP, 0 mA output is expected when all
inputs are set to 0. For DACOUTN, 0 mA output is expected
when all inputs are set to 1.
Gain Error
Gain error is the difference between the actual and ideal output
span. The actual span is determined by the difference between
the output when all inputs are set to 1 and the output when all
inputs are set to 0.
Output Compliance Range
The output compliance range is the range of allowable voltage
at the output of a current output DAC. Operation beyond the
maximum compliance limits can cause either output stage
saturation or breakdown, resulting in nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from
the ambient (25°C) value to the value at either TMIN or TMAX.
For offset and gain drift, the drift is reported in ppm of fullscale range (FSR) per degree Celsius. For reference drift, the
drift is reported in ppm per degree Celsius.
Power Supply Rejection (PSR)
PSR is the maximum change in the full-scale output as the
supplies are varied from minimum to maximum specified
voltages.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
Interpolation Filter
If the digital inputs to the DAC are sampled at a multiple rate of
fDATA (interpolation rate), a digital filter can be constructed that
has a sharp transition band near fDATA/2. Images that typically
appear around fDAC (output data rate) can be greatly suppressed.
Adjacent Channel Leakage Ratio (ACLR)
ACLR is the ratio in decibels relative to the carrier (dBc) between
the measured power within a channel relative to its adjacent
channel.
Complex Image Rejection
In a traditional two-part upconversion, two images are created
around the second IF frequency. These images have the effect
of wasting transmitter power and system bandwidth. By placing
the real part of a second complex modulator in series with the
first complex modulator, either the upper or lower frequency
image near the second IF can be rejected.
Rev. 0 | Page 15 of 56
AD9139
Data Sheet
SERIAL PORT OPERATION
54 CS
SPI
PORT 53 SCLK
52 SDIO
11744-028
The serial port is a flexible, synchronous serial communications
port that allows easy interfacing to many industry standard microcontrollers and microprocessors. The serial I/O is compatible
with most synchronous transfer formats, including both the
Motorola SPI and Intel® SSR protocols. The interface allows
read/write access to all registers that configure the AD9139.
MSB first or LSB first transfer formats are supported. The serial
port interface is a 3-wire only interface. The input and output
share a single input/output (SDIO) pin.
SERIAL PORT PIN DESCRIPTIONS
Serial Clock (SCLK)
The serial clock pin, SCLK, synchronizes data to and from the
device and runs the internal state machines. The maximum
frequency of SCLK is 40 MHz. All data input is read on the rising
edge of SCLK. All data is driven out on the falling edge of SCLK.
Chip Select (CS)
Figure 23. Serial Port Interface Pins
There are two phases to a communication cycle with the AD9139.
Phase 1 is the instruction cycle (the writing of an instruction
byte into the device), coincident with the first 16 SCLK rising
edges. The instruction word provides the serial port controller
with information regarding the data transfer cycle, Phase 2, of
the communication cycle. The Phase 1 instruction word defines
whether the upcoming data transfer is a read or write, together
with the starting register address for the following data transfer.
A logic high on the CS pin, followed by a logic low, resets the
serial port timing to the initial state of the instruction cycle.
From this state, the next 16 rising SCLK edges represent the
instruction bits of the current I/O operation.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the device and
the system controller. Phase 2 of the communication cycle is a
transfer of one data byte. Registers change immediately upon
writing to the last bit of each transfer byte.
DATA FORMAT
The instruction byte contains the information shown in Table 9.
Table 9. Serial Port Instruction Word
I15 (MSB)
R/W
A14 to A0 (Bit 14 to Bit 0 of the instruction word) determine
the register that is accessed during the data transfer portion of
the communication cycle. For multibyte transfers, A14 is the
starting address; the device generates the remaining register
addresses based on the SPI_LSB_FIRST bit.
I[14:0]
A[14:0]
R/W (Bit 15 of the instruction word) determines whether a read
or a write data transfer occurs after the instruction word write.
Logic 1 indicates a read operation, and Logic 0 indicates a write
operation.
CS is an active low input that starts and gates a communication
cycle. It allows the use of multiple devices on the same serial
communications line. The SDIO pin enters a high impedance
state when the CS input is high. During the communication
cycle, CS remains low.
Serial Data I/O (SDIO)
The SDIO pin is a bidirectional data line.
SERIAL PORT OPTIONS
The serial port supports both MSB first and LSB first data
formats; the SPI_LSB_FIRST bit (Register 0x00, Bit 6) controls
this functionality. The default is MSB first (SPI_LSB_FIRST = 0).
When SPI_LSB_FIRST = 0 (MSB first), the instruction and data
bits must be written from MSB to LSB. Multibyte data transfers
in MSB first format start with an instruction word that includes the
register address of the most significant data byte. Subsequent data
bytes must follow from high address to low address. In MSB first
mode, the serial port internal word address generator decrements
for each data byte of the multibyte communication cycle.
When SPI_LSB_FIRST = 1 (LSB first), the instruction and data
bits must be written from LSB to MSB. Multibyte data transfers
in LSB first format start with an instruction word that includes the
register address of the least significant data byte. Subsequent data
bytes must follow from low address to high address. In LSB first
mode, the serial port internal word address generator increments
for each data byte of the multibyte communication cycle.
When the MSB first mode is active, the serial port controller
data address decrements from the data address written toward
0x00 for multibyte I/O operations. If the LSB first mode is
active, the serial port controller data address increments from
the data address written toward 0xFF for multibyte I/O
operations.
Rev. 0 | Page 16 of 56
Data Sheet
AD9139
tDCSB
INSTRUCTION CYCLE
tSCLK
DATA TRANSFER CYCLE
CS
CS
tPWH
SCLK
R/W A14 A13
A3
A2 A1
A0 D7N D6N D5N
D30 D20 D10 D00
tDS
SDIO
Figure 24. Serial Register Interface Timing, MSB First
INSTRUCTION CYCLE
tDH
INSTRUCTION BIT 15
INSTRUCTION BIT 14
11744-031
SCLK
11744-029
SDIO
tPWL
Figure 26. Timing Diagram for Serial Port Register Write
CS
DATA TRANSFER CYCLE
CS
SCLK
A0
A1
A2
A12 A13 A14 R/W D00 D10 D20
D4N D5N D6N D7N
tDV
SDIO
Figure 25. Serial Register Interface Timing, LSB First
DATA BIT n
DATA BIT n – 1
Figure 27. Timing Diagram for Serial Port Register Read
Rev. 0 | Page 17 of 56
11744-032
SDIO
11744-030
SCLK
AD9139
Data Sheet
DATA INTERFACE
LVDS INPUT DATA PORTS
DATA INTERFACE CONFIGURATION OPTIONS
The AD9139 has a 16-bit LVDS bus that accepts 16-bit data
either in word wide (16-bit) or byte wide (8-bit) formats. In the
word wide interface mode, the data is sent over the entire 16-bit
data bus. In the byte wide interface mode, the data is sent over
the lower 8-bit (D7 to D0) LVDS bus. Table 10 lists the pin
assignment of the bus and the SPI register configuration for
each mode.
To provide more flexibility for the data interface, additional
options are listed in Table 11.
Table 10. LVDS Input Data Modes
DLL INTERFACE MODE
Interface Mode
Word
Byte
Input Data
Width
D15 to D0
D7 to D0
Table 11. Data Interface Configuration Options
Register 0x26, Bit 7
DATA_FORMAT
A source synchronous LVDS interface is used between the data
host and the AD9139 to achieve high data rates while simplifying
the interface. The FPGA or ASIC feeds the AD9139 with 16-bit
input data. Together with the input data, the FPGA or ASIC
provides a DDR DCI.
SPI Register Configuration
Register 0x26, Bit 0 = 0
Register 0x26, Bit 0 = 1
WORD INTERFACE MODE
A delay locked loop (DLL) circuit, designed to operate with
DCI clock rates between 250 MHz and 575 MHz, generates a
phase shifted version of the DCI signal, called a data sampling
clock (DSC), to register the input data on both the rising and
falling edges.
In word mode, the digital clock input (DCI) signal is a reference
bit that generates a double data rate (DDR) data sampling clock.
Time align the DCI signal with the data.
AD9139 WORD MODE
INPUT DATA[15:0]
S1
S2
S3
11744-033
S0
DCI
Figure 28. AD9139 Timing Diagram for Word Mode
BYTE INTERFACE MODE
In byte mode, the required sequence of the input data stream is
S0[15:8], S0[7:0], S1[15:8], S1[7:0], and so forth. A frame signal
is required to align the order of input data bytes properly. Time
align both the DCI signal and frame signal with the data. The
rising edge of the frame indicates the start of the sequence. The
frame can be either a one shot or periodical signal as long as its
first rising edge is correctly captured by the device. For a one
shot frame, the frame pulse must be held at high for at least one
DCI cycle. For a periodical frame, the frequency must be
As shown in Figure 31, the DCI clock edges must be coincident
with the data bit transitions with minimum skew and jitter. The
nominal sampling point of the input data occurs in the middle
of the DCI clock edges because this point corresponds to the
center of the data eye. This is also equivalent to a nominal phase
shift of 90°of the DCI clock.
The data timing requirements are defined by a data valid
window (DVW) that is dependent on the data clock input skew,
input data jitter, and the variations of the DLL delay line across
delay settings. The DVW is defined as
DVW = tDATA PERIOD − tDATA SKEW − tDATA JITTER
The available margin for data interface timing is given by
tMARGIN = DVW − (tS + tH)
The difference of the setup and hold times, which is also called
the keep out window, or KOW, is the area where data transitions
are prohibited. The timing margin allows the user to set the
DLL delay, as shown in Figure 30.
fDCI/(2 × n)
where n is a positive integer, that is, 1, 2, 3, …
Figure 29 is an example of signal timing in byte mode.
AD9139 WORD MODE
INPUT DATA[7:0]
S0[15:8]
S0[7:0]
S1[15:8]
S1[7:0]
11744-034
DCI
FRAME
Description
Select between binary and twos
complement formats.
Figure 29. Timing Diagram for Byte Mode
Rev. 0 | Page 18 of 56
Data Sheet
AD9139
tH
tDATA JITTER
tS
INPUT DATA
DATA EYE
tDATA PERIOD
DCI
DATA SAMPLE CLOCK
tDCI SKEW
DLL
PHASE
DELAY
tH + tS
tDATA JITTER
DATA EYE
INPUT DATA
tDATA PERIOD
11744-035
DCI
DATA SAMPLE CLOCK
Figure 30. LVDS Data Port Timing Requirements
Figure 30 shows that the ideal location for the DSC signal is 90°
out of phase from the DCI input; however, due to skew of the
DCI relative to the data, it may be necessary to change the DSC
phase offset to sample the data at the center of its eye diagram.
Vary the sampling instance in discrete increments by offsetting the
nominal DLL phase shift value of 90° via Register 0x0A, Bits[3:0].
This register is a signed value. The MSB is the sign and the LSBs
are the magnitude. The following equation defines the phase
offset relationship:
Phase Offset = 90° + n × 11.25°, |n| < 7
Table 12 lists the guaranteed values across the operating conditions. These values were obtained using a 50% duty cycle and a
DCI swing of 450 mV p-p. For best performance, maintain a
duty cycle variation below ±5% and set the DCI input as high as
possible, up to 1200 mV p-p.
Table 12. DLL Phase Setup and Hold Times (Guaranteed)
Frequency,
fDCI (MHz)
307
where n is the DLL phase offset setting.
Figure 31 shows the DSC setup and hold times with respect to
the DCI signal and data signals.
368
491
DATA
614
DCI
tS
tH
11744-036
DSC
Figure 31. LVDS Data Port Setup and Hold Times
Rev. 0 | Page 19 of 56
Time (ps)
tS
tH
tS
tH
tS
tH
tS
tH
Data Port Setup and Hold Times (ps)
at DLL Phase
−3
0
+3
−125
−385
−695
834
1120
1417
−70
−305
−534
753
967
1207
−81
−245
−402
601
762
928
−54.0
−167
−277
497
603
721
AD9139
Data Sheet
Table 13. DLL Phase Setup and Hold Times (Typical)
Frequency,
fDCI 1
(MHz)
250
275
300
325
350
375
400
425
450
475
500
525
550
575
1
Time
(ps)
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
Data Port Setup and Hold Times (ps) at DLL Phase
−6
−93
468
−87
451
−82
422
−46
405
−23
383
−7
401
−46
385
4
358
11
354
−15
355
9
313
−7
311
−5
300
8
312
−5
−196
579
−172
537
−166
500
−114
483
−92
451
−82
466
−98
445
−52
408
−34
406
−51
399
−28
354
−52
356
−39
340
−28
348
−4
−312
707
−264
646
−256
598
−190
563
−180
524
−150
504
−161
503
−110
465
−92
457
−95
451
−77
399
−100
395
−74
378
−66
379
−3
−416
825
−364
757
−341
703
−271
647
−252
607
−225
569
−243
546
−170
524
−147
516
−147
499
−128
445
−147
438
−107
423
−102
414
−2
−530
947
−464
878
−426
803
−358
740
−328
682
−315
641
−303
604
−229
595
−209
573
−198
556
−183
500
−187
489
−147
468
−143
453
−1
−658
1067
−556
977
−515
897
−447
832
−409
762
−391
718
−384
674
−297
625
−269
637
−255
613
−233
555
−237
537
−192
510
−181
496
0
−770
1188
−653
1092
−622
1000
−538
914
−491
844
−461
783
−448
748
−394
692
−324
693
−313
675
−288
615
−285
592
−249
560
−245
544
+1
−878
1315
−756
1218
−715
1105
−612
1000
−574
930
−526
863
−513
826
−449
762
−386
731
−366
727
−333
668
−335
645
−302
610
−280
599
+2
−983
1442
−859
1311
−809
1203
−706
1100
−654
1011
−595
941
−578
890
−517
829
−446
792
−425
779
−390
726
−387
692
−352
659
−336
654
+3
−1093
1570
−956
1423
−900
1303
−806
1200
−731
1097
−661
1025
−643
965
−579
900
−509
852
−480
815
−438
783
−436
746
−397
710
−366
708
+4
−1193
1697
−1053
1537
−1001
1411
−891
1292
−819
1186
−726
1106
−713
1039
−641
966
−564
917
−530
873
−495
825
−483
799
−440
756
−406
759
+5
−1289
1777
−1151
1653
−1097
1522
−966
1380
−889
1277
−786
1187
−771
1110
−704
1032
−622
983
−585
930
−545
881
−530
850
−486
810
−443
806
+6
−1412
1876
−1251
1728
−1184
1612
−1044
1476
−959
1358
−853
1264
−833
1178
−752
1097
−672
1042
−640
988
−594
934
−581
909
−529
865
−488
847
Table 13 shows characterization data for selected fDCI frequencies. Other frequencies are possible; use Table 13 to estimate performance.
Table 13 shows the typical times for various DCI clock frequencies
that are required to calculate the data valid margin. Use Table 13 to
determine the amount of margin that is available for tuning of
the DSC sampling point.
Maximizing the opening of the eye in both the DCI and data
signals improves the reliability of the data port interface. Use
differential controlled impedance traces of equal length (that is,
delay) between the host processor and the AD9139 input. To
ensure coincident transitions with the data bits, implement the
DCI signal as an additional data line with an alternating
(010101…) bit sequence from the same output drivers that are
used for the data.
The DCI signal is ac-coupled by default; thus, removing the
DCI signal may cause DAC output chatter due to randomness
on the DCI input. To avoid this, disable the DAC output
whenever the DCI signal is not present by setting the DAC output
current power-down bit in Register 0x01[7] to 1. When the DCI
signal is again present, enable the DAC output by programming
Register 0x01[7] to 0.
Register 0x0D optimizes the DLL stability over the operating
frequency range. Table 14 shows the recommended settings.
Table 14. DLL Configuration Options
DCI Speed
≥350 MHz
<350 MHz
Register 0x0D
0x06
0x86
Poll the status of the DLL by reading the data status register at
Address 0x0E. Bit 0 indicates that the DLL is running and
attempting lock; Bit 7 is 1 when the DLL has locked. Bit 2 is 1
when a valid data clock input (DCI) is detected. The warning
bits in [6:4] in Register 0x0E can be used as indicators that the
DAC may be operating in a nonideal location in the delay line.
Note that these bits are read at the SPI port speed, which is
much slower than the actual speed of the DLL. This means they
can only show a snapshot of what is happening as opposed to
giving real-time feedback.
Rev. 0 | Page 20 of 56
Data Sheet
AD9139
In the following DLL configuration example, fDCI = 600 MHz,
DLL is enabled, and DLL phase offset = 0.
1. 0x5E → 0xFE /* Turn off LSB delay cell*/
2. 0x0D → 0x06 /* Select DLL configure
options */
3. 0x0A → 0xC0 /* Enable DLL and duty cycle
correction. Set DLL phase offset to 0 */
4. Read 0x0E[7:4] /* Expect 1000b if the DLL
is locked */
DLL Configuration Example 2
In the following DLL configuration example, fDCI = 300 MHz,
DLL is enable, and DLL phase offset = 0.
1. 0x5E → 0xFE /* Turn off LSB delay cell*/
2. 0x0D → 0x86 /* Select DLL configure
options */
3. 0x0A → 0xC0 /* Enable DLL and duty cycle
correction. Set DLL phase offset to 0 */
4. Read 0x0E[7:4] /* Expect 1000b if the DLL
is locked */
PARITY
The data interface can be continuously monitored by enabling
the parity bit feature in Register 0x6A[7] and configuring the
frame/parity bit as parity by setting Register 0x09 = 0x21. In
this case, the host sends a parity bit with each data sample. This
bit is set according to the following formulas, where n is the
data sample that is being checked:
For even parity,
XOR[FRM(n), D0(n), D1(n), D2(n), …, D15(n)] = 0
For odd parity,
XOR[FRM(n), D0(n), D1(n), D2(n), …, D15(n)] = 1
The parity bit is calculated over 17 bits (including the
frame/parity bit).
If a parity error occurs, the parity error counter (Register 0x6B
or Register 0x6C) increments. Parity errors on the bits sampled
by the rising edge of the DCI signal increment the rising edge
parity counter (Register 0x6B) and set the PARERRRIS bit
(Register 0x6A[0]). Parity errors on the bits sampled by the
falling edge of DCI increment the falling edge parity counter
(Register 0x6C) and set the PARERRFAL bit (Register 0x6A[1]).
The parity counter continues to accumulate until it clears or
until it reaches a maximum value of 255. To clear the count,
write a 1 to Register 0x6A[5].
To trigger an IRQ when a parity error occurs, write 1 to Bit 7 in
Register 0x04. This IRQ triggers when there is either a rising
edge or falling edge parity error. Observe the status of the IRQ
pin via Register 0x06[7] or by using the selected IRQx pin. Clear
the IRQ by writing a 1 to Register 0x06[7].
Use the parity bit feature to validate the interface timing. As
described previously, the host provides a parity bit with the data
samples, as well as configures the AD9139 to generate an IRQ.
The user can then sweep the sampling instance of the input
registers of the AD9139 to determine at what point sampling
errors occur. The sampling instance can be varied in discrete
increments by offsetting the nominal DLL phase shift value of
90° via SPI Register 0x0A[3:0].
SED OPERATION
The AD9139 provides on-chip sample error detection (SED)
circuitry that simplifies verification of the input data interface.
The SED compares the input data samples captured at the digital
input pins with a set of comparison values. The comparison values
are loaded into registers through the SPI port. Differences between
the captured values and the comparison values are detected.
Options are available for customizing SED test sequencing and
error handling.
The SED circuitry allows the application to test a short user
defined pattern to confirm that the high speed source
synchronous data bus is correctly implemented and meets the
timing requirement. Unlike the parity bit, the SED circuitry is
expected to be used during initial system calibration, before the
AD9139 is in use in the application. The SED circuitry operates
on a data set made up of user defined input words, denoted as
S0, S1, S2, and S3. The user defined pattern consists of
sequential data-word samples (S0 is sampled on the rising edge
of DCI, S1 is sampled on the following falling edge of DCI, S2 is
sampled on the following DCI rising edge, and S3 is sampled on
the following DCI falling edge). The user loads this data pattern
in the byte format into Register 0x61 through Register 0x68.
The depth of the user defined pattern is selectable via Bit 4 of
the SED_CTRL register (0x60). A default of 0, means a depth of
two (using S0 and S1), and a 1 means a depth of four (using S0,
S1, S2, and S3, and requiring the use of frame signal input to
define S0 to the SED state machine). To properly align the input
samples using a depth of 4, S0 is indicated by asserting the
frame signal for a minimum of two complete input samples as
shown in. The frame signal can be issued once at the start of the
data transmission, or it can be asserted repeatedly at intervals
coinciding with the S0 word.
FRAME
DATA[15:0]
S0
S1
S2
S3
S0
S1
11744-037
DLL Configuration Example 1
Figure 32. Timing Diagram of Extended FRAMEx Signal Required to Align
Input Data for SED
The SED has three flag bits (Register 0x60, Bit 0, Bit 1, and
Bit 2) that indicate the results of the input sample comparisons.
The sample error detected bit (Register 0x60, Bit 0) is set when
an error is detected and remains set until cleared.
The autosample error detection (AED) mode is an autoclear
mode that has two effects: it activates the compare fail bit and
the compare pass bit (Register 0x60, Bit 1 and Bit 2). The
compare pass bit sets if the last comparison indicated the
sample was error free. The compare fail bit sets if an error is
Rev. 0 | Page 21 of 56
AD9139
Data Sheet
DELAY LINE INTERFACE MODE
detected. The compare fail bit is automatically cleared by the
reception of eight consecutive error free comparisons when
autoclear mode is enabled.
The sample error flag can be configured to trigger an IRQ when
active, if desired, by enabling the appropriate bit in the event
flag register (Register 0x04, Bit 6).
SED EXAMPLE
Normal Operation
The following example illustrates the AD9139 SED configuration
for continuously monitoring the input data and assertion of
an IRQ when a single error is detected.
2.
3.
4.
Write to the following registers to enable the SED and load
the comparison values with a four-deep user pattern.
Comparison values can be chosen arbitrarily; however,
choosing values that require frequent bit toggling provides
the most robust test.
a. Register 0x61[7:0]→ S0[7:0]
b. Register 0x62[7:0]→ S0[15:8]
c. Register 0x63[7:0]→ S1[7:0]
d. Register 0x64[7:0]→ S1[15:8]
e. Register 0x65[7:0]→ S2[7:0]
f. Register 0x66[7:0]→ S2[15:8]
g. Register 0x67[7:0]→ S3[7:0]
h. Register 0x68[7:0]→ S3[15:8]
Enable SED.
a. Register 0x60 → 0xD0
b. Register 0x60 → 0x90
Enable the SED error detect flag to assert the IRQx pin.
a. Register 0x04[6] = 1
Begin transmitting the input data pattern (FRAMEx is also
required because the depth of the pattern is 4).
Table 15. Delay Line Setup and Hold Times (Guaranteed)
Delay Setting
Register 0x5E[7:0]
Register 0x5F[2:0]
tS (ns)1
tH (ns)
|tS + tH| (ns)
1
0
0x00
0x60
−0.81
1.96
1.15
1
0x80
0x67
−0.97
2.20
1.23
3
0xFE
0x67
−1.28
2.79
1.51
There is a fixed 1.38 ns delay on the DCI signal when the delay line
is enabled. Each tap adds a nominal delay of 200 ps to the fixed
delay. To achieve the best timing margin, that is, to center the
setup and hold window in the middle of the data eye, the user
may need to add a delay on the data bus with respect to the DCI
signal in the data source. Figure 33 is an example of calculating
the optimal external delay.
Register 0x0D[4] configures the DCI signal coupling settings
for optimal interface performance over the operating frequency
range. It is recommended that this bit be set to 1 (dc-coupled
DCI) in the delay line interface mode.
tDELAY = 0.13ns
tDATA PERIOD = 2.5ns
INPUT DATA[15:0]
WITH
OPTIMIZED DELAY
2
0xF0
0x67
−1.13
2.53
1.40
The negative sign indicates the direction of the setup time. The setup time is
defined as positive when it is on the left side of the clock edge and negative
when it is on the right side of the clock edge.
DATA EYE
|tS| = 0.81ns
|tH| = 1.96ns
DCI = 200MHz
NO DATA TRANSITION
Figure 33. Example of Interfacing Timing in the Delay Line-Based Mode
Rev. 0 | Page 22 of 56
11744-038
1.
The DLL is designed to help ease the interface timing requirements in very high speed data rate applications. The DLL has
a minimum supported interface speed of 250 MHz, as shown
in Table 2. For interface rates below this speed, use the interface
delay line. In this mode, the DLL is powered off and a four-tap
delay line is provided for the user to adjust the timing between
the data bus and the DCI. Table 15 specifies the setup and hold
times for each delay tap.
Data Sheet
AD9139
Interface Timing Requirements
SPI Sequence to Enable Delay Line-Based Mode
The following example shows how to calculate the optimal
delay at the data source to achieve the best sampling timing in
the delay line interface mode:
Use the following SPI sequence to enable the delay line-based
mode:
•
•
fDCI = 200 MHz
Delay setting = 0
The shadow area in Figure 33 is the interface setup and hold
time window set to 0. To optimize the interface timing, this
window must be placed in the middle of the data transitions.
Because the input is double data rate, the available data period
is 2.5 ns. Therefore, the optimal data bus delay, with respect to
the DCI signal at the data source, can be calculated as
t DELAY =
(| t S | + | t H |) t DATA PERIOD
−
= 1.38 − 1.25 = 0.13 ns
2
2
Rev. 0 | Page 23 of 56
1.
0x5E → 0x00 /* Configure the delay
setting */
2.
0x5F → 0x60
3.
4.
0x0D → 0x16 /* DC couple DCI */
0x0A → 0x00 /* Turn off DLL and duty
cycle correction */
AD9139
Data Sheet
FIFO OPERATION
The AD9139 adopts source synchronous clocking in the data
receiver (see the Data Interface section). The nature of source
synchronous clocking is the creation of a separate clock domain
at the receiving device. In the DAC, it is the DAC clock domain,
that is, the DACCLK. Therefore, there are two clock domains
inside of the DAC: the DCI and the DACCLK. Often, these two
clock domains are not synchronous, requiring an additional
stage to adjust the timing for proper data transfer. In the
AD9139, a FIFO stage is inserted between the DCI and DACCLK
domains to transfer the received data into the core clock
domain (DACCLK) of the DAC.
is read from the FIFO register, which is determined by the read
pointer, and fed into the digital datapath. The value of the read
pointer is incremented every time data is read into the datapath
from the FIFO. The FIFO pointers are incremented at the data
rate, which is the DACCLK rate divided by the interpolation rate.
The AD9139 contains a 2-channel, 16-bit wide, eight-word deep
FIFO. The FIFO acts as a buffer that absorbs timing variations
between the two clock domains. The timing budget between the
two clock domains in the system is significantly relaxed due to
the depth of the FIFO.
Normally, data is written to and read from the FIFO at the same
rate to maintain a constant FIFO depth. If data is written to the
FIFO faster than data is read, the FIFO depth increases. If data
is read from the FIFO faster than data is written to it, the FIFO
depth decreases. For optimal timing margin, maintain the FIFO
depth near half full (a difference of four between the write
pointer and read pointer values). The FIFO depth represents the
FIFO pipeline delay and is part of the overall latency of the
AD9139.
Figure 34 shows the block diagram of the datapath through the
FIFO. The input data is latched into the device, formatted, and
then written into the FIFO register, which is determined by the
FIFO write pointer. The value of the write pointer is incremented
every time a new word is loaded into the FIFO. Meanwhile, data
Valid data is transmitted through the FIFO as long as the FIFO
does not overflow (full) or underflow (empty). An overflow or
underflow condition occurs when the write pointer and read
pointer point to the same FIFO slot. This simultaneous access of
data leads to unreliable data transfer through the FIFO and must be
avoided.
FIFO WRITE CLOCK
FIFO READ CLOCK
DACCLK
÷INT
FIFO
FIFO SLOT 0
LATCHED
DATA[15:0]
DATA
FORMAT
SPI FIFO RESET
REG 0x25[0]
READ POINTER
FIFO SLOT 3
[15:0]
FIFO SLOT 4
[15:0]
WRITE
POINTER
FRAME
FIFO SLOT 2
[15:0]
DATA PATH
DAC
FIFO SLOT 5
FIFO SLOT 6
FIFO SLOT 7
RESET
LOGIC
FIFO LEVEL
FIFO LEVEL REQUEST
REG 0x23
Figure 34. Block Diagram of FIFO
Rev. 0 | Page 24 of 56
11744-039
DATA
RECEIVER
INPUT DATA[15:0]
FIFO SLOT 1
RETIMED DCI
DCI
Data Sheet
AD9139
RESETTING THE FIFO
SERIAL PORT INITIATED FIFO RESET
Upon device power-on, the read and write pointers start to roll
around the FIFO from an arbitrary slot; consequently, the FIFO
depth is unknown. To avoid a concurrent read and write to the
same FIFO address and to assure a fixed pipeline delay from
power-on to power-on, it is important to reset the FIFO pointers to
a known state each time the device powers on or wakes up. This
state is specified in the requested FIFO level (FIFO depth and
FIFO level are used interchangeably in this data sheet), which
consists of two parts: the integer FIFO level and the fractional
FIFO level.
A SPI initiated FIFO reset is the most common method to reset
the FIFO. To initialize the FIFO level through the serial port,
toggle FIFO_SPI_RESET_REQUEST (Register 0x25, Bit 0)
from 0 to 1 and back to 0. When the write to this register is
complete, the FIFO level is initialized to the requested FIFO level
and the readback of FIFO_SPI_RESET_ACK (Register 0x25, Bit 1)
is set to 1. The FIFO level readback, in the same format as the
FIFO level request, must be within ±1 DACCLK cycle of the
requested level. For example, if the requested value is 0x40 in
2× interpolation, the readback value should be one of the
following: 0x31, 0x40, or 0x41. The range of ±1 DACCLK cycle
indicates the default DAC latency uncertainty from power-on
to power-on without turning on synchronization.
The integer FIFO level represents the difference of the states
between the read and write points in the unit of input data period
(1/fDATA). The fractional FIFO level represents the difference of
the FIFO pointers that is smaller than the input data period.
The resolution of the fractional FIFO level is the input data period
divided by the interpolation ratio and, thus, it is equal to one
DACCLK cycle.
The exact FIFO level, that is, the FIFO latency, can be calculated
by
FIFO Latency = Integer Level + Fractional Level
Because the FIFO has eight data slots, there are eight possible
FIFO integer levels. The maximum supported interpolation rate
in the AD9139 is 2× interpolation. Therefore, there are two
possible FIFO fractional levels.
Two 3-bit registers in Register 0x23 are assigned to represent
the two FIFO levels, as follows:
•
•
Bits[6:4] represent the FIFO integer level
Bits[2:0] represent the FIFO fractional level
For example, if the interpolation rate is 2× and the desired total
FIFO depth is 4.5 input data periods, set the FIFO_LEVEL_
CONFIG (Register 0x23) to 0x41 (4 means four data cycles and
1 means one DAC cycle, which is half of a data cycle, in this
case).
Reset the FIFO and initialize the FIFO level using either of the
following methods:
•
•
Serial port (SPI) initiated FIFO reset
Frame initiated FIFO reset
The recommended procedure for a serial port FIFO reset is as
follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Configure the DAC in the desired interpolation mode
(Register 0x28[7]).
Ensure that the DACCLK and DCI clocks are running and
stable at the clock inputs.
Program Register 0x23 to 0x41.
Request the FIFO level reset by setting Register 0x25[0] to 1.
Verify that the device acknowledges the request by setting
Register 0x25[1] to 1.
Remove the request by setting Register 0x25[0] to 0.
Verify that the device drops the acknowledge signal by
setting Register 0x25[1] to 0.
Read back Register 0x06[2] and Register 0x06[1]. If both
bits are 0, continue to Step 9. If any of the two bits is 1,
program Register 0x23 to 0x40.
Read back Register 0x24 multiple times to verify that the
actual FIFO level is set to the requested level (Register 0x23),
and that the readback values are stable. By design, the
readback is within ±1 DACCLK around the requested
level.
FRAME INITIATED FIFO RESET
The frame input has two functions. One function is to indicate
the beginning of a byte stream in the byte interface mode, as
described in the Data Interface section. The other function is
to initialize the FIFO level by asserting the frame signal high
for at least the time interval required to load two samples of
data to the DAC. This corresponds to one DCI period in word
mode and two DCI periods in byte mode. Note that this
requirement of the frame pulse length is longer than that of the
frame signal when it serves only to assemble the byte stream.
The device accepts either a continuous frame or a one shot
frame signal.
Rev. 0 | Page 25 of 56
AD9139
Data Sheet
In the continuous reset mode, the FIFO responds to every valid
frame pulse and resets itself. In the one shot reset mode, the
FIFO responds only to the first valid frame pulse after the
FRAME_RESET_MODE bits (Register 0x22[1:0]) are set.
Therefore, even with a continuous frame input, the FIFO resets
one time only; this prevents the FIFO from toggling between
the two states from periodic resets. The one shot frame reset
mode is the default and the recommended mode.
The recommended procedure for a frame initiated FIFO reset is
as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Configure the DAC in the desired interpolation mode
(Register 0x28[7]).
Ensure that the DACCLK and DCI clocks are running and
stable at the clock inputs.
Ensure that the DLL is locked (if using DLL Mode) or the
DCI clock is being sent properly (if using bypass mode).
Program Register 0x23 to 0x41.
Configure the FRAME_RESET_MODE bits
(Register 0x22[1:0]) to 10.
Choose one shot frame mode by writing 0 to
EN_CON_FRAME_RESET (Register 0x22[2]).
Toggle the frame input from 0 to 1 and back to 0. The pulse
width must be longer than the minimum requirement.
Read back Register 0x06[2] and Register 0x06[1]. If both
bits are 0, continue to Step 9. If any of the two bits are 1,
program Register 0x23 to 0x40.
Read back Register 0x24 multiple times to verify that the
actual FIFO level is set to the requested level (Register 0x23)
and the readback values are stable. By design, the readback
should be within ±1 DACCLK around the requested level.
These procedures apply in synchronization off mode only. For
resetting FIFO in synchronization on mode, refer to the
synchronization procedure in the Multidevice Synchronization
and Fixed Latency section. FIFO reset is one of the steps to
achieve synchronization.
Monitoring the FIFO Status
Monitor the real-time FIFO status from SPI Register 0x24, which
reflects the real-time FIFO depth after a FIFO reset. Without
timing drifts in the system, this readback does not change from
that which resulted from the FIFO reset. When there is a timing
drift or other abnormal clocking situation, the FIFO level
readback can change. However, as long as the FIFO does not
overflow or underflow, there is no error in data trans-mission.
The status bits in Register 0x06, Bits[2:1] indicate if there are
FIFO underflows or overflows. Latch the status of the two bits
to trigger the hardware interrupts, IRQ1 and IRQ2. To enable
latching and interrupts, configure the corresponding bits in
Register 0x03 and Register 0x04.
Rev. 0 | Page 26 of 56
Data Sheet
AD9139
DIGITAL DATAPATH
The block diagram in Figure 35 shows the functionality of the
digital datapath. The digital processing includes
0
One half-band interpolation filter
An inverse sinc filter
A gain and offset adjustment block
DIGITAL GAIN
AND OFFSET
ADJUSTMENT
–0.02
–0.04
–0.06
–0.10
Figure 35. Block Diagram of Digital Datapath
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
1.8
2.0
FREQUENCY (Hz)
INTERPOLATION FILTERS
11744-041
–0.08
Figure 36. Pass-Band Detail of 2× Mode
The transmit path contains a half-band interpolation filter. The
interpolation filters provides a 2× increase in output data rate and a
low-pass function.
The usable bandwidth in 1× interpolation is the DCI rate or half
of the input data rate. The usable bandwidth in 2× interpolation
is 0.8 times the DCI rate or 0.4 times the input data rate. It is
defined as the frequency band over which the filters have a
pass-band ripple of less than ±0.001 dB and a stop-band
rejection of greater than 85 dB.
0
–10
–20
MAGNITUDE (dB)
The AD9139 provides two interpolation modes. Each mode offers
a different usable signal bandwidth in an operating mode. Which
mode to select depends on the required signal bandwidth and the
DAC update rate. Refer to Table 5 for the maximum speed and
signal bandwidth of each interpolation mode.
10
2× Interpolation Mode
Figure 36 and Figure 37 show the pass-band and all-band filter
response for 2× mode. Note that the transition from the
transition band to the stop band is much sharper than the transition from the pass band to the transition band. Therefore, when
the desired output signal moves out of the defined pass band,
the signal image, which is supposed to be suppressed by the stop
band, grows faster than the droop of the signal itself due to the
degraded pass-band flatness. In cases where the degraded image
rejection is acceptable or can be compensated by the analog
low-pass filter at the DAC output, it is possible to let the output
signal extend beyond the specified usable signal bandwidth.
Rev. 0 | Page 27 of 56
–30
–40
–50
–60
–70
–80
–90
–100
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
FREQUENCY (Hz)
Figure 37. All-Band Response of 2× Mode
11744-042
INV
SINC
11744-040
HB1
MAGNITUDE (dB)
•
•
•
0.02
AD9139
Data Sheet
Upper Coefficient
H(55)
H(54)
H(53)
H(52)
H(51)
H(50)
H(49)
H(48)
H(47)
H(46)
H(45)
H(44)
H(43)
H(42)
H(41)
H(40)
H(39)
H(38)
H(37)
H(36)
H(35)
H(34)
H(33)
H(32)
H(31)
H(30)
H(29)
Integer Value
−4
0
+13
0
−32
0
+69
0
−134
0
+239
0
−401
0
+642
0
−994
0
+1512
0
−2307
0
+3665
0
−6638
0
+20,754
+32,768
INVERSE SINC FILTER
The AD9139 provides a digital inverse sinc filter to compensate
for the DAC rolloff over frequency. The inverse sinc (sinc−1) filter
is a seven-tap FIR filter. Figure 38 shows the frequency response
of sin(x)/x rolloff, the inverse sinc filter, and their composite
response. The composite response has less than ±0.05 dB passband ripple up to a frequency of 0.4 × fDAC.
1
0
–1
sin(x)/x ROLLOFF
SINC–1 FILTER
COMPOSITE
–2
–3
–4
–5
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
FREQUENCY (Hz)
0.45
0.50
11744-043
Lower Coefficient
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(7)
H(8)
H(9)
H(10)
H(11)
H(12)
H(13)
H(14)
H(15)
H(16)
H(17)
H(18)
H(19)
H(20)
H(21)
H(22)
H(23)
H(24)
H(25)
H(26)
H(27)
H(28)
To provide the necessary peaking at the upper end of the pass
band, the inverse sinc filter has an intrinsic insertion loss of
approximately 3.8 dB. Offset the loss of the digital gain by
increasing the digital gain adjustment setting to minimize the
impact on the output signal-to-noise ratio (SNR). However, care is
needed to ensure that the additional digital gain does not cause
signal saturation, especially at high output frequencies. The sinc−1
filter is disabled by default; it can be enabled by setting the
INVSINC_ENABLE bit to 1 in Register 0x27[7]).
MAGNITUDE (dB)
Table 16. Half-Band Filter 1 Coefficient
Figure 38. Responses of sin(x)/x Roll-Off (Blue), Sinc−1 Filter (Red), and
Composite of Both (Black)
Table 17. Inverse Sinc Filter
Lower Coefficient
H(1)
H(2)
H(3)
H(4)
Upper Coefficient
H(7)
H(6)
H(5)
Integer Value
−1
+4
−16
+192
DIGITAL FUNCTION CONFIGURATION
The inverse sinc filter can be enabled or disabled. The pipeline
latency of the DAC is dependent on which of the digital
function blocks are enabled or disabled. If fixed DAC pipeline
latency is desired during operation, leave each digital function
block always enabled or always disabled after initial configuration.
Rev. 0 | Page 28 of 56
Data Sheet
AD9139
MULTIDEVICE SYNCHRONIZATION AND FIXED LATENCY
A DAC introduces a variation of pipeline latency to a system.
The latency variation causes the phase of a DAC output to vary
from power-on to power-on. Therefore, the output from
different DAC devices may not be perfectly aligned even with
well aligned clocks and digital inputs. The skew between
multiple DAC outputs varies from power-on to power-on.
In applications such as transmit diversity or digital predistortion,
where deterministic latency is desired, the variation of the
pipeline latency must be minimized. Deterministic latency in
this data sheet is defined as a fixed time delay from the digital
input to the analog output in a DAC from power-on to power-on.
Multiple DAC devices are considered synchronized to each other
when each DAC in this group has the same constant latency
from power-on to power-on. Three conditions must be
identical in all of the ready-to-sync devices before these devices
are considered synchronized:



The phase of DAC internal clocks
The FIFO level
The alignment of the input data
VERY SMALL INHERENT LATENCY VARIATION
The innovative architecture of the AD9139 minimizes the
inherent latency variation. The worst-case variation in the
AD9139 is two DAC clock cycles. For example, in the case of a
1.6 GHz sample rate, the variation is less than 1.25 ns in any
scenario. Therefore, without turning on the synchronization
engine, the DAC outputs from multiple AD9139 devices are
guaranteed to be aligned within two DAC clock cycles, regardless
of the timing between the DCI and the DACCLK. No additional
clocks are required to achieve this accuracy. The user must reset
the FIFO in each DAC device through the SPI at startup.
Therefore, the AD9139 can decrease the complexity of system
design in multiple transmit channel applications.
Note the alignment of the DCI signals in the design. The DCI
signal is used as a reference in the AD9139 design to align the
FIFO and the phase of internal clocks in multiple parts. The
achieved DAC output alignment depends on how well the DCI
signals are aligned at the input of each device. The following
equation is the expression of the worst-case DAC output
alignment accuracy in the case of DCI signal mismatches:
FURTHER REDUCING THE LATENCY VARIATION
For applications that require finer synchronization accuracy
(DAC latency variation < 2 DAC clock cycles), the AD9139 has
a provision for enabling multiple devices to be synchronized to
each other within a single DAC clock cycle.
To reduce further the latency variation in the DAC, the
synchronization machine must be turned on and two external
clocks (frame and sync) must be generated in the system and
fed to all the DAC devices.
Setup and Hold Timing Requirement
The sync clock (SYNCCLK) serves as a reference clock in the
system to reset the clock generation circuitry in multiple AD9139
devices simultaneously. Inside the DAC, the sync clock is sampled
by the DACCLK to generate a reference point for aligning the
internal clocks; consequently, there is a setup and hold timing
requirement between the sync clock and the DAC clock.
Adopting the continuous frame reset mode (where the FIFO
and sync engine periodically reset) demands meeting the timing
requirements between the sync clock and the DAC clock;
otherwise, the device can lose lock and corrupt the output. In
the one shot frame reset mode, it is still recommended that this
timing be met at the time when the sync routine is run because
not meeting the timing can degrade the sync alignment
accuracy by one DAC clock cycle, as shown in Table 18.
The AD9139 also provides a mode by which to synchronize the
device in a one shot manner and to continue to monitor the
synchronization status. It provides a continuous sync and frame
clock to synchronize the device once and ignore the clock cycles
after detecting the first valid frame pulse. In this way, the user can
monitor the sync status without periodically resynchronizing the
device; to engage one shot sync mode, set Register 0x22[2] to 0.
Table 18. Sync Clock and DAC Clock Setup and Hold Times
Falling Edge Sync Timing (Default)
tS (ns)
tH (ns)1
|tS + tH| (ns)
1
Min (ps)
324
−92
232
The negative sign indicates the direction of the setup time. The setup time is
defined as positive when it is on the left side of the clock edge and negative
when it is on the right side of the clock edge.
tSK (OUT) = tSK (DCI) + 2/fDAC
where:
tSK (OUT) is the worst-case skew between the DAC outputs from
two AD9139 devices.
tSK (DCI) is the skew between two DCI signals at the DCI input of
the two AD9139 devices.
fDAC is the DACCLK frequency.
The better the alignment of the DCI signals, the smaller the
overall skew between the two DAC outputs.
SYNCHRONIZATION IMPLEMENTATION
The AD9139 allows the user to choose either the rising or
falling edge of the DAC clock to sample the sync clock, which
makes it easier to meet the timing requirements. Ensure that the
sync clock, fSYNC, is 1/8 × fDCI or slower by a factor of 2n, n being
an integer (1, 2, 3…). Note that there is a limit on how slow the
sync clock can be because of the ac coupling nature of the sync
clock receiver. Choose an appropriate value of the ac coupling
capacitors to ensure that the signal swing meets the data sheet
specification, as listed in Table 2.
Rev. 0 | Page 29 of 56
AD9139
Data Sheet
The frame clock resets the FIFO in multiple AD9139 devices.
The frame can be either a one shot or continuous clock. In either
case, the pulse width of the frame must be longer than one DCI
cycle in the word mode and two DCI cycles in the byte mode.
When the frame is a continuous clock, fFRAME, ensure that it is
1/8 × fDCI or slower by a factor of 2n, n being an integer (1, 2,
3…). One shot frame reset is the recommended method. Because
the DCI and the DAC clock are generated in two separate clock
domains, timing drifts between the two clocks can cause the FIFO
level to toggle between two values in the continuous reset mode
and, thus, to corrupt the DAC output. Table 19 lists the
requirements of the frame clock in various conditions.
SYNCHRONIZATION PROCEDURES
When the sync accuracy of an application is less precise than
two DAC clock cycles, it is recommended to turn off the
synchronization machine because no additional steps are required,
other than the regular start-up procedure sequence.
For applications that require more precise sync accuracy than
two DAC clock cycles, use the procedures in the following
sections to set up the system and configure the device.
Table 19. Frame Clock Speed and Pulse Width Requirement
Sync Clock
One Shot
Continuous
1
Maximum
Speed
N/A1
fDCI/8
Minimum Pulse Width
For both one shot and continuous
sync clocks, word mode = one DCI
cycle, and byte mode = two DCI
cycles.
N/A means not applicable.
Rev. 0 | Page 30 of 56
Data Sheet
AD9139
1. DAC HARDWARE RESET.
PULL THE DAC RESET PIN FROM HIGH TO LOW THEN BACK TO HIGH.
2. SET UP DAC INTERPOLATION MODE.
PROGRAM REG 0x28
3. RUN CLOCKS (DAC CLOCK, SYNC CLOCK, DCI, FRAME).
4. MAKE SURE DLL IS LOCKED IF IN DLL MODE, OR DELAY LINE IS ENABLED
AND PROPERLY CONFIGURED IF IN DELAY LINE MODE.
SYSTEM SETUP;
PROGRAM DAC INTERPOLATION MODES
SET FIFO OFFSET TO 0
WRITE REG 0x23 = 0x00
ENABLE SYNC ENGINE
WRITE REG 0x21 = 0x01, IF RISING EDGE SYNC.
OR = 0x03, IF FALLING EDGE SYNC.
WRITE REG 0x22 = 0x18
IN THIS MODE, THE PART ONLY RESPONDS TO THE
FIRST VALID FRAME PULSE AND RESETS THE FIFO ONE TIME.
SET FRAME UPDATE MODE
REG 0x05[6:5] = 0b00
REG 0x05[6] = 0b1
READ REG 0x05[6:5] ([SYNC_LOST;SYNC_LOCKED]).
IF THE SYNC-DAC SETUP/HOLD TIMES ARE NOT MET, THE SYNC MAY
NOT LOCK. CHANGE THE SYNC EDGE WHEN REENABLING THE SYNC
NEXT ROUND.
SYNC LOST/LOCK
FLAG BITS?
DISABLE SYNC
REG 0x05 [6:5] = 0b01
CALCULATE AND ADJUST
FIFO OFFSET
. LEVEL.
ADJUST FIFO OFFSET TO ACHIEVE THE OPTIMAL FIFO
1. READ BACK REG 0x24. LET A = REG 0x24[6:4], B = REG 0x24[2:0].
2. LET X = INTERPOLATION RATE. (VALID NUMBERS ARE 1 AND 2).
3. OFFSET = (4 × X + 1) – (A × X + B)
4. IF OFFSET ≥ 0,
OFFSET = OFFSET.
ELSE
OFFSET = 8 × X + OFFSET.
5. LET A’ = FLOOR (OFFSET/X), B’ = OFFSET – (A’) × X
6. WRITE REG 0x23[6:4] = A’, REG 0x23[2:0] = B’.
7. SAVE A’ AND B’. (USE THE SAME A’ AND B’ VALUES WHEN
ADJUSTING THE FIFO OFFSET IN THE OTHER DACs).
REG 0x06[2:1] = 0b00
FIFO UF/OFF
LAG BITS?
READ REG 0x06[2:1].
IF NO FLAGS, SYNCHRONIZATION IS COMPLETE.
SKIP THE NEXT STEP.
IF EITHER BIT IS 1, FOLLOW THE NEXT STEP.
REG 0x06[2:1] ≠ 0b00
FURTHER ADJUST FIFO OFFSET
WAKE UP DACs AND RUN
READ REG 0x23 AND RECORD IT AS RB1.
WRITE REG 0x23 = RB1 – 0x01;
READ REG 0x23 AND RECORD IT AS RB2.
WRITE REG 0x23 = RB2 + 0x01
1. WAKE UP DACs
WRITE REG 0x01 = 0x00.
2. START DATA TRANSMISSION.
Figure 39. Synchronization Procedure Diagram
Rev. 0 | Page 31 of 56
11744-044
WRITE REG 0x21 = 0x00
AD9139
Data Sheet
INTERRUPT REQUEST OPERATION
The AD9139 provides an interrupt request output signal on
Pin 50 and Pin 51 (IRQ2 and IRQ1, respectively) to notify
an external host processor of significant device events. Upon
assertion of the interrupt, query the device to determine the
precise event that occurred. The IRQ1 pin and IRQ2 pin are
open-drain, active low outputs. Pull the IRQx pin high
(DVDD18 supply) external to the device. The IRQx pin can be
tied to the interrupt pins of other devices with open-drain
outputs to wire-OR these pins together.
method is by writing 1 to the corresponding event flag bit. The
second method is to use a hardware or software reset to clear the
INTERRUPT_SOURCE signal.
The IRQ2 circuitry works in the same way as the IRQ1 circuitry.
Any one or multiple event flags can be enabled to trigger the
IRQx pins. The user can select one or both hardware interrupt
pins for the enabled event flags. Register 0x07 and Register 0x08
determine the pin to which each event flag is routed. Set Register
0x07 and Register 0x08 to 0 for IRQ1 and set these registers to 1
for IRQ2.
Eleven event flags provide visibility into the device. These flags
are located in the two event flag registers, Register 0x05 and
Register 0x06. The behavior of each event flag is independently
selected in the interrupt enable registers, Register 0x03 and
Register 0x04. When the flag interrupt enable is active, the event
flag latches and triggers the IRQ1 and/or IRQ2 pins. When the
flag interrupt is disabled, the event flag monitors the source
signal, but the IRQ1 and IRQ2 pins remain inactive.
INTERRUPT SERVICE ROUTINE
Interrupt request management starts by selecting the set of
event flags that require host intervention or monitoring. Enable
the events that require host action so that the host is notified
when they occur. For events requiring host intervention upon
IRQx activation, run the following routine to clear an interrupt
request:
INTERRUPT WORKING MECHANISM
1.
Figure 40 shows the interrupt related circuitry and how the event
flag signals propagate to the IRQx output. The INTERRUPT_
ENABLE signal represents one bit from the interrupt enable
register. The EVENT_FLAG_SOURCE signal represents one bit
from the event flag register. The EVENT_FLAG_SOURCE signal
represents one of the device signals that can be monitored, such as
the PLL_LOCK signal from the PLL phase detector or the
FIFO_OVERFLOW signal from the FIFO controller.
2.
3.
4.
5.
6.
When an interrupt enable bit is set high, the corresponding event
flag bit reflects a positively tripped version of the EVENT_FLAG_
SOURCE signal; that is, the event flag bit is latched on the rising
edge of the EVENT_FLAG_SOURCE signal. This signal also
asserts the external IRQx pins.
Read the status of the event flag bits that are being
monitored.
Set the interrupt enable bit low to monitor the unlatched
EVENT_FLAG_SOURCE signal directly.
Perform any actions that may be required to clear the
EVENT_FLAG_SOURCE signal. In many cases, no
specific actions are required.
Read the event flag to verify that the actions taken have
cleared the EVENT_FLAG_SOURCE signal.
Clear the interrupt by writing 1 to the event flag bit.
Set the interrupt enable bits of the events to be monitored.
Note that some EVENT_FLAG_SOURCE signals are latched
signals. Clear these signals by writing to the corresponding
event flag bit. For more information about each of the event
flags, see the Device Configuration Register Map and
Description section.
When an interrupt enable bit is set low, the event flag bit reflects
the present status of the EVENT_FLAG_SOURCE signal, and
the event flag has no effect on the external IRQx pins.
Clear the latched version of an event flag (the INTERRUPT_
SOURCE signal) in one of two ways. The recommended
0
1
EVENT_FLAG
IRQ
INTERRUPT_ENABLE
EVENT_FLAG_SOURCE
INTERRUPT_
SOURCE
OTHER
INTERRUPT
SOURCES
11744-045
WRITE_1_TO_EVENT_FLAG
DEVICE_RESET
Figure 40. Simplified Schematic of IRQx Circuitry
Rev. 0 | Page 32 of 56
Data Sheet
AD9139
TEMPERATURE SENSOR
The AD9139 has a diode-based temperature sensor for measuring
the temperature of the die. The temperature reading is accessed
using Register 0x1D and Register 0x1E. The temperature of the
die can be calculated as
TDIE =
(DIETEMP[15:0] − 41,237)
106
TA = TDIE – PD × θJA = 50 – 0.8 × 20.7 = 33.4°C
where TDIE is the die temperature in degrees Celsius.
The temperature accuracy is ±7°C typical over the −40°C to
+85°C range with one point temperature calibration against a
known temperature. See Figure 41 for a typical plot of the die
temperature code readback vs. die temperature.
51000
49000
where:
TA is the ambient temperature in degrees Celsius.
TDIE is the die temperature in degrees Celsius.
PD is power consumption of the device.
θJA is the thermal resistance from junction to ambient of the
AD9139, as shown in Table 7.
To use the temperature sensor, it must be enabled by setting
Register 0x1C[0] to 1. In addition, to obtain accurate readings,
set the die temperature control register (Register 0x1C) to 0x03.
47000
45000
43000
41000
39000
37000
35000
–40 –30 –20 –10
0
10
20
30
40
50
60
70
80
90
TEMPERATURE (°C)
11744-046
DIE CODE READBACK
Estimates of the ambient temperature can be made if the power
dissipation of the device is known. For example, if the device
power dissipation is 800 mW and the measured die temperature
is 50°C, then calculate the ambient temperature as
Figure 41. Die Temperature Code Readback vs. Die Temperature
Rev. 0 | Page 33 of 56
AD9139
Data Sheet
DAC INPUT CLOCK CONFIGURATIONS
The AD9139 DAC sample clock (DACCLK) can be sourced
directly or by clock multiplying. Clock multiplying employs the
on-chip phase-locked loop (PLL) that accepts a reference clock
operating at a submultiple of the desired DACCLK rate. The
PLL then multiplies the reference clock up to the desired DACCLK
frequency, which then generates all of the internal clocks
required by the DAC. The clock multiplier provides a high
quality clock that meets the performance requirements of most
applications. Using the on-chip clock multiplier removes the
burden of generating and distributing the high speed DACCLK.
The second mode bypasses the clock multiplier circuitry and
sources DACCLK directly to the DAC core. This mode lets the user
source a very high quality clock directly to the DAC core.
DRIVING THE DACCLK AND REFCLK INPUTS
The DACCLKx and REFCLKx differential inputs share similar
clock receiver input circuitry (see Figure 42 for a simplified circuit
diagram of the input). The on-chip clock receiver has a differential
input impedance of about 10 kΩ. It is self biased to a commonmode voltage of about 1.25 V. Drive the inputs by differential
PECL or LVDS drivers with ac coupling between the clock
source and the receiver.
1nF~100nF
AD9139
DACCLKP,
REFP/SYNCP
Direct clocking with a low noise clock produces the lowest noise
spectral density at the DAC outputs. To select the differential
clock inputs as the source for the DAC sampling clock, set the
PLL enable bit (Register 0x12[7]) to 0. This powers down the
internal PLL clock multiplier and selects the input from the
DACCLKP and DACCLKN pins as the source for the internal
DAC sampling clock. The REFCLKx input can remain floating.
The device also has clock duty cycle correction circuitry and
differential input level correction circuitry. Enabling these circuits
can provide improved performance in some cases. The control
bits for these functions are in Register 0x10 and Register 0x11.
CLOCK MULTIPLICATION
The on-chip PLL clock multiplier circuit generates the DAC
sample rate clock from a lower frequency reference clock. When
the PLL enable bit (Register 0x12[7]) is set to 1, the clock
multiplication circuit generates the DAC sampling clock from
the lower rate REFCLK input and the DACCLKx input remains
floating. See Figure 43 for the functional diagram of the clock
multiplier.
The clock multiplier circuit operates such that the VCO outputs
a frequency, fVCO, equal to the REFCLKx input signal frequency
multiplied by N1 × N0. N1 is the divide ratio of the loop
divider; N0 is the divide ratio of the VCO divider.
fVCO = fREFCLK × (N1 × N0)
5kΩ
100Ω
5kΩ
The DAC sample clock frequency, fDACCLK, is equal to
1.25V
fDACCLK = fREFCLK × N1
DACCLKN,
REFN/SYNCN
11744-047
1Nf~100nF
Figure 42. Clock Receiver Input Simplified Equivalent Circuit
The minimum input drive level to the differential clock input is
100 mV p-p differential. The optimal performance is achieved
when the clock input signal is between 800 mV p-p differential
and 1.6 V p-p differential. Whether using the on-chip clock
multiplier or sourcing the DACCLK directly, the input clock
signal to the device must have low jitter and fast edge rates to
optimize the DAC noise performance.
REFP/SYNCP
(PIN 2)
REFN/SYNCN
(PIN 3)
PHASE
FREQUENCY
DETECTION
The output frequency of the VCO must be chosen to keep fVCO
in the optimal operating range of 1.0 GHz to 2.1 GHz. It is
important to select a frequency of the reference clock and values
of N1 and N0 so that the desired DACCLK frequency can be
synthesized and the VCO output frequency is in the correct range.
ADC
PLL CHARGE
PUMP CURRENT
REG 0x14[4:0]
PLL LOOP BW
REG 0x14[7:5]
CHARGE
PUMP
ON-CHIP
LOOP FILTER
VCO
(1GHz~2.1GHz)
LOOP DIVIDER
REG 0x15[1:0]
VCO DIVIDER
REG 0x15[3:2]
DIVIDE BY
2, 4, 8, OR 16
DIVIDE BY
1, 2, OR 4
DACCLKP
(PIN 62)
DACCLKN
(PIN 61)
VCO CONTROL
VOLTAGE
REG 0x16[3:0]
DACCLK
PLL ENABLE
REG 0x12[7]
Figure 43. PLL Clock Multiplier Circuit
Rev. 0 | Page 34 of 56
11744-048
RECOMMENDED
EXTERNAL
CIRCUITRY
DIRECT CLOCKING
Data Sheet
AD9139
PLL SETTINGS
61
57
The PLL circuitry requires three settings to be programmed to
their nominal values. The PLL values listed in Table 20 are the
recommended settings for these parameters.
53
49
45
PLL BAND
41
Table 20. PLL Settings
Optimal Setting
(Binary)
111
00111
0
33
29
25
21
17
13
9
5
1
950
CONFIGURING THE VCO TUNING BAND
1150
1350
1550
1750
1950
VCO FREQUENCY (MHz)
2150
11744-049
PLL SPI Control Register
PLL Loop Bandwidth
PLL Charge Pump Current
PLL Cross Point Control Enable
Register
Address
0x14[7:5]
0x14[4:0]
0x15[4]
37
The PLL VCO has a valid operating range from approximately
1.03 GHz to 2.07 GHz covered in 64 overlapping frequency
bands. For any desired VCO output frequency, there may be
several valid PLL band select values. See Figure 44 for the
frequency bands of a typical device. Device-to-device variations
and operating temperature affect the actual band frequency
range. Therefore, it is necessary to determine the optimal PLL
band select value for each individual device.
The device includes a manual band select mode (PLL auto
manual enable, Register 0x12[6] = 1) that lets the user select the
VCO tuning band. In manual mode, the VCO band is set
directly with the value written to the manual VCO band bits
(Register 0x12[5:0]).
AUTOMATIC VCO BAND SELECT
PLL ENABLE SEQUENCE
The device has an automatic VCO band select feature on chip.
Using the automatic VCO band select feature is a simple and
reliable method of configuring the VCO frequency band.
Enable this feature by starting the PLL in manual mode and then
placing the PLL in autoband select mode by setting Register 0x12
to a value of 0xC0 and then to a value of 0x80. When these
values are written, the device executes an automated routine
that determines the optimal VCO band setting for the device.
To enable the PLL in automatic or manual mode properly, the
following sequence must be followed:
The setting selected by the device ensures that the PLL remains
locked over the full −40°C to +85°C operating temperature
range of the device without further adjustment. The PLL
remains locked over the full temperature range even if the
temperature during initialization is at one of the temperature
extremes.
Figure 44. PLL Lock Range for a Typical Device
MANUAL VCO BAND SELECT
Automatic Mode Sequence
1.
2.
3.
4.
5.
Configure the loop divider and the VCO divider registers
for the desired divide ratios.
Set 00111 to PLL charge pump current and 111 to PLL loop
bandwidth for the best performance. Register 0x14 = 0xE7
(default).
Set the PLL mode to manual using Register 0x12[6] = 1.
Enable the PLL using Register 0x12[7] = 1.
Set the PLL mode to automatic using Register 0x12[6] = 0.
Manual Mode
1.
2.
3.
4.
5.
Rev. 0 | Page 35 of 56
Configure the loop divider and the VCO divider registers
for the desired divide ratios.
Set 00111 to PLL charge pump current and 111 to PLL loop
bandwidth for the best performance. Register 0x14 = 0xE7
(default).
Select the desired band using Register 0x12[5:0].
Set the PLL mode to manual using Register 0x12[6] = 1.
Enable the PLL using Register 0x12[7] = 1.
AD9139
Data Sheet
ANALOG OUTPUTS
TRANSMIT DAC OPERATION
35
Figure 45 shows a simplified block diagram of the transmit path
DACs. The DAC core consists of a current source array, a switch
core, digital control logic, and full-scale output current control.
The DAC full-scale output current (IOUTFS) is nominally 20 mA.
The output currents from the DACOUTP and DACOUTN pins
are complementary, meaning that the sum of the two currents
always equals the full-scale current of the DAC. The digital
input code to the DAC determines the effective differential
current delivered to the load.
DAC FSADJUST
REG 0x18, 0x19
IFS (mA)
0
0
200
DACOUTN
400
600
800
DAC GAIN CODE
1000
Figure 46. DAC Full-Scale Current vs. DAC Gain Code
CURRENT
SCALING
Transmit DAC Transfer Function
11744-050
10kΩ
RSET
Figure 45. Simplified Block Diagram of DAC Core
The DAC has a 1.2 V band gap reference with an output impedance of 5 kΩ. The reference output voltage appears on the VREF
pin. When using the internal reference, decouple the VREF pin
to AVSS with a 0.1 µF capacitor. Use the internal reference only
for external circuits that draw dc currents of 2 µA or less. For
dynamic loads or static loads greater than 2 µA, buffer the VREF
pin. If desired, the internal reference can be overdriven by
applying an external reference (from 1.10 V to 1.30 V) to the pin.
A 10 kΩ external resistor, RSET, must be connected from the
FSADJ pin to AVSS. This resistor, together with the reference
control amplifier, sets up the correct internal bias currents for
the DAC. Because the full-scale current is inversely proportional to
this resistor, the tolerance of RSET is reflected in the full-scale
output amplitude.
The full-scale current equation, where the DAC gain is set in
Register 0x18 and Register 0x19, is as follows:
I FS =
15
5
DACOUTP
VREF
FSADJ
20
10
DAC
5kΩ
0.1µF
25
11744-051
1.2V
30
VREF 
3

×  72 +  × DAC gain  
RSET 
 16

For nominal values of VREF (1.2 V), RSET (10 kΩ), and DAC gain
(512), the full-scale current of the DAC is typically 20 mA. The
DAC full-scale current is adjustable from 8.64 mA to 31.68 mA by
setting the DAC gain parameter, as shown in Figure 46.
The output currents from the DACOUTP and DACOUTN pins
are complementary, meaning that the sum of the two currents
always equals the full-scale current of the DAC. The digital input
code to the DAC determines the effective differential current
delivered to the load. The DACOUTP pin provides maximum
output current when all bits are high. The output currents vs.
DACCODE for the DAC outputs is expressed as
DACCODE 
I OUTP = 
 × I OUTFS
2N

IOUTN = IOUTFS – IOUTP
(1)
(2)
where DACCODE = 0 to 2N − 1.
Transmit DAC Output Configurations
The optimum noise and distortion performance of the AD9139
is realized when it is configured for differential operation. The
common-mode rejection of a transformer or differential amplifier
significantly reduces the common-mode error sources of the DAC
outputs. These common-mode error sources include even-order
distortion products and noise. The enhancement in distortion
performance becomes more significant as the frequency content of
the reconstructed waveform increases and/or its amplitude
increases. This is due to the first-order cancellation of various
dynamic common-mode distortion mechanisms, digital feedthrough, and noise.
Figure 47 shows the most basic DAC output circuitry. A pair of
resistors, RO, converts each of the complementary output currents
to a differential voltage output, VOUT. Because the current
outputs of the DAC are high impedance, the differential driving
point impedance of the DAC outputs, ROUT, is equal to 2 × RO.
See Figure 48 for the output voltage waveforms.
Rev. 0 | Page 36 of 56
Data Sheet
AD9139
DACOUTP
+
VOUTP
67
DACOUTP
VOUT
VOUTN
IBBP
RBIP
50Ω
–
11744-052
RO
ADL537x
AD9139
RO
DACOUTN
RLI
100Ω
RBIN
50Ω
66
IBBN
DACOUTN
Figure 47. Basic Transmit DAC Output Circuit
AD9139
67
DACOUTP
QBBN
RBQN
50Ω
VCM
VN
66
VP
QBBP
DACOUTN
Figure 49. Typical Interface Circuitry Between the AD9139 and the ADL537x
Family of Modulators
0
The baseband inputs of the ADL537x family require a dc bias
of 500 mV. The nominal midscale output current on each output of
the DAC is 10 mA (one-half the full-scale current). Therefore,
a single 50 Ω resistor to ground from each of the DAC outputs
results in the desired 500 mV dc common-mode bias for the
inputs to the ADL537x. The addition of the load resistor in
parallel with the modulator inputs reduces the signal level. The
peak-to-peak voltage swing of the transmitted signal is
11744-053
VOUT
–VPEAK
Figure 48. Output Voltage Waveforms
The common-mode signal voltage, VCM, is calculated as
I FS
× RO
2
VSIGNAL = I FS ×
The differential peak-to-peak output voltage, VPEAK, is
calculated as
(2 × R B × R L )
(2 × R B + R L )
Baseband Filter Implementation
VPEAK = 2 × IFS × RO
Most applications require a baseband anti-imaging filter between
the DAC and the modulator to filter out Nyquist images and
broadband DAC noise. The filter can be inserted between the
termination resistors at the DAC output and the signal level setting
resistor across the modulator input. This configuration
establishes the input and output impedances for the filter.
INTERFACING TO MODULATORS
The AD9139 interfaces to the ADL537x family of modulators
with a minimal number of components. An example of the
recommended interface circuitry is shown in Figure 49.
Figure 50 shows a fifth-order, low-pass filter. Splitting the filter
capacitors into two and grounding the center point creates a
common-mode low-pass filter that provides additional
common-mode rejection of high frequency signals. A purely
differential filter can pass common-mode signals.
For more details about interfacing the AD9139 DAC to an IQ
modulator,see the Circuits from the Lab™, Circuit Note CN-0205,
Interfacing the ADL5375 I/Q Modulator to the AD9122 Dual
Channel, 1.2 GSPS High Speed DAC on the Analog Devices
website.
50Ω
AD9139
22pF
33nH
33nH
33nH
33nH
3.6pF
50Ω
3pF
6pF
22pF
140Ω ADL537x
3pF
Figure 50. DAC Modulator Interface with Fifth-Order, Low-Pass Filter
Rev. 0 | Page 37 of 56
11744-055
VCM =
RLQ
100Ω
RBQP
50Ω
11744-054
+VPEAK
AD9139
Data Sheet
REDUCING LO LEAKAGE AND UNWANTED
SIDEBANDS
(Register 0x18 through Register 0x19) can be used to calibrate
the gain of the transmit paths to optimize sideband suppression.
Analog quadrature modulators can introduce unwanted signals
at the local oscillator (LO) frequency caused by dc offset
voltages in the I and Q baseband inputs, as well as feedthrough
paths from the LO input to the output.
For more information about suppressing LO leakage and
sideband image, refer to Application Note AN-1039, Correcting
Imperfections in IQ Modulators to Improve RF Signal Fidelity
and Application Note AN-1100, Wireless Transmitter IQ Balance
and Sideband Suppression from the Analog Devices website.
Effective sideband suppression requires both gain and phase
matching of the I and Q signals. The DAC FS adjust registers
Rev. 0 | Page 38 of 56
Data Sheet
AD9139
START-UP ROUTINE
Read 0x25[1] /* Expect 1b if the FIFO reset is
complete */
To ensure reliable start up of the AD9139, certain sequences
must be followed.
Read 0x24 /* The readback should be one of the
three values: 0x30, 0x40, or 0x50 */
Device Configuration and Start-Up Sequence 1
1.
2.
3.
4.
Set fDCI = 600 MHz, fDATA = 1200 MHz, and interpolation to 1×.
Enable the PLL, and set fREF = 300 MHz.
Enable the inverse sinc filter.
Use the DLL-based interface mode and set DLL phase
offset = 0.
/* Enable Inverse SINC filter */
0x27 → 0x80
/* Power up DAC outputs */
Derived PLL Settings
0x01 → 0x00
The following PLL settings are derived from the device configuration:
Device Configuration and Start-Up Sequence 2




1.
fDAC = 1200 × 1 = 1200 MHz.
fVCO= fDAC = 1200 MHz (1 GHz < fVCO < 2 GHz).
VCO divider = fVCO/fDAC = 1.
Loop divider = fDAC/fREF = 4.
2.
3.
4.
Start-Up Sequence 1
1.
2.
3.
4.
5.
Power up the device (no specific power supply sequence is
required).
Apply stable DAC clock.
Apply stable DCI clock.
Feed stable input data.
Issue hardware reset (optional).
/* Device configuration register write
sequence */
Set fDCI = 200 MHz, fDATA = 400 MHz, fDAC = 800 MHz, and
interpolation to 2×.
Disable PLL.
Enable the inverse sinc filter.
Use the delay line-based interface mode with a delay
setting of 0.
Start-Up Sequence 2
1.
2.
3.
4.
5.
Power up the device (no specific power supply sequence is
required).
Apply stable DAC clock.
Apply stable DCI clock.
Feed stable input data.
Issue a hardware reset (optional).
0x00 → 0x20 /* Issue software reset */
/* Device configuration register write
sequence */
/* Configure PLL */
0x00 → 0x20 /* Issue software reset */
0x20 → 0x01 /* Device Startup Configuration */
0x14 → 0xE7 /* Configure PLL loop BW and charge
pump current */
0x15 → 0xC1 /* Configure VCO divider and loop
divider */
0x20 → 0x01 /* Device Startup Configuration */
/* Configure Data Interface */
0x12 → 0xC0 /*Enable the PLL */
0x5E → 0x00 /* Configure the delay setting */
Wait 10ms
0x0D → 0x16 /* DC couple DCI */
Read 0x16[7] /* Expect 1b if the PLL is locked
*/
0x0A → 0x00 /* Turn off DLL and duty cycle
correction */
0x5F → 0x60
0x12 → 0x80
/* Configure Interpolation filter */
/* Configure Data Interface */
0x5E → 0xFE /* Turn off LSB delay cell */
0x0A → 0xC0 /* Enable the DLL and duty cycle
correction. Set DLL phase offset to 0 */
Read 0x0E[7:4] /* Expect 1000b if the DLL is
locked */
0x28 → 0x00 /* 2× interpolation */
/* Reset FIFO */
Follow the serial port FIFO reset procedure in
the FIFO Operation section.
/* Enable Inverse SINC filter */
/* Configure Interpolation filter */
0x28 → 0x80 /* 1× interpolation */
/* Reset FIFO */
0x25 → 0x01
0x27 → 0x80
/* Power up DAC outputs */
0x01 → 0x00
Rev. 0 | Page 39 of 56
AD9139
Data Sheet
DEVICE CONFIGURATION REGISTER MAP AND DESCRIPTION
Table 21. Device Configuration Register Map
Reg
0x00
Name
Common
Bits
[7:0]
Bit 7
Reserved
0x01
PD_
CONTROL
INTERRUPT_
ENABLE0
[7:0]
PD_DAC
[7:0]
Reserved
ENABLE_
SYNC_LOST
0x04
INTERRUPT_
ENABLE1
[7:0]
ENABLE_
PARITY_FAIL
0x05
[7:0]
[7:0]
0x07
INTERRUPT_
FLAG0
INTERRUPT_
FLAG1
IRQ_SEL0
0x08
IRQ_SEL1
[7:0]
0x09
0x0A
FRAME_MODE
DATA_CNTR_0
[7:0]
[7:0]
0x0B
0x0C
0x0D
DATA_CNTR_1
DATA_CNTR_2
DATA_CNTR_3
[7:0]
[7:0]
[7:0]
0x0E
DATA_STAT_0
[7:0]
0x10
DACCLK_
[7:0]
RECEIVER_
CTRL
REFCLK_
[7:0]
RECEIVER_CTRL
DACCLK_
DUTYCYCLE_
CORRECTION
DUTYCYCLE_
CORRECTION
0x12
PLL_CTRL0
[7:0]
PLL_ENABLE
0x14
0x15
PLL_CTRL2
PLL_CTRL3
[7:0]
[7:0]
0x16
0x17
0x18
0x19
PLL_STATUS0
PLL_STATUS1
DAC_FS_ADJ0
DAC_FS_ADJ1
[7:0]
[7:0]
[7:0]
[7:0]
PLL_LOCK
0x1C
DIE_TEMP_
SENSOR_CTRL
DIE_TEMP_LSB
DIE_TEMP_MSB
CHIP_ID
INTERRUPT_
CONFIG
SYNC_CTRL
[7:0]
Reserved
0x03
0x06
0x11
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
FRAME_RST_
CTRL
FIFO_LEVEL_
CONFIG
FIFO_LEVEL_
READBACK
FIFO_CTRL
DATA_
FORMAT_SEL
DATAPATH_
CTRL
[7:0]
Bit 6
SPI_LSB_
FIRST
Reserved
Bit 5
DEVICE_RESET
Bit 4
PD_DATARCV
Bit 3
Bit 2
Reserved
Bit 1
Bit 0
Reset RW
0x00 RW
PD_DEVICE
PD_DACCLK
PD_FRAME
0xC0
RW
0x00
RW
ENABLE_
Reserved
FIFO_
OVERFLOW
Reserved
0x00
RW
0x00
R
FIFO_
FIFO_
Reserved
UNDERFLOW
OVERFLOW
SEL_PLL_LOST SEL_PLL_
Reserved
LOCKED
Reserved
FIFO_
FIFO_
Reserved
UNDERFLOW
OVERFLOW
Reserved
FRAME_PIN_USAGE
DLL_PHASE_OFFSET
0x00
R
0x00
RW
0x00
RW
0x00
0x40
RW
RW
0x39
0x64
0x06
RW
RW
RW
0x00
R
0xFF
RW
0x5F
RW
0x00
RW
0xE7
0xC9
RW
RW
0x00
0x00
0xF9
0xE1
R
R
RW
RW
0x02
RW
0x00
0x00
0x0A
0x00
R
R
R
RW
0x00
RW
0x12
RW
0x40
RW
0x00
R
0x00
RW
0x00
RW
0x00
RW
Reserved
ENABLE_
SYNC_DONE
ENABLE_PLL_
LOST
ENABLE_PLL_
LOCKED
ENABLE_SED_
FAIL
ENABLE_
SYNC_
LOCKED
ENABLE_DLL_
WARNING
ENABLE_DLL_
LOCKED
Reserved
ENABLE_FIFO_
UNDERFLOW
Reserved
SYNC_LOST
SYNC_LOCKED
SYNC_DONE
PLL_LOST
PLL_LOCKED
PARITY_
FAIL
Reserved
SED_FAIL
DLL_
WARNING
SEL_SYNC_
LOCKED
SEL_DLL_
WARNING
PARUSAGE
DLL_LOCKED
Reserved
SEL_PARITY_
FAIL
SEL_SYNC_
LOST
SEL_SED_FAIL
Reserved
DUTY_
CORRECTION_
EN
CLEAR_WARN
SEL_SYNC_
DONE
SEL_DLL_
LOCKED
FRMUSAGE
Reserved
DLL_
ENABLE
LOW_
DCI_EN
DLL_LOCK
Reserved
DLL_WARN
DLL_START_
WARNING
DACCLK_
CROSSPOINT_
CTRL_ENABLE
REFCLK_
CROSSPOINT_
CTRL_ENABLE
Reserved
Reserved
AUTO_MANUAL_
SEL
PLL_LOOP_BW
DIGLOGIC_DIVIDER
Reserved
Reserved
Reserved
DC_COUPLE_
Reserved
LOW_EN
DLL_END_
Reserved
DCI_ON
Reserved
WARNING
DACCLK_CROSSPOINT_LEVEL
REFCLK_CROSSPOINT_LEVEL
PLL_CP_CURRENT
VCO_DIVIDER
CROSSPOINT_
CTRL_EN
Reserved
BG_TRIM
FS_CURRENT
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Reserved
Reserved
ARM_FRAME
Reserved
INTEGER_FIFO_LEVEL_REQUEST
Reserved
[7:0]
Reserved
INTEGER_FIFO_LEVEL_READBACK
Reserved
[7:0]
[7:0]
SYNC_CLK_
SYNC_
EDGE_SEL
ENABLE
FRAME_RESET_MODE
EN_CON_
FRAME_RESET
FRACTIONAL_FIFO_LEVEL_REQUEST
FRACTIONAL_FIFO_LEVEL_READBACK
Reserved
DATA_
FORMAT
INVSINC_
ENABLE
FIFO_SPI_
RESET_ACK
Reserved
Reserved
LOOP_DIVIDER
VCO_CTRL_VOLTAGE_READBACK
PLL_BAND_READBACK
DAC_FULLSCALE_ADJUST_LSB
RESERVED
DAC_FULLSCALE_ADJUST_
MSB
REF_CURRENT
DIE_TEMP_
SENSOR_EN
DIE_TEMP_LSB
DIE_TEMP_MSB
CHIP_ID
INTERRUPT_CONFIGURATION
[7:0]
[7:0]
DLL_
RUNNING
PLL_MANUAL_BAND
Reserved
[7:0]
Reserved
DIG_GAIN_
DCOFFSET_
ENABLE
Rev. 0 | Page 40 of 56
Reserved
FIFO_SPI_
RESET_
REQUEST
DATA_BUS_
WIDTH
Data Sheet
AD9139
Reg
0x28
Name
Bits
INTERPOLATION_ [7:0]
CTRL
0x39
LVDS_IN_PWR_
DOWN_0
DAC_DC_
OFFSET0
DAC_DC_
OFFSET1
DAC_DIG_GAIN
GAIN_STEP_
CTRL0
GAIN_STEP_
CTRL1
TX_ENABLE_
CTRL
[7:0]
0x44
DAC_
OUTPUT_ CTRL
[7:0]
0x5E
ENABLE_DLL_
DELAY_CELL0
ENABLE_DLL_
DELAY_CELL1
SED_CTRL
SED_PATT_
L_S0
SED_PATT_
H_S0
SED_PATT_
L_S1
SED_PATT_
H_S1
SED_PATT_
L_S2
SED_PATT_
H_S2
SED_PATT_
L S3
SED_PATT_
H_S3
PARITY_CTRL
[7:0]
0x3B
0x3C
0x3F
0x41
0x42
0x43
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x6A
0x6B
0x6C
0x7F
PARITY_
ERR_RISING
PARITY_
ERR_FALLING
Version
Bit 7
Bit 6
INTERPOLATION_
MODE
Bit 5
Bit 4
Bit 3
Bit 2
Reserved
Bit 1
Bit 0
PWR_DOWN_DATA_INPUT_BITS
Reset RW
0x00 RW
0x00
RW
[7:0]
DAC_DC_OFFSET_LSB
0x00
RW
[7:0]
DAC_DC_OFFSET_MSB
0x00
RW
DAC_DIG_GAIN
RAMP_UP_STEP
0x20
0x01
RW
RW
RAMP_DOWN_STEP
0x01
RW
TXENABLE_ 0x07
POWER_
DOWN_EN
FIFO_
0x8F
ERROR_
SHUTDOWN_
EN
0xFF
RW
[7:0]
[7:0]
[7:0]
Reserved
Reserved
DAC_OUTPUT_
STATUS
DAC_OUTPUT_
ON
Reserved
[7:0]
DAC_OUTPUT_
CTRL_EN
Reserved
FIFO_WARNING_
SHUTDOWN_EN
TXENABLE_
SLEEP_
EN
Reserved
ENABLE_DLL_DELAY_CELL[7:0]
[7:0]
[7:0]
[7:0]
TXENABLE_
GAINSTEP_
EN
Reserved
SED_ENABLE
SED_ERR_CLEAR
ENABLE_DLL_DELAY_CELL[10:8]
AED_ENABLE
SED_DEPTH
Reserved
SED_PATTERN_RISE_S0 [7:0]
AED_PASS
AED_FAIL
SED_FAIL
RW
0x67
RW
0x00
0x00
RW
RW
[7:0]
SED_PATTERN_RISE_S0 [15:8]
0x00
RW
[7:0]
SED_PATTERN_FALL_S1 [7:0]
0x00
RW
[7:0]
SED_PATTERN_FALL_S1 [15:8]
0x00
RW
[7:0]
SED_PATTERN_RISE_S2 [7:0]
0x00
RW
[7:0]
SED_PATTERN_RISE_S2 [15:8]
0x00
RW
[7:0]
SED_PATTERN_FALL_S3 [7:0]
0x00
RW
[7:0]
SED_PATTERN_FALL_S3 [15:8]
0x00
RW
0x00
RW
[7:0]
PARITY_ENABLE
PARITY_EVEN
PARITY_
ERR_CLEAR
Reserved
PARERRFAL
PARERRRIS
[7:0]
PARITY RISING EDGE ERROR COUNT
0x00
R
[7:0]
PARITY FALLING EDGE ERROR COUNT
0x00
R
[7:0]
Version
0x07
R
Rev. 0 | Page 41 of 56
AD9139
Data Sheet
SPI CONFIGURE REGISTER
Address: 0x00, Reset: 0x00, Name: Common
Table 22. Bit Descriptions for Common
Bit No.
6
Bit Name
SPI_LSB_FIRST
Settings
0
1
5
DEVICE_RESET
Description
Serial port communication, MSB first or LSB first selection.
MSB first.
LSB first.
The device resets when 1 is written to this bit. DEVICE_RESET is a self clear bit.
After the reset, the bit returns to 0 automatically. The readback is always 0.
Reset
0
Access
R/W
0
R/W
POWER-DOWN CONTROL REGISTER
Address: 0x01, Reset: 0xC0, Name: PD_CONTROL
Table 23. Bit Descriptions for PD_CONTROL
Bit No.
7
Bit Name
PD_DAC
6
5
Reserved
PD_DATARCV
2
PD_DEVICE
1
PD_DACCLK
0
PD_FRAME
Settings
Description
The DAC is powered down when PD_DAC is set to 1. This bit powers down only the
analog portion of the DAC. The DAC digital data path is not affected.
Must set to default value.
The data interface circuitry is powered down when PD_DATARCV is set to 1. This bit
powers down the data interface and the write side of the FIFO.
The band gap circuitry is powered down when set to 1. This bit powers down the
entire chip.
The DAC clock powers down when PD_DEVICE is set to 1. This bit powers down the
DAC clocking path and, thus, the majority of the digital functions.
The frame receiver powers down when PD_FRAME is set to 1. The frame signal is
internally pulled low. Set to 1 when frame is not used.
Reset
1
Access
R/W
1
0
R/W
R/W
0
R/W
0
R/W
0
R/W
INTERRUPT ENABLE 0 REGISTER
Address: 0x03, Reset: 0x00, Name: INTERRUPT_ENABLE0
Table 24. Bit Descriptions for INTERRUPT_ENABLE0
Bit No.
6
5
4
3
2
Bit Name
ENABLE_SYNC_LOST
ENABLE_SYNC_LOCKED
ENABLE_SYNC_DONE
ENABLE_PLL_LOST
ENABLE_PLL_LOCKED
Settings
Description
Enable interrupt for sync lost.
Enable interrupt for sync lock.
Enable interrupt for sync done.
Enable interrupt for PLL lost.
Enable interrupt for PLL locked.
Reset
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
INTERRUPT ENABLE 1 REGISTER
Address: 0x04, Reset: 0x00, Name: INTERRUPT_ENABLE1
Table 25. Bit Descriptions for INTERRUPT_ENABLE1
Bit No.
7
6
5
4
2
1
Bit Name
ENABLE_PARITY_FAIL
ENABLE_SED_FAIL
ENABLE_DLL_WARNING
ENABLE_DLL_LOCKED
ENABLE_FIFO_UNDERFLOW
ENABLE_FIFO_OVERFLOW
Settings
Description
Enable interrupt for parity failure
Enable interrupt for SED failure
Enable interrupt for DLL warning.
Enable interrupt for DLL locked.
Enable interrupt for FIFO underflow.
Enable interrupt for FIFO overflow.
Rev. 0 | Page 42 of 56
Reset
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
Data Sheet
AD9139
INTERRUPT FLAG 0 REGISTER
Address: 0x05, Reset: 0x00, Name: INTERRUPT_FLAG0
Table 26. Bit Descriptions for INTERRUPT_FLAG0
Bit No.
6
5
4
3
2
Bit Name
SYNC_LOST
SYNC_LOCKED
SYNC_DONE
PLL_LOST
PLL_LOCKED
Settings
Description
SYNC_LOST is set to 1 when sync is lost.
SYNC_LOCKED is set to 1 when sync is locked.
SYNC_DONE is set to 1 when sync is done.
PLL_LOST is set to 1 when PLL loses lock.
PLL_LOCKED is set to 1 when PLL is locked.
Reset
0
0
0
0
0
Access
R
R
R
R
R
Reset
0
0
0
0
0
Access
R
R
R
R
R
0
R
INTERRUPT FLAG 1 REGISTER
Address: 0x06, Reset: 0x00, Name: INTERRUPT_FLAG1
Table 27. Bit Descriptions for INTERRUPT_FLAG1
Bit No.
7
6
5
4
2
Bit Name
PARITY_FAIL
SED_FAIL
DLL_WARNING
DLL_LOCKED
FIFO_UNDERFLOW
1
FIFO_OVERFLOW
Settings
Description
PARITY_FAIL is set to 1 when the parity check fails.
SED_FAIL is set to 1 when the SED comparison fails.
DLL_WARNING is set to 1 when the DLL raises a warning.
DLL_LOCKED is set to 1 when the DLL is locked.
FIFO_UNDERFLOW is set to 1 when the FIFO read
pointer catches the FIFO write pointer.
FIFO_OVERFLOW is set to 1 when the FIFO write pointer
catches the FIFO read pointer.
INTERRUPT SELECT 0 REGISTER
Address: 0x07, Reset: 0x00, Name: IRQ_SEL0
Table 28. Bit Descriptions for IRQ_SEL0
Bit No.
6
Bit Name
SEL_SYNC_LOST
5
Settings
0
1
Description
Selects the IRQ1 pin.
Selects the IRQ2 pin.
Reset
0
Access
R/W
SEL_SYNC_LOCKED
0
1
Selects the IRQ1 pin.
Selects the IRQ2 pin.
0
R/W
4
SEL_SYNC_DONE
0
1
Selects the IRQ1 pin.
Selects the IRQ2 pin.
0
R/W
3
SEL_PLL_LOST
0
1
Selects the IRQ1 pin.
Selects the IRQ2 pin.
0
R/W
2
SEL_PLL_LOCKED
0
1
Selects the IRQ1 pin.
Selects the IRQ2 pin.
0
R/W
Rev. 0 | Page 43 of 56
AD9139
Data Sheet
INTERRUPT SELECT 1 REGISTER
Address: 0x08, Reset: 0x00, Name: IRQ_SEL1
Table 29. Bit Descriptions for IRQ_SEL1
Bit No.
7
Bit Name
SEL_PARITY_FAIL
6
Settings
1
0
Description
Selects the IRQ2 pin.
Selects the IRQ1 pin.
Reset
Access
SEL_SED_FAIL
1
0
Selects the IRQ2 pin.
Selects the IRQ1 pin.
0
R/W
5
SEL_DLL_WARNING
0
Selects the IRQ1 pin.
0
R/W
0
R/W
4
SEL_DLL_LOCKED
1
0
Selects the IRQ2 pin.
Selects the IRQ1 pin.
2
SEL_FIFO_UNDERFLOW
0
R/W
1
0
Selects the IRQ2 pin.
Selects the IRQ1 pin.
1
SEL_FIFO_OVERFLOW
0
R/W
1
0
Selects the IRQ2 pin.
Selects the IRQ1 pin.
0
R/W
FRAME MODE REGISTER
Address: 0x09, Reset: 0x00, Name: FRAME_MODE
Table 30. Bit Descriptions for FRAME_MODE
Bit No.
5
4
[1:0]
Bit Name
PARUSAGE
FRMUSAGE
FRAME_PIN_USAGE
Description
Must be set to 1 when parity is used
Must be set to 1 when frame is used.
0 = no effect.
1 = parity.
2 = frame.
3 = reserved.
Reset
0
0
0x0
Access
R/W
R/W
R/W
DATA CONTROL 0 REGISTER
Address: 0x0A, Reset: 0x40, Name: DATA_CNTR_0
Table 31. Bit Descriptions for DATA_CNTR_0
Bit No.
7
Bit Name
DLL_ENABLE
6
DUTY_CORRECTION_EN
[3:0]
DLL_PHASE_OFFSET
Description
1 = enable DLL.
0 = disable DLL.
1 = enable duty cycle correction.
0 = disable duty cycle correction.
Locked phase = 90° + n × 11.25°, where n is the 4-bit signed magnitude
number.
Reset
0
Access
R/W
1
R/W
0x0
R/W
DATA CONTROL 1 REGISTER
Address: 0x0B, Reset: 0x39, Name: DATA_CNTR_1
Table 32. Bit Descriptions for DATA_CNTR_1
Bit No.
7
[6:0]
Bit Name
CLEAR_WARN
Reserved
Description
1: clears data receiver warning bits (Register 0x0E[6:4]).
Must write the default value for optimal performance.
Rev. 0 | Page 44 of 56
Reset
0
0x39
Access
R/W
R/W
Data Sheet
AD9139
DATA CONTROL 2 REGISTER
Address: 0x0C, Reset: 0x64, Name: DATA_CNTR_2
Table 33. Bit Descriptions for DATA_CNTR_2
Bit No.
[7:0]
Bit Name
Reserved
Description
Must write the default value for optimal performance.
Reset
0x64
Access
R/W
DATA CONTROL 3 REGISTER
Address: 0x0D, Reset: 0x06, Name: DATA_CNTR_3
Table 34. Bit Descriptions for DATA_CNTR_3
Bit No.
7
Bit Name
LOW_DCI_EN
4
DC_COUPLE_LOW_EN
[3:0]
Reserved
Description
Set to 0 when the DLL is enabled and the DCI rate ≥350 MHz.
Set to 1 when the DLL is enabled and the DCI rate <350 MHz.
Set to 0 when the DLL is enabled and the delay line is disabled.
Set to 1 when the DLL is disabled and the delay line is enabled.
It is recommended that DLL mode be used for DCI rates faster than 250 MHz and
delay line mode be used for DCI rates slower than 250 MHz.
Must write the default value for optimal performance.
Reset
0
Access
R/W
0
R/W
0x6
R/W
DATA STATUS 0 REGISTER
Address: 0x0E, Reset: 0x00, Name: DATA_STAT_0
Table 35. Bit Descriptions for DATA_STAT_0
Bit No.
7
6
5
4
3
2
1
0
Bit Name
DLL_LOCK
DLL_WARN
DLL_START_WARNING
DLL_END_WARNING
Reserved
DCI_ON
Reserved
DLL_RUNNING
Description
1 = DLL lock.
1 = DLL near the beginning/end of the delay line.
1 = DLL at the beginning of the delay line.
1 = DLL at the end of the delay line.
Reserved.
1 = user has provided a DCI clock.
Reserved.
1 = closed-loop DLL attempting to lock.
0 = delay fixed at middle of the delay line.
Rev. 0 | Page 45 of 56
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
AD9139
Data Sheet
DAC CLOCK RECEIVER CONTROL REGISTER
Address: 0x10, Reset: 0xFF, Name: DACCLK_RECEIVER_CTRL
Table 36. Bit Descriptions for DACCLK_RECEIVER_CTRL
Bit No.
7
Bit Name
DACCLK_DUTYCYCLE_CORRECTION
6
5
Reserved
DACCLK_CROSSPOINT_CTRL_ENABLE
[4:0]
DACCLK_CROSSPOINT_LEVEL
Settings
01111
11111
Description
Enables duty cycle correction at the DACCLK input. For
best performance, the default and recommended status is
turned on.
Must write the default value for optimal performance
Enables crosspoint control at the DACCLK input. For best
performance, the default and recommended status is
turned on.
A twos complement value. For best performance, set the
DACCLK_CROSSPOINT_LEVEL to the default value.
Highest crosspoint.
Lowest crosspoint.
Reset
1
Access
R/W
1
1
R/W
R/W
0x1F
R/W
Reset
0
Access
RW
1
0
R/W
RW
0x1F
RW
Reset
0
0
Access
R/W
R/W
0x00
R/W
REFERENCE CLOCK RECEIVER CONTROL REGISTER
Address: 0x11, Reset: 0x5F, Name: REFCLK_RECEIVER_CTRL
Table 37. Bit Descriptions for REFCLK_RECEIVER_CTRL
Bit
No.
7
Bit Name
DUTYCYCLE_CORRECTION
6
5
Reserved
REFCLK_CROSSPOINT_CTRL_ENABLE
[4:0]
REFCLK_CROSSPOINT_LEVEL
Settings
01111
11111
Description
Enables duty cycle correction at the REFCLK input. For best
performance, the default and recommended status is turned
off.
Must write the default value for optimal performance.
Enables crosspoint control at the REFCLK input. For best
performance, the default and recommended status is turned
off.
A twos complement value. For best performance, set
REFCLK_CROSSPOINT_LEVEL to the default value.
Highest crosspoint.
Lowest crosspoint.
PLL CONTROL 0 REGISTER
Address: 0x12, Reset: 0x00, Name: PLL_CTRL0
Table 38. Bit Descriptions for PLL_CTRL0
Bit No.
7
6
Bit Name
PLL_ENABLE
AUTO_MANUAL_SEL
Settings
0
1
[5:0]
PLL_MANUAL_BAND
000000
111111
Description
Enables PLL clock multiplier.
PLL band selection mode.
Automatic mode.
Manual mode.
PLL band setting in manual mode. 64 bands in total, covering a 1 GHz to
2.1 GHz VCO range.
Lowest band (1.03 GHz).
Highest band (2.07 GHz).
Rev. 0 | Page 46 of 56
Data Sheet
AD9139
PLL CONTROL 2 REGISTER
Address: 0x14, Reset: 0xE7, Name: PLL_CTRL2
Table 39. Bit Descriptions for PLL_CTRL2
Bit No.
[7:5]
Bit Name
PLL_LOOP_BW
Settings
Description
Selects the PLL loop filter bandwidth. The default and recommended
setting is 111 for optimal PLL performance.
Lowest setting.
Highest setting.
Sets nominal PLL charge pump current. The default and
recommended setting is 00111 for optimal PLL performance.
Lowest setting.
Highest setting.
0x00
0x1F
[4:0]
PLL_CP_CURRENT
0x00
0x1F
Reset
0x7
Access
R/W
0x07
R/W
PLL CONTROL 3 REGISTER
Address: 0x15, Reset: 0xC9, Name: PLL_CTRL3
Table 40. Bit Descriptions for PLL_CTRL3
Bit No.
[7:6]
Bit Name
DIGLOGIC_DIVIDER
Settings
00
01
10
11
4
CROSSPOINT_CTRL_EN
[3:2]
VCO_DIVIDER
00
01
10
11
[1:0]
LOOP_DIVIDER
00
01
10
11
Description
REFCLKx to PLL digital clock divide ratio. The PLL digital clock drives the
internal PLL logics. The divide ratio must be set to ensure that the PLL
digital clock is below 75 MHz.
fREFCLK/fDIG = 2.
fREFCLK/fDIG = 4.
fREFCLK/fDIG = 8.
fREFCLK/fDIG = 16.
Enable loop divider crosspoint control. The default and recommended
setting is set to 0 for optimal PLL performance.
PLL VCO divider. This divider determines the ratio of the VCO frequency to
the DACCLK frequency.
fVCO/fDACCLK = 1.
fVCO/fDACCLK = 2.
fVCO/fDACCLK = 4.
fVCO/fDACCLK = 4.
PLL loop divider. This divider determines the ratio of the DACCLK
frequency to the REFCLK frequency.
fDACCLK/fREFCLK = 2.
fDACCLK/fREFCLK = 4.
fDACCLK/fREFCLK = 8.
fDACCLK/fREFCLK = 16.
Reset
0x3
Access
R/W
0
R/W
0x2
R/W
0x1
R/W
PLL STATUS 0 REGISTER
Address: 0x16, Reset: 0x00, Name: PLL_STATUS0
Table 41. Bit Descriptions for PLL_STATUS0
Bit
No.
7
[3:0]
Bit Name
PLL_LOCK
VCO_CTRL_VOLTAGE_READBACK
Settings
1111
0111
0000
Description
PLL clock multiplier output is stable.
VCO control voltage readback. A binary value.
The highest VCO control voltage.
The midvalue when a proper VCO band is selected. When
the PLL is locked, selecting a higher VCO band decreases this
value and selecting a lower VCO band increases this value.
The lowest VCO control voltage.
Rev. 0 | Page 47 of 56
Reset
0
0x0
Access
R
R
AD9139
Data Sheet
PLL STATUS 1 REGISTER
Address: 0x17, Reset: 0x00, Name: PLL_STATUS1
Table 42. Bit Descriptions for PLL_STATUS1
Bit No.
[5:0]
Bit Name
PLL_BAND_READBACK
Settings
Description
Indicates the VCO band that is currently selected.
Reset
0x00
Access
R
Description
See Register 0x19.
Reset
0xF9
Access
R/W
Description
Bandgap trim code. Set to the default value for optimal
performance.
DAC full-scale adjust, Bits[9:0] sets the full-scale current of
the DAC. The full-scale current can be adjusted from 8.64 mA
to 31.68 mA. The default value (0x1F9) sets the full-scale
current to 20 mA.
Reset
0x7
Access
R/W
0x1
R/W
DAC FS ADJUST LSB REGISTER
Address: 0x18, Reset: 0xF9, Name: DAC_FS_ADJ0
Table 43. Bit Descriptions for DAC_FS_ADJ0
Bit No.
[7:0]
Bit Name
DAC_FULLSCALE_ADJUST_LSB
Settings
DAC FS ADJUST MSB REGISTER
Address: 0x19, Reset: 0xE1, Name: DAC_FS_ADJ1
Table 44. Bit Descriptions for DAC_FS_ADJ1
Bit No.
[7:5]
Bit Name
BG_TRIM
[1:0]
DAC_FULLSCALE_ADJUST_MSB
Settings
DIE TEMPERATURE SENSOR CONTROL REGISTER
Address: 0x1C, Reset: 0x02, Name: DIE_TEMP_SENSOR_CTRL
Table 45. Bit Descriptions for DIE_TEMP_SENSOR_CTRL
Bit No.
[6:4]
Bit Name
FS_CURRENT
Settings
000
001
…
110
111
[3:1]
REF_CURRENT
000
001
…
110
111
0
DIE_TEMP_SENSOR_EN
Description
Temperature sensor ADC full-scale current. Using the default
setting is recommended.
50 μA.
62.5 μA.
…
125 μA.
137.5 μA.
Temperature sensor ADC reference current. Using the default
setting is recommended.
12.5 μA.
19 μA.
…
50 μA.
56.5 μA.
Enable the on-chip temperature sensor.
Reset
0x0
Access
R/W
0x1
R/W
0x0
R/W
Description
This register is used together with Register 0x1E.
Reset
0x00
Access
R
DIE TEMPERATURE LSB REGISTER
Address: 0x1D, Reset: 0x00, Name: DIE_TEMP_LSB
Table 46. Bit Descriptions for DIE_TEMP_LSB
Bit No.
[7:0]
Bit Name
DIE_TEMP_LSB
Settings
Rev. 0 | Page 48 of 56
Data Sheet
AD9139
DIE TEMPERATURE MSB REGISTER
Address: 0x1E, Reset: 0x00, Name: DIE_TEMP_MSB
Table 47. Bit Descriptions for DIE_TEMP_MSB
Bit No.
[7:0]
Bit Name
DIE_TEMP_MSB
Settings
Description
Die temperature, Bits[15:0] indicate the approximate die temperature.
For more information, see the Temperature Sensor section.
Reset
0x00
Access
R
CHIP ID REGISTER
Address: 0x1F, Reset: 0x0A, Name: CHIP_ID
Table 48. Bit Descriptions for CHIP_ID
Bit No.
[7:0]
Bit Name
CHIP_ID
Settings
Description
The AD9139 chip ID is 0x0A.
Reset
0x0A
Access
R
Rese
t
0x00
Acces
s
R/W
INTERRUPT CONFIGURATION REGISTER
Address: 0x20, Reset: 0x00, Name: INTERRUPT_CONFIG
Table 49. Bit Descriptions for INTERRUPT_CONFIG
Bit No
.
[7:0]
Bit Name
INTERRUPT_CONFIGURATION
Settings
0x00
0x01
Description
Test mode.
Recommended mode (described in the Interrupt Request
Operation section).
SYNC CONTROL REGISTER
Address: 0x21, Reset: 0x00, Name: SYNC_CTRL
Table 50. Bit Descriptions for SYNC_CTRL
Bit No.
1
Bit Name
SYNC_CLK_EDGE_SEL
Settings
0
1
0
SYNC_ENABLE
Description
Selects the sampling edge of the DACCLK on the sync clock.
SYNC CLK is sampled by rising edges of DACCLK.
SYNC CLK is sampled by falling edges of DACCLK.
Enables multichip synchronization.
Reset
0
Access
R/W
0
R/W
FRAME RESET CONTROL REGISTER
Address: 0x22, Reset: 0x12, Name: FRAME_RST_CTRL
Table 51. Bit Descriptions for FRAME_RST_CTRL
Bit No.
3
Bit Name
ARM_FRAME
2
EN_CON_FRAME_RESET
Settings
0
1
[1:0]
FRAME_RESET_MODE
10
11
Description
This bit is used to retrigger a frame reset in one shot mode (when Bit
2 is set to 0). Setting this bit to 1 requests that the device respond to
the next valid frame pulse.
Frame reset mode selection.
Responds to the first valid frame pulse and resets the FIFO one time
only. This is the default and recommended mode.
Responds to every valid frame pulse and resets the FIFO
continuously.
These bits determine what is to be reset when the device receives a
valid frame signal.
FIFO.
None.
Rev. 0 | Page 49 of 56
Reset
0
Access
R/W
0
R/W
0x2
R/W
AD9139
Data Sheet
FIFO LEVEL CONFIGURATION REGISTER
Address: 0x23, Reset: 0x40, Name: FIFO_LEVEL_CONFIG
Table 52. Bit Descriptions for FIFO_LEVEL_CONFIG
Bit No.
[6:4]
Bit Name
INTEGER_FIFO_LEVEL_REQUEST
Settings
Description
Set the integer FIFO level. This is the difference between the
read pointer and the write pointer values in the unit of
input data rate (fDATA). The default and recommended
FIFO level is integer level = 4 and fractional level = 0. See
the FIFO Operation section for details.
0
1
…
7
Set the fractional FIFO level. This is the difference between
the read pointer and the write pointer values in the unit
of DACCLK rate (FDAC). The maximum allowed setting
value = interpolation rate − 1. See the FIFO Operation
section for details.
0
1
000
001
…
111
[2:0]
FRACTIONAL_FIFO_LEVEL_REQUEST
000
001
Reset
0x4
Access
R/W
0x0
R/W
Reset
0x0
Access
R
0x0
R
FIFO LEVEL READBACK REGISTER
Address: 0x24, Reset: 0x00, Name: FIFO_LEVEL_READBACK
Table 53. Bit Descriptions for FIFO_LEVEL_READBACK
Bit No.
[6:4]
Bit Name
INTEGER_FIFO_LEVEL_READBACK
Settings
[2:0]
FRACTIONAL_FIFO_LEVEL_READBACK
Description
The integer FIFO level read back. The difference between
the overall FIFO level request and readback is within two
DACCLK cycles. See the FIFO Operation section for
details.
The fractional FIFO level read back. This value is used in
combination with the readback in Bit[6:4].
FIFO CONTROL REGISTER
Address: 0x25, Reset: 0x00, Name: FIFO_CTRL
Table 54. Bit Descriptions for FIFO_CTRL
Bit No.
1
0
Bit Name
FIFO_SPI_RESET_ACK
FIFO_SPI_RESET_REQUEST
Settings
Description
Acknowledge a serial port initialized FIFO reset.
Initialize a FIFO reset via the serial port.
Rev. 0 | Page 50 of 56
Reset
0x0
0x0
Access
R
R/W
Data Sheet
AD9139
DATA FORMAT SELECT REGISTER
Address: 0x26, Reset: 0x00, Name: DATA_FORMAT_SEL
Table 55. Bit Descriptions for DATA_FORMAT_SEL
Bit No.
7
Bit Name
DATA_FORMAT
Settings
0
1
0
DATA_BUS_WIDTH
0
1
Description
Select binary or twos complement data format.
Input data in twos complement format.
Input data in binary format.
Data interface mode. See the LVDS Input Data Ports section for
information about the operation of the different interface modes.
Word mode; 16-bit interface bus width.
Byte mode; 8-bit interface bus width.
Reset
0
Access
R/W
0
R/W
DATAPATH CONTROL REGISTER
Address: 0x27, Reset: 0x00, Name: DATAPATH_CTRL
Table 56. Bit Descriptions for DATAPATH_CTRL
Bit No.
7
5
Bit Name
INVSINC_ENABLE
DIG_GAIN_DCOFFSET_ENABLE
Settings
Description
Enable the inverse sinc filter.
Enable digital gain adjustment and dc offset.
Reset
0
0
Access
RW
RW
INTERPOLATION CONTROL REGISTER
Address: 0x28, Reset: 0x00, Name: INTERPOLATION_CTRL
Table 57. Bit Descriptions for INTERPOLATION_CTRL
Bit No.
7
Bit Name
INTERPOLATION_MODE
Settings
Description
Interpolation mode selection.
2× mode.
1× mode.
0
1
Reset
0x0
Access
RW
POWER-DOWN DATA INPUT 0 REGISTER
Address: 0x39, Reset: 0x00, Name: LVDS_IN_PWR_DOWN_0
Table 58. Bit Descriptions for LVDS_IN_PWR_DOWN_0
Bit No.
[3:0]
Bit Name
PWR_DOWN_DATA_INPUT_BITS
Settings
Description
Powers down Data Input Bits[3:0]. Each bit controls one data
input bit. These bits can be powered down individually.
Reset
0x0
Access
R/W
Reset
0x00
Access
RW
Reset
0x00
Access
RW
DAC DC OFFSET 0 REGISTER
Address: 0x3B, Reset: 0x00, Name: DAC_DC_OFFSET0
Table 59. Bit Descriptions for DAC_DC_OFFSET0
Bit No.
[7:0]
Bit Name
DAC_DC_OFFSET_LSB
Settings
Description
See Register 0x3C.
DAC DC OFFSET 1 REGISTER
Address: 0x3C, Reset: 0x00, Name: DAC_DC_OFFSET1
Table 60. Bit Descriptions for DAC_DC_OFFSET1
Bit No.
[7:0]
Bit Name
DAC_DC_OFFSET_MSB
Settings
Description
DAC DC offset, Bits[15:0], is a dc value that is added directly to the
sample values written to the DAC.
Rev. 0 | Page 51 of 56
AD9139
Data Sheet
DAC GAIN ADJ REGISTER
Address: 0x3F, Reset: 0x20, Name: DAC_DIG_GAIN
Table 61. Bit Descriptions for DAC_GAIN_ADJ
Bit No.
[5:0]
Bit Name
DAC_DIG_GAIN
Settings
Description
This register is the 6-bit digital gain adjust. The bit weighting is MSB =
20, LSB = 2−5, which yields a multiplier range of 0 to 2 or −∞ to 6 dB. The
default gain setting is 0x20, which maps to unity gain (0 dB).
Reset
0x20
Access
RW
Reset
0x01
Access
RW
Reset
0x0
Access
RW
0x0
R
0x01
RW
GAIN STEP CONTROL 0 REGISTER
Address: 0x41, Reset: 0x01, Name: GAIN_STEP_CTRL0
Table 62. Bit Descriptions for GAIN_STEP_CTRL0
Bit No.
[5:0]
Bit Name
RAMP_UP_STEP
Settings
Description
This register sets the step size of the increasing gain. The digital gain
increases by the configured amount in every four DAC cycles until the
gain reaches the setting in DAC_GAIN_ADJ (Register 0x3F). The bit
weighting is MSB = 21, LSB = 2−4. Note that the value in this register
must not be greater than the values in the DAC_GAIN_ADJ.
GAIN STEP CONTROL 1 REGISTER
Address: 0x42, Reset: 0x01, Name: GAIN_STEP_CTRL1
Table 63. Bit Descriptions for GAIN_STEP_CTRL1
Bit No.
7
Bit Name
DAC_OUTPUT_STATUS
6
DAC_OUTPUT_ON
[5:0]
RAMP_DOWN_STEP
Settings
Description
This bit indicates the DAC output on/off status. When the DAC output
is automatically turned off, this bit is 1.
In the case where the DAC output is automatically turned off in the Tx
enable mode, this register allows for turning on the DAC output
manually. It is a self clear bit.
This register sets the step size of the decreasing gain. The digital gain
decreases by the configured amount in every four DAC cycles until the
gain reaches zero. The bit weighting is MSB = 21, LSB = 2−4. Note that the
value in this register must not be greater than the values in the
DAC_GAIN_ADJ (Register 0x3F).
TX ENABLE CONTROL REGISTER
Address: 0x43, Reset: 0x07, Name: TX_ENABLE_CTRL
Table 64. Bit Descriptions for TX_ENABLE_CTRL
Bit No.
2
Bit Name
TXENABLE_GAINSTEP_EN
1
TXENABLE_SLEEP_EN
0
TXENABLE_POWER_DOWN_EN
Settings
Description
DAC output gradually turns on/off under the control of the
TXENABLE signal from the TXEN pin according to the settings in
Register 0x41 and Register 0x42.
When set to 1, the device enters sleep mode when the TXENABLE
signal from the TXEN pin is low.
When set to 1, the device enters power-down mode when the
TXENABLE signal from the TXEN pin is low.
Rev. 0 | Page 52 of 56
Reset
1
Access
RW
1
RW
1
RW
Data Sheet
AD9139
DAC OUTPUT CONTROL REGISTER
Address: 0x44, Reset: 0x8F, Name: DAC_OUTPUT_CTRL
Table 65. Bit Descriptions for DAC_OUTPUT_CTRL
Bit No.
7
Bit Name
DAC_OUTPUT_CTRL_EN
Settings
3
FIFO_WARNING_SHUTDOWN_EN
0
FIFO_ERROR_SHUTDOWN_EN
Description
Enable the DAC output control. This bit needs to be set to 1
to enable the rest of the bits in this register.
When this bit and Bit 7 are both high, if a FIFO warning
occurs, the DAC output shuts down automatically. By
default, this function is on.
The DAC output is turned off when the FIFO reports
warnings.
Reset
0x1
Access
RW
0x1
RW
0x1
RW
DLL CELL ENABLE 0 REGISTER
Address: 0x5E, Reset: 0xFF, Name: ENABLE_DLL_DELAY_CELL0
Table 66. Bit Descriptions for ENABLE_DLL_DELAY_CELL0
Bit No.
Bit Name
Description
[7:0]
DELAY_CELL_ENABLE [7:0]
Set each bit to enable or disable the delay cell. Delay cell number corresponds
to bit number.
1 = enable delay cell (default).
0 = disable delay cell.
Rese
t
0xFF
Access
Reset
0x0C
0x7
Access
RW
RW
Reset
0
0
0
0
0
0
0
0
Access
RW
RW
RW
RW
R
RW
R
R
RW
Different recommended values should be used in DLL mode and delay line mode. See the
DLL Interface Mode section.
DLL CELL ENABLE 1 REGISTER
Address: 0x5F, Reset: 0x67, Name: ENABLE_DLL_DELAY_CELL1
Table 67. Bit Descriptions for ENABLE_DLL_DELAY_CELL1
Bit No.
[7:3]
[2:0]
Bit Name
Reserved
DELAY_CELL_ENABLE [10:8]
Description
Must write the default value for optimal performance.
Set each bit to enable or disable the delay cell. Delay cell numbers are (10, 9, 8)
corresponding to bits (2, 1, 0).
1 = enable delay cell (default).
0 = disable delay cell.
SED CONTROL REGISTER
Address: 0x60, Reset: 0x00, Name: SED_CTRL
Table 68. Bit Descriptions for SED_CTRL
Bit No.
7
6
5
4
3
2
1
0
Bit Name
SED_ENABLE
SED_ERR_CLEAR
AED_ENABLE
SED_DEPTH
Reserved
AED_PASS
AED_FAIL
SED_FAIL
Description
Set to 1 to enable the SED compare logic.
When 1, clears all SED reported error bits, Bit 2, Bit 1, and Bit 0.
When 1, enables the AED function (SED with autoclear after eight passing sets).
0 = SED depth of two words, 1 = SED depth of four words.
Reserved.
When AED = 1, it signals eight true compare cycles.
When AED = 1, it signals a mismatch in comparison.
Signals that an SED mismatch in comparison occurred (with SED or AED enabled).
Rev. 0 | Page 53 of 56
AD9139
Data Sheet
SED PATTERN S0 LOW BITS REGISTER
Address: 0x61, Reset: 0x00, Name: SED_PATT_L_S0
Table 69. Bit Descriptions for SED_PATT_L_S0
Bit No.
[7:0]
Bit Name
SED_PATTERN_RISE_S0 [7:0]
Description
SED S0 rising edge low bits.
Reset
0x00
Access
RW
Description
SED S0 rising edge high bits.
Reset
0x00
Access
RW
Description
SED S1 falling edge low bits.
Reset
0x00
Access
RW
Description
SED S1 falling edge high bits.
Reset
0x00
Access
RW
SED PATTERN S0 HIGH BITS REGISTER
Address: 0x62, Reset: 0x00, Name: SED_PATT_H_S0
Table 70. Bit Descriptions for SED_PATT_H_S0
Bit No.
[7:0]
Bit Name
SED_PATTERN_RISE_S0 [15:8]
SED PATTERN S1 LOW BITS REGISTER
Address: 0x63, Reset: 0x00, Name: SED_PATT_L_S1
Table 71. Bit Descriptions for SED_PATT_L_S1
Bit No.
[7:0]
Bit Name
SED_PATTERN_FALL_S1 [7:0]
SED PATTERN S1 HIGH BITS REGISTER
Address: 0x64, Reset: 0x00, Name: SED_PATT_H_S1
Table 72. Bit Descriptions for SED_PATT_H_S1
Bit No.
[7:0]
Bit Name
SED_PATTERN_FALL_S1 [15:8]
SED PATTERN S2 LOW BITS REGISTER
Address: 0x65, Reset: 0x00, Name: SED_PATT_L_S2
Table 73. Bit Descriptions for SED_PATT_L_S2
Bit No.
[7:0]
Bit Name
SED_PATTERN_RISE_S2 [7:0]
Description
SED S2 rising edge low bits.
Reset
0x00
Access
RW
Description
SED S2 rising edge high bits.
Reset
0x00
Access
RW
Description
SED s3 falling edge low bits.
Reset
0x00
Access
RW
SED PATTERN S2 HIGH BITS REGISTER
Address: 0x66, Reset: 0x00, Name: SED_PATT_H_S2
Table 74. Bit Descriptions for SED_PATT_H_S2
Bit No.
[2:0]
Bit Name
SED_PATTERN_RISE_S2 [15:8]
SED PATTERN S3 LOW BITS REGISTER
Address: 0x67, Reset: 0x00, Name: SED_PATT_L_S3
Table 75. Bit Descriptions for SED_PATT_L_S3
Bit No.
[7:0]
Bit Name
SED_PATTERN_FALL_S3 [7:0]
Rev. 0 | Page 54 of 56
Data Sheet
AD9139
SED PATTERN S3 HIGH BITS REGISTER
Address: 0x68, Reset: 0x00, Name: SED_PATT_H_S3
Table 76. Bit Descriptions for SED_PATT_H_S3
Bit No.
[2:0]
Bit Name
SED_PATTERN_FALL_S3 [15:8]
Description
SED S3 falling edge high bits.
Reset
0x00
Access
RW
PARITY CONTROL REGISTER
Address: 0x6A, Reset: 0x00, Name: PARITY_CTRL
Table 77. Bit Descriptions for PARITY_CTRL
Bit No.
7
6
Bit Name
PARITY_ENABLE
PARITY_EVEN
5
[4:2]
1
0
PARITY_ERR_CLEAR
Reserved
PARERRFAL
PARERRRIS
Settings
1
0
1
Description
Enable parity.
Odd parity.
Even parity.
Set to 1 to clear parity error counters.
Reserved.
When 1, signals a falling edge parity error was detected.
When 1, signals a rising edge parity error was detected.
Reset
0
0
Access
RW
RW
0
0x0
0
0
RW
R
R
R
Reset
0x00
Access
R
Reset
0x00
Access
R
PARITY ERROR RISING EDGE REGISTER
Address: 0x6B, Reset: 0x00, Name: PARITY_ERR_RISING
Table 78. Bit Descriptions for PARITY_ERR_RISING
Bit No.
[7:0]
Bit Name
PARITY RISING EDGE ERROR
COUNT
Description
Number of rising edge-based errors detected (S0 and S2). Clipped to 256.
PARITY ERROR FALLING EDGE REGISTER
Address: 0x6C, Reset: 0x00, Name: PARITY_ERR_FALLING
Table 79. Bit Descriptions for PARITY_ERR_FALLING
Bit No.
[7:0]
Bit Name
PARITY FALLING EDGE ERROR
COUNT
Description
Number of falling edge-based errors detected (S1 and S3). Clipped to 256.
VERSION REGISTER
Address: 0x7F, Reset: 0x07, Name: Version
Table 80. Bit Descriptions for Version
Bit No.
[7:0]
Bit Name
Version
Settings
Description
Chip version
Rev. 0 | Page 55 of 56
Reset
0x07
Access
R
AD9139
Data Sheet
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
10.10
10.00 SQ
9.90
0.60
0.42
0.24
0.60
0.42
0.24
0.30
0.23
0.18
55
54
72
1
PIN 1
INDICATOR
PIN 1
INDICATOR
9.85
9.75 SQ
9.65
0.50
BSC
0.50
0.40
0.30
18
37
BOTTOM VIEW
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
0.25 MIN
8.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4
06-25-2012-A
1.00
0.85
0.80
19
36
TOP VIEW
12° MAX
6.15
6.00 SQ
5.85
EXPOSED
PAD
Figure 51. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
10 mm × 10 mm Body, Very Thin Quad
(CP-72-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD9139BCPZ
AD9139BCPZRL
AD9139-EBZ
AD9139-DUAL-EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
72-lead LFCSP_VQ
72-lead LFCSP_VQ
Evaluation Board for Single AD9139 Evaluation
Evaluation Board for Dual AD9139 Evaluation
Z = RoHS Compliant Part.
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11744-0-10/13(0)
Rev. 0 | Page 56 of 56
Package Option
CP-72-7
CP-72-7