CY29947
2.5 V or 3.3 V, 200 MHz,
1:9 Clock Distribution Buffer
2.5 V or 3.3 V, 200 MHz, 1:9 Clock Distribution Buffer
Features
Functional Description
■
2.5 V or 3.3 V operation
■
200 MHz clock support
■
LVCMOS-/LVTTL-compatible inputs
■
9 clock outputs: drive up to 18 clock lines
■
Synchronous Output Enable
■
Output three-state control
■
250 ps max. output-to-output skew
■
Pin compatible with MPC947, MPC9447
■
Available in Industrial and Commercial temp. range
■
32-pin TQFP package
The CY29947 is a low-voltage 200 MHz clock distribution buffer
with the capability to select one of two LVCMOS/LVTTL
compatible clock inputs. The two clock sources can be used to
provide for a test clock as well as the primary system clock. All
other control inputs are LVCMOS/LVTTL compatible. The 9
outputs are LVCMOS or LVTTL compatible and can drive 50
series or parallel terminated transmission lines.For series
terminated transmission lines, each output can drive one or two
traces giving the device an effective fanout of 1:18. The outputs
can also be three-stated via the three-state input TS#. Low
output-to-output skews make the CY29947 an ideal clock
distribution buffer for nested clock trees in the most demanding
of synchronous systems.
The CY29947 also provides a synchronous output enable input
for enabling or disabling the output clocks. Since this input is
internally synchronized to the input clock, potential output
glitching or runt pulse generation is eliminated.
For a complete list of related documentation, click here.
Block Diagram
VDD
TCLK0
0
TCLK1
1
VDDC
9
Q0-Q8
TCLK_SEL
SYNC_OE
TS#
Cypress Semiconductor Corporation
Document Number: 38-07287 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 13, 2016
CY29947
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Output Enable/Disable ..................................................... 4
Maximum Ratings ............................................................. 5
DC Parameters .................................................................. 5
Thermal Resistance .......................................................... 5
AC Parameters .................................................................. 6
Ordering Information ........................................................ 8
Ordering Code Definitions ........................................... 8
Package Drawing and Dimension ................................... 9
Document Number: 38-07287 Rev. *H
Acronyms ........................................................................ 10
Document Conventions ................................................. 10
Units of Measure ....................................................... 10
Revision History ............................................................. 11
Sales, Solutions, and Legal Information ...................... 12
Worldwide Sales and Design Support ....................... 12
Products .................................................................... 12
PSoC®Solutions ....................................................... 12
Cypress Developer Community ................................. 12
Technical Support ..................................................... 12
Page 2 of 12
CY29947
Pinouts
VSS
VDDC
Q0
VSS
Q1
VDDC
Q2
VSS
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
Q8
VSS
Q7
VDDC
Q6
VSS
CY29947
VDDC
VSS
TCLK_SEL
TCLK0
TCLK1
SYNC_OE
TS#
VDD
VSS
32
Figure 1. 32-pin TQFP pinout
24
23
22
21
20
19
18
17
VSS
Q3
VDDC
Q4
VSS
Q5
VDDC
VSS
Pin Definitions
Pin
Name
3
TCLK0
PWR
I/O [1]
Description
I, PU
Test Clock Input
4
TCLK1
I, PU
Test Clock Input
2
TCLK_SEL
I, PU
Test Clock Select Input. When LOW, TCLK0 is selected. When
asserted HIGH, TCLK1 is selected.
11, 13, 15, 19,
21, 23, 26, 28,
30
Q(8:0)
5
SYNC_OE
I, PU
Output Enable Input. When asserted HIGH, the outputs are enabled
and when set LOW the outputs are disabled in a LOW state.
6
TS#
I, PU
Three-state Control Input. When asserted LOW, the output buffers
are three-stated. When set HIGH, the output buffers are enabled.
10, 14, 18, 22,
27, 31
VDDC
7
VDD
3.3 V or 2.5 V Power Supply
1, 8, 9, 12, 16,
17, 20, 24, 25,
29, 32
VSS
Common Ground
VDDC
O
Clock Outputs
3.3 V or 2.5 V Power Supply for Output Clock Buffers
Note
1. PD = internal pull-down, PU = internal pull-up.
Document Number: 38-07287 Rev. *H
Page 3 of 12
CY29947
Output Enable/Disable
The CY29947 features a control input to enable or disable the
outputs. This data is latched on the falling edge of the input clock.
When SYNC_OE is asserted LOW, the outputs are disabled in a
LOW state. When SYNC_OE is set HIGH, the outputs are
enabled as shown in Figure 2.
Figure 2. SYNC_OE Timing Diagram
TCLK
SYNC_OE
Q
Document Number: 38-07287 Rev. *H
Page 4 of 12
CY29947
Maximum Ratings
Maximum Power Supply: .............................................. 5.5 V
Exceeding maximum ratings [2] may shorten the useful life of the
device. User guidelines are not tested.
Maximum Input Voltage Relative to VSS: ........... VSS – 0.3 V
Maximum Input Voltage Relative to VDD: ........... VDD + 0.3 V
Storage Temperature: ............................. –65 °C to + 150 °C
Maximum Input Current: ........................................... ±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For proper
operation, Vin and Vout should be constrained to the range:
VSS < (Vin or Vout) < VDD
Operating Temperature: ............................. –40 °C to +85 °C
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
Maximum ESD protection .............................................. 2 kV
DC Parameters
VDD = VDDC = 3.3 V ± 10% or 2.5 V ± 5%, Over the specified temperature range
Min
Typ
Max
Unit
VIL
Parameter
Input Low Voltage
Description
VSS
–
0.8
V
VIH
Input High Voltage
2.0
–
VDD
V
–
–
–100
µA
Input Low
Current[3]
IIH
Input High
Current[3]
VOL
Output Low Voltage[4]
VOH
Voltage[4]
IIL
Output High
IDDQ
Quiescent Supply Current
IDD
Dynamic Supply Current
Zout
Cin
Output Impedance
Conditions
–
–
10
µA
–
–
0.4
V
IOH = –20 mA, VDD = 3.3 V
2.5
–
–
V
IOH = –20 mA, VDD = 2.5 V
1.8
–
–
IOL = 20 mA
–
5
7
mA
VDD = 3.3 V, Outputs @ 100 MHz,
CL = 30 pF
–
120
–
mA
VDD = 3.3 V, Outputs @ 160 MHz,
CL = 30 pF
–
200
–
VDD = 2.5 V, Outputs @ 100 MHz,
CL = 30 pF
–
85
–
VDD = 2.5 V, Outputs @ 160 MHz,
CL = 30 pF
–
140
–
VDD = 3.3 V
12
15
18
VDD = 2.5 V
14
18
22
–
4
–
Input Capacitance
pF
Thermal Resistance
Parameter [5]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
32-pin TQFP
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
65
°C/W
12
°C/W
Notes
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. Driving series or parallel terminated 50 (or 50 to VDD/2) transmission lines.
5. These parameters are guaranteed by design and are not tested.
Document Number: 38-07287 Rev. *H
Page 5 of 12
CY29947
AC Parameters
VDD = VDDC = 3.3 V ± 10% or 2.5 V ± 5%, Over the specified temperature range
Parameter [6]
Description
Min
Typ
Max
Unit
–
–
200
MHz
VDD = 2.5 V
–
–
170
VDD = 3.3 V
4.75
–
9.25
VDD = 2.5 V
6.50
–
10.50
45
–
55
%
Output Enable Time (all outputs)
2
–
10
ns
Output Disable Time (all outputs)
2
–
10
ns
–
150
250
ps
–
–
2.0
ns
Fmax
Input Frequency[7]
Tpd
TCLK To Q Delay[7]
FoutDC
Output Duty Cycle[7, 8]
tpZL, tpZH
tpLZ, tpHZ
Conditions
VDD = 3.3 V
Measured at VDD/2
[7, 9]
ns
Tskew
Output-to-Output Skew
Tskew(pp)
Part-to-Part Skew[10]
Ts
Set-up Time[7, 11]
SYNC_OE to TCLK
0.0
–
–
ps
Th
Hold Time[7, 11]
TCLK to SYNC_OE
1.0
–
–
ps
0.8 V to 2.0 V, VDD = 3.3 V
0.20
–
1.0
ns
0.6 V to 1.8 V, VDD = 2.5 V
0.20
–
1.3
Tr/Tf
Output Clocks Rise/Fall
Time[9]
Notes
6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
7. Outputs driving 50 transmission lines.
8. 50% input duty cycle.
9. See Figure 3 on page 7.
10. Part-to-Part skew at a given temperature and voltage.
11. Set-up and hold times are relative to the falling edge of the input clock.
Document Number: 38-07287 Rev. *H
Page 6 of 12
CY29947
Figure 3. LVCMOS_CLK CY29947 Test Reference for VCC = 3.3 V and VCC = 2.5 V
CY29947 DUT
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 4. LVCMOS Propagation Delay (TPD) Test Reference
VCC
LVCMOS_CLK
VCC /2
GND
VCC
Q
VCC /2
tPD
GND
Figure 5. Output Duty Cycle (FoutDC)
VCC
VCC /2
tP
GND
T0
DC = tP / T0 x 100%
Figure 6. Output-to-Output Skew tsk(0)
VCC
VCC /2
GND
VCC
VCC /2
tSK(0)
Document Number: 38-07287 Rev. *H
GND
Page 7 of 12
CY29947
Ordering Information
Part Number
Package Type
Production Flow
CY29947AXI
32-pin TQFP
Industrial, –40 °C to +85 °C
CY29947AXIT
32-pin TQFP – Tape and Reel
Industrial, –40 °C to +85 °C
Ordering Code Definitions
CY 29947 A
X
X
T
T = Tape and Reel
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type:
A = 32-pin TQFP
Base Device Part Number
Company ID: CY = Cypress
Document Number: 38-07287 Rev. *H
Page 8 of 12
CY29947
Package Drawing and Dimension
Figure 7. 32-pin TQFP (7 × 7 × 1.0 mm) Package Outline, 51-85063
51-85063 *E
Document Number: 38-07287 Rev. *H
Page 9 of 12
CY29947
Acronyms
Acronym
Document Conventions
Description
CMOS
Complementary Metal Oxide Semiconductor
ESD
Electrostatic Discharge
I/O
Input/Output
LVCMOS
Low Voltage Complementary Metal Oxide
Semiconductor
LVTTL
Units of Measure
Symbol
°C
Unit of Measure
degree Celsius
Hz
hertz
kHz
kilohertz
Low Voltage Transistor-Transistor Logic
kV
kilovolt
PLL
Phase Locked Loop
MHz
megahertz
TQFP
Thin Quad Flat Pack
µA
microampere
Voltage-Controlled Oscillator
mA
milliampere
ms
millisecond
mV
millivolt
ns
nanosecond
ohm
VCO
Document Number: 38-07287 Rev. *H
%
percent
pF
picofarad
ps
picosecond
V
volt
W
watt
Page 10 of 12
CY29947
Revision History
Document Title: CY29947, 2.5 V or 3.3 V, 200 MHz, 1:9 Clock Distribution Buffer
Document Number: 38-07287
Rev.
ECN No.
Issue Date
Orig. of
Change
**
111098
02/07/02
BRK
New data sheet
*A
116781
08/14/02
HWT
Added Commercial Temperature Range in the ordering information
*B
118462
09/09/02
HWT
Corrected the Package Drawing and Dimension in page 6 from 32 LQFP to 32
TQFP
*C
122879
12/22/02
RBI
*D
2899714
03/26/10
BASH
Removed inactive parts from the ordering table. Replaced with active parts.
Updated package diagram
*E
3163585
02/05/2011
CXQ
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated to new template.
*F
4311272
03/17/2014
CINM
Updated Package Drawing and Dimension:
spec 51-85063 – Changed revision from *C to *D.
Updated to new template.
Completing Sunset Review.
*G
4586288
12/03/2014
CINM
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Ordering Information:
Removed the prune part numbers CY29947AXC and CY29947AXCT.
*H
5270507
05/13/2016
PSR
Added Thermal Resistance.
Updated Package Drawing and Dimension:
spec 51-85063 – Changed revision from *D to *E.
Updated to new template.
Document Number: 38-07287 Rev. *H
Description of Change
Added power up requirements to Maximum Ratings
Page 11 of 12
CY29947
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Document Number: 38-07287 Rev. *H
Revised May 13, 2016
Page 12 of 12