CY2DM1502
1:2 CML Fanout Buffer
with Selectable Clock Input
1:2 CML Fanout Buffer with Selectable Clock Input
Features
Functional Description
■
One current mode logic (CML), High-speed current steering
logic (HCSL), or low-voltage positive emitter-coupled logic
(LVPECL) input pair distributed to two CML output pairs
■
20-ps maximum output-to-output skew
■
480-ps maximum propagation delay
■
0.15-ps maximum additive RMS phase jitter at 156.25 MHz
(12-kHz to 20-MHz offset)
■
Up to 1.5 GHz operation
■
8-pin thin shrunk small outline package (TSSOP) package
■
2.5-V or 3.3-V operating voltage [1]
■
Commercial and industrial operating temperature range
The CY2DM1502 is an ultra-low noise, low-skew,
low-propagation delay 1:2 CML, HCSL, or LVPECL to CML
fanout buffer targeted to meet the requirements of high-speed
clock distribution applications. The device has a fully differential
internal architecture that is optimized to achieve low additive jitter
and low skew at operating frequencies of up to 1.5 GHz.
For a complete list of related documentation, click here.
Logic Block Diagram
VDD
VDD
VSS
Q0
Q0#
IN
IN#
Q1
Q1#
Note
1. Input AC-coupling capacitors are required for voltage-translation applications.
Cypress Semiconductor Corporation
Document Number: 001-56315 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 16, 2016
CY2DM1502
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Absolute Maximum Ratings ............................................ 4
Operating Conditions ....................................................... 4
DC Electrical Specifications ............................................ 5
Thermal Resistance .......................................................... 5
AC Electrical Specifications ............................................ 6
Ordering Information ........................................................ 9
Ordering Code Definitions ........................................... 9
Package Diagram ............................................................ 10
Document Number: 001-56315 Rev. *J
Acronyms ........................................................................ 11
Document Conventions ................................................. 11
Units of Measure ....................................................... 11
Document History Page ................................................. 12
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products .................................................................... 14
PSoC®Solutions ....................................................... 14
Cypress Developer Community ................................. 14
Technical Support ..................................................... 14
Page 2 of 14
CY2DM1502
Pinouts
Q0
1
Q0#
2
Q1
3
Q1#
4
CY2DM1502
Figure 1. 8-pin TSSOP Package pinout
8
VDD
7
IN
6
IN#
5
VSS
Pin Definitions
Pin No.
Pin Name
Pin Type
Description
1, 3
Q(0:1)
Output
CML output clocks
2, 4
Q(0:1)#
Output
CML complementary output clocks
5
VSS
Power
Ground
6
IN#
Input
CML/HCSL/LVPECL complementary input clock
7
IN
Input
CML/HCSL//LVPECL input clock
8
VDD
Power
Power supply
Document Number: 001-56315 Rev. *J
Page 3 of 14
CY2DM1502
Absolute Maximum Ratings
Parameter
VDD
Description
Condition
Min
Max
Unit
Supply voltage
Nonfunctional
–0.5
4.6
V
Input voltage, relative to VSS
Nonfunctional
–0.5
lesser of
4.0 or
VDD + 0.4
V
VOUT[2]
DC output or I/O voltage, relative Nonfunctional
to VSS
–0.5
lesser of
4.0 or
VDD + 0.4
V
TS
Storage temperature
Nonfunctional
–55
150
°C
ESDHBM
Electrostatic discharge (ESD)
protection (Human body model)
JEDEC STD 22-A114-B
2000
–
V
LU
Latch up
UL–94
Flammability rating
MSL
Moisture sensitivity level
VIN
[2]
Meets or exceeds JEDEC Spec
JESD78B IC Latch-up Test
At 1/8 in
V-0
3
Operating Conditions
Parameter
VDD
TA
tPU
Description
Supply voltage
Ambient operating temperature
Power ramp time
Condition
Min
Max
Unit
2.5-V supply
2.375
2.625
V
3.3-V supply
3.135
3.465
V
Commercial
0
70
°C
Industrial
–40
85
°C
Power-up time for VDD to reach minimum
specified voltage (power ramp must be
monotonic).
0.05
500
ms
Note
2. The voltage on any I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
Document Number: 001-56315 Rev. *J
Page 4 of 14
CY2DM1502
DC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
Description
Min
Max
Unit
–
50
mA
Input high voltage,
CML/HCSL/LVPECL inputs
IN and IN#
–
VDD + 0.3
V
VIL
Input low voltage,
CML/HCSL/LVPECL inputs
IN and IN#
–0.3
–
V
VID[3]
Input differential amplitude
See Figure 2 on page 7
0.4
1.0
V
VICM
Input common mode voltage
See Figure 2 on page 7
0.2
VDD – 0.2
V
–
150
A
–150
–
A
IDD
Operating supply current
VIH
Condition
All CML outputs floating (internal IDD)
[4]
IIH
Input high current,
CML/HCSL/LVPECL inputs
IN and IN#
Input = VDD
IIL
Input low current,
CML/HCSL/LVPECL inputs
IN and IN#
Input = VSS[4]
VOH
CML output high voltage
Terminated with 50 to VDD[5]
VDD – 0.1
–
V
VOL
CML output low voltage
Terminated with 50 to VDD[5]
VDD – 0.7
VDD – 0.3
V
CIN
Input capacitance
Measured at 10 MHz; per pin
–
3
pF
Thermal Resistance
Parameter [6]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
8-pin TSSOP
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
162
°C/W
29
°C/W
Notes
3. VID minimum of 400 mV is required to meet all output AC Electrical Specifications. The device is functional with VID minimum of greater than 200 mV.
4. Positive current flows into the input pin, negative current flows out of the input pin.
5. Refer to Figure 3 on page 7.
6. These parameters are guaranteed by design and are not tested.
Document Number: 001-56315 Rev. *J
Page 5 of 14
CY2DM1502
AC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
Description
Min
Typ
Max
Unit
DC
–
1.5
GHz
FOUT = FIN
DC
–
1.5
GHz
Fout = DC to 150 MHz
250
–
700
mV
Fout = >150 MHz to 1.5 GHz
250
–
600
mV
Input rise/fall time < 1.5 ns
(20% to 80%)
–
–
480
ps
Output duty cycle
50% duty cycle at input
Frequency range up to 1 GHz
48
–
52
%
tSK1[9]
Output-to-output skew
Any output to any output, with
same load conditions at DUT
–
–
20
ps
tSK1 D[9]
Device-to-device output skew
Any output to any output between
two or more devices. Devices must
have the same input and have the
same output load.
–
–
150
ps
PNADD
Additive RMS phase noise
156.25-MHz Input
Rise/fall time < 150 ps
(20% to 80%)
VID > 400 mV
Offset = 1 kHz
–
–
–120
dBc/
Hz
Offset = 10 kHz
–
–
–130
dBc/
Hz
Offset = 100 kHz
–
–
–135
dBc/
Hz
Offset = 1 MHz
–
–
–145
dBc/
Hz
Offset = 10 MHz
–
–
–153
dBc/
Hz
Offset = 20 MHz
–
–
–155
dBc/
Hz
FIN
Input frequency
FOUT
Output frequency
VPP
CML differential output voltage
peak-to-peak, single-ended.
Terminated with 50 to VDD[5]
tPD[7]
Propagation delay input pair to
output pair
tODC[8]
Condition
tJIT[10]
Additive RMS phase jitter
(Random)
156.25 MHz,
12 kHz to 20 MHz offset;
input rise/fall time < 150 ps
(20% to 80%),
VID > 400 mV
–
–
0.15
ps
tR, tF[11]
Output rise/fall time
50% duty cycle at input,
20% to 80% of full swing
(VOL to VOH)
Input rise/fall time < 1.5 ns
(20% to 80%)
Measured at 1 GHz
–
–
250
ps
Notes
7. Refer to Figure 4 on page 7.
8. Refer to Figure 5 on page 7.
9. Refer to Figure 6 on page 8.
10. Refer to Figure 7 on page 8.
11. Refer to Figure 8 on page 8.
Document Number: 001-56315 Rev. *J
Page 6 of 14
CY2DM1502
Figure 2. Input Differential and Common Mode Voltages
VA
IN
VICM = (VA + VB)/2
VID
IN#
VB
Figure 3. Output Differential Voltage
VOH
Q
VPP
Q#
VOL
Figure 4. Input to Any Output Pair Propagation Delay
IN
IN#
QX
QX#
tPD
Figure 5. Output Duty Cycle
QX
QX#
tPW
tPERIOD
tODC =
Document Number: 001-56315 Rev. *J
tPW
tPERIOD
Page 7 of 14
CY2DM1502
Figure 6. Output-to-Output and Device-to-Device Skew
QX
Device 1
QX#
QY
QY#
tSK1
QZ
Device 2
QZ#
tSK1 D
Figure 7. RMS Phase Jitter
Phase noise
Noise Power
Phase noise mark
Offset Frequency
f2
f1
RMS Jitter
Area Under the Masked Phase Noise Plot
Figure 8. Output Rise/Fall Time
QX
80% 80%
VPP
20%
QX#
20%
tR
Document Number: 001-56315 Rev. *J
tF
Page 8 of 14
CY2DM1502
Ordering Information
Part Number
Type
Production Flow
Pb-free
CY2DM1502ZXI
8-pin TSSOP
Industrial, –40 °C to 85 °C
CY2DM1502ZXIT
8-pin TSSOP tape and reel
Industrial, –40 °C to 85 °C
Ordering Code Definitions
CY 2
D M15
02
Z
X
X
X
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type:
Z = 8-pin TSSOP
Number of differential output pairs
Base part number
Technology Code: D = CML
Marketing Code: 2 = Buffer
Company ID: CY = Cypress
Document Number: 001-56315 Rev. *J
Page 9 of 14
CY2DM1502
Package Diagram
Figure 9. 8-pin TSSOP (4.40 MM Body) Z08.173/ZZ08.173 Package Outline, 51-85093
51-85093 *E
Document Number: 001-56315 Rev. *J
Page 10 of 14
CY2DM1502
Acronyms
Document Conventions
Table 1. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 2. Units of Measure
CML
current mode logic
ESD
electrostatic discharge
°C
degree Celsius
HBM
human body model
dBc
decibels relative to the carrier
HCSL
high-speed current steering logic
GHz
gigahertz
JEDEC
joint electron devices engineering council
Hz
hertz
LVDS
low-voltage differential signal
k
kilohm
LVCMOS
low-voltage complementary metal oxide
semiconductor
µA
microampere
LVPECL
low-voltage positive emitter-coupled logic
µF
microfarad
RMS
root mean square
µs
microsecond
TSSOP
thin shrunk small outline package
mA
milliampere
ms
millisecond
mV
millivolt
MHz
megahertz
Document Number: 001-56315 Rev. *J
Symbol
Unit of Measure
ns
nanosecond
ohm
pF
picofarad
ps
picosecond
V
volt
W
watt
Page 11 of 14
CY2DM1502
Document History Page
Document Title: CY2DM1502, 1:2 CML Fanout Buffer with Selectable Clock Input
Document Number: 001-56315
Revision
ECN
Orig. of
Change
Submission
Date
**
2782891
CXQ
10/09/09
*A
2838916
CXQ
01/05/2010
Changed status from “ADVANCE” to “PRELIMINARY”.
Changed from 0.34 ps to 0.25 ps maximum additive jitter in “Features” on page
1 and in tJIT in the AC Electrical Specs table on page 4.
Added tPU spec to the Operating Conditions table on page 2.
Removed VOH spec maximum of VDD in the DC Electrical Specs table on page
3.
Changed VOL spec min from VDD - 0.6V to VDD - 0.7V; changed max from VDD
- 0.4V to VDD - 0.3V in the DC Electrical Specs table on page 3.
Removed VOD spec of minimum 300 mV, maximum 450 mV in the DC Electrical
Specs table on page 3.
Added RP spec in the DC Electrical Specs table on page 3. Min = 60 k, Max
= 140 k.
Added a measurement definition for CIN in the DC Electrical Specs table on
page 3.
Added VPP spec to the AC Electrical Specs table on page 4. VPP max = 700
mV for DC - 150 MHz and max = 600 mV for 150 MHz to 1.5 GHz. VPP min =
250 mV over the entire range.
Changed letter case and some names of all the timing parameters in the AC
Electrical Specs table on page 4 to be consistent with EROS.
Lowered all additive phase noise mask specs by 3 dB in in the AC Electrical
Specs table on page 4.
Added condition to tR and tF specs in the AC Electrical specs table on page 4
that input rise/fall time must be less than 1.5 ns (20% to 80%).
Changed letter case and some names of all the timing parameters in Figures
3, 4, 5, 6 and 8, to be consistent with EROS.
*B
3011766
CXQ
08/20/2010
Changed from 0.25 ps to 0.11 ps maximum additive jitter in “Features” on page
1 and in tJIT in the AC Electrical Specs table.
Added note 3 to describe IIH and IIL specs.
Removed reference to data distribution from “Functional Description”.
Changed RP for diff inputs from 100 k to 150 k in the Logic Block Diagram
and from 60 k min / 140 k max to 90 k min / 210 k max in the DC Electrical
Specs table.
Added max VID of 1.0V in DC Electrical Specs table.
Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset to
-120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC Electrical Specs
table.
Added “Frequency range up to 1 GHz” condition to tODC spec.
Updated package diagram.
Added Acronyms and Ordering Code Definition.
*C
3017258
CXQ
08/27/2010
Corrected Output Rise/Fall time diagram.
*D
3100234
CXQ
11/18/2010
Updated Phase jitter to 0.15ps max from 0.11ps max.
Changed VIN and VOUT specs from 4.0V to “lesser of 4.0 or VDD + 0.4”
Removed 200mA min LU spec, replaced with “Meets or exceeds JEDEC Spec
JESD78B IC Latchup Test”
Removed RP spec for differential input clock pins INX and INX#.
Changed CIN condition to “Measured at 10 MHz”.
Changed PNADD specs for 1MHz, 10MHz, and 20MHz offsets.
Added condition “Measured at 1 GHz” to tR, tF specs.
*E
3137726
CXQ
01/13/2011
Removed “Preliminary” status heading.
Removed resistors from IN/IN# in Logic Block Diagram.
*F
3090938
CXQ
02/25/2011
Post to external web.
Document Number: 001-56315 Rev. *J
Description of Change
New Datasheet.
Page 12 of 14
CY2DM1502
Document History Page (continued)
Document Title: CY2DM1502, 1:2 CML Fanout Buffer with Selectable Clock Input
Document Number: 001-56315
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
*G
3410372
PURU
10/18/2011
Adding HCSL to Features, Functional Description, Pin Definitions, and DC
Electrical Specifications sections.
The min value of VICM is changed from 0.5 to 0.2 in DC Electrical Specifications.
*H
3878396
PURU
01/21/2013
Updated to new template.
*I
4587249
PURU
12/04/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Ordering Information:
Removed the prune part numbers CY2DM1502ZXC and CY2DM1502ZXCT.
Updated Package Diagram:
spec 51-85093 – Changed revision from *D to *E.
*J
5272915
PSR
05/16/2016
Added Thermal Resistance.
Updated to new template.
Document Number: 001-56315 Rev. *J
Page 13 of 14
CY2DM1502
Sales, Solutions, and Legal Information
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closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2009-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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Document Number: 001-56315 Rev. *J
Revised May 16, 2016
Page 14 of 14