Fujitsu Semiconductor Europe GmbH User Guide FSEUMCU-UG-9E0008-13 FCR4 FAMILY FCR4 CLUSTER SERIES EMULATION BOARD EMA-MB9DF120-001 USER GUIDE EMA-MB9DF120-001 User Guide Revision History Revision History Date 2011-09-13 2011-10-12 2011-10-27 2011-11-02 2012-03-20 Issue V0.1 OBe, started V1.0 NFl, first release V1.1 NFl, layout guidelines added V1.2 NFL Abbreviations updated V1.3, MNa Updated company name, added EU declaration of conformity chapter, updated recycling chapter, updated information in the WWW chapter, updated warranty disclaimer chapter Applies To Order-No. EMA-MB9DF120-001 Reference STD Description Standard-Version If not mentioned otherwise, this guide applies to all boards listed in the table above. Variantspecific features/differences are tagged by the name listed Reference. This Document contains 33 pages. Abbreviations DVM Digital Volt-Meter FSEU Fujitsu Semiconductor Europe GmbH FJ Fujitsu Japan MCU Microcontroller Unit ARM® Registered trademark of ARM Ltd. APIX® Automotive Pixel Link is a registered trademark of INOVA Semiconductors GmbH UG-9E0008-13 -2- © Fujitsu Semiconductor Europe GmbH EMA-MB9DF120-001 User Guide Warranty and Disclaimer Warranty and Disclaimer The use of the deliverables (e.g. software, application examples, target boards, evaluation boards, starter kits, schematics, engineering samples of IC’s etc.) is subject to the conditions of Fujitsu Semiconductor Europe GmbH (“FSEU”) as set out in (i) the terms of the License Agreement and/or the Sale and Purchase Agreement under which agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying written materials. Please note that the deliverables are intended for and must only be used for reference in an evaluation laboratory environment. The software deliverables are provided on an as-is basis without charge and are subject to alterations. It is the user’s obligation to fully test the software in its environment and to ensure proper functionality, qualification and compliance with component specifications. Regarding hardware deliverables, FSEU warrants that they will be free from defects in material and workmanship under use and service as specified in the accompanying written materials for a duration of 1 year from the date of receipt by the customer. Should a hardware deliverable turn out to be defect, FSEU’s entire liability and the customer’s exclusive remedy shall be, at FSEU´s sole discretion, either return of the purchase price and the license fee, or replacement of the hardware deliverable or parts thereof, if the deliverable is returned to FSEU in original packing and without further defects resulting from the customer’s use or the transport. However, this warranty is excluded if the defect has resulted from an accident not attributable to FSEU, or abuse or misapplication attributable to the customer or any other third party not relating to FSEU or to unauthorised decompiling and/or reverse engineering and/or disassembling. FSEU does not warrant that the deliverables do not infringe any third party intellectual property right (IPR). In the event that the deliverables infringe a third party IPR it is the sole responsibility of the customer to obtain necessary licenses to continue the usage of the deliverable. In the event the software deliverables include the use of open source components, the provisions of the governing open source license agreement shall apply with respect to such software deliverables. To the maximum extent permitted by applicable law FSEU disclaims all other warranties, whether express or implied, in particular, but not limited to, warranties of merchantability and fitness for a particular purpose for which the deliverables are not designated. To the maximum extent permitted by applicable law, FSEU’s liability is restricted to intention and gross negligence. FSEU is not liable for consequential damages. Should one of the above stipulations be or become invalid and/or unenforceable, the remaining stipulations shall stay in full effect. The contents of this document are subject to change without a prior notice, thus contact FSEU about the latest one. This board and its deliverables must only be used for test applications in an evaluation laboratory environment. © Fujitsu Semiconductor Europe GmbH -3- UG-9E0008-13 EMA-MB9DF120-001 User Guide Contents Contents REVISION HISTORY ............................................................................................................ 2 APPLIES TO......................................................................................................................... 2 ABBREVIATIONS ................................................................................................................ 2 WARRANTY AND DISCLAIMER ......................................................................................... 3 CONTENTS .......................................................................................................................... 4 1 OVERVIEW ...................................................................................................................... 6 1.1 Introduction ............................................................................................................. 6 1.2 Features .................................................................................................................. 6 1.3 Kit contents ............................................................................................................. 6 2 HARDWARE .................................................................................................................... 7 2.1 PCB Overview ......................................................................................................... 7 2.1.1 2.1.2 MCU-Board ................................................................................................ 7 2.1.1.1 Top-View ................................................................................... 7 2.1.1.2 Bottom View............................................................................... 8 Trace-Board ............................................................................................... 9 2.1.2.1 Top-View ................................................................................... 9 2.1.2.2 Bottom-View ............................................................................ 10 2.2 Module Stack......................................................................................................... 10 2.3 Power Supply ........................................................................................................ 11 2.4 2.3.1 Input-stage............................................................................................... 11 2.3.2 Buck Regulator ........................................................................................ 11 2.3.3 Power Distribution .................................................................................... 11 2.3.4 Debug-Supply .......................................................................................... 12 2.3.5 Power-Domain Monitors (LEDs) .............................................................. 12 2.3.6 Reset ....................................................................................................... 12 MCU Clocks .......................................................................................................... 12 2.4.1 Main Clock ............................................................................................... 12 2.4.1.1 2.5 Sub-Clock (RTC-Clock)............................................................ 12 On-Board Peripherals ............................................................................................ 12 2.5.1 APIX ........................................................................................................ 12 2.6 Target Connector .................................................................................................. 13 2.7 Debugging Facilities .............................................................................................. 13 3 INSTALLATION ............................................................................................................. 14 3.1 First Contact .......................................................................................................... 14 3.2 Engage .................................................................................................................. 14 UG-9E0008-13 -4- © Fujitsu Semiconductor Europe GmbH EMA-MB9DF120-001 User Guide Contents 3.3 Lifesigns ................................................................................................................ 14 4 CONFIGURATION AND TEST-POINTS ........................................................................ 15 4.1 Target-Supply Issues............................................................................................. 15 4.2 Target-Debugging ................................................................................................. 15 4.3 Jumpers ................................................................................................................ 15 4.4 Headers................................................................................................................. 17 4.5 Test-Points ............................................................................................................ 18 5 STATUS DISPLAY ......................................................................................................... 19 6 CONNECTORS .............................................................................................................. 20 6.1 MCU-Board ........................................................................................................... 20 6.1.1 6.2 APIX Connector (X2) ............................................................................... 20 Trace-Board .......................................................................................................... 20 6.2.1 Debug Connector (X3) ............................................................................. 21 6.2.2 Trace Connectors (X4, X5) ...................................................................... 22 6.2.2.1 Primary Trace-Connector (X4) ................................................. 22 6.2.2.2 Extension Trace-Connector (X5) .............................................. 23 6.3 DC In Plug (X2) ..................................................................................................... 23 6.4 Target Header (U5) ............................................................................................... 24 7 LAYOUT GUIDELINES FOR TARGET BOARD ............................................................ 25 7.1 Emulator Assembly Stack-up................................................................................. 25 7.2 Target Board Recommendations ........................................................................... 26 8 TROUBLE SHOOTING .................................................................................................. 27 9 RELATED PRODUCTS.................................................................................................. 28 10 INFORMATION IN THE WWW....................................................................................... 29 11 EU-KONFORMITÄTSERKLÄRUNG / EU DECLARATION OF CONFORMITY ............. 31 12 CHINA-ROHS REGULATION ........................................................................................ 32 13 RECYCLING .................................................................................................................. 33 © Fujitsu Semiconductor Europe GmbH -5- UG-9E0008-13 EMA-MB9DF120-001 User Guide Chapter 1 Overview 1 Overview 1.1 Introduction The EMA-MB9DF120-001 is a emulation and trace-adapter board for the Fujitsu FCR4 cluster series flash microcontroller MB96DF126 (Atlas). It can be used stand-alone for software development and testing or as a target board to work with the emulator system. It is intended as a plug-in replacement for the original 176 pin Atlas MCU. This requires a special header in the target-board which adopts to the original QFP176 footprint and to the EMAMB9DF120-001. This header is separately available. The great benefit for using this device is the fully supported trace-capability which can be accessed from the plug-in trace-adapter-board on top of the MCU-board. 1.2 Features Supports Fujitsu’s MB9DF126 (Atlas) Series of microcontrollers 5V external DC power supply (provided) On-board 3V3 and 1V2 voltage regulators for I/O- and MCU supply on stand-alone operation. Indication-LEDs for all generated supply-rails and reset. Full debug (JTAG, Trace) capabilities. Powered from target-system, optionally external supply through AC-adaptor possible. All power-domains available for selection. On-board crystals eliminate the need for target-supplied crystals. Full APIX high-speed serial interface on-board. An 4-pin FireWire-connector allows to use a standard-FW cable. 1:1 MCU-signal mapping to target system ARM standard 20 pin IDC JTAG connector Trace-probe connector for up to 16 bit wide tracing Test-points for internal signals 1.3 Kit contents MCU PCB and Trace-PCB mounted as a single module. UG-9E0008-13 -6- © Fujitsu Semiconductor Europe GmbH EMA-MB9DF120-001 User Guide Chapter 2 Hardware 2 Hardware 2.1 PCB Overview 2.1.1 MCU-Board This is mounted under the trace-board. For normal operation, there is no need to unmount both boards to access jumpers. etc. 2.1.1.1 Top-View A B C D E F G H I J K L M N O P Q R 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 A B C D E F G H I J K L M N O P Q R U3: MCU – MB9DF126 (Atlas) Series in PQFP296 package Q1: 32768Hz RTC-crystal (SubClk) Q3: 20MHz crystal for MainClk. © Fujitsu Semiconductor Europe GmbH -7- UG-9E0008-13 EMA-MB9DF120-001 User Guide Chapter 2 Hardware X2: APIX-connector (FW-4pin type). Testpoints. Soldering-jumpers for critical options. X1: B2B-connector to trace-board. 2.1.1.2 Bottom View A B C D E F G H I J K L M N O P Q R 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 A B C D E F G H I J K L M N O P Q R Q2: 4MHz alternate crystal. Should not be used (use 20MHz oscillator instead). R4, R5: Solder-Jumper to select 4MHz oscillator instead of default 20MHz. Only change for lowest power applications. UG-9E0008-13 -8- © Fujitsu Semiconductor Europe GmbH EMA-MB9DF120-001 User Guide Chapter 2 Hardware 2.1.2 Trace-Board This is mounted on top of the MCU-board. 2.1.2.1 Top-View A B C D E F G H I J K L M N O P Q R 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 A B C D E F G H I J K L M N O P Q R Jumpers to supply power to the MCU-board (MCU must be supplied from the target-board if disconnected). Indicator-LEDs for power-supply domains and reset. X2: external DC-Plug for 5V/1A AC-adapter. X4, X5: ARM-standard trace-headers for up to 32 bit tracing (only 16 bits used for Atlas). X3: ARM-standard 20pin IDC connector for JTAG-interface. © Fujitsu Semiconductor Europe GmbH -9- UG-9E0008-13 EMA-MB9DF120-001 User Guide Chapter 2 Hardware 2.1.2.2 Bottom-View A B C D E F G H I J K L M N O P Q R 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 A B C D E F G H I J K L M N O P Q R X1: B2B-connector to MCU-board. 2.2 Module Stack The EMA-MB9DF120-001 is actually a dual-PCB module which consists of the MCU-board and a trace-interface board. Both can be treated as a single module; there is no need for most applications to disassemble the PCBs. The MCU-board includes the trace version of the MB9DF126 (Atlas) >microcontroller along with some vital components which cannot be left on the target-PCB due to special signal requirements and/or noise (APIX, crystal oscillators). All other signals are routed to a bottom receptacle which fits into a mating header on the targetboard. This allows for (almost) 100% replacement of the target-CPU. However, there may be some restrictions on signal quality and/or data-rate due to the increased routing lengths and nonoptimal matching. See section APIX for the most restricted issue. UG-9E0008-13 - 10 - © Fujitsu Semiconductor Europe GmbH EMA-MB9DF120-001 User Guide Chapter 2 Hardware The JTAG-interface for debugging can be connected to the target-board, allowing the use of customer-specific connectors. Alternatively, a standard ARM JTAG-connector is available on the module which can be used alternatively to the trace-connector. The selection betwen both variants is done by a jumper which controls bus-switches. The trace-board also provides access to the trace-interface (along with the JTAG-signals) through an ARM standard connector. In addition, the trace-board provides a power-supply for stand-alone operation. If not used, some jumpers must be changed to disconnect the on-board power supply from the MCU voltage domains. However, power to the JTAG- and trace connectors still comes from the on-board regulators. 2.3 Power Supply The power supply circuit consists of the input-stage and a dual-channel step-down (buck) switching regulator. Power-cycling, power-down, etc. is not supported by the design. 2.3.1 Input-stage The power input consists of a standard DC-plug for a wall-cube adapter. It requires a 5.0V/1A ACadaptor. The (inner) 2.1mm pin must provide the positive potential and the ring GND. Care must be taken not to exceed the absolute maximum input voltage of 6V, otherwise the regulator might be damaged. Protection diodes and a ferrite-bead protect against reverse polarity (unlimited) and high voltage spikes (not permanent or periodic overvoltages allowed!) and also provide EMC. 2.3.2 Buck Regulator The dual channel switch-mode voltage regulator gets its input voltage either from the input stage (external supply), or from the VDP5 power domain which must then be driven from the target system. With the necessity to power the debug-connectors, a sufficient, permanent supply on either source is required. If VDP5 is operating at 3.3V, the regulator operates in 100% mode, connecting the input to the output, thus providing 3.3V at its 3V3 output. The 1V2 rail is enabled after the 3V3 rail is up, so proper power-sequencing is guaranteed. Both rails are designed to drive only the EMA-MB9DF120-001. They are not intended to power external components like the target-board. 2.3.3 Power Distribution Four jumpers are available to connect the on-board supply-rails to the MCU's power domains. While the 1V2 rail only connects to the MCU_VDD domain, the 3V3-rail can be connected to MCU_VDP3, MCU_VDP5 and MCU_DVCC. For the latter two, 5V operation is not supported by the on-board power supply. However, if target-power is used, they can also work with 5V (with the restrictions given by the MB9DF126 (Atlas) datasheet. All domains are supplied through filters to keep noise-levels low. If the MCU is to be supplied from the target-system, the jumpers on the trace-board must be opened. Otherwise reverse-current may flow into the regulator, destroying the device. For the ADC-supplies, additional jumpers allow to connect them separately to the related MCUdomains. All jumpers can also be used to measure the current of the domain. © Fujitsu Semiconductor Europe GmbH - 11 - UG-9E0008-13 EMA-MB9DF120-001 User Guide Chapter 2 Hardware 2.3.4 Debug-Supply Both connectors JTAG and trace require an on-board 3.3V supply at least to drive the internal buffers. This is also required to drive the level-limiters/switches which protect the JTAG-signals on the trace-board from 5.0V-levels if MCU_VDP5 is driven with 5.0V . To archive this, if supply from the target-board is chosen, JP19 must be set to 1-2, thus powering the 3V3 power regulator from the MCU_VDP5 domain. 2.3.5 Power-Domain Monitors (LEDs) Each power-domain has its own LED-indicator. For the 1V2 rail, the LED is driven from the VDP3 rail and just switched from the 1V2 rail. This guarantees the min. required Voltage-drop of 1.82.0V at the LED. All rails are additionally monitored by a system-voltage supervisor. 2.3.6 Reset Two sources for reset exist on the module: Either from one of the debug-interfaces, or from the on-board system-voltage-supervisor (SVS) for the 1V2 and 3V3 rails. Both can be disabled independently by pulling a jumper. If target-supply is used, it may be good to disconnect the SVS, as the status of the on-board supply has no effect on the MCU. Another reset-source is the target-board. This may be used from normal operation. 2.4 MCU Clocks 2.4.1 Main Clock The MCU is clocked using its internal 4-20MHz (Q3) oscillator by default. If the APIX is used, 20MHz must be applied, otherwise any crystal in the valid range can be used. The default crystal is a 20MHz-Version to provide full functionality. The second oscillator at Q2 is mostly for special applications and should not be used without contact from Fujitsu It can be selected by changing the solder-jumper R4/R5. 2.4.1.1 Sub-Clock (RTC-Clock) Q1 is a 32.768kHz crystal connected to the MCU's real-time clock oscillator. This clock is used to track time, while the other crystal oscillator is disabled. 2.5 On-Board Peripherals The board provides only one peripheral, the APIX, as the rest can be used on the underlying PCB. 2.5.1 APIX The MB9DF126 (Atlas) provides a dedicated PHY with separate pads for the APIX high-speed serial interface. The signals are routed to a 4-pin Firewire connector allowing standard twistedpair cable to be used. Although the signals can also be routed to the default pin-out on the target, it is strongly recommended to use only the on-board connector, because the routing to the targetsocket is not guaranteed to match signal-impedance or length or any other critical electrical parameters. UG-9E0008-13 - 12 - © Fujitsu Semiconductor Europe GmbH EMA-MB9DF120-001 User Guide Chapter 2 Hardware 2.6 Target Connector Connection to the target-system is done by a header/footer which provide the standard QFP176 pin-out of the Atlas-Chip. 2.7 Debugging Facilities The trace-board of the EMA-MB9DF120-001 provides a JTAG-Interface on a 20-pin 2.54mm (0.1in) IDC-header (X3) for debugging. The header uses the standard ARM pin-out. The second facility is a ARM-standard trace-connector. Although there are two connectors available, forming a 32-bit trace-bus, only the lower 16 bits are supported by the Atlas trace-chip, so connecting to X4 is sufficient, X5 can be ignored for the Atlas configuration (the trace-board is used by other devices, like Calypso-EMA, which provide 32-bit tracing, too). The trace-connector also handles the JTAG signals, so only one connector (X3 or X4) may be used at the same time. Debugging requires a proper interface and corresponding software on the host system. © Fujitsu Semiconductor Europe GmbH - 13 - UG-9E0008-13 EMA-MB9DF120-001 User Guide Chapter 3 Installation 3 Installation 3.1 First Contact After opening the box, please check first if all parts are included. If any parts are missing, ask your vendor. The kit includes electrostatic sensitive devices. Unpacking should be done in an anti-static environment. After removing the packing-material, check all parts and especially the PCBs and targetconnectors for damages. Also check the jumper-settings before initial powering up the board. 3.2 Engage First very carefully mount the EMA on top of the target-connector. This requires a good eye and some dexterity. Also double-check the orientation (the cut-edge marks the pin 1-position of the Atlas-device). After proper mounting, and with all jumpers set correctly, the target can be powered up and the MCU should operate as normally. For the main-task of debugging/tracing, connect the traceadapter to the X4 before powering up. 3.3 Lifesigns While powered, the LEDs on the trace-board signal the availability of the MCU power-domains. An LED is lit if the corresponding domain is powered. The reset-LED is active if the reset-signal is driven. If it is permanently lit, either the on-board 3V3-rail is not powered, or the MCU_VDD-domain is below the reset-threshold of ~1.1V. See section 4.1 for details. If the reset-LED flashes from time to time (maybe with a constant frequency), check if the powersupply used can satisfy the current requirements and measure the voltages on the power-rails. Most times this occurs, one or multiple power-rails are at the edge of the SVS' trigger-level and drop below, eg. if more current is drawn by a device. UG-9E0008-13 - 14 - © Fujitsu Semiconductor Europe GmbH EMA-MB9DF120-001 User Guide Chapter 4 Configuration and Test-Points 4 Configuration and Test-Points 4.1 Target-Supply Issues The EMA-MB9DF120-001 can either be self-supplied from an AC-adaptor, or get its internal supplies from the target-board. For the first, the power-distribution-jumpers must be closed and the DC-input must be selected as the buck-regulator input (JP19 to 2-3). As the module is not designed to supply power to the target-this is mostly for stand-alone operation and testing. When target-supply is used, the power-distribution jumpers have to be pulled (opened). Power is now drawn from the MCU power-pins on the target-board. As the buck-regulator is still used to supply the JTAG-facilities (external interfaces and on-board switches), it always must be powered. Although it is possible to use the external power supply, by selecting VDP5 as the input to the buck-regulator (JP19 to 1-2), the additional AC-adaptor can be omitted. As a drawback, the VDP5 domain has to supply some extra mA of current. Additionally, there are some issues with the reset-signal. The on-board supervisor monitors the internal 3V3 rail (which is the always required voltage rail for the EMA) and MCU_VDD. For stand-alone operation, this is sufficient, as these are the only two MCU supplies. For targetsupply, however, VDP3, VDP5, DVCC can be separate domains with different voltage-levels. As for any normal design, these rails have to be supervised from the target-board by a proper device and the EMA's on-board SVS can be disconnected from RST_X. 4.2 Target-Debugging While the trace signals are only available on the trace-board of the EMA, the JTAG-port can be accessed either from the EMA, or the target-board. Jumper JP8 selects which of the two ports is connected to the MCUs JTAG-signals. If it is open, both ports are disabled. 4.3 Jumpers The EMA-MB9DF120-001 provides multiple options to access signals and configure its properties. For this, it has two variants of jumpers. (regular) Jumpers consist of two or three pin-headers and a small cap. They can be changed without extra tools. They are used where changes are likely to occur. Wide jumpers (W) use a 2.54mm raster, while small jumpers use 2.00mm . The former are used for power-connections where also measuring may be required, while the latter are sole configuration jumpers. solder-jumpers change more basic options, the vast majority of applications do not require changing them from their defaults. A solder-jumper is either a single 0R0 resistor or two resistors of which only one may be placed. For the latter, a shared pad is often used to avoid placing both resistors accidentally. For the APIX, also some capacitors are used as jumpers. © Fujitsu Semiconductor Europe GmbH - 15 - UG-9E0008-13 EMA-MB9DF120-001 User Guide Chapter 4 Configuration and Test-Points Name Label Description Type Default Position AVDD connect ADC-supply: closed = MCU_VDP5 open = from target-board. Caution: the ADC is an analog subsystem and therefore sensitive to noise induced from the power-supply lines. 2-pin small open top B-1/2 AVRH connect ADC reference: closed = MCU_VDP5 open = from target-board. Caution: the ADC is an analog subsystem and therefore sensitive to noise induced from the power-supply lines. 2-pin small open top C-1/2 JP5 AVSS connect ADC GND: closed = EMA-GND open = from target-board. Caution: the ADC is an analog subsystem and therefore sensitive to noise induced from the power-supply lines. 2-pin small open top C/D-1/2 JP7 VDP5 select VDP5 supply-rail: closed = 3V3 (3.3V on-board rail) open = from target 2-pin small open top H-4/5 JP6 DVCC select DVCC supply-rail: closed = 3V3 (3.3V on-board rail) open = from target 2-pin small open top H/I-4/5 JP4 VDP3 select VDP3 supply-rail: closed = 3V3 (3.3V on-board rail) open = from target 2-pin small open top I/J-4/5 JP1 VDD select VDD supply-rail: closed = 1V2 (1.2V on-board rail) open = from target 2-pin small open top J-4/5 PWR_SRC select buck-regulator source: 1-2 = VDP5 (target-supply) 2-3 = external AC-adapter open = illegal 3-pin small 1-2 top R-4/5 JP17 MODE mode-pin level: closed = GND open = factory testing only This signal is for testing. 2-pin small closed top A/B-1/2 JP8 JTAG_SEL select JTAG access: 1-2 = target board 2-3 = trace-board 3-pin small 2-3 top N/O-5 RTCK-sel enable/disable RTCK on JTAG: 1-2 = disable (pulled to GND) 2-3 = enable open = invalid see also solder-jumper R6 3-pin small 1-2 top I-9:11 T_RST enable reset from trace and debugconnectors: closed = enables reset from trace/debug open = no reset from trace/debug Quite likely not to be changed. 2-pin small closed top N-2/3 The following jumpers are all located on the trace-board. JP2 JP3 JP19 JP14 JP9 UG-9E0008-13 - 16 - © Fujitsu Semiconductor Europe GmbH EMA-MB9DF120-001 User Guide Chapter 4 Configuration and Test-Points Name Label Description Type Default Position JP18 PWR_RST enable reset from SVS: closed = SVS can generate reset open = SVS cannot generate reset 2-pin small open top B-6 The following solder-jumpers are all on the MCU-board of the module VOSC Oscillator supply: R11 = MCU_VDP5 R12 = from target solder, 2R R11 bot G-3/4 APX_VCC12 APIX 1.2V supply: R13 = MCU_VDD R14 = from target solder, 2R Caution: the APIX is an analog subsystem and therefore sensitive to noise induced from the power-supply lines. R13 bot B-6/7 R15/R16 APX_VCC3 APIX 3.3V supply: R15 = MCU_VDP3 R16 = from target solder, 2R Caution: the APIX is an analog subsystem and therefore sensitive to noise induced from the power-supply lines. R15 bot C/D-9/10 R4/R5 OSC_SEL select main oscillator: R4 = 4-20MHz osc (for APIX) R5 = 4MHz osc (low-power) solder, 2R R4 bot E-5/6 RTCKfb JTAG-RTCK feedback: closed = return TCK as RTCK open = disconnect RTCK RTCK must also be enabled on the traceboard to be routed properly. solder, R open top L/M-13/14 solder, 4x2C right-side bot D/E-7/8, top C/D-8/9 R11/R12 R13/R14 R6 APIX data-lines select (all 100nF): C64/C18, C65/C19, C67/C37, C66/C62 4.4 left-side caps = from target right-side caps = from on-board connector APIX_SEL Always replace as a whole block The target-connection is only for experimentation. The signals are not guaranteed to work properly at any data-rate. Headers There are no headers on this module. © Fujitsu Semiconductor Europe GmbH - 17 - UG-9E0008-13 EMA-MB9DF120-001 User Guide Chapter 4 Configuration and Test-Points 4.5 Test-Points Testpoints are not for permanent connection, but mostly for failure-tracking. Normally, there is no need to access them. They are all located on the MCU-board. Name Label Description Position TP1 SubClk input of 32768Hz crystal-oscillator (RTC, etc.). top C-12 TP2 MainClk 4MHz crystal clock bot D/E-5/6 TP3 APIXClk 4-20MHz crystal clock (primary oscillator) top C-10 TP4 SYSC_CKOT MCU-port P0_41 which can have this signal multiplexed on its output. top F/G-14 TP5 SYSC_CKOTX MCU-port P0_42 which can have this signal multiplexed on its output. top G-14 TP6 RTC_WOT MCU-port P0_40 which can have this signal multiplexed on its output. top F-14 TP7 WDG_OBSERVE MCU-port P0_43 which can have this signal multiplexed on its output. top G/H-14 The crystal testpoints TP1-3 are very sensitive to noise and load-factors, especially capacitive loads can change the frequency dramatically. If possible, the clocks should be measured indirectly using a high-speed timer or SYSC_CKOT. UG-9E0008-13 - 18 - © Fujitsu Semiconductor Europe GmbH EMA-MB9DF120-001 User Guide Chapter 5 Status Display 5 Status Display For user information, there are four LEDs on the trace-board. Each power-domain is monitored by a single LED. In addition, the reset-LED shows the status of the reset-line. For the default configuration and no external reset (JTAG, button or from a plugged-under PCB), this is the status of the systemvoltage supervisor (SVS). It will be lit if any voltage domain is out of limits. Name Color Description (when lit) Position LD1 orange MCU_DVCC domain up top B/C-11 LD2 orange MCU_VDP5 domain up top B/C-10/11 LD3 yellow MCU_VDP3 domain up top B/C-10 LD4 green MCU_VDD domain up (driven by trace-board 3V3 rail) top B/C-9/10 LD5 red reset active (driven by trace-board 3V3 rail) top B/C-9 © Fujitsu Semiconductor Europe GmbH - 19 - UG-9E0008-13 EMA-MB9DF120-001 User Guide Chapter 6 Connectors 6 Connectors The following table lists the location of all connectors on the boards. The pin-out of each connector is listed in separate sections. 6.1 MCU-Board Name Type Description Position U2 Receptacle Target-Board connector. Requires matching header. bot F:M-5:12 X1 0.8mm 2*40pin Connector to the trace-board top P:R-2:14 X2 Firewire 4pin Receptacle APIX-Interface connector. top A:C-2:6 6.1.1 APIX Connector (X2) Pin Signal Description 1 2 3 4 Shield SDINM SDINP SDOUTM SDOUTP Shield Serial Input, negative Serial Input, positive Serial Output, negative Serial Output, positive Tied to GND via 1M0||100nF This is actually a 4-pin Firewire-connector, so a crossover FW-cable can be used to connect two stations. 6.2 Trace-Board Name Type Description Position X1 0.8mm 2*40pin Connector to the MCU-board bot E:O-1:3 X3 2*10 2.54mm IDC header (male) Standard ARM 20pin debug-header with JTAG-interface. Must not top E:M-11:13 be connected at the same time as X3. X4,X5 TYCO 5767054-1 38pin connector for standard ARM trace interface (32 bits). Includes also JTAG. Must not be connected at the same time as X3. Atlas only uses X4. top A:Q-6:8 X2 DC-plug 2.1mm pin DC plug for external power-supply. top N:R-9:12 UG-9E0008-13 - 20 - © Fujitsu Semiconductor Europe GmbH EMA-MB9DF120-001 User Guide Chapter 6 Connectors 6.2.1 Debug Connector (X3) This is an ARM-standard 20 pin JTAG connector. Pin Signal Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Vsns VCCt nTRST GND TDI GND TMS GND TCK GND RTCK GND TDO GND nRESET GND DBREQ GND TVcc GND Target voltage reference Target power JTAG TAP reset, active low Ground JTAG Test Data In Ground JTAG Test Machine State Ground JTAG TAP Clock Ground Return TCK (optional) Ground JTAG Test Data Out Ground Target reset, active low (system reset) Ground Debug Request (not used) Ground Debug Acknowledge (not used) Ground RTCK is deactivated by jumpers by default. It is only required for high-speed clocking. See jumper-settings on how to enable this functionality. This connector must not be used at the same time as the trace-connector. © Fujitsu Semiconductor Europe GmbH - 21 - UG-9E0008-13 EMA-MB9DF120-001 User Guide Chapter 6 Connectors 6.2.2 Trace Connectors (X4, X5) Much like the Debug-connector, this is also defined by ARM. These connectors must not be used at the same time as the debug-connector. 6.2.2.1 Primary Trace-Connector (X4) This can be used without X5, providing an up to 16-bits trace-port. Pin Signal Description 1-4, 10 5, 30, 32 14, 34 12 6 7 8 9 11 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 33 35 36 37 38 NC GND VSUPPLY VTREF TRACECLK DBREQ DBACK nRESET TDO RTCK TCK TRACE7 TMS TRACE6 TDI TRACE5 nTRST TRACE4 TRACE15 TRACE3 TRACE14 TRACE2 TRACE13 TRACE1 TRACE12 TRACE11 TRACE10 TRACE9 TRACECTL TRACE8 TRACE0 No connection Signal Ground Voltage Supply pin Target reference voltage Trace Clock pin Probe Debug Request (unused) Probe Debug Acknowledge (unused) Target reset, active low JTAG Test Data Out JTAG Return TCK (optional) JTAG TAP Clock Trace data JTAG Test Machine State Trace data JTAG Test Data In Trace data JTAG TAP Reset, active low Trace data Trace data Trace data Trace data Trace data Trace data Trace data Trace data Trace data Trace data Trace data Trace Control Trace data Trace data UG-9E0008-13 - 22 - © Fujitsu Semiconductor Europe GmbH EMA-MB9DF120-001 User Guide Chapter 6 Connectors For the JTAG-signals see section 6.2.1 for details. 6.2.2.2 Extension Trace-Connector (X5) This connector extends the trace-bus width to 32 bits. It is the same type as X5. For the Atlas, this connector is not used. Pin Signal Description 1-4, 6-11, 13-15, 17, 19, 21 5, 30, 32, 36 34 12 16 18 20 22 23 24 25 26 27 28 29 31 33 35 37 38 NC No connection GND Signal Ground VSUPPLY VTREF TRACE23 TRACE22 TRACE21 TRACE20 TRACE31 TRACE19 TRACE30 TRACE18 TRACE29 TRACE17 TRACE28 TRACE27 TRACE26 TRACE25 TRACE24 TRACE16 Voltage Supply pin Target reference voltage Trace data Trace data Trace data Trace data Trace data Trace data Trace data Trace data Trace data Trace data Trace data Trace data Trace data Trace data Trace data Trace data 6.3 DC In Plug (X2) The following figure shows the power connection plug. This connector is used to connect an external DC power supply with 5V0/1.5A DC to the EMA-MB9DF120-001. Observe the polarity of the power-supply lines. Connector X2: Shield is connected to GND (-) + Center is connected to positive voltage supply (+) Figure 6-1: Power connector connection scheme © Fujitsu Semiconductor Europe GmbH - 23 - UG-9E0008-13 EMA-MB9DF120-001 User Guide Chapter 6 Connectors 6.4 Target Header (U5) The target header, a receptacle fitting onto the target board’s associated footer is placed on the bottom side of the Emulator Board. The footer has the same FPT-176P-M07 footprint as the target MCU and needs to be soldered to the target board (please obey dimensions sketched in the drawings in chapter 7) for direct interconnection of target board pins and the Emulator Board. Regarding electrical connection, corresponding pins are linked to equivalent Atlas port pins one by one. When mounting the Emulator Assembly to the target board pin 1 is indicated by a cut edge on the Emulator Board, align guide pins support the right placement. Firmly, but carefully press the receptacle onto the footer. Figure 6-2: Receptacle U2 location and pin assignment UG-9E0008-13 - 24 - © Fujitsu Semiconductor Europe GmbH EMA-MB9DF120-001 User Guide Chapter 7 Layout Guidelines for Target Board 7 Layout Guidelines for Target Board 7.1 Emulator Assembly Stack-up The dimensions indicated in the following drawings have to be observed when designing your target board: Figure 7-1: Emulator Assembly Stack-up dimensions © Fujitsu Semiconductor Europe GmbH - 25 - UG-9E0008-13 EMA-MB9DF120-001 User Guide Chapter 7 Layout Guidelines for Target Board Figure 7-2: Emulator Footer drawing 7.2 Target Board Recommendations Power requirements the Emulator Assembly have to be met. In addition to the target board requirements, at least 1A for VDD (1.2V) and 500mA for VDP3, VDP5 and DVDD should be available. All Power pins described in 4.3 ‘Target header’ should be used not only to compensate for target headers contact resistances. No extensive filtering is done on the Emulator Board with the exception of analogue supply voltages AVDD5, AVSS5 and AVRH5, Filters must be provided on the target board. UG-9E0008-13 - 26 - © Fujitsu Semiconductor Europe GmbH EMA-MB9DF120-001 User Guide Chapter 8 Trouble shooting 8 Trouble shooting © Fujitsu Semiconductor Europe GmbH - 27 - UG-9E0008-13 EMA-MB9DF120-001 User Guide Chapter 9 Related Products 9 Related Products SK-MB9EF120-002 Calypso MCU starterkit SK-MB9DF120-001 Atlas MCU starterkit ADA-FCR4-MULTIIO-001 Base board for using of MCU board with several IO interfaces like CAN, LIN, MediaLB, Ethernet, Video and Audio accessing ADA-FCR4-CLUSTER-001 Automobile dashboard sample with stepper-motors and other functions. Information on the Web UG-9E0008-13 - 28 - © Fujitsu Semiconductor Europe GmbH EMA-MB9DF120-001 User Guide Chapter 10 Information in the WWW 10 Information in the WWW Information about FUJITSU SEMICONDUCTOR Products can be found on the following Internet pages: Microcontrollers (8-, 16- and 32bit), Graphics Controllers Datasheets and Hardware Manuals, Support Tools (Hard- and Software) http://mcu.emea.fujitsu.com/ Power Management Products http://www.fujitsu.com/emea/services/microelectronics/powerman/index.html For more information about FUJITSU SEMICONDUCTOR http://emea.fujitsu.com/semiconductor Information about and software drivers for the peripheral devices used on the starter kit can be found on the following Internet pages: ARM architecture and software development tools http://infocenter.arm.com USB to serial converter http://www.ftdichip.com Power Supply and Monitoring http://www.linear.com http://www.national.com CAN transceiver http://www.infineon.com © Fujitsu Semiconductor Europe GmbH - 29 - UG-9E0008-13 EMA-MB9DF120-001 User Guide Chapter 10 Information in the WWW Quartz Crystal Units http://www.ndk.com http://www.microcrystal.ch Flash Memory http://www.spansion.com UG-9E0008-13 - 30 - © Fujitsu Semiconductor Europe GmbH EMA-MB9DF120-001 User Guide Chapter 11 EU-Konformitätserklärung / EU declaration of conformity 11 EU-Konformitätserklärung / EU declaration of conformity Hiermit erklären wir, Fujitsu Semiconductor Europe GmbH, Pittlerstrasse 47, 63225 Langen, Germany dass dieses Board aufgrund seiner Konzipierung und Bauart sowie in den von uns in Verkehr gebrachten Ausführung(en) den grundlegenden Anforderungen der EU-Richtlinie 2004/108/EC „Elektromagnetische Verträglichkeit“ entspricht. Durch eine Veränderung des Boards (Hard- und/ oder Software) verliert diese Erklärung ihre Gültigkeit! We, Fujitsu Semiconductor Europe GmbH, Pittlerstrasse 47, 63225 Langen, Germany hereby declare that the design, construction and description circulated by us of this board complies with the appropriate basic requirements according to the EU Guideline 2004/108/EC entitled ’Electro-Magnetic Compatibility’. Any changes to the equipment (hardware and/ or software) will render this declaration invalid! Note: All data and power supply lines connected to this starter kit should be kept as short as possible, with a maximum allowable length of 3m. Shielded cables should be used for data lines. As a rule of thumb, the cable length used when connecting external circuitry to the MCU pin header connectors for example should be less than 20cm. Longer cables may affect EMC performance and cause radio interference. This evaluation board is a Class A product according to EN61326-1. It is intended to be used only in a laboratory environment and might cause radio interference when used in residential areas. In this case, the user must take appropriate measures to control and limit electromagnetic interference. © Fujitsu Semiconductor Europe GmbH - 31 - UG-9E0008-13 EMA-MB9DF120-001 User Guide Chapter 12 China-RoHS regulation 12 China-RoHS regulation This board is compliant with China RoHS. UG-9E0008-13 - 32 - © Fujitsu Semiconductor Europe GmbH EMA-MB9DF120-001 User Guide Chapter 13 Recycling 13 Recycling Gültig für EU-Länder: Gemäß der Europäischen WEEE-Richtlinie und deren Umsetzung in landesspezifische Gesetze nehmen wir dieses Gerät wieder zurück. Zur Entsorgung schicken Sie das Gerät bitte an die folgende Adresse: Fujitsu Semiconductor Europe GmbH Warehouse/Disposal Monzastraße 4a D-63225 Langen Valid for European Union Countries: According to the European WEEE-Directive and its implementation into national laws we take this device back. For disposal please send the device to the following address: Fujitsu Semiconductor Europe GmbH Warehouse/Disposal Monzastraße 4a D-63225 Langen GERMANY -- END -- © Fujitsu Semiconductor Europe GmbH - 33 - UG-9E0008-13