CY2CC910 1:10 Clock Fanout Buffer 1:10 Clock Fanout Buffer Features ■ Industrial temperature range ■ Available in SSOP package ■ Low voltage operation ■ Full range support: ❐ 3.3 V ❐ 2.5 V ❐ 1.8 V Functional Description ■ Over voltage tolerant input hot swappable ■ 1:10 Fanout ■ Drives either a 50-Ohm or 75-Ohm load The Cypress CY2CC910 fanout buffer features one input and 10 outputs. It is ideal for conversion from and to 3.3 V, 2.5 V, and 1.8 V ■ Low input capacitance ■ Low output skew ■ Low propagation delay ■ Typical (tpd less than 4 ns) ■ High speed operation: ❐ 200 MHz at1.8 V ❐ 650 MHz at 2.5 V and 3.3 V The Cypress series of network circuits are produced using advanced 0.35 micron CMOS technology, achieving the industry’s fastest logic and buffers. Designed for Data Communications clock management applications, the large fanout from a single input reduces loading on the input clock. For a complete list of related documentation, click here. Logic Block Diagram 3 5 7 VDD 9 4 ,8 1 5 ,2 0 11 IN 1 12 INPUT (AVCMOS) 2 ,6 ,1 0 1 3 ,1 7 14 16 GND 18 19 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q 10 OUTPUT (AVCMOS) Cypress Semiconductor Corporation Document Number: 38-07348 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 20, 2014 CY2CC910 Contents Pin Configuration ............................................................. 3 Pin Description ................................................................. 3 Maximum Ratings ............................................................. 4 DC Electrical Characteristics .......................................... 4 DC Electrical Characteristics .......................................... 4 DC Electrical Characteristics .......................................... 5 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 Power Supply Characteristics ......................................... 5 High Frequency Parametrics ........................................... 6 AC Switching Characteristics ......................................... 7 AC Switching Characteristics ......................................... 7 AC Switching Characteristics ......................................... 7 Parameter Measurement Information: VDD at 3.3 V to 2.5 V ......................................................... 8 Document Number: 38-07348 Rev. *I Parameter Measurement Information: VDD at 8 V ......................................................................... 9 Ordering Information ...................................................... 10 Ordering Code Definitions ......................................... 10 Package Diagram ............................................................ 11 Acronyms ........................................................................ 12 Document Conventions ................................................. 12 Units of Measure ....................................................... 12 Document History Page ................................................. 13 Sales, Solutions, and Legal Information ...................... 14 Worldwide Sales and Design Support ....................... 14 Products .................................................................... 14 PSoC®Solutions ....................................................... 14 Cypress Developer Community ................................. 14 Technical Support ..................................................... 14 Page 2 of 14 CY2CC910 Pin Configuration IN GND Q1 VDD Q2 GND Q3 VDD Q4 GND 1 2 3 4 5 6 7 8 9 10 CY2CC910 Figure 1. 20-Pin SOIP/SSOP pinout 20 19 18 17 16 15 14 13 12 11 VDD Q10 Q9 GND Q8 VDD Q7 GND Q6 Q5 20 pin SOIC/SSOP Pin Description Pin Number Pin Name Description 1 IN Input 2,6,10,13,17 GND VDD Ground 4,8,15,20 3,5,7,9,11,12,14,16,18,19 Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10 Output Document Number: 38-07348 Rev. *I Power Supply Page 3 of 14 CY2CC910 Maximum Ratings VCC .................................................................–0.5 V to 4.6 V Exceeding maximum ratings[1] may shorten the useful life of the device. User guidelines are not tested. Input................................................................–0.5 V to 5.8 V Supply voltage to ground potential Storage temperature:................................ –65C to +150C (Outputs only) ......................................... –0.5 V to VDD + 1 V Ambient temperature: ................................. –40C to +85C DC output voltage................................... –0.5 V to VDD + 1 V Supply voltage to ground potential Power dissipation ....................................................... 0.75 W DC Electrical Characteristics At 3.3 V (See Figure 2) Parameter Description Conditions Min Typ 2.3 3.3 Max Unit 0.5 V 5.8 V VOH Output high voltage VDD = Min, VIN = VIH or VIL IOH = –12 mA VOL Output low voltage VDD = Min, VIN = VIH or VIL IOL = 12 mA VIH Input high voltage Guaranteed Logic High Level VIL Input low voltage Guaranteed Logic Low Level 0.8 V IIH Input high current VDD = Max VIN = 2.7 V 1 A IIL Input low current VDD = Max VIN = 0.5 V –1 A II Input high current VDD = Max, VIN = VDD(Max) 20 A VIK Clamp diode voltage VDD = Min, IIN = –18 mA IOK Continuous clamp current VDD = Max, VOUT = GND OOFF Power-down disable VDD = GND, VOUT = < 4.5 V VH Input hysteresis 0.2 2 –0.7 V –1.2 V –50 mA 100 80 A mV DC Electrical Characteristics At 2.5 V (See Figure 2) Parameter Description Conditions Min VOH Output high voltage VDD = Min, VIN = VIH or VIL IOH = –7 mA 1.8 IOH = 12 mA 1.6 VOL Output low voltage VDD = Min, VIN = VIH or VIL IOL = 12 mA VIH Input high voltage Guaranteed Logic High Level VIL Input low voltage Guaranteed Logic Low Level Typ Max Unit V V 0.65 1.6 V 5.0 V 0.8 V IIH Input high current VDD = Max VIN = 2.4 V 1 A IIL Input low current VDD = Max VIN = 0.5 V –1 A II Input high current VDD = Max, VIN = VDD(Max) VIK Clamp diode voltage VDD = Min, IIN = –18 mA IOK Continuous clamp current OOFF Power down disable VH Input hysteresis 20 A –1.2 V VDD = Max, VOUT = GND –50 mA VDD = GND, VOUT = < 4.5 V 100 A –0.7 80 mV Note 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Document Number: 38-07348 Rev. *I Page 4 of 14 CY2CC910 DC Electrical Characteristics At 1.8 V (See Figure 6) Parameter Description Test Condition[2] VDD Supply voltage VIH Input high voltage VIL Input low voltage VOH Output high voltage IOH = –2 mA VOL Output low voltage IOH = 2 mA Min Max Unit 1.71 1.89 V 0.65 VDD[1.1] 4.3 V –0.3 0.35 VDD[0.6] V VDD – 0.45[1.2] V 0.45 V Capacitance Parameter Description Test Conditions Typ Max Unit CIN Input capacitance VIN = 0 V 2.5 pF COUT Output capacitance VOUT = 0 V 6.5 pF Thermal Resistance Parameter [3] Description θJA Thermal resistance (junction to ambient) θJC Thermal resistance (junction to case) Test Conditions 20-pin SSOP Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 79 °C/W 35 °C/W Power Supply Characteristics (See Figure 2) Parameter Description Test Conditions ICC Delta ICC Quiescent Power Supply Current (IDD @ VDD = Max and VIN = VDD) – (IDD @ VDD = Max and VIN = VDD – 0.6 V6 V) ICCD Dynamic power supply current VDD = Max Input toggling 50% Duty Cycle, Outputs Open IC Total power supply current VDD = Max Input toggling 50% Duty Cycle, Outputs Open fL = 40 MHZ Min Typ Max Unit 50 A 0.63 mA/ MHz 25 mA Notes 2. Test load conditions: 500-Ohm to ground with approximately 6-pF total loading and 200-MHz maximum frequency. 3. These parameters are guaranteed by design and are not tested. Document Number: 38-07348 Rev. *I Page 5 of 14 CY2CC910 High Frequency Parametrics Max Unit DJ Parameter Jitter, Deterministic Description 50% duty cycle tW(50–50) The “point to point load circuit” | Output Jitter – Input Jitter | Test Conditions See Figure 4 Min Typ 20 ps Fmax 3.3 V Maximum frequency VDD = 3.3 V 50% duty cycle tW(50–50) Standard Load Circuit. See Figure 2 160 MHz 50% duty cycle tW(50–50) The “point to point load circuit” See Figure 4 650 Fmax 2.5 V Maximum frequency VDD = 2.5 V The “point-to-point load circuit” See Figure 4 VIN = 2.4 V/0.0 V VOUT = 1.7 V/0.7 V 200 MHz Fmax 1.8 V Maximum frequency VDD = 1.8 V The “6-pF load circuit” See Figure 6 VIN = 1.7/0.0 V VOUT = 1.2 V/0.4 V 200 MHz Fmax(20) Maximum frequency VDD = 3.3 V See Figure 5 20% duty cycle tW(20-80) The “point to point load circuit” VIN = 3.0 V/0.0 V VOUT = 2.3 V/0.4 V 250 MHz tW 3.3 V Minimum pulse VDD = 3.3 V The “point-to-point load circuit” VIN = 3.0 V/0.0 V F = 100 MHz VOUT = 2.0 V/0.8 V See Figure 4 1 ns tW 2.5 V Minimum pulse VDD = 2.5 V The “point-to-point load circuit” VIN = 2.4 V/0.0 V F = 100 MHz VOUT = 1.7 V/0.7 V See Figure 4 1 ns tW 1.8 V Minimum pulse VDD = 1.8 V The “6-pF load circuit” See Figure 6 VIN = 1.7 V/0.0 V VOUT = 1.2 V/0.4 V 1 ns Document Number: 38-07348 Rev. *I Page 6 of 14 CY2CC910 AC Switching Characteristics At 3.3 V (VDD = 3.3 V ± 5%, Temperature = –40C to +85C) Parameter Description tPLH Propagation delay – Low to High See Figure 3 Min Typ Max Unit 1.5 2.7 3.5 ns 2.7 3.5 tPHL Propagation delay – High to Low tR Output rise time 1.5 ns tF Output fall time tSK(0) Output Skew: Skew between outputs of the same package (in phase). See Figure 10 0.2 ns tSK(p) Pulse Skew: Skew between opposite transitions of the same output (tPHL – tPLH). See Figure 9 0.2 ns tSK(t) Package Skew: Skew between outputs of different packages at See Figure 11 the same power supply voltage, temperature and package type. 0.4 ns 0.8 V/ns 0.8 V/ns AC Switching Characteristics At 2.5 V (VDD = 2.5 V ± 5%, Temperature = –40 C to +85 C) Parameter Description tPLH Propagation delay – Low to High tPHL Propagation delay – High to Low Min See Figure 3 Typ Max Unit 1.5 2.7 3.5 ns 1.5 2.7 3.5 ns tR Output rise time 0.8 V/ns tF Output fall time 0.8 V/ns tSK(0) Output Skew: Skew between outputs of the same package (in phase). 0.2 ns tSK(p) Pulse Skew: Skew between opposite transitions of the same output (tPHL See Figure 9 – tPLH). 0.2 ns tSK(t) Package Skew: Skew between outputs of different packages at the same See Figure 11 power supply voltage, temperature and package type. 0.4 ns See Figure 10 AC Switching Characteristics At 1.8 V (VDD = 1.8 V ±5%, Temperature = –40C to +85C) Parameter Description Min Typ Max Unit 1.5 2.7 3.5 ns Propagation delay – High to Low 1.5 2.7 3.5 ns Output rise time 20 – 80% 0.2 1.5 ns 0.2 1.5 ns 0.2 ns Pulse Skew: Skew between opposite transitions of the same output (tPHL See Figure 9 – tPLH). 0.2 ns Package Skew: Skew between outputs of different packages at the same See Figure 11 power supply voltage, temperature and package type. 0.4 ns tPLH Propagation delay – Low to High tPHL tR tF Output fall time 20 – 80% tSK(0) Output Skew: Skew between outputs of the same package (in phase). tSK(p) tSK(t) Document Number: 38-07348 Rev. *I See Figure 7 See Figure 10 Page 7 of 14 CY2CC910 Parameter Measurement Information: VDD at 3.3 V to 2.5 V Figure 2. Load Circuit [3, 4, 5] Figure 4. Point to Point Load Circuit [3, 4, 5] From Output Under Test From Output Under Test C L = 50 pF 500 ohm CL = 3 pF Figure 3. Voltage Waveforms Propagation Delay Times [6] VDD/2 Input tPLH Output Figure 5. Voltage Waveforms – Pulse Duration [4] 0.8VDD VDD/2 0V 500 ohm tw(50-50) Input 0.8VDD VDD/2 VDD/2 tPHL VDD/2 Document Number: 38-07348 Rev. *I VDD/2 0V tw(20-80) VOH VOL Input 0.8VDD VDD/2 0V Page 8 of 14 CY2CC910 Parameter Measurement Information: VDD at 8 V Figure 6. Load Circuit [3, 4, 5] Figure 8. Voltage Waveforms – Pulse Duration [4] From Output Under Test tw(50-50) Input CL = 6 pF 1.8V 0.9V 0.9V 500 ohm 0V tw(20-80) Input 1.8V 0.9V 0V Figure 9. Pulse Skew - tsk(p) Figure 7. Voltage Waveforms Propagation 3V 1.8V 0.9V Input 0.9V tPLH Output 1.5V INPUT 0V tPHL 0.9V 0.9V tPHL tPLH 0V VOH 1.5V VOH OUTPUT VOL VOL tsk(P) = l tPHL - tPLH l Figure 10. Output Skew - tsk(0) 3V 1.5V INPUT 0V tPHL1 tPLH1 VOH 1.5V OUTPUT 1 tsk (O) tsk (O) VOL VOH 1.5V OUTPUT 2 tPLH 2 tsk (P) = tPLH 2 VOL l tPLH2 - tPLH1 l or tPHL2 - tPHL1 l Notes 3. CL includes probe and jig capacitance. 4. All input pulses are supplied by generators having the following characteristics: PRR < 100 MHz, Z0 = 50, tR < 2.5 ns, tF < 2.5 ns. 5. The outputs are measured one at a time with one transition per measurement. 6. TPLH and TPHL are the same as tpd. Document Number: 38-07348 Rev. *I Page 9 of 14 CY2CC910 Figure 11. Package Skew - tsk(t) 3V 1.5V INPUT 0V tPHL1 tPLH1 VOH 1.5V PACKAGE 1 OUTPUT tsk(t) VOL tsk(t) VOH 1.5V PACKAGE 2 OUTPUT tPLH 2 tsk(t) = VOL tPLH 2 l tPLH2 - tPLH1 l or tPHL2 - tPHL1 l Ordering Information Part Number Package Type Product Flow Pb-free CY2CC910OXI 20-pin SSOP Industrial, –40C to 85C CY2CC910OXIT 20-pin SSOP–Tape and Reel Industrial, –40C to 85C Ordering Code Definitions CY 2CC910 O X I T T = Tape and Reel, Blank = Tube Temperature Range: I = Industrial X = Pb-free O = 20 pin SSOP Base Part Number Company ID: CY = Cypress Document Number: 38-07348 Rev. *I Page 10 of 14 CY2CC910 Package Diagram Figure 12. 20-pin SSOP (210 Mils) O20.21 Package Outline, 51-85077 51-85077 *F Document Number: 38-07348 Rev. *I Page 11 of 14 CY2CC910 Acronyms Document Conventions Acronym Description Units of Measure CMOS complementary metal oxide semiconductor DJ deterministic jitter C degree Celsius SSOP shrunk small outline package MHZ megahertz uA microamperes Document Number: 38-07348 Rev. *I Symbol Unit of Measure mA milliamperes ms milliseconds ns nanoseconds % percent pF picofarads ps picoseconds V volt Page 12 of 14 CY2CC910 Document History Page Document Title: CY2CC910, 1:10 Clock Fanout Buffer Document No: 38-07348 Rev. ECN No. Orig. of Change Submission Date ** 114318 TSM 05/10/02 New data sheet *A 119148 RGL 10/07/02 Added 5.8 as the Max value for VIH in the DC Electrical Characteristics @3.3 V table. Changed the Max value of VIH from 5.8 to 5.0 in the DC Electrical Characteristics @2.5 V table. Changed the value of VIH from VDD+0.3 [2.25] to 4.3 in the DC Electrical Characteristics @1.8 V table. Description of Change *B 404287 RGL See ECN Added Lead-free devices for SSOP *C 2595534 CXQ / PYRS 10/23/08 Added “Status” column to Ordering Information table Updated Package Diagram 51-85024 Updated to new template. *D 2896073 CXQ 03/19/10 Removed SOIC packages related information in all instances across the document. Updated Ordering Information: Removed obsolete parts from ordering information table and added CY2CC910OXI-1, CY2CC910OXI-1T. Updated Package Diagram. *E 3056154 CXQ 10/08/2010 Updated Ordering Information: Removed CY2CC910OXI-1, CY2CC910OXI-1T, CY2CC910OXC, and CY2CC910OXCT parts. Removed the Note “Devices with part numbers ending with -1 are identical to devices without the -1 suffix. There are no differences in specification.” and its reference. *F 3411742 PURU 10/18/2011 Added Contents. Updated Functional Description: Removed “Cypress employs the unique AVCMOS type outputs VOI (Variable Output Impedance) that dynamically adjust for variable impedance matching, eliminate the need for series damping resistors, and reduce overall noise.” Removed “Variable Output Impedance Control (VOI)”. Updated Ordering Information Updated Package Diagram. Added Acronyms and Units of Measure. *G 4575136 TAVA 11/20/2014 Updated Functional Description: Added “For a complete list of related resources, click here.” at the end. Updated to new template. Completing Sunset Review. *H 4586288 TAVA 12/03/2014 Updated Functional Description: Replaced “resources” with “documentation”. *I 5272946 PSR 05/16/2016 Added Thermal Resistance. Updated Package Diagram: spec 51-85077 – Changed revision from *E to *F. Updated to new template. Document Number: 38-07348 Rev. *I Page 13 of 14 CY2CC910 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC®Solutions Products ARM® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers cypress.com/clocks Interface Lighting & Power Control cypress.com/interface cypress.com/powerpsoc Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/memory PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/psoc cypress.com/touch cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2002-2016. 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Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 38-07348 Rev. *I Revised November 20, 2014 Page 14 of 14