Freescale Semiconductor Document Number: AN4701 Rev. 0, 03/2013 Application Note Demodulating Communication Signals of Qi-Compliant Low-Power Wireless Charger Using MC56F8006 DSC by: Xiang Gao Contents 1 Introduction Wireless power is becoming more and more popular today, through which a number of electronic items like mobiles, laptops, media players, can be charged without cords or wires. It is beginning to show great potential in the consumer market. Wireless Power Consortium (WPC) has developed a standard called Qi, which defines the types of inductive coupling and the communications protocol to be used for lowpower wireless devices. Qi creates interoperability between the Power Transmitter and the Power Receiver. As a regular member of WPC, Freescale has its own Qi-compliant low-power wireless charger reference design for the customers now. 1 Introduction ......................................................1 2 Qi communication interface .............................2 3 4 Qi-compliant wireless devices use amplitudeshift keying (ASK) modulation to communicate 5 2.1 Modulation scheme...................................2 2.2 Bit encoding scheme .................................3 2.3 Byte encoding scheme ..............................4 2.4 Packet structure.........................................4 Demodulation circuit design .............................5 3.1 Voltage scale down circuit........................6 3.2 Rectify and DC filter circuit .....................7 3.3 Low-pass filter design...............................8 3.4 Comparator .............................................10 3.5 Voltage divider .......................................11 Demodulation software design .......................12 4.1 Preamble decoding scheme.....................13 4.2 Bit decoding scheme ...............................14 4.3 Byte decoding scheme ............................16 4.4 Packet decoding scheme .........................17 4.5 Overtime detection..................................18 Test Results and Conclusion...........................18 5.1 Test result ...............................................18 5.2 Conclusion ..............................................20 © Freescale Semiconductor Inc., 2013 _______________________________________________________________________ between Power Receiver and Power Transmitter. This application note aims to describe the Qi communication data demodulation design for wireless charger transmitter with MC56F8006 digital signal controller (DSC) including Qi communication interface, demodulation circuits design, and demodulation software design. 2 Qi communication interface Amplitude shift keying (ASK) is a relatively simple modulation scheme. ASK is equivalent to the amplitude modulation of the analog signal, and the carrier frequency signal is multiplied by a binary digital. The frequency and phase of the carrier are kept constant, and the amplitude is variable. Information bits are passed through the carrier's amplitude. It is called binary amplitude shift keying (2ASK) because the modulation signal can take only two binary levels, 0 or 1. The multiplication result of this binary digit with the carrier frequency is equivalent to the carrier frequency on or off. It means that the modulated digital signal is 1 when carrier transmission takes place and 0 when there is no carrier transmission. The Power Receiver communicates to the Power Transmitter using backscatter modulation. For this purpose, the Power Receiver modulates the amount of power drawn from the Power Signal. The Power Transmitter detects this as a modulation of the current through and/or voltage across the Primary Cell. In other words, the Power Receiver and Power Transmitter use amplitude modulated Power Signal to provide a Power Receiver to Power Transmitter communications channel. 2.1 Modulation scheme The Power Receiver shall modulate the amount of power drawn from the Power Signal, such that the Primary Cell current or Primary Cell voltage assumes two states, namely a HI state and a LO state. A state is characterized in that the amplitude is constant within a certain variation Δ for at least ts ms. The difference of the amplitude of the Primary Cell current in the HI and LO state is at least 15 mA. The difference of the amplitude of the Primary Cell voltage in the HI and LO state is at least 200 mV. Figure 1 and Table 1 show the details. 2 Demodulating Communication Signals of Qi-Compliant Low-Power Wireless Charger Using MC56F8006 DSC, Rev. 0, 03/2013 Freescale Semiconductor, Inc. Figure 1. Modulation scheme Parameter Symbol Value tT 100 Maximum transition time ts 150 Minimum stable time Δ 8 Current amplitude variation Δ 110 Voltage amplitude variation Table 1. Modulation timing definition Unit us us mA mV 2.2 Bit encoding scheme The Power Receiver shall use a differential bi-phase encoding scheme to modulate data bits onto the Power Signal. For this purpose, the Power Receiver shall align each data bit to a full period tCLK of an internal clock signal, such that the start of a data bit coincides with the rising edge of the clock signal. This internal clock signal shall have a frequency fCLK = 2±4% kHz. The Receiver shall encode a ONE bit using two transitions in the Power Signal, such that the first transition coincides with the rising-edge of the clock signal, and the second transition coincides with the falling-edge of the clock signal. The Receiver shall encode a ZERO bit using a single transition in the Power Signal, which coincides with the rising-edge of the clock signal. The following figure shows an example. tCLK ONE ZERO ONE ZERO ONE ONE ZERO ZERO Figure 2. Bit encoding scheme Demodulating Communication Signals of Qi-Compliant Low-Power Wireless Charger Using MC56F8006 DSC, Rev. 0, 03/2013 Freescale Semiconductor, Inc. 2.3 Byte encoding scheme The Power Receiver shall use an 11-bit asynchronous serial format to transmit a data byte. This format consists of a start bit, the 8 data bits of the byte, a parity bit, and a single stop bit. The start bit is a ZERO. The order of the data bits is LSB first and the parity bit is odd. This means that the Power Receiver shall set the parity bit to ONE if the data byte contains an even number of ONE bits. Otherwise, the Power Receiver shall set the parity bit to ZERO. The stop bit is a ONE. The following figure shows the data byte format including the differential bi-phase encoding of each individual bit, using the value 0x35 as an example. Start b0 b1 b2 b3 b4 b5 b6 b7 Parity Stop Figure 3. Byte encoding scheme 2.4 Packet structure The Power Receiver shall communicate to the Power Transmitter using data packets. As shown in Figure 4, a packet consists of four parts, namely a preamble, a header, a message, and a checksum. The preamble consists of a minimum of 11 and a maximum of 25 bits, all set to ONE, and encoded as defined in Bit encoding scheme. The preamble enables the Power Transmitter to synchronize with the incoming data and accurately detect the start bit of the header. The header, message, and checksum consist of a sequence of three or more bytes encoded as defined in Header, Message, and Checksum. Preamble Header Message Checksum Figure 4. Packet structure The Power Transmitter shall consider a data packet as received correctly if: • The Power Transmitter has detected at least four preamble bits that are followed by a start bit. • The Power Transmitter has not detected a parity error in any of the bytes that comprise the packet. This includes the header byte, the message bytes, and the checksum byte. • The Power Transmitter has detected the stop bit of the checksum byte. • The Power Transmitter has determined that the checksum byte is consistent. (see Checksum) If the Power Transmitter does not receive a packet correctly, the Power Transmitter shall discard the packet, and not use any of the information contained therein. In the ping phase as well as in the identification and configuration phase, this typically leads to a timeout, which causes the Power Transmitter to remove the Power Signal. 4 Demodulating Communication Signals of Qi-Compliant Low-Power Wireless Charger Using MC56F8006 DSC, Rev. 0, 03/2013 Freescale Semiconductor, Inc. 2.4.1 Header The header consists of a single byte that indicates the packet type. In addition, the header implicitly provides the size of the message contained in the packet. 2.4.2 Message The Power Receiver shall ensure that the message contained in the packet is consistent with the packet type indicated in the header. See Qi Specification, Part1 Section 6 for a detailed definition of the possible messages. The first byte of the message, byte B0, directly follows the header. 2.4.3 Checksum The checksum consists of a single byte, which enables the Power Transmitter to check for transmission errors. The Power Transmitter shall calculate the checksum as follows: C : = H ⊕ B0 ⊕ B1 ⊕ ... ⊕ Blast Where C represents the calculated checksum, H represents the header byte, and B0, B1,…, Blast represent the message bytes. If the calculated checksum and the checksum byte contained in the packet are not equal, the Power Transmitter shall determine that the checksum is inconsistent. 3 Demodulation circuit design The Power Receiver communicates to the Power Transmitter using backscatter modulation as defined in Modulation scheme. The function of communication demodulation circuit is to detect the 2 kHz Communication Signal from the 110 kHz Power Signal. Coil Voltage Voltage Scale Down Rectify & DC Filter Low Pass Filter Electric Level Comparator Communication Wave Voltage Divider DSC Figure 5. Block diagram of communication demodulation circuit Figure 5 shows the block diagram of communication demodulation circuit. The input of the circuit is coil voltage with communication signals, and the output is communication data following bit encoding scheme. The circuit can be divided into the following five parts: • Voltage scale down part • Rectifier and DC filter • Low-pass filter • Electric level comparator • Communication wave voltage divider Each of these components is described in the following subsections. Figure 6 shows the input of the demodulation circuit. The fundamental waves are the primary voltage and the carrier waves are communication signals. Demodulating Communication Signals of Qi-Compliant Low-Power Wireless Charger Using MC56F8006 DSC, Rev. 0, 03/2013 Freescale Semiconductor, Inc. Communication signals Figure 6. Waveform of primary coil voltage 3.1 Voltage scale down circuit The range of coil voltage is from 16-32 V pk-pk, and can reach levels exceeding 40 V pk-pk. As shown in Figure 7, the function of a voltage scale down circuit is to scale down the voltage Coil_IN to GNDA and Coil_OUT to GNDA. Differential circuit is used to adjust the midpoint of the wave to 2.5 V and the amplitude of the wave between 0–5 V. OUTPUT Figure 7. Voltage scale down circuit Figure 8 shows the communication wave after the voltage scale down circuit. 6 Demodulating Communication Signals of Qi-Compliant Low-Power Wireless Charger Using MC56F8006 DSC, Rev. 0, 03/2013 Freescale Semiconductor, Inc. Between 0-5 V Middle point 2.5 Figure 8. Communication wave after the voltage scale down circuit 3.2 Rectify and DC filter circuit As shown in Figure 9, the functions of rectify and DC filter circuit are as follows. 1. Rectify the wave to get the first half cycle, transfer the sinusoidal wave to saw tooth wave. 2. Filter the DC part of the wave to make 2.5 V the middle point of the sawtooth wave. INPUT OUTPUT Figure 9. Rectifier and DC filter circuit Figure 10 shows the communication wave after rectify and DC filter circuit. Demodulating Communication Signals of Qi-Compliant Low-Power Wireless Charger Using MC56F8006 DSC, Rev. 0, 03/2013 Freescale Semiconductor, Inc. Positive Halfwave Figure 10. Communication wave after the rectify and DC filter circuits 3.3 Low-pass filter design Figure 11 shows the low-pass filter circuit. Improved second-order low pass filter is used. The function is to filter the 107 kHz high-frequency power wave to get the 2 kHz low-speed communication data. OUTPUT INPUT GNDA Figure 11. Low-pass filter 8 Demodulating Communication Signals of Qi-Compliant Low-Power Wireless Charger Using MC56F8006 DSC, Rev. 0, 03/2013 Freescale Semiconductor, Inc. Figure 12. Improved second-order low-pass filter Figure 12 shows the schematic of improved second-order low-pass filter selected in the design. The following equations can be used to determine several parameters of the low-pass filter. Vo ( s ) = −1 VN ( s) sC 2 R2 Where Vo(s) is the output of the second-order low pass filter, and VN(s) is the voltage at point N. The current to point N is 0. See the following equation. Vi ( s ) − VN ( s ) V ( s ) VN ( s ) − Vo ( s ) − VN ( s ) sC1 − N − =0 R1 R2 Rf Vi(s) is the input of the second-order low-pass filter. Resistors R1, R2, Rf and capacitors C1 and C2 determine the parameters of low-pass filters. Transfer function can be calculated using the following equation. Av (s ) = − Rf / R1 1 1 1 1 + sC 2 R2 Rf ( + + ) + s 2 C1C 2 R2 Rf R1 R2 Rf Set s = jω , then the frequency response can be calculated as: A v = ( ( f0 = 1 2 π C1C2 R2 Rf , Avp 1− ( Avp = − f 2 1 f ) +j f0 Q f0 C1 Rf , Q = ( R1 ∥ R2 ∥ Rf ) R2 Rf C2 R1 f 0 : Pass band Cut off frequency, Avp : Pass band gain, Q : Av ( f = f0 ) ) = QAvp ) Set R1 = 4.3 kΩ, R2= 2.4 kΩ, Rf =149 kΩ, C1 =11 nF and C2= 0.47 nF. Demodulating Communication Signals of Qi-Compliant Low-Power Wireless Charger Using MC56F8006 DSC, Rev. 0, 03/2013 Freescale Semiconductor, Inc. f0 = = 1 2 π C1C 2 R2 Rf 1 2π 11 * 10 * 0.47 * 10 −9 * 2.4 * 10 3 * 149 * 10 3 = 3.7 kHz −9 Avp = − Rf = 34.65 R1 Q = ( R1 ∥ R2 ∥ Rf ) |1− ( C1 = 1.13 R 2 Rf C 2 fc 2 1 fc ) +j |= 2 f0 Q f0 f c = 1.33 f 0 = 4.9kHz ( f c : -3 db cut-off frequency) The following figure shows the communication wave after the second-order LPF. Figure 13. Communication wave after the second-order low-pass filter 3.4 Comparator The function of comparator is to compare the input signal value with reference (2.5 V) to get a square wave. A comparator circuit is shown in the following figure. 10 Demodulating Communication Signals of Qi-Compliant Low-Power Wireless Charger Using MC56F8006 DSC, Rev. 0, 03/2013 Freescale Semiconductor, Inc. INPUT OUTPUT Figure 14. Comparator circuits The following figure shows the communication wave after comparator circuit. Between 0–5V Figure 15. Communication wave after the comparator circuit 3.5 Voltage divider The voltage divider circuit is shown in Figure 16. The function of this circuit is to make the amplitude of square wave to be 3.3 V for the DSC to detect. Demodulating Communication Signals of Qi-Compliant Low-Power Wireless Charger Using MC56F8006 DSC, Rev. 0, 03/2013 Freescale Semiconductor, Inc. INPUT Figure 16. Voltage divider circuit Figure 17 shows the communication wave after the voltage divider circuit. The output of the circuit is connected to DSC capture input channel. Between 0-3.3 V Figure 17. Communication wave after the voltage divider circuit 4 Demodulation software design The timer module (TMR) of MC56F8006 DSC contains two identical counter/timer groups. Both counters have capture and compare capability. The capture register enables an external signal to take a “snapshot” of the counter’s current value. Freescale’s Wireless Charger Transmitter uses the capture function of MC568006 DSC DTMR1 to realize the demodulation. The capture register will enable both the rising- and falling-edge trigger mode. When rising or falling edge occurs, the current counter value is triggered to be captured. By calculating the high-level and low-level signal lasting time, the data received can be demodulated. 12 Demodulating Communication Signals of Qi-Compliant Low-Power Wireless Charger Using MC56F8006 DSC, Rev. 0, 03/2013 Freescale Semiconductor, Inc. 4.1 Preamble decoding scheme In the beginning stages of a data packet, there may be some electric level transition lost, so it is critical to find the starting point of a header received. The preamble enables the Power Transmitter to synchronize with the incoming data and accurately detect the start bit of the header. The preamble consists of a minimum of 11 and a maximum of 25 bits, all set to ONE. A ZERO bit received means the end of preamble and the starting bit of the next byte. Figure 18 shows the preamble decoding flowchart. When the Capture ISR occurs, it will record the capture value and check the receiving mode first. Considering the communication speed to be 2 Kbit/s, the period of a bit is 500 µs; a minimum of 11 and a maximum of 25 bits set to ONE means a minimum of 22 and maximum 50 of 250 µs pulses are captured. Figure 18. Preamble decoding flowchart According to the Qi Protocol definition in Byte encoding scheme, the Power Transmitter has detected at least four preamble bits that are followed by a start bit, which means at least eight 250 µs pulses are captured. In order to increase redundancy and reliability, set the half cycle time to be 200–300 µs, and full cycle time to be 400–600 µs. Demodulating Communication Signals of Qi-Compliant Low-Power Wireless Charger Using MC56F8006 DSC, Rev. 0, 03/2013 Freescale Semiconductor, Inc. 4.2 Bit decoding scheme 4.2.1 Method 1: Traditional method After the preamble is successfully received, bit receiving of the following header and data begins. One electrical level transition at half cycle during full cycle means a bit ONE received, or a bit ZERO received. If the electrical level transition is not at half cycle point or full cycle point, the bit receive fails and returns to the initial preamble receiving mode. The following figure shows the bit decoding flowchart of method 1. Figure 19. BIT decoding flowchart of method 1 4.2.2 Method 2: Optimized anti-jamming algorithm In order to improve the communication reliability between the Power Receiver and Transmitter, a new method with optimized anti-jamming algorithm is developed to filter the glitch on the communication wave. The flowchart is shown in the following figure. 14 Demodulating Communication Signals of Qi-Compliant Low-Power Wireless Charger Using MC56F8006 DSC, Rev. 0, 03/2013 Freescale Semiconductor, Inc. Figure 20. Optimized anti-jamming algorithm flowchart Glitch Figure 21. Bit receiving wave with anti-jamming algorithm Demodulating Communication Signals of Qi-Compliant Low-Power Wireless Charger Using MC56F8006 DSC, Rev. 0, 03/2013 Freescale Semiconductor, Inc. As shown in Figure 21, Channel 1 indicates communication wave, and Channel 2 indicates the data bit received by DSC. By using the optimized anti-jamming algorithm in software, the glitch on the communication wave is filtered and the DSC receives the correct data. Thus, the communication system becomes more reliable. 4.3 Byte decoding scheme Figure 22 shows the byte decoding flowchart. An 11-bit asynchronous serial format is used to transmit a data byte. Each time a bit received success will be stored. After 11 bits received, even check will determine whether the byte received is correct or incorrect. An incorrect byte received will make the state return to initial preamble receiving mode. Figure 22. Byte decoding flowchart 16 Demodulating Communication Signals of Qi-Compliant Low-Power Wireless Charger Using MC56F8006 DSC, Rev. 0, 03/2013 Freescale Semiconductor, Inc. 4.4 Packet decoding scheme The header consists of a single byte that indicates the packet type. In addition, the header implicitly provides the size of the message contained in the packet. After the first byte (Header) is successfully received, the length of the packet can be determined. Figure 23 shows the packet decoding flowchart. When all bytes of the packet have been received, checksum will be calculated to judge whether the packet received is correct or not. If a correct packet is received, packet analysis will start, or the packet will be discarded. Figure 23. Packet decoding flowchart Demodulating Communication Signals of Qi-Compliant Low-Power Wireless Charger Using MC56F8006 DSC, Rev. 0, 03/2013 Freescale Semiconductor, Inc. 4.5 Overtime detection Overtime detection helps to make the state return to preamble receiving mode when the DTMR1 counter exceeds 800 µs. The compare ISR of DTMR1 is used to realize this function. If the overtime compare event occurs, all the related registers and variables will be cleared. The following figure shows the overtime detection flowchart. Entry Clear Preamble Counter Clear ONE Flag Clear BIT Counter Clear BYTE Counter Return Figure 24. Overtime detection flowchart 5 Test results and conclusion 5.1 Test result As shown in Figure 25, demodulation circuits correctly demodulate the communication data from the input coil voltage as channel 3. DTM1 module of MC56F8006 DSC analyses the input wave as channel 2, and the correct ONE or ZERO bit information as channel 1. 18 Demodulating Communication Signals of Qi-Compliant Low-Power Wireless Charger Using MC56F8006 DSC, Rev. 0, 03/2013 Freescale Semiconductor, Inc. 11 0 Figure 25. Communication demodulation test wave The complete packet demodulated by MC56F8006 DSC is shown in Figure 26. This data is obtained from FreeMASTER debugging tools when the system is operating. All the starting packets including Signal Strength Packet, Identification Packet, and Configuration Packet are received correctly according to the Qi protocol. Current Receive Control Error Packet Signal Strength Packet Identification Packet Configuration Packet Figure 26. Packet demodulation by MC56F8006 DSC Demodulating Communication Signals of Qi-Compliant Low-Power Wireless Charger Using MC56F8006 DSC, Rev. 0, 03/2013 Freescale Semiconductor, Inc. 5.2 Conclusion The low-power wireless charger compliant to the Qi protocol is becoming more common today. Communication signal demodulation strategy is the most critical technology to the charging performance. In this application note, a complete solution to demodulating communication signals from power wave with MC56F8006 DSC is provided, which has high reliability and very low cost. It can be easily used in all Qicompliant A types and B types low-power wireless chargers with wide input voltage from 5–19 V. The solution could also be easily used for other parts of Freescale DSC family. 20 Demodulating Communication Signals of Qi-Compliant Low-Power Wireless Charger Using MC56F8006 DSC, Rev. 0, 03/2013 Freescale Semiconductor, Inc. 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All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2013. All rights reserved. Document Number: AN4701 Rev. 0 03/2013