AD AD9508BCPZ

1.65 GHz Clock Fanout Buffer with
Output Dividers and Delay Adjust
AD9508
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
1.65 GHz differential clock inputs/outputs
10-bit programmable dividers, 1 to 1024, all integers
Up to 4 differential outputs or 8 CMOS outputs
Pin strapping capability for hardwired programming at
power-up
<115 fs rms broadband random jitter (see Figure 25)
Additive output jitter: 41 fs rms typical (12 kHz to 20 MHz)
Excellent output-to-output isolation
Automatic synchronization of all outputs
Single 2.5 V/3.3 V power supply
Internal LDO (low drop-out) voltage regulator for enhanced
power supply immunity
Phase offset select for output-to-output coarse delay adjust
3 programmable output logic levels, LVDS, HSTL, and CMOS
Serial control port (SPI/I2C) or pin-programmable mode
Space-saving 24-lead LFCSP
AD9508
DIV/Φ
CLK
DIV/Φ
CLK
DIV/Φ
SCLK/SCL/SC0
SDIO/SDA/S1
SDO/S3
CS/C2
DIV/Φ
CONTROL
INTERFACE
SPI/I2C/PINS
PIN CONTROL
RESET
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
SYNC
11161-001
FEATURES
Figure 1.
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
GENERAL DESCRIPTION
The AD9508 provides clock fanout capability in a design that
emphasizes low jitter to maximize system performance. This
device benefits applications like clocking data converters with
demanding phase noise and low jitter requirements.
Each output has a programmable divider that can be bypassed
or be set to divide by any integer up to 1024. In addition, the
AD9508 supports a coarse output phase adjustment between the
outputs.
There are four independent differential clock outputs, each with
various types of logic levels available. Available logic types
include LVDS (1.65 GHz), HSTL (1.65 GHz), and 1.8 V CMOS
(250 MHz). In 1.8 V CMOS output mode, the differential output
becomes two CMOS single-ended signals. The CMOS outputs
are 1.8 V logic levels, regardless of the operating supply voltage.
The device can also be pin programmed for various fixed
configurations at power-up without the need for SPI or I2C
programming.
Rev. A
The AD9508 is available in a 24-lead LFCSP and operates from
a either a single 2.5 V or 3.3 V supply. The temperature range is
−40°C to +85°C.
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AD9508
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Programming Mode Selection.................................................. 21
Applications ....................................................................................... 1
Clock Input.................................................................................. 21
Functional Block Diagram .............................................................. 1
Clock Dividers ............................................................................ 23
General Description ......................................................................... 1
Phase Delay Control .................................................................. 23
Revision History ............................................................................... 2
Reset Modes ................................................................................ 23
Specifications..................................................................................... 3
Power-Down Mode .................................................................... 23
Electrical Characteristics ............................................................. 3
Output Clock Synchronization ................................................. 24
Power Supply Current and Temperature Conditions .............. 3
Power Supply............................................................................... 24
Clock Inputs and Output DC Specifications ............................ 4
Thermally Enhanced Package Mounting Guidelines ............ 24
Output Driver Timing Characteristics ...................................... 5
Pin Strapping to Program Upon Power-Up ................................ 25
Logic Inputs ................................................................................... 6
Serial Control Port ......................................................................... 26
Serial Port Specifications—SPI Mode........................................ 6
SPI/I²C Port Selection................................................................ 26
Serial Port Specifications—I C Mode ........................................ 7
SPI Serial Port Operation .......................................................... 26
External Resistor Values For Pin Strapping Mode ................... 8
I2C Serial Port Operation .......................................................... 29
Clock Output Additive Phase Noise .......................................... 8
Register Map ................................................................................... 32
Clock Output Additive Time Jitter ............................................. 9
Register Map Bit Descriptions ...................................................... 33
Absolute Maximum Ratings ..................................................... 10
Serial Port Configuration (Register 0x00) .............................. 33
Thermal Characteristics ............................................................ 10
Silicon Revision (Register 0x0A to Register 0x0D) ............... 33
ESD Caution ................................................................................ 10
Chip Level Functions (Register 0x12 to Register 0x14) ........ 33
Pin Configuration and Function Descriptions ........................... 11
OUT0 Functions (Register 0x15 to Register 0x1A) ............... 34
Typical Performance Characteristics ........................................... 13
OUT1 Functions (Register 0x1B to Register 0x20) ............... 35
Test Circuits ..................................................................................... 19
OUT2 Functions (Register 0x21 to Register 0x26) ................ 36
Input/Output Termination Recommendations ...................... 19
OUT3 Functions (Register 0x27 to Register 0x2C) ............... 37
Terminology .................................................................................... 20
Packaging and Ordering Information ......................................... 38
Theory of Operation ...................................................................... 21
Outline Dimensions ................................................................... 38
Detailed Block Diagram ............................................................ 21
Ordering Guide .......................................................................... 38
2
REVISION HISTORY
4/13—Rev. 0 to Rev. A
Changes to Table 9 ............................................................................ 9
Changes to Figure 10 ...................................................................... 14
Changes to Figure 15 ...................................................................... 15
Changes to Figure 24 and Figure 26............................................. 16
Changes to Figure 27, Figure 29 to Figure 32 ............................. 17
Changes to Figure 33 ...................................................................... 18
1/13—Revision 0: Initial Version
Rev. A | Page 2 of 40
Data Sheet
AD9508
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical values are given for VS = 3.3 V and 2.5 V and TA = 25°C; minimum and maximum values are given over the full VDD = 3.3 V + 5% down
to 2.5 V − 5% and TA = −40°C to +85°C variation; and input slew rate > 1 V/ns, unless otherwise noted.
POWER SUPPLY CURRENT AND TEMPERATURE CONDITIONS
Table 1.
Parameter
SUPPLY VOLTAGE
Min
2.375
CURRENT CONSUMPTION
LVDS Configuration
HSTL Configuration
CMOS Configuration
Full Power-Down
TEMPERATURE
Ambient Temperature Range, TA
Junction Temperature, TJ
−40
Typ
2.5
Max
3.465
Unit
V
Test Conditions/Comments
Use supply voltage setting (2.5 V or 3.3 V) and
appropriate current consumption configuration (see Current Consumption parameters in
Table 1) to calculate total power dissipation
152
168
mA
122
134
mA
182
200
mA
118
131
mA
92
101
mA
141
185
mA
122
134
mA
85
94
mA
Input clock: 1500 MHz in differential mode, all
LVDS output drivers at 1500 MHz
Input clock: 800 MHz in differential mode, all
LVDS output drivers at 200 MHz
Input clock: 1500 MHz in differential mode, all
HSTL output drivers at 1500 MHz
Input clock: 491.52 MHz in differential mode, all
output drivers at 491.52 MHz
Input clock: 122.88 MHz in differential mode, all
output drivers at 122.88 MHz
Input clock: 1500 MHz in differential mode, all
CMOS output drivers at 250 MHz, 10 pF load
Input clock: 800 MHz in differential mode, all
CMOS outputs drivers at 200 MHz, 10 pF load
Input clock: 100 MHz in differential mode, all
CMOS outputs drivers at 100 MHz, 10 pF load
6
10
mA
+25
+85
115
°C
°C
Rev. A | Page 3 of 40
Junction temperatures above 115°C can
degrade performance but no damage should
occur, unless the absolute temperature is
exceeded
AD9508
Data Sheet
CLOCK INPUTS AND OUTPUT DC SPECIFICATIONS
Table 2.
Parameter
CLOCK INPUTS
Differential Mode
Input Frequency
Input Sensitivity
Input Common-Mode Voltage
Input Voltage Offset
DC-Coupled Input CommonMode Range
Pulse Width
Low
High
Input Resistance (Differential)
Input Capacitance
Input Bias Current (Each Pin)
CMOS CLOCK MODE (SINGLE-ENDED)
Input Frequency
Input Voltage
High
Low
Input Current
High
Low
Input Capacitance
LVDS CLOCK OUTPUTS
Output Frequency
Output Voltage Differential
Symbol
Min
Typ
0
360
VICM
0.95
VCMR
0.58
1.05
Max
Unit
Test Conditions/Comments
1650
2200
MHz
mV p-p
1.15
V
Differential input
As measured with a differential probe; jitter
performance improves with higher slew
rates (greater voltage swing)
Input pins are internally self biased, which
enables ac coupling
1.67
mV
V
30
303
303
5.0
7
2
CIN
100
VIH
VIL
400
ps
ps
kΩ
pF
µA
250
MHz
VDD/2 + 0.15
V
V
9
VDD/2 − 0.15
IINH
IINL
CIN
1
Full input swing
µA
µA
pF
−142
2
Termination = 100 Ω differential (OUTx, OUTx)
VOD
Delta VOD
ΔVOD
Offset Voltage
Delta VOS
VOS
ΔVOS
Short-Circuit Current
LVDS Duty Cycle
ISA, ISB
247
1.125
1650
454
MHz
mV
50
mV
1.18
1.375
50
V
mV
13.6
24
55
61
mA
%
%
%
1650
978
971
55
60
MHz
mV
mV
%
%
%
375
45
39
50.1
HSTL CLOCK OUTPUTS
Output Frequency
Differential Output Voltage
Common-Mode Output Voltage
HSTL Duty Cycle
This is the allowable common-mode voltage
range when dc-coupled
VO
VOCM
859
905
45
40
925
940
50.9
Rev. A | Page 4 of 40
VOH − VOL measurement across a differential
pair at the default amplitude setting with
output driver not toggling; see Figure 6 for
variation over frequency
This is the absolute value of the difference
between VOD when the normal output is high
vs. when the complementary output is high
(VOH + VOL)/2 across a differential pair
This is the absolute value of the difference
between VOS when the normal output is high
vs. when the complementary output is high
Each pin (output shorted to GND)
Up to 750 MHz input
750 MHz to1500 MHz input
1650 MHz input
100 Ω across differential pair; default
amplitude setting
VOH − VOL with output driver static
(VOH + VOL)/2 with output driver static
Up to 750 MHz input
750 MHz to 1500 MHz input
1650 MHz input
Data Sheet
Parameter
CMOS CLOCK OUTPUTS
AD9508
Symbol
Min
Typ
Output Frequency
Output Voltage
@ 1 mA Load
High
Low
@ 10 mA load
High
Low
@ 10 mA Load (2 × CMOS Mode)
High
Low
CMOS Duty Cycle
VOH
VOL
1.7
VOH
VOL
1.2
VOH
VOL
1.45
45
Max
Unit
250
MHz
0.1
V
V
0.6
V
V
0.35
55
V
V
%
Test Conditions/Comments
Single-ended; termination = open; OUTx
and OUTx in phase
With 10 pF load per output, see Figure 14
for swing vs. frequency
Up to 250 MHz
OUTPUT DRIVER TIMING CHARACTERISTICS
Table 3.
Parameter
LVDS OUTPUTS
Output Rise/Fall Time
Propagation Delay, Clock-to-LVDS Output
Temperature Coefficient
Output Skew 1
All LVDS Outputs
On the Same Part
Across Multiple Parts
HSTL OUTPUTS
Output Rise/Fall Time
Propagation Delay, Clock-to-HSTL Output
Temperature Coefficient
Output Skew1
All HSTL Outputs
On the Same Part
Across Multiple Parts
CMOS OUTPUTS
Output Rise/Fall Time
Propagation Delay, Clock-to-CMOS Output
Temperature Coefficient
Output Skew1
All CMOS Outputs
On the Same Part
Across Multiple Parts
Symbol
Min
Typ
Max
Unit
tR , tF
tPD
1.56
152
2.01
2.8
177
2.43
ps
ns
ps/°C
48
781
ps
ps
143
2.5
ps
ns
ps/°C
59
825
ps
ps
1.45
3.07
ns
ns
ps/°C
112
965
ps
ps
tR , tF
tPD
tR, tF
tPD
1.59
2.04
118
2.05
2.9
1.18
2.56
3.3
Rev. A | Page 5 of 40
Test Conditions/Comments
Termination = 100 Ω differential, 1 × LVDS
20% to 80% measured differentially
Assumes same temperature and supply;
takes into account worst-case propagation delay delta due to worst-case
process variation
Termination = 100 Ω differential, 1 × HSTL
20% to 80% measured differentially
Assumes same temperature and supply;
takes into account worst-case propagation delay delta due to worst-case
process variation
20% to 80%; CLOAD = 10 pF
10 pF load
Assumes same temperature and supply;
takes into account worst-case
propagation delay delta due to worstcase process variation
AD9508
Data Sheet
Parameter
OUTPUT LOGIC SKEW1
LVDS Output(s) and HSTL Output(s)
1
Symbol
Min
Typ
Max
Unit
77
119
ps
LVDS Output(s) and CMOS Output(s)
497
700
ps
HSTL Output(s) and CMOS Output(s)
424
622
ps
Test Conditions/Comments
CMOS load = 10 pF and LVDS load = 100 Ω
Outputs on the same device; assumes
worst-case output combination
Outputs on the same device; assumes
worst-case output combination
Outputs on the same device; assumes
worst-case output combination
Output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
LOGIC INPUTS
Table 4.
Parameter
Symbol
Min
LOGIC INPUTS RESET, SYNC, IN_SEL
Input Voltage
High
VIH
1.7
2.0
Low
Input Current
Input Capacitance
Typ
Max
VIL
IINH, IINL
CIN
0.7
0.8
+100
−300
2
Unit
Test Conditions/Comments
V
V
V
V
µA
pF
2.5 V supply voltage operation
3.3 V supply voltage operation
2.5 V supply voltage operation
3.3 V supply voltage operation
SERIAL PORT SPECIFICATIONS—SPI MODE
Table 5.
Parameter
CS
Input Voltage
Logic 1
Logic 0
Input Current
Logic 1
Logic 0
Input Capacitance
SCLK
Input Voltage
Logic 1
Logic 0
Input Current
Logic 1
Logic 0
Input Capacitance
SDIO
As Input
Input Voltage
Logic 1
Logic 0
Input Current
Logic 1
Logic 0
Input Capacitance
Min
Typ
Max
Unit
0.4
V
V
VDD − 0.4
−4
−85
2
µA
µA
µA
VDD − 0.4
0.4
70
13
2
µA
µA
pF
VDD − 0.4
0.4
−1
−1
2
V
V
V
V
µA
µA
pF
Rev. A | Page 6 of 40
Test Conditions/Comments
SCLK has a 200 kΩ internal pull-down resistor
Data Sheet
Parameter
As Output
Output Voltage
Logic 1
Logic 0
SDO
Output Voltage
Logic 1
Logic 0
TIMING
SCLK
Clock Rate, 1/tCLK
Pulse Width High, tHIGH
Pulse Width Low, tLOW
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO and SDO, tDV
CS to SCLK Setup (tS)
CS to SCLK Hold (tC)
CS Minimum Pulse Width High
E
A
E
A
A
E
A
A
AD9508
Min
Typ
Max
Unit
Test Conditions/Comments
0.4
V
V
1 mA load current
1 mA load current
0.4
V
V
1 mA load current
1 mA load current
VDD − 0.4
VDD − 0.4
30
4.6
3.5
2.9
0
15
3.4
0
3.4
MHz
ns
ns
ns
ns
ns
ns
ns
ns
SERIAL PORT SPECIFICATIONS—I2C MODE
Table 6.
Parameter
SDA, SCL (AS INPUT)
Input Voltage
Logic 1
Logic 0
Input Current
Hysteresis of Schmitt Trigger Inputs
SDA (AS OUTPUT)
Output Logic 0 Voltage
Output Fall Time from VIH (MIN) to VIL (MAX)
TIMING
SCL Clock Rate
Bus-Free Time Between a Stop and Start
Condition, tBUF
Repeated Start Condition Setup Time, tSU; STA
Repeated Hold Time Start Condition, tHD; STA
Stop Condition Setup Time, tSU; STO
Low Period of the SCL Clock, tLOW
High Period of the SCL Clock, tHIGH
Data Setup Time, tSU; DAT
Data Hold Time, tHD; DAT
Min
Typ
Max
Unit
0.4
0
V
V
µA
mV
0.4
250
V
ns
400
kHz
µs
0.6
0.6
µs
µs
0.6
1.3
0.6
100
0
µs
µs
µs
ns
µs
VDD − 0.4
−40
150
1.3
0.9
Rev. A | Page 7 of 40
Test Conditions/Comments
For VIN = 10% to 90% DVDD3
IO = 3 mA
10 pF ≤ Cb ≤ 400 pF
After this period, the first clock pulse is
generated
AD9508
Data Sheet
EXTERNAL RESISTOR VALUES FOR PIN STRAPPING MODE
Table 7.
Parameter
EXTERNAL RESISTORS
Voltage Level 0
Voltage Level 1
Voltage Level 2
Voltage Level 3
Voltage Level 4
Voltage Level 5
Voltage Level 6
Voltage Level 7
Resistor Polarity
Min
Pull down to ground
Pull down to ground
Pull down to ground
Pull down to ground
Pull up to VDD
Pull up to VDD
Pull up to VDD
Pull up to VDD
Typ
Max
820
1.8
3.9
8.2
820
1.8
3.9
8.2
Unit
Test Conditions/Comments
Using 10% tolerance resistor
Ω
kΩ
kΩ
kΩ
Ω
kΩ
kΩ
kΩ
CLOCK OUTPUT ADDITIVE PHASE NOISE
Table 8.
Parameter
CLK-TO-HSTL OR LVDS ADDITIVE PHASE NOISE
CLK = 1474.56 MHz, OUTx = 1474.56 MHz
Divide Ratio = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 100 MHz Offset
CLK-TO-HSTL OR LVDS or CMOS ADDITIVE PHASE NOISE
CLK = 625 MHz, OUTx = 125 MHz
Divide Ratio = 5
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 20 MHz Offset
CLK-TO-HSTL OR LVDS ADDITIVE PHASE NOISE
CLK = 491.52 MHz, OUTx = 491.52 MHz
Divide Ratio = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 20 MHz Offset
Min
Typ
Max
Unit
Test Conditions/Comments
Input slew rate > 1 V/ns
−88
−100
−109
−116
−135
−144
−148
−149
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input slew rate > 1 V/ns
−114
−125
−133
−141
−159
−162
−163
−163
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input slew rate > 1 V/ns
−100
−111
−120
−127
−146
−153
−153
−153
Rev. A | Page 8 of 40
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Data Sheet
AD9508
CLOCK OUTPUT ADDITIVE TIME JITTER
Table 9.
Parameter
LVDS OUTPUT ADDITIVE TIME JITTER
CLK = 622.08 MHz, Outputs = 622.08 MHz
CLK = 622.08 MHz, Outputs = 155.52 MHz
CLK = 125 MHz, Outputs = 125 MHz
CLK = 400 MHz, Outputs = 50 MHz
HSTL OUTPUT ADDITIVE TIME JITTER
CLK = 622.08 MHz, Outputs = 622.08 MHz
CLK = 622.08 MHz, Outputs = 155.52 MHz
CMOS OUTPUT ADDITIVE TIME JITTER
CLK = 100 MHz, Outputs = 100 MHz
Min
Typ
Unit
Test Conditions/Comments
41
70
69
93
144
142
105
209
206
184
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
BW = 12 kHz to 20 MHz
BW = 20 kHz to 80 MHz
BW = 50 kHz to 80 MHz
BW = 12 kHz to 20 MHz
BW = 20 kHz to 80 MHz
BW = 50 kHz to 80 MHz
BW = 12 kHz to 20 MHz
BW = 20 kHz to 80 MHz
BW = 50 kHz to 80 MHz
BW = 12 kHz to 20 MHz
41
56
72
70
76
87
158
156
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
BW = 12 kHz to 20 MHz
BW = 100 Hz to 20 MHz
BW = 20 kHz to 80 MHz
BW = 50 kHz to 80 MHz
BW = 12 kHz to 20 MHz
BW = 100 Hz to 20 MHz
BW = 20 kHz to 80 MHz
BW = 50 kHz to 80 MHz
91
fs rms
BW = 12 kHz to 20 MHz
Rev. A | Page 9 of 40
Max
AD9508
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 10.
Parameter
Supply Voltage (VDD)
Maximum Digital Input Voltage
CLK and CLK
Maximum Digital Output Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
Rating
3.6 V
−0.5 V to VDD + 0.5 V
−0.5 V to VDD + 0.5 V
−0.5 V to VDD + 0.5 V
−65°C to +150°C
−40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Values of θJC are provided for package comparison and PCB
design considerations when an external heat sink is required.
Values of θJB are provided for package comparison and PCB
design considerations.
THERMAL CHARACTERISTICS
Thermal characteristics established using JEDEC51-7 and
JEDEC51-5 2S2P test boards.
Table 11. Thermal Characteristics, 24-Lead LFCSP
Symbol
θJA
θJMA
θJMA
The following equation determines the junction temperature on
the application PCB:
θJB
TJ = TCASE + (ΨJT × PD)
where:
TJ is the junction temperature (°C).
TCASE is the case temperature (°C) measured by the customer at
the top center of the package.
ΨJT is the value as indicated in Table 11.
PD is the power dissipation.
Values of θJA are provided for package comparison and PCB
design considerations. θJA can be used for a first-order approximation of TJ by the following equation:
TJ = TA + (θJA × PD)
θJC
ΨJT
1
2
Thermal Characteristic
(JEDEC51-7 and JEDEC51-5 2S2P
Test Boards1)
Junction-to-ambient thermal
resistance per JEDEC JESD51-2 (still
air)
Junction-to-ambient thermal
resistance, 1.0 m/sec airflow per
JEDEC JESD51-6 (moving air)
Junction-to-ambient thermal
resistance, 2.5 m/sec airflow per
JEDEC JESD51-6 (moving air)
Junction-to-board thermal
resistance per JEDEC JESD51-8 (still
air)
Junction-to-case thermal resistance
(die-to-heat sink) per MIL-STD-883,
Method 1012.1
Junction-to-top-of-package
characterization parameter per
JEDEC JESD51-2 (still air)
Value2
43.5
Unit
°C/W
40
°C/W
38.5
°C/W
16.2
°C/W
7.1
°C/W
0.33
°C/W
The exposed pad on the bottom of the package must be soldered to ground
(VSS) to achieve the specified thermal performance.
Results are from simulations. The PCB is a JEDEC multilayer type. Thermal
performance for actual applications requires careful inspection of the
conditions in the application to determine if they are similar to those
assumed in these calculations.
where TA is the ambient temperature (°C).
ESD CAUTION
Rev. A | Page 10 of 40
Data Sheet
AD9508
20 SYNC
19 SCLK/SCL/S0
21 CLK
22 CLK
24 SDIO/SDA/S1
23 IN_SEL
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
18 RESET
CS/S2 1
OUT0 2
17 OUT3
OUT0 3
AD9508
SDO/S3 4
TOP VIEW
16 OUT3
15 PROG_SEL
EXT_CAP0 5
14 EXT_CAP1
VDD 6
NOTES
1. THE EXPOSED DIE PAD MUST BE CONNECTED
TO GROUND (VSS).
11161-002
OUT2 12
OUT2 11
S4 9
S5 10
OUT1 8
OUT1 7
13 VDD
Figure 2. Pin Configuration
Table 12. Pin Function Descriptions
Pin No.
1
Mnemonic
CS/S2
2
3
4
OUT0
OUT0
SDO/S3
5
6
7
8
9
EXT_CAP0
VDD
OUT1
OUT1
S4
10
S5
11
12
13
14
15
OUT2
OUT2
VDD
EXT_CAP1
PROG_SEL
16
17
OUT3
OUT3
Description
Chip Select/Pin Programming. Multipurpose pin. This pin is controlled by the PROG_SEL pin. Chip
Select (CS) is an active logic low CMOS input used in the SPI operation mode. When programming a
device via SPI mode, CS must be held low. In systems where more than one AD9508 is present, this pin
enables individual programming of each AD9508. In pin programming mode, this pin becomes S2. In
this mode, S2 is hard wired with a resistor to either VDD or ground. The resistor value and resistor
biasing determine the channel divider value for the outputs on Pin 11 and Pin 12. See the Pin Strapping
to Program on Power-Up section for more details.
LVDS/HSTL Differential Output or Single-Ended CMOS Output.
Complementary LVDS/HSTL Differential Output or Single-Ended CMOS Output.
Serial Data Output/Pin Programming. Multipurpose pin. This pin is controlled by the PROG_SEL pin.
SDO is configured as an output to read back the internal register settings in SPI mode operation. In pin
programming mode, this pin becomes S3, which is hard wired with a resistor to either VDD or ground.
The resistor value and resistor biasing determine the channel divider value for the outputs on Pin 16
and Pin 17. See the Pin Strapping to Program on Power-Up section for more details.
Node for External Decoupling Capacitor for LDO. Tie this pin to a 0.47 μF capacitor to ground.
Power Supply (2.5 V or 3.3 V Operation).
LVDS/HSTL Differential Output or Single-Ended CMOS Output.
Complementary LVDS/HSTL Differential Output or Single-Ended CMOS Output.
Pin Programming. Use this pin in pin programming mode only. The PROG_SEL pin determines which
programming mode is used. In pin programming mode, S4 is hardwired with a resistor to either VDD or
ground. The resistor value and resistor biasing determine the output logic levels used for the outputs
on Pin 2, Pin 3, Pin 7, and Pin 8. See the Pin Strapping to Program on Power-Up section for more details.
Pin Programming. Use this pin in pin programming mode only. The PROG_SEL pin determines which
programming mode is used. In pin programming mode, S5 is hardwired with a resistor to either VDD or
ground. The resistor value and resistor biasing determine the output logic levels used for the outputs
on Pin 11, Pin 12, Pin 16, and Pin 17. See the Pin Strapping to Program on Power-Up section for more
details.
LVDS/HSTL Differential Output or Single-Ended CMOS Output.
Complementary LVDS/HSTL Differential Output or Single-Ended CMOS Output.
Power Supply (2.5 V or 3.3 V Operation).
Node for External Decoupling Capacitor for LDO. Tie this pin to a 0.47 μF capacitor to ground.
Three-State CMOS Input. Pin 15 selects the type of device programming interface to be used (SPI, I2C,
or pin programming).
LVDS/HSTL Differential Output or Single-Ended CMOS Output.
Complementary LVDS/HSTL Differential Output or Single-Ended CMOS Output.
Rev. A | Page 11 of 40
AD9508
Pin No.
18
Data Sheet
Mnemonic
RESET
E
A
Description
CMOS Input. Device Reset. When this active low pin is asserted, the internal register settings enter their
default state after the RESET is released. Note that RESET also serves as a power-down of the device
while an active low signal is applied to the pin. The RESET pin has an internal 24 kΩ pull-up resistor.
Serial Programming Clock/Data Clock/Programming Pin. Multipurpose pin controlled by the PROG_SEL
pin used for serial programming clock (SCLK) in SPI mode or data clock (SCL) for serial programming in
I2C Mode. The PROG_SEL pin determines which programming mode is used. In pin programming
mode, this pin becomes S0. In this mode, S0 is hardwired with a resistor to either VDD or ground. The
resistor value and resistor biasing determine the channel divider values for the outputs on Pin 2 and
Pin 3. See the Pin Strapping to Program on Power-Up section for more details.
Clock Synchronization. When this pin is active low, the output drivers are held static and then
synchronized on a low-to-high transition of this pin. The SYNC pin has an internal 24 kΩ pull-up
resistor.
Differential Clock Input or Single-Ended CMOS Input. Whether this pin serves as the differential clock
input or the single-ended CMOS input depends on the logic state of the IN_SEL pin.
Complementary Differential Clock Input.
CMOS Input. A logic high configures the CLK and CLK inputs for a differential input signal. A logic low
configures the input for single-ended CMOS applied to the CLK pin. AC-couple the unused CLK to
ground with a 0.1 μF capacitor.
Serial Data Input and Output (SPI)/Serial Data (I2C)/Pin Programming. Pin 24 is a multipurpose input
controlled by the PROG_SEL pin used for SPI (SDIO), I2C (SDA), and pin strapping modes (S1). When the
device is in 4-wire SPI mode, data is written via SDIO. In 3-wire mode, both data reads and writes occur
on this pin. There is no internal pull-up/pull-down resistor on this pin. In I2C mode, SDA serves as the
serial data pin. The PROG_SEL pin determines which programming mode is used. In pin programming
mode, this pin becomes S1. In this mode, S1 is hardwired with a resistor to either VDD or ground. The
resistor value and resistor biasing determine the channel divider values for the outputs on Pin 7 and
Pin 8. See the Pin Strapping to Program on Power-Up section for more details.
Exposed Pad. The exposed die pad must be connected to ground (VSS).
E
A
E
A
A
A
E
A
19
20
SCLK/SCL/S0
SYNC
E
A
A
E
A
21
22
23
CLK
CLK
IN_SEL
E
A
A
E
A
A
E
A
24
SDIO/SDA/S1
EP
Rev. A | Page 12 of 40
A
Data Sheet
AD9508
TYPICAL PERFORMANCE CHARACTERISTICS
700
600
TIME (250ps/DIV)
400
100
300
500
700
900
1100
1300
11161-006
500
11161-003
VOLTAGE (100mV/DIV)
DIFFERENTIAL OUTPUT SWING (mV p-p)
800
1500
FREQUENCY (MHz)
Figure 6. LVDS Differential Output Swing vs. Frequency
Figure 3. LVDS Differential Output Waveform @ 800 MHz
TIME (1.5ns/DIV)
780
760
740
720
700
2.3
2.5
2.7
2.9
3.1
3.3
11161-008
11161-004
VOLTAGE (100mV/DIV)
DIFFERENTIAL OUTPUT SWING (mV p-p)
800
3.5
POWER SUPPLY (V)
Figure 7. LVDS Differential Output Swing vs. Power Supply Voltage
Figure 4. LVDS Differential Output Waveform @ 156.25 MHz
200
2.4
ONE OUTPUT (mA)
TWO OUTPUTS (mA)
THREE OUTPUTS (mA)
FOUR OUTPUTS (mA)
PROPAGATION DELAY (ns)
2.3
CURRENT (mA)
150
100
50
2.2
2.1
2.0
1.9
0
400
800
FREQUENCY (MHz)
1200
1600
Figure 5. Power Supply Current vs. Frequency and Number of Outputs Used,
LVDS
Rev. A | Page 13 of 40
1.7
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
INPUT DIFFERENTIAL (V p-p)
Figure 8. LVDS Propagation Delay vs. Input Differential Voltage
11161-009
0
11161-005
1.8
AD9508
Data Sheet
2.6
VOLTAGE (300mV/DIV)
PROPAGATION DELAY (ns)
2.4
2.2
2.0
1.8
500
700
900
1100
1300
1500
COMMON-MODE VOLTAGE (mV)
TIME (5ns/DIV)
11161-010
1.4
300
Figure 12. CMOS Output Waveform @ 50 MHz with 10 pF Load
Figure 9. LVDS Propagation Delay vs. Input Common-Mode Voltage
60
125
DIVIDER 1
DIVIDER 2 (FREQUENCY RANGE NORMALIZED FROM 0Hz TO 800MHz)
DIVIDER 3 (FREQUENCY RANGE NORMALIZED FROM 0Hz TO 500MHz)
ONE OUTPUT (mA)
TWO OUTPUTS (mA)
THREE OUTPUTS (mA)
FOUR OUTPUTS (mA)
FIVE OUTPUTS (mA)
SIX OUTPUTS (mA)
SEVEN OUTPUTS (mA)
EIGHT OUTPUTS (mA)
100
CURRENT (mA)
55
50
75
0
200
400
600
800
1000
1200
1400
1600
FREQUENCY (MHz)
25
25
11161-011
40
50
75
100
125
150
175
200
225
250
FREQUENCY (MHz)
11161-014
50
45
Figure 13. Power Supply Current vs. Frequency vs. Number of Outputs Used,
CMOS
Figure 10. LVDS Output Duty Cycle vs. Output Frequency
1.9
300Ω LOAD
500Ω LOAD
750Ω LOAD
1kΩ LOAD
1.8
OUTPUT SWING (V p-p)
VOLTAGE (300mV/DIV)
1.7
1.6
TIME (1.25ns/DIV)
1.4
0
50
100
150
200
250
FREQUENCY (MHz)
Figure 11. CMOS Output Waveform @ 200 MHz with 10 pF Load
Figure 14. CMOS Output Swing vs. Frequency and Resistive Load
Rev. A | Page 14 of 40
11161-015
1.5
11161-012
DUTY CYCLE (%)
11161-013
1.6
Data Sheet
AD9508
2.0
VOLTAGE (300mV/DIV)
OUTPUT SWING (V p-p)
1.8
1.6
1.4
1.2
0
50
100
150
200
250
FREQUENCY (MHz)
TIME (1.5ns/DIV)
Figure 18. HSTL Differential Output Waveform @ 156.25 MHz
200
1.7
150
CURRENT (mA)
1.9
1.3
ONE OUTPUT (mA)
TWO OUTPUTS (mA)
THREE OUTPUTS (mA)
FOUR OUTPUTS (mA)
100
50
0
50
100
150
200
250
FREQUENCY (MHz)
Figure 16. CMOS Output Swing vs. Frequency and Capacitive Load
(2 pF, 5 pF, 10 pF, 20 pF)
0
11161-017
1.1
0
400
800
1600
1200
FREQUENCY (MHz)
11161-020
2pF LOAD
5pF LOAD
10pF LOAD
20pF LOAD
Figure 19. Power Supply Current vs. Frequency and Number of Outputs Used,
HSTL
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
100
300
500
700
900
1100
1300
1500
FREQUENCY (MHz)
Figure 20. HSTL Differential Output Swing vs. Frequency
Figure 17. HSTL Differential Output Waveform @ 800 MHz
Rev. A | Page 15 of 40
11161-007
11161-018
TIME (250ps/DIV)
DIFFERENTIAL OUTPUT SWING (mV p-p)
2.0
VOLTAGE (300mV/DIV)
OUTPUT SWING (V p-p)
Figure 15. CMOS Output Swing vs. Frequency and Temperature (10 pF Load)
1.5
11161-019
1.0
11161-016
–40°C
+25°C
+85°C
AD9508
Data Sheet
60
DIVIDER 1
DIVIDER 2 (FREQUENCY RANGE NORMALIZED FROM 0Hz TO 800MHz)
DIVIDER 3 (FREQUENCY RANGE NORMALIZED FROM 0Hz TO 500MHz)
1.9
DUTY CYCLE (%)
55
1.8
1.7
50
45
2.5
2.7
2.9
3.1
3.5
3.3
POWER SUPPLY (V)
40
0
140
2.2
130
JITTER (fs rms)
2.3
2.1
2.0
100
1.8
90
80
1.0
1.2
1.4
1.6
1.8
2.0
INPUT DIFFERENTIAL (V p-p)
1000
1200
1400
1600
110
1.9
0.8
800
120
11161-022
PROPAGATION DELAY (ns)
150
0.6
600
Figure 24. HSTL Output Duty Cycle vs. Output Frequency
2.4
0.4
400
FREQUENCY (MHz)
Figure 21. HSTL Differential Output Swing vs. Power Supply Voltage
1.7
0.2
200
0
2
4
6
8
10
SLEW RATE (V/ns)
11161-227
1.5
2.3
11161-024
1.6
11161-021
DIFFERENTIAL OUTPUT SWING (mV p-p)
2.0
Figure 25. Additive Broadband Jitter vs. Input Slew Rate, LVDS, HSTL
(Calculated from SNR of ADC Method)
Figure 22. HSTL Propagation Delay vs. Input Differential Voltage
–80
2.6
HSTL 155.52MHz
HSTL 311.04MHz
HSTL 622.08MHz
–90
–100
PHASE NOISE (dBc/Hz)
PROPAGATION DELAY (ns)
2.4
2.2
2.0
1.8
–110
–120
–130
–140
–150
1.6
500
700
900
1100
COMMON-MODE VOLTAGE (mV)
1300
1500
Figure 23. HSTL Propagation Delay vs. Input Common-Mode Voltage
Rev. A | Page 16 of 40
–170
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
Figure 26. Absolute Phase Noise in HSTL Mode with Clock Input @
622.08 MHz and Outputs = 622.08 MHz, 311.04 MHz, 155.52 MHz
11161-228
1.4
300
11161-023
–160
Data Sheet
AD9508
–80
–90
–90
–100
–100
PHASE NOISE (dBc/Hz)
–110
–120
–130
–140
1
–120
AMPLITUDE
1.
2.
3.
4.
5.
6.
7.
–116.04dBc/Hz
–126.68dBc/Hz
–135.27dBc/Hz
–142.56dBc/Hz
–159.42dBc/Hz
–161.97dBc/Hz
–164.55dBc/Hz
10Hz
100Hz
1kHz
10kHz
100.5kHz
1MHz
10MHz
2
–130
3
4
–140
–150
5
6
7
–160
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
–170
10
Figure 27. Absolute Phase Noise in LVDS Mode with Clock Input @
622.08 MHz and Outputs = 622.08 MHz, 311.04 MHz, 155.52 MHz
100
1k
10k
100k
1M
–90
–90
–100
–100
PHASE NOISE (dBc/Hz)
–80
–110
–120
–130
–140
1
–110
2
–120
MARKER
FREQUENCY
AMPLITUDE
1.
2.
3.
4.
5.
6.
7.
8.
–112.35dBc/Hz
–118.81dBc/Hz
–127.84dBc/Hz
–135.97dBc/Hz
–151.91dBc/Hz
–157.87dBc/Hz
–159.78dBc/Hz
–157.88dBc/Hz
10Hz
100Hz
1kHz
10kHz
100.5kHz
1MHz
10MHz
20MHz
3
–130
4
–140
–150
–150
–160
–160
5
6
1000
100000
–170
10
11161-230
1
10000000
FREQUENCY OFFSET (MHz)
100
1k
10k
100k
1M
8
7
10M
100M
FREQUENCY (Hz)
Figure 31. Additive Phase Noise with Clock Input = 622.08 MHz with HSTL
Outputs = 155.52 MHz
Figure 28. Absolute Phase Noise of Clock Source @ 622.08 MHz
–80
–80
–90
2
–100
3
–110
4
–120
–130
MARKER
FREQUENCY
AMPLITUDE
1.
2.
3.
4.
5.
6.
7.
8.
–89.57dBc/Hz
–100.45dBc/Hz
–109.97dBc/Hz
–116.93dBc/Hz
–135.33dBc/Hz
–144.39dBc/Hz
–148.66dBc/Hz
–149.78dBc/Hz
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
100MHz
–90
1
–100
PHASE NOISE (dBc/Hz)
1
5
–140
6
7
8
2
–110
–140
–160
–160
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100M
Figure 29. Additive Phase Noise with Clock Input = 1474.56 MHz with HSTL
Outputs = 1474.76 MHz
4
MARKER
FREQUENCY
AMPLITUDE
1.
2.
3.
4.
5.
6.
7.
8.
–100.17dBc/Hz
–109.18dBc/Hz
–117.67dBc/Hz
–124.94dBc/Hz
–143.83dBc/Hz
–151.64dBc/Hz
–153.81dBc/Hz
–152.87dBc/Hz
10Hz
100Hz
1kHz
10kHz
100.5kHz
1MHz
10MHz
20MHz
–130
–150
–170
10
3
–120
–150
–170
10
11161-329
PHASE NOISE (dBc/Hz)
100M
Figure 30. Additive Phase Noise with Clock Input = 1500 MHz with HSTL
Outputs = 100 MHz
–80
–170
10M
FREQUENCY (Hz)
11161-129
100
11161-229
–160
10
11161-330
–150
PHASE NOISE (dBc/Hz)
–110
MARKER
FREQUENCY
5
100
1k
10k
100k
FREQUENCY (Hz)
6
7
1M
10M
8
100M
11161-130
PHASE NOISE (dBc/Hz)
–80
LVDS 155.52MHz
LVDS 311.04MHz
LVDS 622.08MHz
Figure 32. Additive Phase Noise with Clock Input = 622.08 MHz with LVDS
Outputs = 622.08 MHz
Rev. A | Page 17 of 40
AD9508
Data Sheet
–80
–90
PHASE NOISE (dBc/Hz)
–100
–110 1
–120
MARKER
FREQUENCY
AMPLITUDE
1.
2.
3.
4.
5.
6.
7.
8.
–114.15dBc/Hz
–127.18dBc/Hz
–134.13dBc/Hz
–141.63dBc/Hz
–154.66dBc/Hz
–155.37dBc/Hz
–152.86dBc/Hz
–153.09dBc/Hz
10Hz
100Hz
1kHz
10kHz
100.5kHz
1MHz
10MHz
20MHz
2
–130
3
4
–140
–150
5
6
100k
1M
7 8
–170
10
100
1k
10k
FREQUENCY (Hz)
10M
100M
11161-131
–160
Figure 33. Additive Phase Noise with Clock Input = 100 MHz with CMOS
Outputs = 100 MHz
Rev. A | Page 18 of 40
Data Sheet
AD9508
TEST CIRCUITS
INPUT/OUTPUT TERMINATION RECOMMENDATIONS
100Ω
0.1µF
AD9508
DOWNSTREAM
DEVICE
WITH HIGH
IMPEDANCE
INPUT AND
INTERNAL
DC-BIAS
CLK
AD9508
100Ω
0.1µF
HSTL OR
LVDS
CLK
AD9508
11161-132
100Ω
CLK
Figure 34. Typical AC-Coupled or DC-Coupled LVDS or HSTL Configurations
11161-136
CLK
Figure 38. AC-Coupled LVDS or HSTL Output Driver (100 Ω Resistor Can Go
on Either Side of Decoupling Capacitors Placed As Close As Possible To The
Destination Receiver)
VCC
Z0 = 50Ω
CLK
SINGLE-ENDED
(NOT COUPLED)
AD9508
AD9508
HSTL OR
LVDS
CLK
LVDS OR 1.8V HSTL
HIGH-IMPEDANCE
DIFFERENTIAL
RECEIVER
100Ω
11161-137
Z0 = 50Ω
VCC
CLK
11161-133
AD9508
CLK
Figure 35. Typical AC-Coupled or DC-Coupled CML Configurations
Figure 39. DC-Coupled LVDS or HSTL Output Driver
VS = 3.3V
CLK
0.1µF
50Ω
Z0 = 50Ω
82Ω
82Ω
50Ω
VCC – 2V
0.1µF
CLK
AD9508
3.3V
LVPECL
SINGLE-ENDED
(NOT COUPLED)
AD9508
1.8V
HSTL
Z0 = 50Ω
127Ω
127Ω
11161-138
AD9508
CLK
CLK
50Ω
11161-134
50Ω
VCC – 2V
Figure 36. Typical AC-Coupled or DC-Coupled LVPECL Configurations
Figure 40. Interfacing the HSTL Driver to a 3.3 V LVPECL Input (This method
incorporates impedance matching and dc biasing for bipolar LVPECL
receivers. If the receiver is self-biased, the termination scheme shown in
Figure 38 is recommended.)
CLK
AD9508
11161-135
CLK
Figure 37. Typical 1.8 V CMOS Configurations for Short Trace Lengths
Rev. A | Page 19 of 40
AD9508
Data Sheet
TERMINOLOGY
Phase Jitter and Phase Noise
An ideal sine wave can be thought of as having a continuous
and an even progression phase with time from 0 degrees to
360 degrees for each cycle. Actual signals, however, display a
certain amount of variation from ideal phase progression over
time. This phenomenon is phase jitter. Although many causes
can contribute to phase jitter, one major cause is random noise,
characterized statistically as being Gaussian (normal) in
distribution.
Phase jitter leads to a spreading out of the energy of the sine wave
in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of
values whose units are dBc/Hz at a given offset in frequency
from the sine wave (carrier). The value is a ratio (expressed in
dB) of the power contained within a 1 Hz bandwidth with respect
to the power at the carrier frequency. For each measurement,
the offset from the carrier frequency is also given.
It is meaningful to integrate the total power contained within
some interval of offset frequencies (for example, 10 kHz to
10 MHz). This is called the integrated phase noise over that
frequency offset interval and can be readily related to the time
jitter due to the phase noise contained within that offset frequency
interval.
Phase noise has a detrimental effect on the performance of
ADCs, DACs, and RF mixers. It lowers the achievable dynamic
range of the converters and mixers, although they are affected
in somewhat different ways.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as with time jitter. When
observing a sine wave, the time of successive zero crossings
varies. In a square wave, the time jitter is a displacement of the
edges from their ideal (regular) times of occurrence. In both
cases, the variations in timing from the ideal are the time jitter.
Because these variations are random in nature, the time jitter is
specified in units of seconds root mean square (rms) or one
sigma of the Gaussian distribution.
Time jitter that occurs on a sampling clock for a DAC or an
ADC decreases the SNR and dynamic range of the converter.
A sampling clock with the lowest possible jitter provides the
highest performance from a given converter.
Additive Phase Noise
Additive phase noise is the amount of phase noise that is
attributable only to the device or subsystem being measured.
The residual phase noise system makes use of two devices
operating in perfect quadrature. The correlated noise of any
external components common to both devices (such as clock
sources) is not present. This makes it possible to predict the
degree to which the device is going to affect the total system
phase noise when used in conjunction with the various oscillators
and clock sources, each of which contribute their own phase
noise to the total. In many cases, the phase noise of one element
dominates the system phase noise.
Additive Time Jitter
Additive time jitter refers to the amount of time jitter that is
attributable to the device or subsystem being measured. It is
calculated by integrating the additive phase noise over a specific
range. This makes it possible to predict the degree to which the
device is going to impact the total system time jitter when used
in conjunction with the various oscillators and clock sources,
each of which contribute their own time jitter to the total. In
many cases, the time jitter of the external oscillators and clock
sources dominates the system time jitter.
Rev. A | Page 20 of 40
Data Sheet
AD9508
THEORY OF OPERATION
DETAILED BLOCK DIAGRAM
VDD
LDO
EXT_CAP0
LVDS/HSTL/CMOS
OUTPUTS
SUB LDO
CLK
10-BIT
DIVIDER
11-BIT
∆Φ
OUT0
10-BIT
DIVIDER
11-BIT
∆Φ
OUT1
10-BIT
DIVIDER
11-BIT
∆Φ
OUT2
10-BIT
DIVIDER
11-BIT
∆Φ
OUT3
CLK
IN_SEL
SPI/I2C/PIN_
PROG
PROG_SEL
SPI
INTERFACE
SDIO/SDA/S1
SDO/S3
OUT1
REVISION ID
CS/S2
SCLK/SCL/S0
OUT0
DIGITAL LOGIC
AND
REGISTERS
SUB LDO
OUT2
OUT3
S4
S5
SCL
SDA
EXT_CAP1
I2 C
INTERFACE
LDO
VDD
6
COARSE
A/D
PIN PROGRAM
READ CONTROL
11161-139
SYNC
RESET
Figure 41. Detailed Block Diagram
The AD9508 accepts either a differential input clock applied to
the CLK and CLK pins or a single-ended 1.8 V CMOS clock
applied to the CLK pin. The input clock signal is sent to the clock
distribution section, which has programmable dividers and
phase offset adjustment. The clock distribution section operates
at speeds of up to 1650 MHz.
The divider range under SPI or I2C control ranges from 1 to
divide-by-1024 and the phase offset adjustment is equipped with
11 bits of resolution. However, in pin programming mode, the
divider range is limited to a maximum divide-by-16 and there is
no phase offset adjustment available.
The outputs can be configured to as many as four LVDS/HSTL
differential outputs or as many as eight 1.8 V CMOS singleended outputs. In addition, the output current for the different
outputs is adjustable for output drive strength.
The device can be powered with either a 3.3 V or 2.5 V external
supply; however, the internal supply on the chip runs off an
internal 1.8 V LDO, delivering high performance with minimal
power consumption.
PROGRAMMING MODE SELECTION
The AD9508 supports both SPI and I2C protocols, and a pin
strapping option to program the device. The active interface
depends on the logic state of the PROG_SEL pin. See Table 13
for programming mode selections. See the Serial Control Port
and Pin Strapping to Program on Power-Up sections for more
detailed information.
Table 13. SPI/I2C/Pin Serial Port Setup
PROG_SEL
Float
Logic 0
Logic 1
SPI/I²C/Pin
SPI
I²C
Pin programming control
CLOCK INPUT
The IN_SEL pin controls the desired input clock configuration.
When the IN_SEL pin is set for single-ended operation, the
device expects 1.8 V, 2.5 V, or 3.3 V CMOS-compatible logic
levels on the CLK input pin. Bypass the unused CLK pin to
ground with a 0.1 μF capacitor.
When the IN_SEL pin is set for differential input clock mode,
the inputs of the AD9508 are internally self biased. The internal
Rev. A | Page 21 of 40
AD9508
Data Sheet
inputs have a resistor divider, which sets the common-mode
level. The complementary input is biased about 30 mV lower
than the true input to avoid oscillations in the event that the
input signal ceases. See Figure 42 for the equivalent differential
input circuit.
VDD
VDD
OUTxA
11161-142
OUTxB
VDD
13kΩ
Figure 44. CMOS Equivalent Output Circuit
16.5kΩ
16kΩ
GND
11161-140
CLK
Figure 42. AD9508 Differential Input Stage
The inputs can be ac-coupled or dc-coupled in differential
mode. See Table 14 for input logic compatibility. The user can
supply a single-ended input with the input in differential mode
by ac or dc coupling to one side of the differential input and
bypassing the other input to ground by a capacitor.
Note that jitter performance degrades with low input slew rate,
as shown in Figure 25. See Figure 34 through Figure 37 for
different input clock termination schemes.
CLOCK OUTPUTS
Each channel output driver can be configured for either a
differential LVDS/HSTL output or two single-ended CMOS
outputs. When the LVDS/HSTL driver is enabled, the
corresponding CMOS driver is in tristate. When the CMOS
driver is enabled, the corresponding LVDS/HSTL driver is
powered down and tristated. See Figure 43 and Figure 44 for
the equivalent output stages.
In LVDS or HSTL modes, there are register settings to control the
output logic type and current drive strength. The LVDS output
current can be set to the nominal 3.5 mA, additional settings
include 0.5, 0.75, 1.0 (default), and 1.25 multiplied by 3.5 mA.
The HSTL output current can be set to 8 mA (nominal) or
16 mA (double amplitude). For pin programming mode, see the
Pin Strapping to Program on Power-Up section for details and
limitations of the device. Under pin programming mode, the
nominal current is the default setting and is nonadjustable.
When routing single-ended CMOS signals, avoid driving multiple
input receivers with one output. Series termination at the source
is generally required to provide transmission line matching and/or
to reduce current transients at the driver. The value of the series
resistor is dependent on the board design and timing requirements (typically 10 Ω to 100 Ω). CMOS outputs are also limited in
terms of the capacitive load or trace length that they can drive.
Typically, trace lengths less than 3 inches are recommended to
preserve signal rise/fall times and signal integrity.
AD9508
10Ω
60.4Ω
(1.0 INCH)
CMOS
MICROSTRIP
VDD
11161-143
12.5kΩ
CLK
Figure 45. Series Termination of CMOS Output
OUTx
11161-141
OUTx
Figure 43. LVDS/HSTL Output Simplified Equivalent Circuit
Table 14. CLK and CLK Differential Input Logic Compatibility
E
A
Supply (V)
3.3
2.5
1.8
3.3 1
2.51
1.81
1.5
N/A 2
3.3
2.5
1.8
1F
2F
1
2
A
Logic
CML
CML
CML
CMOS
CMOS
CMOS
HSTL
LVDS
LVPECL
LVPECL
LVPECL
Common Mode (V)
2.9
2.1
1.4
1.65
1.25
0.9
0.75
1.25
2.0
1.2
0.5
Output Swing (V)
0.8
0.8
0.8
3.3
2.5
1.8
0.75
0.4
0.8
0.8
0.8
IN_SEL is set for single-ended CMOS mode.
N/A means not applicable.
Rev. A | Page 22 of 40
AC-Coupled
Yes
Yes
Yes
Not allowed
Not allowed
Not allowed
Yes
Yes
Yes
Yes
Yes
DC-Coupled
Not allowed
Not allowed
Yes
Yes
Yes
Yes
Yes
Yes
Not allowed
Yes
Yes
Data Sheet
AD9508
CLOCK DIVIDERS
RESET MODES
The four independent channel dividers are 10-bit integer
dividers with a divide range of 1 to 1024 in SPI and I2C modes.
The channel divider block contains duty cycle correction that
guarantees 50% duty cycle for both even and odd divide ratios.
In pin programming mode, divide values of 1 to 8 and 16 are
supported.
The AD9508 has a power-on reset (POR) and other ways to
apply a reset condition to the chip.
PHASE DELAY CONTROL
The AD9508 provides a coarse output phase delay adjustment
between outputs but with a wide delay range that is beneficial
for some applications. The minimum delay step is equivalent to
half the period of the input clock rate. This minimum delay step
can be multiplied from 1 to 2047 times the minimum delay step
to cover a wide delay range. The multiplication of the minimum
delay step is provided for each channel output via the appropriate
internal programming register. Phase delay is not supported in
pin programming mode.
Note that the phase delay adjustment requires the use of the
SYNC function pin. Phase adjustment and output synchronization occurs on the rising edge of the SYNC pin. Therefore, the
SYNC pin must be pulled low and released to produce the
desired phase relationship between outputs. If the SYNC is not
active low prior to a phase delay change, the desired output
phase delay between outputs is not guaranteed to occur;
instead, a random phase delay can occur between outputs.
However, a future SYNC pulse corrects to the desired phase
relationship, if initiated. During the active low SYNC period,
the outputs are forced to a static state.
Figure 46 shows three independent outputs, each set for DIV = 4
of the input clock rate. By incrementing the phase offset value
in the programming registers from 0 to 2, each output is offset
from the initial edge by a multiple of ½ tCLK. Note that the SYNC
signal is not shown in this timing diagram.
0
1
2
3
4
5
6
7
8
9 10
11 12 13 14 15
CLOCK INPUT
CLK
DIVIDER OUTPUTS
DIV = 4, DUTY = 50%
START = 0,
PHASE = 0
Power-On Reset
During chip power-up, an internal power-on reset pulse is
issued when VDD reaches ~1.15 V and restores the chip to the
default on-chip setting. It takes ~20 ms for the outputs to begin
toggling after the power-on reset pulse signal is internally
generated.
In SPI or I2C modes, the default power-on state of the AD9508
is configured as a buffer with the dividers set to divide by 1. In
pin programmable mode, the part is configured per the
hardwiring of the S0 to S5 pins.
Hardware Reset via the RESET Pin
A hard asynchronous reset is executed by briefly pulling RESET
low. This restores the chip to the on-chip default register settings.
It takes ~20 ms for the outputs to begin toggling after RESET is
released.
Soft Reset via the Serial Port
A soft reset is initiated by setting Bit 2 and Bit 5 in Register 0x000.
Except for Register 0x000, when Bit 5 and Bit 2 are set, the chip
enters a soft reset mode and restores the chip to the on-chip
setting. These bits are self clearing. However, the self clearing
operation does not complete until an additional serial port SCLK
cycle occurs, and the AD9508 is held in reset until that happens.
POWER-DOWN MODE
Individual Clock Channel Power-Down
In SPI or I²C programming mode, the clock distribution
channels can be powered down individually by writing to the
appropriate registers. Powering down a clock channel is similar
to powering down an individual driver, but it saves more power
because additional circuits are also powered down. The register
map details the individual power-down settings for each output
channel. These settings are found in Register 0x0F0, Bit 4; Register 0x0F2, Bit 4; Register 0x0F4, Bit 4; and Register 0x0F6, Bit 4.
Note that in all three programming modes, a logic low on the
RESET pin can be used to power down the device.
START = 0,
PHASE = 2
tCLK
11161-144
START = 0,
PHASE = 1
Figure 46. Phase Offset—All Dividers Set for DIV = 4, Phase Set from 0 to 2
Rev. A | Page 23 of 40
AD9508
Data Sheet
OUTPUT CLOCK SYNCHRONIZATION
On power up, the default output channel divider value is divideby-1 if SPI and I2C programming modes are used. Therefore,
there is no real requirement for synchronization after power up
unless a change in divider value or a phase offset value is
desired. A hard asynchronous output synchronization is
executed by briefly pulling the SYNC pin low. This forces the
outputs to be edge aligned regardless of their divide ratio after
the SYNC pin is released.
If the sync mask bit is set to a Logic 1 in any output channel,
those channels continue working uninterrupted while a sync
operation is being applied to other channels. Outputs are pulled
low while SYNC is low if they are not masked by the sync mask
bit. This only applies if outputs are functioning under normal
operation with its logic level set to 11 or toggle mode.
THERMALLY ENHANCED PACKAGE MOUNTING
GUIDELINES
Exposed Metal Paddle
The exposed metal paddle on the AD9508 package is an
electrical connection, as well as a thermal enhancement. For the
device to function properly, the paddle must be properly
attached to ground (VSS). The AD9508 dissipates heat through
its exposed paddle. The PCB acts as a heat sink for the AD9508.
The PCB attachment must provide a good thermal path to a
larger heat dissipation area, such as the ground plane on the
PCB. This requires a grid of vias from the top layer down to the
ground plane. See Figure 47 for an example.
POWER SUPPLY
The AD9508 is designed to work off a 3.3 V + 5% power supply
down to a 2.5 V − 5% power supply. Best practice recommends
bypassing the power supply on the printed circuit board (PCB)
with adequate capacitance (>10 µF) and bypassing all power pins
with adequate capacitance (0.1 µF) as close to the part as possible.
The layout of the AD9508 evaluation board (AD9508/PCBZ),
available at www.analog.com, provides a good layout example
for this device.
11161-145
VIAS TO GND PLANE
Figure 47. PCB Land Example for Attaching Exposed Paddle
Refer to the AN-772 Application Note, A Design and
Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP), for more information about mounting devices with
an exposed paddle.
Rev. A | Page 24 of 40
Data Sheet
AD9508
PIN STRAPPING TO PROGRAM ON POWER-UP
The PROG_SEL input when set to Logic 1 places the AD9508 in
pin strapping control mode without the need for SPI or I2C
operations. In this mode, Pin S0 through Pin S5 program the
desired internal divider value and output logic type for each
output or to set the output to a high-Z state.
The maximum divide value is limited to divide-by-16 and phase
offset delay control is not supported in this mode. LVDS and
HSTL logic types are supported in this mode. However, if HSTL
mode is set and the 100 Ω output termination is removed, the
output swings to 1.8 V CMOS logic levels. In this configuration, the differential outputs of the channel selected become two
single-ended CMOS signals. Those outputs maintain a 180° phase
relationship and share the same channel divider value.
Programming individual outputs and the output logic type is
performed by hardwiring specific resistor values to each of the
S0 to S5 pins. The other side of the resistor is then biased to
ground or VDD, depending on the desired settings. The actual
settings are applied after an internal ADC scans each one of the
S0 to S5 pins. An ADC scan is initiated by either the internal
power-on reset when the device is powered up or by toggling
the SYNC pin. If changes are made after the internal power-on
reset, the SYNC pin must be toggled before any new changes are
accepted.
Table 15 depicts all the pin strapping selections available for
each output channel divider value and logic type. The resistors
listed in Table 15 must have 10% or better tolerance.
Note that if all outputs use an output divider value of one and
use either HSTL outputs or 1.8 V CMOS output levels, then the
S0 to S5 pins can be grounded to accomplish that particular
configuration instead of using the 820 Ω resistor.
Table 15. Selection Table for Pin Strapping Control
Programming
Pins
S0
ADC Voltage Level (0 Through 7) vs. Resistor Value vs. Divide Value and Logic Type
0 = 820 Ω 1 = 1.8 kΩ 2 = 3.9 kΩ 3 = 8.2 kΩ 4 = 820 Ω 5 = 1.8 kΩ 6 = 3.9 kΩ 7 = 8.2 kΩ
Pulled to
Pulled to
Pulled to
Pulled to
Pulled to
Pulled to
Pulled to Pulled to
VDD
VDD
VDD
VDD
GND
GND
GND
GND
÷1
÷2
÷3
÷4
÷5
÷6
÷8
÷16
S1
÷1
÷2
÷3
÷4
÷5
÷6
÷8
÷16
S2
÷1
÷2
÷3
÷4
÷5
÷6
÷8
÷16
S3
÷1
÷2
÷3
÷4
÷5
÷6
÷8
÷16
S4
HSTL/
HSTL
HSTL/
LVDS
HSTL/
high-Z
LVDS/
HSTL
LVDS/
LVDS
LVDS/
high-Z
High-Z/
HSTL
High Z/
high-Z
S5
HSTL/
HSTL
HSTL/
LVDS
HSTL/
high-Z
LVDS/
HSTL
LVDS/
LVDS
LVDS/
high-Z
High-Z/
HSTL
High-Z/
high-Z
Rev. A | Page 25 of 40
Description
SO is assigned to the
Channel 0 divider ratio only
S1 is assigned to the
Channel 1 divider ratio only
S2 is assigned to the
Channel 2 divider ratio only
S3 is assigned to the
Channel 3 divider ratio only
S4 is assigned to Channel 0
and Channel 1 to select their
output logic types
S5 is assigned to Channel 2
and Channel 3 to select their
output logic types
AD9508
Data Sheet
SERIAL CONTROL PORT
The AD9508 serial control port is a flexible, synchronous serial
communications port that provides a convenient interface to
many industry-standard microcontrollers and microprocessors.
The serial control port is compatible with most synchronous
transfer formats, including I²C, Motorola SPI, and Intel SSR
protocols. The serial control port allows read/write access to the
AD9508 register map.
In SPI mode, single- or multiple-byte transfers are supported.
The SPI port configuration is programmable via Register 0x00.
This register is integrated into the SPI control logic rather than
in the register map and it is distinct from the I2C Register 0x00.
SPI/I²C PORT SELECTION
Table 16. Serial Port Mode Selection
S5
Low
High
Low
High
Address
I²C, 1101100
I²C, 1101101
I²C, 1101110
I²C, 1101111
E
A
A
A
E
A
A
During stall high periods, the serial control port state machine
enters a wait state until all data is sent. If the system controller
decides to abort a transfer midstream, the state machine must be
reset either by completing the transfer or by asserting the CS
pin for at least one complete SCLK cycle (but less than eight
SCLK cycles). Deasserting the CS pin on a nonbyte boundary
terminates the serial transfer and flushes the buffer.
A
A
In streaming mode (see Table 17), any number of data bytes can
be transferred in a continuous stream. The register address is
automatically incremented or decremented. CS must be deasserted
at the end of the last byte that is transferred, thereby ending the
stream mode.
E
A
The SDO (serial data output) pin is useful only in unidirectional
I/O mode. It serves as the data output pin for read operations.
The CS (chip select) pin is an active low control that gates read
and write operations. This pin is internally connected to a 30 kΩ
pull-up resistor. When CS is high, the SDO and SDIO pins enter
a high impedance state.
A
A
E
The SDIO (serial data input/output) pin is a dual-purpose pin
and acts either as an input only (unidirectional mode) or as both
an input and an output (bidirectional mode). The AD9508
default SPI mode is bidirectional.
E
A
A
The SCLK (serial clock) pin serves as the serial shift clock. This
pin is an input. SCLK synchronizes serial control port read and
write operations. The rising edge SCLK registers write data bits,
and the falling edge registers read data bits. The SCLK pin
supports a maximum clock rate of 40 MHz.
A
E
A
E
Pin Descriptions
A
Assertion (active low) of the CS pin initiates a write or read
operation to the AD9508 SPI port. For data transfers of three
bytes or fewer (excluding the instruction word), the device
supports the CS stalled high mode. In this mode, the CS pin can
be temporarily deasserted on any byte boundary, allowing time
for the system controller to process the next byte. However, CS
can be deasserted on byte boundaries only; this applies to both
the instruction and data portions of the transfer.
A
SPI SERIAL PORT OPERATION
E
The SPI port supports both 3-wire (bidirectional) and 4-wire
(unidirectional) hardware configurations and both MSB first
and LSB first data formats. Both the hardware configuration
and data format features are programmable. By default, the
AD9508 uses the bidirectional MSB first mode. The reason that
bidirectional is the default mode is so that the user can continue
to write to the device (if it is wired for unidirectional operation)
to switch to unidirectional mode.
E
The AD9508 has two serial interfaces, SPI and I²C. Users can
select either SPI or I²C depending on the state of the PROG_SEL
pin. In I²C operation, four different I²C slave address (seven bits
wide) settings are available, see Table 16. The five MSBs of the
slave address are hardware coded as 11011 and Pin S4 and Pin
S5 program the two LSBs.
S4
Low
Low
High
High
SPI Mode Operation
A
Table 17. Byte Transfer Count
W1
0
0
1
1
W0
0
1
0
1
Bytes to Transfer
1
2
3
Streaming mode
Communication Cycle—Instruction Plus Data
The SPI protocol consists of a two part communication cycle.
The first part is a 16-bit instruction word that is coincident with
the first 16 SCLK rising edges and a payload. The instruction
word provides the AD9508 serial control port with information
regarding the payload. The instruction word includes the R/W
bit that indicates the direction of the payload transfer; that is, a
read or write operation. The instruction word also indicates the
number of bytes in the payload and the starting register address
of the first payload byte.
Rev. A | Page 26 of 40
E
A
A
Data Sheet
AD9508
Write
SPI MSB First and LSB First Transfers
When the instruction word indicates a write operation, the payload
is written into the serial control port buffer of the AD9508. Data
bits are registered on the rising edge of SCLK. The length of the
transfer (one, two, or three bytes or streaming mode) depends
on the W0 and W1 bits in the instruction byte. When not
streaming, CS can be deasserted after each sequence of eight
bits to stall the bus (except after the last byte, where it ends the
cycle). When the bus is stalled, the serial transfer resumes when CS
is asserted. Deasserting the CS pin on a nonbyte boundary resets
the serial control port. Reserved or blank registers are not skipped
automatically during a write sequence. Therefore, the user must
know what bit pattern to write to the reserved registers to preserve
proper operation of the device. Generally, it does not matter what
data is written to blank registers, but it is customary to write 0s.
The AD9508 instruction word and payload can be MSB first or
LSB first; the default is MSB first. The LSB first mode can be set by
writing a 1 to Register 0x00, Bit 6. Immediately after the LSB first
bit is set, subsequent serial control port operations are LSB first.
When MSB first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant payload byte. Subsequent
data bytes must follow, in order, from high address to low address.
In MSB first mode, the serial control port internal address generator decrements for each data byte of the multibyte transfer cycle.
E
A
A
E
A
A
E
A
A
When Register 0x00, Bit 6 = 1 (LSB first), the instruction and
data bytes must be written from LSB to MSB. Multibyte data
transfers in LSB first format start with an instruction byte that
includes the register address of the least significant payload byte,
followed by multiple data bytes. The serial control port internal
byte address generator increments for each byte of the multibyte
transfer cycle.
Most of the serial port registers are buffered. This means that
data written into buffered registers do not take effect until the
user issues an I/O update. An I/O update operation is executed
by writing a Logic 1 to Register 0x0005, Bit 0 (which is an autoclearing bit) or by programming a multifunction pin to perform
the I/O update function and applying an external signal to that
pin. The user can change as many register bits as needed before
executing an I/O update. The I/O update operation transfers the
buffer register contents to their active register counterparts.
For multibyte MSB first (default) I/O operations, the serial control
port register address decrements from the specified starting address
toward Address 0x00. For multibyte LSB first I/O operations, the
serial control port register address increments from the starting
address toward Address 0x2C. Reserved addresses are not skipped
during multibyte I/O operations; therefore, the user writes the
default value to a reserved register and writes 0s to unmapped
registers. Note that it is more efficient to issue a new write
command than to write the default value to more than two
consecutive reserved (or unmapped) registers.
Read
The AD9508 supports the long instruction mode only. If the
instruction word indicates a read operation, the next N × 8
SCLK cycles clock out the data from the address specified in
the instruction word. N is the number of data bytes read and
depends on the W0 and W1 bits of the instruction word. The
readback data is valid on the falling edge of SCLK. Blank registers
are not skipped during readback.
Table 18. Streaming Mode (No Addresses Skipped)
Write Mode
LSB First
MSB First
A readback operation takes data from either the serial control
port buffer registers or the active registers.
Address Direction
Increment
Decrement
Stop Sequence
0x00 … 0x2C
0x2C … 0x00
SPI Instruction Word (16 Bits)
The MSB of the 16-bit instruction word is R/W, which indicates
whether the instruction is a read or a write. The next two bits, W1
and W0, indicate the number of bytes in the transfer. The final 13
bits are the register address (A12 to A0), which indicates the
starting register address of the read/write operation (see Table 19).
E
A
A
Table 19. Serial Control Port, 16-Bit Instruction Word, MSB First Bit Map
MSB
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
LSB
I0
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
E
A
CS
SCLK DON'T CARE
R/W W1 W0 A12 A11 A10 A9 A8
A7
A6 A5
A4 A3 A2
16-BIT INSTRUCTION HEADER
A1 A0
D7 D6 D5
D4 D3
D2 D1
REGISTER (N) DATA
D0
D7
D6 D5
D4 D3 D2
Figure 48. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes of Data
Rev. A | Page 27 of 40
D1 D0
REGISTER (N – 1) DATA
DON'T CARE
11161-028
SDIO DON'T CARE
DON'T CARE
AD9508
Data Sheet
CS
SCLK
DON'T CARE
DON'T CARE
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
SDO DON'T CARE
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
16-BIT INSTRUCTION HEADER
REGISTER (N) DATA
REGISTER (N – 1) DATA
REGISTER (N – 2) DATA
REGISTER (N – 3) DATA
DON'T
CARE
11161-029
SDIO
Figure 49. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes of Data
tDS
tHIGH
tS
tDH
DON'T CARE
SDIO
DON'T CARE
DON'T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
DON'T CARE
11161-030
SCLK
tC
tCLK
tLOW
CS
Figure 50. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements
CS
SCLK
DATA BIT N
11161-031
tDV
SDIO
SDO
DATA BIT N – 1
Figure 51. Timing Diagram for Serial Control Port Register Read
CS
SDIO DON'T CARE
A0 A1 A2 A3
A4
A5 A6 A7
A8
A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4
16-BIT INSTRUCTION HEADER
D5 D6
REGISTER (N) DATA
D7
D0
D1 D2
D3 D4 D5
D6
D7
DON'T CARE
REGISTER (N + 1) DATA
Figure 52. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes of Data
CS
tS
tC
tCLK
tHIGH
tLOW
tDS
SCLK
SDIO
BIT N
BIT N + 1
Figure 53. Serial Control Port Timing—Write
Rev. A | Page 28 of 40
11161-033
tDH
11161-032
DON'T CARE
SCLK DON'T CARE
Data Sheet
AD9508
Table 20. Serial Control Port Timing
Parameter
tDS
tDH
tCLK
tS
tC
tHIGH
tLOW
tDV
Description
Setup time between data and the rising edge of SCLK
Hold time between data and the rising edge of SCLK
Period of the clock
Setup time between the CS falling edge and the SCLK rising edge (start of the communication cycle)
Setup time between the SCLK rising edge and CS rising edge (end of the communication cycle)
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
SCLK to valid SDIO and SDO (see Figure 51)
E
A
A
E
A
I2C SERIAL PORT OPERATION
The I2C interface has the advantage of requiring only two control
pins and is a de facto standard throughout the I2C industry.
However, its disadvantage is the programming speed, which is
400 kbps maximum. The AD9508 I2C port design is based on
the I2C fast mode standard; therefore, it supports both the 100 kHz
standard mode and 400 kHz fast mode. Fast mode imposes a glitch
tolerance requirement on the control signals; that is, the input
receivers ignore pulses of less than 50 ns duration.
A
The transfer of data is shown in Figure 54. One clock pulse is
generated for each data bit transferred. The data on the SDA
line must be stable during the high period of the clock. The
high or low state of the data line can change only when the
clock signal on the SCL line is low.
SDA
The AD9508 allows up to four unique slave devices to occupy
the I2C bus. These slave devices are accessed via a 7-bit slave
address that is transmitted as part of an I2C packet. Only the
device that has a matching slave address responds to subsequent
I2C commands. Table 16 lists the supported device slave
addresses.
I2C Bus Characteristics
Table 21 provides a summary of the various I2C abbreviations
used in the protocol.
Table 21. I2C Bus Abbreviation Definitions
Abbreviation
S
Sr
P
ACK
NACK
W
R
E
A
Definition
Start
Repeated start
Stop
Acknowledge
No acknowledge
Write
Read
CHANGE
OF DATA
ALLOWED
DATA LINE
STABLE;
DATA VALID
Figure 54. Valid Bit Transfer
Start/stop functionality is shown in Figure 55. The start condition
is characterized by a high-to-low transition on the SDA line while
SCL is high. The start condition is always generated by the master
to initialize a data transfer. The stop condition is characterized
by a low-to-high transition on the SDA line while SCL is high.
The stop condition is always generated by the master to terminate
a data transfer. Every byte on the SDA line must be eight bits long.
Each byte must be followed by an acknowledge bit; bytes are sent
MSB first.
The acknowledge bit (ACK) is the ninth bit attached to any
8-bit data byte. An acknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the
byte has been received. The acknowledge bit is communicated
by pulling the SDA line low during the ninth clock pulse after
each 8-bit data byte (see Figure 56).
The no acknowledge bit (NACK) is the ninth bit attached to any
8-bit data byte. The receiving device (receiver) always generates
the no acknowledge bit to inform the transmitter that the byte
has not been received. The no acknowledge bit is communicated by leaving the SDA line high during the ninth clock pulse
after each 8-bit data byte.
A
Rev. A | Page 29 of 40
A
11161-034
SCL
The AD9508 I2C port consists of a serial data line (SDA) and
a serial clock line (SCL). In an I2C bus system, the AD9508 is
connected to the serial bus (data bus SDA and clock bus SCL)
as a slave device; that is, no clock is generated by the AD9508.
The AD9508 uses direct 16-bit memory addressing rather than
traditional 8-bit memory addressing.
AD9508
Data Sheet
SDA
SCL
S
START CONDITION
11161-035
P
STOP CONDITION
Figure 55. Start and Stop Conditions
MSB
ACK FROM
SLAVE RECEIVER
1
SCL
2
3 TO 7
8
9
ACK FROM
SLAVE RECEIVER
1
2
3 TO 7
8
9
S
10
P
11161-036
SDA
Figure 56. Acknowledge Bit
Data Transfer Process
bytes immediately after the slave address byte serve as the internal memory (control registers) address bytes, with the high
address byte first. This addressing scheme gives a memory
address of up to 216 − 1 = 65,535. The data bytes after these
two memory address bytes are register data that are written
to or read from the control registers. In read mode, the data
bytes after the slave address byte are register data that are
written to or read from the control registers.
The master initiates a data transfer by asserting a start condition,
which indicates that a data stream follows. All I2C slave devices
connected to the serial bus respond to the start condition.
The master then sends an 8-bit address byte over the SDA line,
consisting of a 7-bit slave address (MSB first) plus an R/W bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device (0 =
write, 1 = read).
E
A
A
When all data bytes are read or written, stop conditions are
established. In write mode, the master (transmitter) asserts a
stop condition to end data transfer during the 10th clock pulse
following the acknowledge bit for the last data byte from the
slave device (receiver). In read mode, the master device (receiver)
receives the last data byte from the slave device (transmitter)
but does not pull SDA low during the ninth clock pulse. This
condition is known as a no acknowledge bit. By receiving the no
acknowledge bit, the slave device knows that the data transfer is
finished and enters idle mode. The master then takes the data
line low during the low period before the 10th clock pulse and
high during the 10th clock pulse to assert a stop condition.
The peripheral whose address corresponds to the transmitted
address responds by sending an acknowledge bit. All other
devices on the bus remain idle while the selected device waits
for data to be read from or written to it. If the R/W bit is 0, the
master (transmitter) writes to the slave device (receiver). If the
R/W bit is 1, the master (receiver) reads from the slave device
(transmitter). The format for these commands is described in
the Data Transfer Format section.
E
A
A
E
A
Data is then sent over the serial bus in the format of nine clock
pulses: one data byte (eight bits) from either master (write mode)
or slave (read mode) followed by an acknowledge bit from the
receiving device. The number of bytes that can be transmitted
per transfer is unrestricted. In write mode, the first two data
A start condition can be used in place of a stop condition.
Furthermore, a start or stop condition can occur at any time,
and partially transferred bytes are discarded.
MSB
SDA
ACK FROM
SLAVE RECEIVER
1
SCL
2
3 TO 7
8
9
ACK FROM
SLAVE RECEIVER
1
2
3 TO 7
S
8
9
10
P
Figure 57. Data Transfer Process (Master Write Mode, Two-Byte Transfer)
Rev. A | Page 30 of 40
11161-037
A
Data Sheet
AD9508
SDA
ACK FROM
MASTER RECEIVER
1
3 TO 7
2
8
9
1
3 TO 7
2
8
9
11161-039
SCL
NACK FROM
MASTER RECEIVER
10
S
P
Figure 58. Data Transfer Process (Master Read Mode, Two-Byte Transfer)
Data Transfer Format
Write byte format: The write byte protocol writes a register address to the RAM, starting from the specified RAM address.
S
Slave
Address
A
W
E
A
RAM Address
High Byte
A
RAM Address
Low Byte
A
RAM
Data 0
A
RAM
Data 1
A
RAM
Data 2
A
P
Send byte format: The send byte protocol sets up the register address for subsequent reads.
S
Slave Address
A
W
E
A
RAM Address High Byte
A
RAM Address Low Byte
A
P
Receive byte format: The receive byte protocol reads the data byte(s) from RAM, starting from the current address.
S
Slave Address
R
A
RAM Data 0
A
RAM Data 1
A
RAM Data 2
P
A
A
E
Read byte format: This is the combined format of the send byte and the receive byte.
S
Slave
Address
W
E
A
A
RAM
Address
High Byte
A
RAM
Address
Low Byte
A
Sr
Slave
Address
R
A
RAM
Data 0
A
RAM
Data 1
A
RAM
Data 2
A
A
I²C Serial Port Timing
SDA
tLOW
tF
tR
tSU; DAT
tHD; STA
tSP
tBUF
tR
tF
tHD; STA
S
tHD; DAT
tHIGH
tSU; STO
tSU; STA
Sr
Figure 59. I²C Serial Port Timing
Table 22. I2C Timing Definitions
Parameter
fSCL
tBUF
tHD; STA
tSU; STA
tSU; STO
tHD; DAT
tSU; DAT
tLOW
tHIGH
tR
tF
tSP
Description
Serial clock
Bus free time between stop and start conditions
Repeated hold time start condition
Repeated start condition setup time
Stop condition setup time
Data hold time
Date setup time
SCL clock low period
SCL clock high period
Minimum/maximum receive SCL and SDA rise time
Minimum/maximum receive SCL and SDA fall time
Pulse width of voltage spikes that must be suppressed by the input filter
Rev. A | Page 31 of 40
P
S
11161-038
SCL
E
P
AD9508
Data Sheet
REGISTER MAP
Register addresses that are not listed in Table 23 are unused, and writing to those registers has no effect. The user should write the default
value to sections of registers marked reserved.
The abbreviation, R, in the optional (Opt) column in Table 23 means read only and NS means that the value does not change during a soft
reset. Note that the default column is represented by Def.
Table 23. Register Map
Reg
Addr
(Hex)
Opt
Name
D7
D6
Serial Control Port Configuration and Part Identification
0x00
NS
SPI control
SDO enable
LSB first/
increment
address
0x00
NS
I²C control
Reserved
0x0A
R, NS
Silicon rev
0x0B
R, NS
Reserved
0x0C
R, NS
Part ID
0x0D
R,NS
Part ID
Chip Level Functions
0x12
Reserved
0x13
Sleep
Reserved
0x14
NS
OUT0 Functions
0x15
0x16
0x17
0x18
0x19
0x1A
OUT1 Functions
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
OUT2 Functions
0x21
0x22
0x23
0x24
0x25
0x26
OUT3 Functions
0x27
0x28
0x29
0x2A
0x2B
0x2C
SYNC_BAR
PD_0
EN_CMOS_0P
PD_1
EN_CMOS_1P
Soft reset
Reserved
Reserved
Silicon Revision[7:0]
Reserved
Clock Part Family ID[7:0]
Clock Part Family ID[15:8]
PD_2
EN_CMOS_2P
D1
Soft reset
LSB first/
SDO enable
increment
address
Reserved
Soft reset
D0
Def
00
00
00
00
05
00
02
00
Reserved
SYNC_BAR
01
OUT0 Divide Ratio[9:8]
00
00
OUT0 Phase[7:0]
Reserved
OUT0 Phase[10:8]
SYNCMASK0
OUT0 Driver Phase[1:0]
OUT0 Mode[2:0]
Reserved
CMOS_0P_PHASE[1:0]
EN_CMOS_0N
CMOS_0N_PHASE[1:0]
Reserved
00
00
14
00
OUT1 Divide Ratio[9:8]
00
00
OUT1 Phase[7:0]
Reserved
OUT1 Phase[10:8]
SYNCMASK1
OUT1 Driver Phase[1:0]
OUT1 Mode[2:0]
Reserved
CMOS_1P_PHASE[1:0]
EN_CMOS_1N
CMOS_1N_PHASE[1:0]
Reserved
00
00
14
00
OUT2 Divide Ratio[9:8]
OUT2 Phase [7:0]
Reserved
OUT2 Phase[10:8]
SYNCMASK2
OUT2 Driver Phase[1:0]
OUT2 Mode[2:0]
Reserved
CMOS_2P_PHASE[1:0]
EN_CMOS_2N
CMOS_2N_PHASE[1:0]
Reserved
OUT3 Divide Ratio[7:0]
Reserved
PD_3
EN_CMOS_3P
D2
Reserved
Sleep
OUT2 Divide Ratio[7:0]
Reserved
OUT3
Divide
Ratio[9:0]
OUT3
Phase[9:0]
OUT3 Driver
OUT3 CMOS
Soft reset
OUT1 Divide Ratio[7:0]
Reserved
OUT2
Divide
Ratio[9:0]
OUT2
Phase[9:0]
OUT2 Driver
OUT2 CMOS
D3
OUT0 Divide Ratio[7:0]
Reserved
OUT1
Divide
Ratio[9:0]
OUT1
Phase[9:0]
OUT1 Driver
OUT1 CMOS
D4
Reserved
OUT0
Divide
Ratio[9:0]
OUT0
Phase[9:0]
OUT0 Driver
OUT0 CMOS
D5
OUT3 Divide Ratio[9:8]
OUT3 Phase[7:0]
Reserved
OUT3 Phase[10:8]
SYNCMASK3
OUT3 Driver Phase[1:0]
OUT3 Mode[2:0]
Reserved
CMOS_3P_PHASE[1:0]
EN_CMOS_3N
CMOS_3N_PHASE[1:0]
Reserved
Rev. A | Page 32 of 40
00
00
00
00
14
00
00
00
00
00
14
00
Data Sheet
AD9508
REGISTER MAP BIT DESCRIPTIONS
SERIAL PORT CONFIGURATION (REGISTER 0x00)
Table 24. Serial Configuration
Address
0x00
Bits
7
Bit Name
SDO enable
6
LSB first/increment address
5
[4:3]
2
1
0
Soft reset
Reserved
Soft reset
LSB first/increment address
SDO enable
Description
Enables SPI port SDO pin. This bit does nothing in I²C mode.
1 = 4-wire (SDO pin enabled).
0 = 3-wire (default).
Bit order for the SPI port. This bit is nonfunctional in I²C mode.
1 = LSB and byte first. Register addresses are automatically incremented in multibyte
transfers.
0 = MSB and byte first (default). Register addresses are automatically decremented in
multibyte transfers.
Device reset.
Reserved.
Same function as Bit 5 of this register, set Bit 2 and Bit 5 to the same value.
Same function as Bit 6 of this register, set Bit 1 and Bit 6 to the same value.
Same function as Bit 7 of this register, set Bit 7 and Bit 0 to the same value.
SILICON REVISION (REGISTER 0x0A TO REGISTER 0x0D)
Table 25. Silicon Revision
Address
0x0A
0x0B
0x0C
Bits
[7:0]
[7:0]
[7:0]
Bit Name
Silicon Revision[7:0]
Reserved
Clock Part Family ID[7:0]
0x0D
[7:0]
Clock Part Family ID[15:8]
Description
A read-only register. Identifies the revision level of the AD9508.
0x00 = default.
A read-only register. This register, together with Register 0x000D, uniquely identifies an
AD9508. No other device in the Analog Devices, Inc., AD95xx family has a value of 0x0005 in
these two registers.
0x05 = default.
This register is a continuation of Register 0x000C.
0x00 = default.
CHIP LEVEL FUNCTIONS (REGISTER 0x12 TO REGISTER 0x14)
Table 26. Sleep and Synchronization
Address
0x12
0x13
0x14
Bits
[7:0]
[7:5]
4
Bit Name
Reserved
Reserved
Sleep
[3:0]
[7:1]
0
Reserved
Reserved
SYNC_BAR
Description
0x00000010 = default
0x000 = default
0 = disables sleep mode (default)
1 = enables sleep mode
0x0000 = default
0x0000000 = default
0 = enables a software output synchronization routine
1 = output synchronization via software disabled (default)
Rev. A | Page 33 of 40
AD9508
Data Sheet
OUT0 FUNCTIONS (REGISTER 0x15 TO REGISTER 0x1A)
Table 27. Divide Ratio and Phase
Address
0x15
0x16
0x17
0x18
Bits
[7:0]
[7:2]
[1:0]
[7:0]
[7:3]
[2:0]
Bit Name
OUT0 Divide Ratio[7:0]
Reserved
OUT0 Divide Ratio[9:8]
OUT0 Phase[7:0]
Reserved
OUT0 Phase[10:8]
Description
Channel 0 divide ratio, Bits[7:0]
0x00 = default
Channel 0 divide ratio, Bits[9:8]
Channel 0 divider phase, Bits[7:0]
0x00 = default
Channel 0 divider phase, Bits[9:8]
Table 28. Output Driver, Power Down, and Sync
Address
0x19
0x1A
Bits
7
6
Bit Name
PD_0
SYNCMASK0
[5:4]
OUT0 Driver Phase[1:0]
[3:1]
OUT0 Mode[2:0]
0
7
Reserved
EN_CMOS_0P
[6:5]
CMOS_0P_PHASE[1:0]
4
EN_CMOS_0N
[3:2]
CMOS_0N_PHASE[1:0]
[1:0]
Reserved
Description
Channel 0 power down
Setting this bit masks Channel 0 from the output sync function
0 = Channel 0 is synchronized during output sync (default)
1 = Channel 0 is excluded from an output sync
These bits determine the phase of the OUT0 driver
00 = force high
01 = noninverting (default)
10 = inverting
11 = force low
These bits determine the OUT0 driver mode
000 = LVDS 0.5 × 3.5 mA (1/2 amplitude)
001 = LVDS 0.75 × 3.5 mA (3/4 amplitude)
010 = LVDS 1 × 3.5 mA (default)
011 = LVDS 1.25 × 3.5 mA (1.25 amplitude)
100 = HSTL 1 × 3.5 mA (normal amplitude)
101 = HSTL 2 × 3.5 mA (double amplitude)
110 = high-Z/CMOS
111 = high-Z/CMOS
0b = default
Setting this bit enables the OUT0P CMOS driver
0 = disables the OUT0P CMOS driver (default)
1 = enables the OUT0P CMOS driver
These bits determine the phase of the OUT0P CMOS driver
00 = force high (default)
01 = noninverting
10 = inverting
11 = force low
Setting this bit enables the OUT0N CMOS driver
0 = disables the OUT0N CMOS driver (default)
1 = enables the OUT0N CMOS driver
These bits determine the phase of the OUT0N CMOS driver
00 = force high (default)
01 = noninverting
10 = inverting
11 = force low
00b = default
Rev. A | Page 34 of 40
Data Sheet
AD9508
OUT1 FUNCTIONS (REGISTER 0x1B TO REGISTER 0x20)
Table 29. Divide Ratio and Phase
Address
0x1B
0x1C
0x1D
0x1E
Bits
[7:0]
[7:2]
[1:0]
[7:0]
[7:3]
[2:0]
Bit Name
OUT1 Divide Ratio[7:0]
Reserved
OUT1 Divide Ratio[9:8]
OUT1 Phase[7:0]
Reserved
OUT1 Phase[10:8]
Description
Channel 1 divide ratio, Bits[7:0]
0x00 = default
Channel 1 divide ratio, Bits[9:8]
Channel 1 divider phase, Bits[7:0]
0x00 = default
Channel 1 divider phase, Bits[9:8]
Table 30. Output Driver, Power Down, and Sync
Address
0x1F
0x20
Bits
7
6
Bit Name
PD_1
SYNCMASK1
[5:4]
OUT1 Driver Phase[1:0]
[3:1]
OUT1 Mode[2:0]
0
7
Reserved
EN_CMOS_1P
[6:5]
CMOS_1P_PHASE[1:0]
[4]
EN_CMOS_1N
[3:2]
CMOS_1N_PHASE[1:0]
[1:0]
Reserved
Description
Channel 1 power-down
Setting this bit masks Channel 1 from the output sync function
0 = Channel 1 is synchronized during output sync (default)
1 = Channel 1 is excluded from an output sync
These bits determine the phase of the OUT1 driver
00 = force high
01 = noninverting (default)
10 = inverting
11 = force low
These bits determine the OUT1 driver mode
000 = LVDS 0.5 × 3.5 mA (1/2 amplitude)
001 = LVDS 0.75 × 3.5 mA (3/4 amplitude)
010 = LVDS 1 × 3.5 mA (default)
011 = LVDS 1.25 × 3.5 mA (1.25 amplitude)
100 = HSTL 1 × 3.5 mA (normal amplitude)
101 = HSTL 2 × 3.5 mA (double amplitude)
110 = high-Z/CMOS
111 = high-Z/CMOS
0b = default
Setting this bit enables the OUT1P CMOS driver
0 = disables the OUT1P CMOS driver (default)
1 = enables the OUT1P CMOS driver
These bits determine the phase of the OUT1P CMOS driver
00 = force high (default)
01 = noninverting
10 = inverting
11 = force low
Setting this bit enables the OUT1N CMOS driver
0 = disables the OUT1N CMOS driver (default)
1 = enables the OUT1N CMOS driver
These bits determine the phase of the OUT1N CMOS driver
00 = force high (default)
01 = noninverting
10 = inverting
11 = force low
00b = default
Rev. A | Page 35 of 40
AD9508
Data Sheet
OUT2 FUNCTIONS (REGISTER 0x21 TO REGISTER 0x26)
Table 31. Divide Ratio and Phase
Address
0x21
0x22
0x23
0x24
Bits
[7:0]
[7:2]
[1:0]
[7:0]
[7:3]
[2:0]
Bit Name
OUT2 Divide Ratio[7:0]
Reserved
OUT2 Divide Ratio[9:8]
OUT2 Phase[7:0]
Reserved
OUT2 Phase[10:8]
Description
Channel 2 divide ratio, Bits[7:0]
0x00 = default
Channel 2 divide ratio, Bits[9:8]
Channel 2 divider phase, Bits[7:0]
0x00 = default
Channel 2 divider phase, Bits[9:8]
Table 32. Output Driver, Power Down, and Sync
Address
0x25
0x26
Bits
7
6
Bit Name
PD_2
SYNCMASK2
[5:4]
OUT2 Driver Phase[1:0]
[3:1]
OUT2 Mode[2:0]
0
7
Reserved
EN_CMOS_2P
[6:5]
CMOS_2P_PHASE[1:0]
4
EN_CMOS_2N
[3:2]
CMOS_2N_PHASE[1:0]
[1:0]
Reserved
Description
Channel 2 power-down
Setting this bit masks OUT2 from the output sync function
0 = Channel 2 is synchronized during output sync (default)
1 = Channel 2 is excluded from an output sync
These bits determine the phase of the OUT2 driver
00 = force high
01 = noninverting (default)
10 = inverting
11 = force low
These bits determine the OUT2 driver mode
000 = LVDS 0.5 × 3.5 mA (1/2 amplitude)
001 = LVDS 0.75 × 3.5 mA (3/4 amplitude)
010 = LVDS 1 × 3.5 mA (default)
011 = LVDS 1.25 × 3.5 mA (1.25 amplitude)
100 = HSTL 1 × 3.5 mA (normal amplitude)
101 = HSTL 2 × 3.5 mA (double amplitude)
110 = high-Z/CMOS
111 = high-Z/CMOS
0b = default
Setting this bit enables the OUT2P CMOS driver
0 = disables the OUT2P CMOS driver (default)
1 = enables OUT2P CMOS driver
These bits determine the phase of the OUT2P CMOS driver
00 = force high (default)
01 = noninverting
10 = inverting
11 = force low
Setting this bit enables the OUT2N CMOS driver
0 = disables the OUT2N CMOS driver (default)
1 = enables OUT2N CMOS driver
These bits determine the phase of the OUT2N CMOS driver
00 = force high (default)
01 = noninverting
10 = inverting
11 = force low
00b = default
Rev. A | Page 36 of 40
Data Sheet
AD9508
OUT3 FUNCTIONS (REGISTER 0x27 TO REGISTER 0x2C)
Table 33. Divide Ratio and Phase
Address
0x27
0x28
0x29
0x2A
Bits
[7:0]
[7:2]
[1:0]
[7:0]
[7:3]
[2:0]
Bit Name
OUT3 Divide Ratio[7:0]
Reserved
OUT3 Divide Ratio[9:8]
OUT3 Phase[7:0]
Reserved
OUT3 Phase[10:8]
Description
Channel 3 divide ratio, Bits[7:0]
0x00 = default
Channel 3 divide ratio, Bits[9:8]
Channel 3 divider phase, Bits[7:0]
0x00 = default
Channel 3 divider phase, Bits[9:8]
Table 34. Output Driver, Power Down, and Sync
Address
0x2B
0x2C
Bits
7
6
Bit Name
PD_3
SYNCMASK3
[5:4]
OUT3 Driver Phase[1:0]
[3:1]
OUT3 Mode[2:0]
0
7
Reserved
EN_CMOS_3P
[6:5]
CMOS_3P_PHASE[1:0]
4
EN_CMOS_3N
[3:2]
CMOS_3N_PHASE[1:0]
[1:0]
Reserved
Description
Channel 3 power-down
Setting this bit masks OUT3 from the output sync function
0 = Channel 3 is synchronized during output sync (default)
1 = Channel 3 is excluded from an output sync
These bits determine the phase of the OUT3 driver
00 = force high
01 = noninverting
10 = inverting
11 = force low
These bits determine the OUT3 driver mode
000 = LVDS 0.5 × 3.5 mA (1/2 amplitude)
001 = LVDS 0.75 × 3.5 mA (3/4 amplitude)
010 = LVDS 1 × 3.5 mA (default)
011 = LVDS 1.25 × 3.5 mA (1.25 amplitude)
100 = HSTL 1 × 3.5 mA (normal amplitude)
101 = HSTL 2 × 3.5 mA (double amplitude)
110 = high-Z/CMOS
111 = high-Z/CMOS
0b = default
Setting this bit enables the OUT3P CMOS driver
0 = disables the OUT3P CMOS driver (default)
1 = enables OUT3P CMOS driver
These bits determine the phase of the OUT3P CMOS driver
00 = force high (default)
01 = noninverting
10 = inverting
11 = force low
Setting this bit enables the OUT3N CMOS driver
0 = disables the OUT3N CMOS driver (default)
1 = enables OUT3N CMOS driver
These bits determine the phase of the OUT3N CMOS driver
00 = force high (default)
01 = noninverting
10 = inverting
11 = force low
00b = default
Rev. A | Page 37 of 40
AD9508
Data Sheet
PACKAGING AND ORDERING INFORMATION
OUTLINE DIMENSIONS
0.30
0.25
0.18
0.50
BSC
PIN 1
INDICATOR
24
19
18
1
EXPOSED
PAD
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
13
12
2.65
2.50 SQ
2.45
6
7
0.25 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
04-12-2012-A
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
Figure 60. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9508BCPZ
AD9508BCPZ-REEL7
AD9508/PCBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
24-Lead Lead Frame Chip Scale Package (LFCSP_WQ)
24-Lead Lead Frame Chip Scale Package (LFCSP_WQ)
Evaluation Board
Z = RoHS Compliant Part.
Rev. A | Page 38 of 40
Package Option
CP-24-7
CP-24-7
Data Sheet
AD9508
NOTES
Rev. A | Page 39 of 40
AD9508
Data Sheet
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11161-0-4/13(A)
www.analog.com/AD9508
Rev. A | Page 40 of 40