5 4 3 2 1 Table of Contents page 1 Table and Revision page 2 Notes page 3 MCU page 4 OpenSDA page 5 Power and Peripherals Revisions Rev Description Approved Date X1 Initial May 15, 2012 A Release June 29, 2012 A1 Revise J7, J8, J9, JP1. Remove U5. September 3, 2012 A2 Rename J10 for 1x6 connector September 4, 2012 A3 Add R27, R28 with DNP Populate J4, J5 September 6, 2012 A4 Populate R27, R28 and DNP J4, J5 September 6, 2012 B Release September 18, 2012 B1 Label J1 as SWD, release September 20, 2012 Wang Peng Michael Norman D D Wang Peng Michael Norman C C B B Microcontroller Solutions Group A A 6501 William Cannon Drive West Austin, TX 78735-8598 This document contains information proprietary to Freescale Semiconductor and shall not be used for engineering design, procurement or manufacture in whole or in part without the express written permission of Freescale Semiconductor. ICAP Classification: FCP: ____ FIUO: X PUBI: ____ Designer: Drawing Title: Wang Peng FRDM-KL05Z 5 4 3 2 Drawn by: Qiao Jun Page Title: Approved: Michael Norman Size C Document Number Date: Friday, September 21, 2012 Table of Contents/Revisions Rev B1 SCH-27626 PDF:SPF-27626 Sheet 1 1 of 5 5 4 3 2 1 D D C C B B A A ICAP Classification: Drawing Title: FCP: ___ FIUO: X PUBI: ___ FRDM-KL05Z Page Title: NOTES 5 4 3 2 Size C Document Number Date: Friday, September 21, 2012 Rev B1 SCH-27626 PDF:SPF-27626 Sheet 1 2 of 5 5 4 3 2 1 SWD CONNECTOR J1 1 3 5 7 9 D 2 4 6 8 10 PTA2/CMP0_OUT/SWD_DIO 3,4 SWD_CLK/PTA0 3,4,5 D 2 1 P3V3_MCU RST_TGTMCU 3,4,5 HDR 2X5 DNP J6 HDR 1X2 TH DNP There is a bottom-layer trace shorting pin 1 to pin 2 of jumper U1 5 5 P3V3_MCU C PTB6/IRQ_2/FTM0_CH3 PTB7/IRQ_3/FTM0_CH2 3 3 C22 C1 0.1UF 1.0UF 5 5 Vrefh Vrefl 3 EXTAL 3 XTAL PTA5/RTC_CLK_IN/FTM0_CH5/SPI0_SS_b 5 PTA6/FTM0_CH4/SPI0_MISO 5 ADC0_SE11/PTB8/FTM0_CH3 5 ADC0_SE10/PTB9/FTM0_CH2 5 ADC0_SE9/TSI0_IN7/PTB10/FTM0_CH1 5 ADC0_SE8/TSI0_IN6/PTB11/FTM0_CH0 ADC0_SE7/TSI0_IN5/PTA7/IRQ_7/SPI0_MOSI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ADC0_SE6/TSI0_IN4/PTB0/IRQ_8/LLWU_P4/EXTRG_IN/SPI0_SCK ADC0_SE5/TSI0_IN3/DAC0_OUT/CMP0_IN3/PTB1/IRQ_9/UART0_TX/UART0_RX ADC0_SE4/TSI0_IN2/PTB2/IRQ_10/LLWU_P5/UART0_RX/UART0_TX ADC0_SE3/TSI0_IN1/PTA8 ADC0_SE2/TSI0_IN0/PTA9 TSI0_IN11/PTA10/IRQ_12 TSI0_IN10/PTA11/IRQ_13 PTB3/IRQ_14/I2C0_SCL/UART0_TX PTB4/IRQ_15/LLWU_P6/I2C0_SDA/UART0_RX ADC0_SE1/CMP0_IN1/PTB5/IRQ_16/FTM1_CH1/NMI ADC0_SE0/CMP0_IN0/PTA12/IRQ_17/FTM1_CH0/LPTMR0_ALT2 TSI0_IN9/PTA13 TSI0_IN8/PTB12 ADC0_SE13/PTB13/FTM1_CH1/RTC_CLKOUT ADC0_SE12/CMP0_IN2/PTA0/IRQ_0/LLWU_P7/FTM1_CH0/SWD_CLK PTA1/IRQ_1/RESET/LPTMR0_ALT1 PTA2/CMP0_OUT/SWD_DIO EX_PAD PTB6/IRQ_2/FTM0_CH3/LPTMR0_ALT3 PTB7/IRQ_3/FTM0_CH2 VDD VREFH VREFL VSS EXTAL0/PTA3/I2C0_SCL/I2C0_SDA XTAL0/PTA4/LLWU_P0/I2C0_SDA/I2C0_SCL PTA5/LLWU_P1/RTC_CLK_IN/FTM0_CH5/SPI0_SS PTA6/LLWU_P2/FTM0_CH4/SPI0_MISO ADC0_SE11/PTB8/FTM0_CH3 ADC0_SE10/PTB9/FTM0_CH2 ADC0_SE9/TSI0_IN7/PTB10/FTM0_CH1 ADC0_SE8/TSI0_IN6/PTB11/FTM0_CH0 ADC0_SE7/TSI0_IN5/PTA7/IRQ_7/LLWU_P3/SPI0_MISO/SPI0_MOSI 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 ADC0_SE6/TSI0_IN4/PTB0/IRQ_8/EXTRG_IN/SPI0_SCK 5 ADC0_SE5/TSI0_IN3/DAC0_OUT/CMP0_IN3/PTB1/IRQ_9/UART0_TX ADC0_SE4/TSI0_IN2/PTB2/IRQ_10/UART0_RX 5 ADC0_SE3/TSI0_IN1/PTA8 5 ADC0_SE2/TSI0_IN0/PTA9 5 TSI0_IN11/PTA10/IRQ_12 5 TSI0_IN10/PTA11/IRQ_13 5 PTB3/IRQ_14/I2C0_SCL/UART0_TX 5 PTB4/IRQ_15/LLWU_P6/I2C0_SDA/UART0_RX 5 ADC0_SE1/CMP0_IN1/PTB5/IRQ_16/FTM1_CH1 5 ADC0_SE0/CMP0_IN0/PTA12/IRQ_17/FTM1_CH0 5 TSI0_IN9/PTA13 5 TSI0_IN8/PTB12 5 ADC0_SE13/PTB13/FTM1_CH1/RTC_CLKOUT 4,5 SWD_CLK/PTA0 3,4,5 RST_TGTMCU 3,4,5 PTA2/CMP0_OUT/SWD_DIO 3,4 5 C KL05Z32M B B R25 AREF 0 DNP 5 SH1 P3V3_MCU C2 Vrefh 3 3 EXTAL R1 0 Y1 1 SOLDER SHORT 2 C21 C4 10UF C3 0.1UF SH2 C6 0.1uF 1.0UF Vrefl 12PF DNP R2 10M 3 3 4 C7 SOLDER SHORT 32.768KHZ 3 XTAL R3 0 12PF DNP A A FCP: ___ ICAP Classification: Drawing Title: FIUO: X PUBI: ___ FRDM-KL05Z Page Title: MCU 5 4 3 2 Size B Document Number Date: Friday, September 21, 2012 Rev B1 SCH-27626 PDF:SPF-27626 Sheet 1 3 of 5 5 4 3 2 1 TO LEVERAGE OPENSDA INTERFACE IN YOUR DESIGN PLEASE PROVIDE +3.3VDC REGULATION TO P3V3_USBSER FROM P5V0_USBSER VOLTAGE RAIL ALSO PROVIDE +3.3VDC REGULATION TO P3V3 FROM TARGET MCU VOLTAGE RAIL D D U2 P3V3_USBSER 1 VDD1 C9 1.0UF 7 8 P5V0_USBSER S1 TC_VBAT_TP C8 1.0UF SDA_USB_CONN_DP 4 TC_SDA_USB_ID_TP G 33 33 SDA_USB_DN SDA_USB_DP C12 2.2UF D6 USB TYPE B J2 TP3 TP4 L4 P3V3_USBSER R4 10K SDA_SWD_EN VBAT 6 5 4 3 EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0 XTAL0/PTA19/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1 17 18 SDA_EXTAL SDA_XTAL 10 9 Y2 4 1 VREGIN VOUT33 USB0_DM USB0_DP ADC0_SE8/TSI0_CH0/PTB0/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA/LLWU_P5 ADC0_SE9/TSI0_CH6/PTB1/I2C0_SDA/FTM1_CH1/FTM1_QD_PHB C11 22PF DNP 8MHZ 20 21 RST_TGTMCU EXTAL32 XTAL32 3,4,5 P3V3_USBSER R7 C SDA_SWD_OE_B 10K 19 2 UART1_TX_TGTMCU RESET 5 UART1_RX_TGTMCU 330 OHM 5 P3V3_USBSER 2 VSS1 P5V0_USBSER R8 4.7K ADC0_SE15/TSI0_CH14/PTC1/SPI0_PCS3/UART1_RTS/FTM0_CH0/I2S0_TXD0/LLWU_P6 ADC0_SE4B/CMP1_IN0/TSI0_CH15/PTC2/SPI0_PCS2/UART1_CTS/FTM0_CH1/I2S0_TX_FS CMP1_IN1/PTC3/SPI0_PCS1/UART1_RX/FTM0_CH2/CLKOUT/I2S0_TX_BCLK/LLWU_P7 PTC4/SPI0_PCS0/UART1_TX/FTM0_CH3/CMP1_OUT/LLWU_P8 PTC5/SPI0_SCK/LPTMR0_ALT2/I2S0_RXD0/CMP0_OUT/LLWU_P9 CMP0_IN0/PTC6/SPI0_SOUT/PDB0_EXTRG/I2S0_RX_BCLK/I2S0_MCLK/LLWU_P10 CMP0_IN1/PTC7/SPI0_SIN/USB_SOF_OUT/I2S0_RX_FS 22 23 24 25 26 27 28 UART1_TX_TGTMCU UART1_RX_TGTMCU SDA_SPI0_SCK SDA_SPI0_SOUT SDA_SPI0_SIN VCC 2 7 SDA_RST SDA_RST 33 LED GREEN PU/PD LOGIC: SERIAL INTERFACE IS ALWAYS RESET WHEN USB PORT IS DISCONNECTED 3 U4C SDA_LED_R 8 74LVC125ADB SDA_LED C SDA_PTD5 5 U4D 13 29 30 31 32 9 D1 TP6 PTD4/SPI0_PCS1/UART0_RTS/FTM0_CH4/EWM_IN/LLWU_P14 ADC0_SE6B/PTD5/SPI0_PCS2/UART0_CTS/UART0_COL/FTM0_CH5/EWM_OUT ADC0_SE7B/PTD6/SPI0_PCS3/UART0_RX/FTM0_CH6/FTM0_FLT0/LLWU_P15 PTD7/CMT_IRO/UART0_TX/FTM0_CH7/FTM0_FLT1 PTA2/CMP0_OUT/SWD_DIO 74LVC125ADB R10 220 EPAD A TP5 3 GND P3V3_USBSER R9 10K U4A 1 14 2 1 TARGET MCU INTERFACE SIGNALS 3 2 GND2 GND1 C10 22PF DNP TC_EXTAL_TP TC_XTAL_TP TVLS14302AC0 1 SDA_JTAG_TCLK SDA_JTAG_TDI SDA_JTAG_TDO SDA_JTAG_TMS SDA_SWD_EN TP2 3 3 R5 R6 11 12 13 14 15 16 P5V0_USBSER SDA_USB_VOUT33 4 S3 D- VBUS D+ ID SDA_USB_CONN_DN 5 S2 S4 SDA_USBSHIELD C P5V0_SDA_USB_CONN_VBUS 2 JTAG_TCLK/SWD_CLK/EZP_CLK/TSI0_CH1/PTA0/UART0_CTS/UART0_COL/FTM0_CH5 JTAG_TDI/EZP_DI/TSI0_CH2/PTA1/UART0_RX/FTM0_CH6 JTAG_TDO/TRACE_SWO/EZP_DO/TSI0_CH3/PTA2/UART0_TX/FTM0_CH7 JTAG_TMS/SWD_DIO/TSI0_CH4/PTA3/UART0_RTS/FTM0_CH0 NMI/EZP_CS/TSI0_CH5/PTA4/FTM0_CH1/LLWU_P3 TP1 2 330 OHM 1 VSSA 10 L3 1 VDDA 12 B R11 11 SWD_CLK/PTA0 3,5 B 74LVC125ADB SDA_PTD6 A5 0 P5V0_USBSER 3,5 KL05Z Pin ADC0_SE13/PTB13/FTM1_CH1/RTC_CLKOUT PK20DX128VFM5 Target reset and bootloader mode push button OPEN-SDA INTERFACE R12 4.7K P3V3 SDA_USB_P5V_SENSE R13 10K 3,4,5 TP7 SW1 1 RST_TGTMCU C13 1.0UF R14 10K 2 EVQ-PE105K SPARE 74HC125 buffer OPEN-SDA INTERFACE JTAG CONNECTOR P3V3_USBSER P3V3_USBSER R15 10K A J3 4 P3V3_USBSER 1 3 5 7 9 U4B TP11 TP13 TC_74125_SPARE_I_TP 5 6 TC_74125_SPARE_O_TP 2 4 6 8 10 ICAP Classification: Drawing Title: HDR 2X5 DNP 74LVC125ADB A SDA_JTAG_TMS SDA_JTAG_TCLK SDA_JTAG_TDO SDA_JTAG_TDI SDA_RST FCP: ___ FIUO: ___ PUBI: X FRDM-KL05Z Page Title: OPEN-SDA interface 5 4 3 2 Size C Document Number Date: Friday, September 21, 2012 Rev B1 SCH-27626 | PDF: SPF-27626 Sheet 1 4 of 5 4 3 OPTIONAL COIN CELL HOLDER 2 TP15 BT1 3003 3 D 2 1 P3V3_BATT - C14 10uF + DNP P3V3_MCU 2 3 3 VIN C15 10uF NCP1117ST33T3G GND U6 3 VOUT TAB 2 P3V3_VREG 4 C16 10uF 1 R27 BAT54C 0 DNP J5 HDR 1X2 TH 1 P5V0-9V0_VIN TP16 20mOhm Resistor in layout P3V3_USBSER 1 2 RGB LED FEATURE D DNP J4 HDR 1X2 TH P3V3 D3 2 1 P5V0_USBSER D2 BAT54C 1 1 2 5 TP17 TP18 D4 R28 3,5 ADC0_SE11/PTB8/FTM0_CH3 R18 220 1 LEDRGB_RED P3V3 R 4 LEDRGB_GREEN R19 3 LEDRGB_BLUE R20 G 2 B 220 ADC0_SE10/PTB9/FTM0_CH2 220 ADC0_SE9/TSI0_IN7/PTB10/FTM0_CH1 3,5 TP19 CLV1A-FKB-CJ1M1F1BB7R4S3 3 C 0 3,5 4 UART1_TX_TGTMCU 4 UART1_RX_TGTMCU R16 1K R17 1K 3 ADC0_SE4/TSI0_IN2/PTB2/IRQ_10/UART0_RX ADC0_SE5/TSI0_IN3/DAC0_OUT/CMP0_IN3/PTB1/IRQ_9/UART0_TX 3 TSI0_IN10/PTA11/IRQ_13 3 ADC0_SE1/CMP0_IN1/PTB5/IRQ_16/FTM1_CH1 3,5 TSI0_IN11/PTA10/IRQ_12 3 ADC0_SE0/CMP0_IN0/PTA12/IRQ_17/FTM1_CH0 3 PTB6/IRQ_2/FTM0_CH3 3 PTB7/IRQ_3/FTM0_CH2 C DEBUG GROUND HOOK 3,5 ADC0_SE9/TSI0_IN7/PTB10/FTM0_CH1 3 ADC0_SE8/TSI0_IN6/PTB11/FTM0_CH0 3 PTA5/RTC_CLK_IN/FTM0_CH5/SPI0_SS_b 3 ADC0_SE7/TSI0_IN5/PTA7/IRQ_7/SPI0_MOSI 3 PTA6/FTM0_CH4/SPI0_MISO ADC0_SE6/TSI0_IN4/PTB0/IRQ_8/EXTRG_IN/SPI0_SCK 3,5 PTB4/IRQ_15/LLWU_P6/I2C0_SDA/UART0_RX 3,5 PTB3/IRQ_14/I2C0_SCL/UART0_TX 3 DNP AREF 8 7 6 5 4 3 2 1 3 TP20 10 9 8 7 6 5 4 3 2 1 IN CIRCUIT TEST GND PROBING I2C INERTIAL SENSOR J8 CON_1X8 TP21 TP22 DNP TP23 P3V3 P3V3 C17 0.1UF C18 10uF 7 B SCL SDA SA0 INT1 INT2 BYP NC3 NC8 NC13 NC15 NC16 TP24 MMA8451_BYP 2 GND1 GND2 GND3 C19 0.1UF MMA8451Q 11 9 R26 0 B TSI0_IN11/PTA10/IRQ_12 3,5 3 8 13 15 16 5 10 12 R23 10K TP25 14 1 VDDIO 4 6 3,5 PTB3/IRQ_14/I2C0_SCL/UART0_TX PTB4/IRQ_15/LLWU_P6/I2C0_SDA/UART0_RX P3V3_USBSER DNP R22 4.7K U7 3,5 CON_1X10 VDD R21 4.7K J7 P3V3 R24 10K DNP ARDUINO UNO COMPATIBLE SHIELDS DNP J10 CON_1X6 DNP 3,4 1 2 3 4 5 6 1 2 3 4 5 6 7 8 D5 BAT54C C20 2.2UF RST_TGTMCU P3V3 TSI0_IN9/PTA13 P5V_USB_CONNECTORS 3 3 J9 CON_1X8 P3V3 2 1 P5V0_USBSER E1 P5V0-9V0_VIN 4 A TOUCH ELECTRODES 3,4 ADC0_SE11/PTB8/FTM0_CH3 ADC0_SE10/PTB9/FTM0_CH2 3 ADC0_SE3/TSI0_IN1/PTA8 3,4 SWD_CLK/PTA0 3 ADC0_SE2/TSI0_IN0/PTA9 ADC0_SE13/PTB13/FTM1_CH1/RTC_CLKOUT 3,4 Slider_4 3 SDA_PTD5 3,5 3,5 A A0 A1 A2 A3 A5 ICAP Classification: Drawing Title: A5 FCP: ___ FIUO: ___ PUBI: X FRDM-KL05Z TSI0_IN8/PTB12 Page Title: ARDUINO SHIELDS & PWR SUPPLY 5 4 3 2 Size C Document Number Date: Friday, September 21, 2012 Rev B1 SCH-27626 | PDF: SPF-27626 Sheet 1 5 of 5