Features • • • • • • • 10-bit Resolution 1.5 Gsps Sampling Rate Selectable 1:2 or 1:4 Demultiplexed Output 500 mVpp Differential 100Ω or Single-ended 50Ω Analog Input 100Ω Differential or Single-ended 50Ω Clock input LVDS Output Compatibility Functions: – ADC Gain Adjust – Sampling Delay Adjust – 1:4 Demultiplexed Simultaneous or Staggered Digital Outputs – Data Ready Output with Asynchronous Reset – Out-of-range Output Bit (11th Bit) • Power Consumption : 6.5W • Power Supplies: -5V, -2.2V, 3.3V and VPLUSD Output Power Supply • Package – Cavity Down EBGA 317 (Enhanced Ball Grid Array) – 25 × 35 mm Overall Dimensions 10-bit 1.5 Gsps ADC With 1:4 DMUX Performances • 3 GHz Full-power Analog Input Bandwidth • ±0.4 dB Gain Flatness from DC up to 1.5 GHz • Single-tone Performance at Fs = 1.5 Gsps, Full Nyquist Zone • – ENOB = 8.0 Effective Bits, FIN = 750 MHz – SNR = 52 dB, SFDR = -60 dBFS, FIN = 750 MHz AT84AS003 Summary Dual-tone Performance (IMD3) at Fs = 1.5 Gsps (-7 dBFS each tone) – Fin1 = 745 MHz, Fin2 = 755 MHz: IMD3 = -60 dBFS – Fin1 = 1244 MHz, Fin2 = 1255 MHz: IMD3 = -60 dBFS Screening • Temperature Range: – TC > 0°C; TJ < 90°C (Commercial “C” Grade) – TC > -20°C; TJ < 110°C (Industrial “V” Grade) Applications • Direct RF Down Conversion • Ultra Wide Band Satellite Receivers • Radars and Countermeasures • High-speed Acquisition Systems • High Energy Physics • Automatic Test Equipment Description The AT84AS003 combines a 10-bit 1.5 Gsps analog-to-digital converter with a 1:4 DMUX, designed for accurate digitization of broadband signals. It features 8.0 Effective Number of Bits (ENOB) and -60 dBFS Spurious Free Dynamic Range (SFDR) at 1.5 Gsps over the full first Nyquist zone. 5403AS–BDC–10/04 This is a summary document. A complete document is not available at this time. For more information, please contact your local Atmel sales office. The 1:4 demultiplexed digital outputs are LVDS logic compatible, allowing easy interfacing with standard FPGAs or DSPs .The AT84AS003 operates at up to 1.5 Gsps, without additional tuning of the synchronization between the ADC and DMUX. The AT84AS003 comes in a 25 × 35 mm EBGA317 package. This package has the same TCE as FR4 boards, offering excellent reliability when subjected to large thermal variations. Figure 1. Block Diagram BIST ASYNRST PGEB DRRB SDA 2 CLK/CLKN 20 SDA 2 VINN Demultiplexer 1:2 or 1:4 LVDS Buffers S/H Logic Block VIN Quantizer 20 2 20 2 20 2 2 Port A AOR/AORN Port B BOR/BORN Port C COR/CORN Port D DOR/DORN DR/DRN GA B/GB SLEEP STAGG RS DRTYPE 2 AT84AS003 5403AS–BDC–10/04 AT84AS003 Functional Description The AT84AS003 is a 10-bit 1.5 Gsps ADC combined with a high-speed demultiplexer (DMUX) used to lower the LVDS output bit stream (10-bit data and one out-of range bit) by a factor of 2 or 4. The ADC works in fully differential mode from the analog input to the digital outputs. It provides an on-chip 100Ω differential termination for the clock input. The analog input is 500 mVpp on a 100Ω differential input impedance. 50Ω reverse terminations are required for the analog input. They should be placed as close as possible to the EBGA package input pins (2 mm maximum). The output clock and the output data are LVDS compatible (100Ω differentially terminated). The AT84AS003 ADC features two asynchronous resets: • DRRB, which ensures that the first digitized data corresponds to the first acquisition • ASYNCRST, which initializes the DMUX The gain control pin GA is used to finely adjust the ADC gain to a unity gain. The control pin B/GB is provided to select either a binary or gray data output format. A Sampling Delay Adjust function (SDA, activated via the SDAEN signal) may be used to fine-tune the ADC aperture delay by approximately 120 ps around its nominal value. This function is useful when interleaving multiple ADCs. The control pin B/GB is provided to select either a binary or Gray data output format. A tunable delay cell (controlled via CLKDACTRL) is integrated between the ADC and the DMUX on the clock path to fine-tune the data according to the clock alignment at the interface between the ADC and the DMUX. This delay can be tuned from -250 to 250 ps around a default center value, featuring a 500 ps typical tuning range. No tuning should be necessary for operating frequencies up to 1.5 Gsps. An extra stand-alone delay cell is also provided. It is controlled via analog DACTRL control input and activated via DAEN. The tuning range is typically 500 ps. A pattern generator (PGEB) is integrated in the ADC block for debugging purposes or acquisition setup. Similarly, a Built-in Self Test (BIST) is provided for quick debug of the DMUX block. The demultiplexer ratio can be selected using RS (1:2 or 1:4 ratio). Two modes for the output clock (via DRTYPE) are selectable: • DR mode: only the output clock’s rising egde is active, the output clock rate is the same as the output data rate • DR/2 mode: both the output clock’s rising and falling edges are active, the output clock rate is half the output data rate The AT84AS003’s data is output in two different modes: • Staggered: even and odd bits are output with half a data period delay • Simultaneous: even and odd bits are output at the same time A sleep mode is provided to lower the power consumption of the DMUX block. Die junction temperature monitoring is also provided to facilitate management of the junction temperature, by sensing the voltage drop across two diodes implemented on the ADC and DMUX respectively, close to the chip’s hot point. The AT84AS003 is delivered in an Enhanced Ball Grid Array (EBGA). Its TCE, which is similar to that of the FR4 material, makes it highly suitable for applications exposed to large thermal variations. 3 5403AS–BDC–10/04 Table 1. Description of Functions Name Function Name Function VCCA Analog 3.3VV power supply DOR, DORN Additional output bit port D VCCD Digital 3.3V power supply RS DMUX ratio selection signal VEE Analog -5V power supply CLKDACTRL Control signal for clock delay cell VMINUSD Digital -2.2V power supply DACTRL Control signal for standalone delay cell VPLUSD Output 2.5 power supply DAEN Enable signal for standalone delay cell AGND Analog ground DAI, DAIN Input signals for standalone delay cell DGND Digital ground DAO, DAON Output signals for standalone delay cell CLK, CLKN Input clock signals GA ADC gain adjust VIN, VINN Analog input data SDA ADC sampling delay adjust DRRB ADC reset SDAEN ADC SDA enable ASYNCRST DMUX asynchronous reset PGEB ADC pattern generator DR/DRN Output clock signals B/GB Binary or gray output code selection A0…A9 A0N…A9N Output data port A SLEEP Sleep mode selection signal AOR, AORN Additional output bit port A STAGG Staggered mode selection for data outputs B0…B9 B0N…B9N Output data port B CLKTYPE Input clock type selection signal BOR, BORN Additional output bit port B DRTYPE Output clock type selection signal C0…C9 C0N…C9N Output data port C BIST Built-in self test COR, CORN Additional output bit port C DIODE ADC Diode for die junction temperature monitoring (ADC) D0…D9 D0N…D9N Output data port D DIODE DMUX Diode for die junction temperature monitoring (DMUX) 4 AT84AS003 5403AS–BDC–10/04 AT84AS003 Figure 2. Device Pinout VCCA VEE 3.3V -5V -2.2V 3.3V 2.5V VMINUSD VCCD 20 2 VIN, VINN CLK, CLKN DRRB ASYNCRST SDAEN SDA GA PGEB B/GB DACTRL CLKDACTRL DAI, DAIN SLEEP STAGG CLKTYPE RS DAEN BIST DRTYPE VPLUSD 2 2 20 2 20 2 AT84AS003 2 2 20 2 2 2 [A0…A9] [A0N…A9N] AOR, AORN [B0…B9] [B0N…B9N] BOR, BORN [C0…C9] [C0N…C9N] COR, CORN [D0…D9] [D0N…D9N] DOR, DORN DR, DRN DAO, DAON DIODE ADC DIODE DMUX AGND DGND 5 5403AS–BDC–10/04 Package Information Figure 3. EBGA 317 Package Outline (Bottom View) 25 mm 35 mm 25 mm 35 mm 6 AT84AS003 5403AS–BDC–10/04 AT84AS003 Ordering Information Part Number Package Temperature Range Screening Comments AT84XAS003TP EBGA 317 Ambient Prototype Prototype version Please contact your local Atmel sales office AT84AS003CTP EBGA 317 Commercial “C” TC > 0°C; TJ < 90°C Standard AT84AS003VTP EBGA 317 Industrial “V” TC> -20°C; TJ < 110°C Standard AT84AS003TP-EB EBGA 317 Ambient Prototype Evaluation kit 7 5403AS–BDC–10/04 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. © Atmel Corporation 2004. All rights reserved. Atmel® and combinations thereof are the registered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others. Printed on recycled paper. 5403AS–BDC–10/04