Atmel AT88SA102S Atmel CryptoAuthentication Product Authentication Chip DATASHEET Features • • • • • • • • • • • Secure authentication and key exchange Superior SHA-256 hash algorithm Best in class 256-bit key length Guaranteed unique 48-bit serial number High speed single wire interface Supply voltage: 2.7 – 5.25 V 1.8 – 5.25 V communications <150 na sleep current Multi-level hardware security Secure personalization Green compliant (exceeds rohs) 3-pin SOT-23 and 8-pin TSSOP or SOIC packages Applications • • • • • • • • • Authentication of replaceable items Software anti-piracy Network and computer access control Portable media player and GPS system Key exchange for encrypted downloads Prevention of clones for demo and evaluation boards Authenticated communications for control networks Anti-clone authentication for daughter cards Physical access control (electronic lock and key) 8584G−CRYPTO−9/11 Figure 1. Pin Configurations Pin name Function SIGNAL Serial data, single-wire clock and data GND Ground VCC Power supply 8-lead SOIC NC NC NC GND 1. 1 8 2 7 3 6 4 5 8-lead TSSOP 3-lead VCC NC NC SIGNAL 2 GND VCC 3 1 SIGNAL NC 1 8 VCC NC 2 7 NC NC 3 6 NC GND 4 5 SIGNAL Introduction The Atmel® AT88SA102S is a member of the Atmel CryptoAuthentication family of cost-effective authentication chips designed to securely authenticate an item to which it is attached. It can also be used to exchange session keys with some remote entity so that the system microprocessor can securely encrypt/decrypt data. Each AT88SA102S chip contains a preprogrammed serial number which is guaranteed to be unique. In addition, it has been designed to permit secure personalization so that third parties can build devices containing an OEM secret without concern for the theft of that secret. It is the first small standard product to implement the SHA-256 hash algorithm, which is part of the latest set of recommended algorithms by the US Government. The 256-bit key space renders any exhaustive attacks impossible. The CryptoAuthentication family uses a standard challenge response protocol to simplify programming. The system generates a random number challenge and sends it to the AT88SA102S chip. The chip hashes that with a 256-bit key using the SHA-256 algorithm to generate a keyed 256-bit response which is sent back to the system. The chip includes 128-single bit one time programmable fuses that can be used for personalization, status or consumption logging. Atmel programs 40 of these bits prior to the chip leaving the factory, leaving 88 for user purposes. See Section 1.3 for more information. Note: 1.1 The chip implements a failsafe internal watchdog timer that forces it into a very low power mode after a certain time interval regardless of any command execution or IO transfers that may be happening at the time the timer expires. System programming must take this into consideration. See Section 5.4 for more details Usage There are many different ways in which the AT88SA102S can add an authentication capability to a system. For more information, see the “Atmel CryptoAuthentication Usage Examples” applications note. In general, however, all these security models usually employ one of two general key management strategies: • • Fixed challenge response number pair stored in the host. In this case, the host sends its particular challenge and only an authentic AT88SA102S can generate the correct response. Since no secret is stored on the host, there is no security cost on the host. Depending on the particulars of the system, each host may have a different challenge response pair and/or each client may have the same key. Host computes the response that should be provided for a particular client against a random challenge and/or include the client ID number in the calculation. In this case, the host needs to have the capability to securely store the secret from which diversified response will be computed. One way to do this is to use a CryptoAuthentication host chip. Since each client is unique, the host can maintain a dynamic black list of clients that have been found to be fraudulent. Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 2 1.2 1.3 Memory Resources Fuse Block of 128-fuse bits that can be written through the one wire interface. Fuse and Fuse have special meanings, see Section 1.3 for more details. Fuse[88:95] are part of the manufacturing ID value fixed by Atmel. Fuse[96:127] are part of the serial number programmed by Atmel which is guaranteed to be unique. See Section 1.4 for more details on the Manufacturing ID and Serial Number. ROM Metal mask programmed memory. Unrestricted reads are permitted on the first 64-bits of this array. The physical ROM will be larger and will contain other information that cannot be read. ROM MfrID 2-bytes of ROM that specifies part of the manufacturing ID code. This value is assigned by Atmel and is always the same for all chips of a particular model number. For the AT88SA102S, this value is 0x2301 (appears on the bus: 0x0123), ROM MfrID can be read by accessing ROM bytes 0 and 1 of Address 0. ROM SN 2-bytes of ROM that can be used to identify chips among others on the wafer. These bits reduce the number of fuses necessary to construct a unique serial number. The ROM SN is read by accessing ROM bytes 2 and 3 of Address 0. ROM SN can always be read by the system and is optionally included in the message digested by the MAC command. RevNum 4-bytes of ROM that are used by Atmel to identify the model mask and/or design revision of the AT88SA102S chip. These bytes can be freely read as the four bytes returned ROM address one, however system code should not depend on this value as it may change from time to time. Fuse Map The AT88SA102S incorporates 128 one-time fuses within the chip. Once burned, there is no way to reset the value of a fuse. Fuses, with the exception of the manufacturer ID and serial number bits initialized by Atmel have a value of one when shipped from the Atmel factory and transition to a zero when they are burned. Bits 0-63 can never be read, while bits 64-128 can always be read. Table 1-1. The 128 Fuses in the Atmel AT88SA102S Chip are Arranged in the Following Manner Fuse # Name Description 1 BurnFuse Enable If this fuse is one, then the BurnFuse command is enabled. If it is burned to zero, then the BurnFuse command is disabled 0 and 2 63 Secret Fuses These fuses can be securely written by the BurnSecure command but can never be read directly with the Read command 64 83 Status Fuses These fuses can be written with the BurnSecure command and can always be read with the Read command. They are totally user-defined. 84 86 Status Fuses These fuses can be written with the BurnSecure command and can always be read with the Read command. They are user-defined, but have special significance for the Pause Long command. See Section 6.6. 87 Fuse Disable The MAC command ignores the values of Fuse[0-86] while this fuse is an one Once it is burned to zero, the BurnSecure command is disabled 88 95 Fuse MfrID See Section 1.4. Set by Atmel; cannot be modified in the field 96 127 Fuse SN See Section 1.4. Set by Atmel; cannot be modified in the field BurnFuse Enable This fuse is used to prevent operation of the BurnFuse command in the application. This fuse may only be burned to 0 using the BurnSecure command. Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 3 Secret Fuses These 63-fuses are used to augment the keys stored elsewhere in the chip. Knowledge of both the internally stored keys and the values of the Secret Fuses are required to generate the correct response to the Cryptographic command of the AT88SA102S. An arbitrary selection of these fuses is burned during personalization via the BurnSecure command. Within this document, “Secret Fuses” is used to refer to the entire array of 64-bits: Fuse[0-63], even though the value of Fuse is fixed for most applications and its value can be derived from the operation of the chip. Status Fuses These 23-fuses can be used to store information which is not secret, as their value can always be determined using the read command. They can be written at the same time as the secret fuses using the BurnSecure command, or they can be individually burned at a later time with the BurnFuse command. Two common usage models for these fuses are: 1. Calibration or model number information. In this situation, the 23-bits are written at the factory. This method can also be used for feature enabling. In this case, the BurnFuse command should not be run in the field, and the BurnFuse Enable bit should be zero. 2. Consumption logging, i.e. burn one bit after every n uses, the host system keeps track of the number of uses so far for this serial number. In this case, the BurnFuse command is necessary to individually burn one of these 23-bits, and the BurnFuse enable bit should be a one. Within this document, “Status Fuses” is used to refer to the entire array of 24-bits: Fuse[64-87], even though the value of Fuse is fixed after personalization and cannot be modified in the field. Fuse Disable 1.4 This fuse is used to disable/enable the ability of the MAC command to read the fuse values until the BurnSecure command has completed properly. When it has a value of one (unburned), the bit values in the message that would normally have been filled in with Fuse values are all set to a one. When FuseDisable is burned, the MAC command fills in the message with the requested fuse values. Additionally, this bit, when burned, disables the BurnSecure command to prevent modification of the secret fuses and BurnFuse enable bit in the end customer application. Chip Identification The chip includes a total of 72-bits of information that can be used to distinguish between individual chips in a reliable manner. The information is distributed between the ROM and fuse blocks in the following manner. 1.5 Serial Number This 48-bit value is composed of ROM SN (16-bits) and Fuse SN (32-bits). Together they form a serial number that is guaranteed to be unique for all devices ever manufactured within the Atmel CryptoAuthentication family. This value is optionally included in the MAC calculation. Manufacturing ID This 24-bit value is composed of ROM MfrID (16-bits) and Fuse MfrID (8-bits). Typically this value is the same for all chips of a given type. It is always included in the cryptographic computations. Key Values The values stored in the Atmel AT88SA102S internal key array are hardwired into the masking layers of the chip during wafer manufacture. All chips have the same keys stored internally, though the value of a particular key cannot be determined externally from the chip. For this reason, customers should ensure that they program a unique (and secret) number into the 64-secret fuses and they should store the Atmel provided key values securely. Individual key values are made available to qualified customers upon request to Atmel and are always transmitted in a secure manner. When the serial number is included in the MAC calculation then the response is considered to be diversified and the host needs to know the base secret in order to be able to verify the authenticity of the client. A diversified response can also be obtained by including the serial number in the computation of the value written to the secret fuses. A CryptoAuthentication host chip provides a secure hardware mechanism to validate responses to determine if they are authentic. Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 4 1.6 SHA-256 Computation AT88SA102S performs only one cryptographic calculation – a keyed digest of an input challenge. It includes optionally various other information stored on the chip within the digested message. AT88SA102S computes the SHA-256 digest based on the algorithm documented here: http://csrc.nist.gov/publications/fips/fips180-2/fips180-2.pdf Throughout this document, the complete message processed by the AT88SA102S chip is documented. According to the above specification, this always includes a single bit of ‘1’ pad after the message, followed by a 64-bit value representing the total number of bits being hashed (less pad and length). If the length is less than 447 (512-64-1), then the necessary number of ‘0’ bits are included between the ‘1’ pad and ‘length’ to stretch the last message block out to 512-bits. When using standard libraries to calculate the SHA-256 digest, these pad and length bits should probably not be passed to the library as most standard software implementations of the algorithm add them in automatically. 1.6.1 SHA Computation Example In order to ensure that there is no ambiguity, the following example vector is provided in addition to the sample vectors in the NIST document. In this example, all values are listed in hex format. For all but the key, bytes are listed in the order that they appear on the bus – first on the bus is listed on the left side of the page. The key value below is listed in the same order as the challenge, so the 01 at the left of the key string corresponds to the first byte in the SHA-256 document. SHA Computation Example Key Challenge 01030507090B0D0F11131517191B1D1F21232527292B2D2F31333537393B3D3F 020406080A0C0E10121416181A1C1E20222426282A2C2E30323436383A3C3E40 Opcode Mode KeyID 08 50 (all optional information included in message) Secret Fuses Status Fuses Fuse MfrID Fuse SN 0000111122223333 445566 77 8899AABB ROMMfrID ROM SN CCDD EEFF The 88-bytes over which the digest is calculated are: 0103…3D3F0204…3E400850FFFF00001111…EEFF And the resulting digest is: 6CA7129C8DA9CE80EA6357DDCFB1DDCBBBD89ED373419A5A332D728B42642C62 1.7 Security Features The AT88SA102S incorporates a number of physical security features designed to protect the keys from release. These include an active shield over the entire surface of the part, internal memory encryption, internal clock generation, glitch protection, voltage tamper detection and other physical design features. Pre-programmed keys stored on the AT88SA102S are encrypted in such a way as to make retrieval of their values via outside analysis very difficult. Both the clock and logic supply voltage are internally generated, preventing any direct attack via the pins on these two signals. Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 5 2. IO Protocol Communications to and from the AT88SA102S take place over a single asynchronously timed wire using a pulse count scheme. The overall communications structure is a hierarchy: Table 2-1. IO Hierarchy Tokens Implement a single data bit transmitted on the bus, or the wake-up event. Flags Comprised of eight tokens (bits) which convey the direction and meaning of the next group of bits (if any) which may be transmitted. Blocks Of data follow the command and Transmit flags. They incorporate both a byte count and a checksum to ensure proper data transmission. Packets Of bytes form the core of the block without the count and CRC. They are either the input or output parameters of an Atmel AT88SA102S command or status information from the Atmel AT88SA102S. See applications notes on the Atmel website for more details on how to use any microprocessor to easily generate the signaling necessary to send these values to the chip. 2.1 IO Tokens There are a number of IO tokens that may be transmitted along the bus: Input: (To AT88SA102S) Wake Wake AT88SA102S up from sleep (low power) state Zero Send a single bit from system to AT88SA102S with a value of zero One Send a single bit from system to AT88SA102S with a value of one Output: (From AT88SA102S) ZeroOut Send a single bit from AT88SA102S to the system with a value of zero OneOut Send a single bit from AT88SA102S to the system with a value of one The waveforms are the same in either direction, however there are some differences in timing based on the expectation that the host has a very accurate and consistent clock while AT88SA102S has significant part to part variability in its internal clock generator due to normal manufacturing and environmental fluctuations. The bit timings are designed to permit a standard UART running at 230.4K baud to transmit and receive the tokens efficiently. Each byte transmitted or received by the UART corresponds to a single bit received or transmitted by AT88SA102S. See applications notes on the Atmel website for more details. Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 6 2.2 AC Parameters WAKE data comm tWLO tWHI LOGIC Ø tSTART tZHI tZLO tBIT LOGIC 1 tSTART NOISE SUPPRESION tLIGNORE 3. tHIGNORE Absolute Maximum Ratings* Operating temperature.................. −40° C to +85° C Storage temperature ................. −65° C to + 150° C Voltage on any pin with respect to ground ................− 0.5 to VCC+0.5 V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 7 4. AC Parameters Table 4-1. AC Parameters Parameter Symbol Direction Wake low duration t WLO To Atmel AT88SA102S Wake delay to data comm. t WHI Start pulse duration t START Zero transmission high pulse Zero transmission low pulse Bit time Turn around delay t ZHI t ZLO t BIT t TURNAROUND Min Typ Max Unit 60 - µs Signal can be stable in either high or low levels during extended sleep intervals. To Atmel AT88SA102S 2.5 45 ms Signal should be stable high for this entire duration. tWHI must not exceed tTIMEOUT or the chip will transition to sleep. To Atmel AT88SA102S 4.1 4.34 4.56 µs From Atmel AT88SA102S 4.6 6.0 8.6 µs To Atmel AT88SA102S 4.1 4.34 4.56 µs From Atmel AT88SA102S 4.6 6.0 8.6 µs To Atmel AT88SA102S 4.1 4.34 4.56 µs From Atmel AT88SA102S 4.6 6.0 8.6 µs To Atmel AT88SA102S 37 39 - µs From Atmel AT88SA102S 41 54 78 µs From Atmel AT88SA102S 28 60 95 µs To Atmel AT88SA102S 15 µs 45 ms Notes If the bit time exceeds t TIMEOUT then the AT88SA102S will enter sleep mode and the Wake token must be resent. The AT88SA102S will initiate the first low going transition after this time interval following the end of the Transmit flag After the AT88SA102S transmits the last bit of a block, system must wait this interval before sending the first bit of a flag High side glitch filter @ active t HIGNORE_A To Atmel AT88SA102S 45 ns Pulses shorter than this in width will be ignored by the chip, regardless of its state when active Low side glitch filter @ active t LIGNORE_A To Atmel AT88SA102S 45 ns Pulses shorter than this in width will be ignored by the chip, regardless of its state when active Low side glitch filter @ sleep t LIGNORE_S To Atmel AT88SA102S 500 ns Pulses shorter than this in width will be ignored by the chip when in sleep mode IO Timeout t TIMEOUT To Atmel AT88SA102S 45 65 85 ms See Section 5.3.1 Watchdog reset t WATCHDOG To Atmel AT88SA102S 3 4 5.7 s Max time from Wake until chip is forced into sleep mode. See Section 5.4 Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 8 5. DC Parameters Table 5-1. DC Parameters Parameter Symbol Min Operating temperature TA Power supply voltage Typ Max Unit -40 85 °C Vcc 2.7 5.25 V Fuse burning voltage VBURN 3.0 Active power supply current ICC Sleep power supply current @ -40C to 55C Sleep power supply current @ 85C 5.25 V 6 mA I SLEEP 150 nA I SLEEP 1 - Notes Voltage applied to Vcc pin. See Sections 6.3 and 6.5. When chip is in sleep mode, Vcc = 5.25 V, Vsig = 0.0 to 0.3 V or Vsig = Vcc-0.3 V to Vcc µA When chip is in sleep mode, Vcc = 5.25 V Vsig = 0.0 to 0.3 V or Vsig = Vcc-0.3 V to Vcc Input low voltage @ VIL -0.5 0.75 V Voltage levels for Wake token when chip is in sleep mode VIL -0.5 0.5 V Voltage levels for Wake token when chip is in sleep mode VIH 1.5 5.25 V Voltage levels for Wake token when chip is in sleep mode VIH 1.25 3.0 V Voltage levels for Wake token when chip is in sleep mode VIL -0.5 0.5 V When chip is in active mode, Vcc = 5.25 V Input low voltage @ Vcc = 2.7 V Input high voltage @ Vcc = 5.25 V Input high voltage @ Vcc = 2.7 V Input low voltage when active Vcc = 2.7 – 5.25 V Input high voltage when active VIH 1.2 5.25 V When chip is in active mode, Vcc = 2.7 – 5.25 V Output low voltage VOL 0.4 V Maximum input voltage VMAX 5.25 V When chip is in active mode, Vcc = 2.7 – 5.25 V 5.1 IO Flags The system is always the bus master, so before any IO transaction, the system must send an 8-bit flag to the chip to indicate the IO operation that is to be performed, as follows: Value Name Meaning 0x77 Command After this flag, the system starts sending a command block to the chip. The first bit of the block can follow immediately after the last bit of the flag. 0x88 Transmit After a turn-around delay, the chip will start transmitting the response block for a previously transmitted command block. 0xCC Sleep Upon receipt of a sleep flag, the chip will enter a low power mode until the next Wake token is received. All other values are reserved and will be ignored. As the single signal wire may be shared with a CryptoAuthentication host chip, the AT88SA102S chip includes a PauseLong command which causes it to ignore all activity on the signal pin until the expiration of the watchdog timer. Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 9 5.1.1 Command Timing After a command flag is transmitted, a command block should be sent to the chip. During parsing of the parameters and subsequent execution of a properly received command, the chip will be busy and not respond to transitions on the signal pin. The delays for these operations are listed in the table below: Table 5-2. Command Timing (Guaranteed by design; not tested) Parameter Symbol Max Unit Notes Parsing Delay t PARSE 100 µs Delay to check CRC and parse opcode and parameters before an error indication will be available MacDelay t EXEC_MAC 30 ms Delay to execute MAC command MemoryDelay t EXEC_READ 3 ms Delay to execute Read command Fuse Delay t EXEC_FUSE 700 µs Delay to execute BurnFuse command See Section 6.3 for more details. SecureDelay t EXEC_SECURE 36 ms Max delay to execute BurnSecure command See Section 6.5 for more details. PersonalizeDelay t PERSON 13 ms Delay to execute GenPersonalizationKey In this document, tEXEC is used as shorthand for the delay corresponding to whatever command has been sent to the chip. 5.1.2 Transmit Flag The Transmit flag is used to turn around the signal so that the AT88SA102S can send data back to the system, depending on its current state. The bytes that the AT88SA102S returns to the system depend on its current state as follows: Table 5-3. Return Codes State Description Error/Status Description After Wake, but prior to first command 0x11 Indication that a proper Wake token has been received by Atmel AT88SA102S After successful command execution – Return bytes per “Output Parameters” in Section 6, Commands. In some cases this is a single byte with a value of 0x00 indicating success. The Transmit flag can be resent to the AT88SA102S repeatedly if a re-read of the output is necessary. Execution error 0x0F Command was properly received but could not be executed by the AT88SA102S. Changes in the AT88SA102S state or the value of the command bits must happen before it is re-attempted. After CRC or other communications error 0xFF Command was not properly received by the AT88SA102S and should be re-issued by the system. No attempt was made to execute the command The AT88SA102S always transmits complete blocks to the system, so in the above table the status/error bytes result in 4-bytes going to the system – count, status/error, CRC x 2. After receipt of a command block, AT88SA102S will parse the command for errors, a process which takes tPARSE (See Section 5.1.1). After this interval the system can send a transmit token to AT88SA102S – if there was an error, then AT88SA102S will respond with an error code. If there is no error, then AT88SA102S internally transitions automatically from tPARSE to tEXEC and will not respond to any transmit tokens until both delays are complete. Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 10 5.1.3 Sleep Flag The sleep flag is used to transition AT88SA102S to the low power state, which causes a complete reset of the AT88SA102S internal command engine and input/output buffer. It can be sent to AT88SA102S at any time when AT88SA102S will accept a flag. To achieve the specified ISLEEP, Atmel recommends that the input signal be brought below VIL when the chip is asleep. To achieve ISLEEP if the sleep state of the input pin is high, the voltage on the input signal should be within 0.3 V of VCC to avoid additional leakage on the input circuit of the chip. The system must calculate the total time required for all commands to be sent to AT88SA102S during a single session, including any inter-bit/byte delays. If this total time exceeds tWATCHDOG then the system must issue a partial set of commands, then a Sleep flag, then a Wake token, and finally after the Wake delay the remaining commands. 5.1.4 Pause State The pause state is entered via the PauseLong command and can be exited only when the watchdog timer has expired and the chip transitions to a sleep state. When in the pause state, the chip ignores all transitions on the signal pin but does not enter a low power consumption mode. The pause state provides a mechanism for multiple AT88SA102S chips on the same wire to be selected and to exchange data with the host microprocessor. The PauseLong command includes an optional address field which is compared to the values in Fuses 84-87. If the two matches, then the chip enter the pause state, otherwise it continues to monitor the bus for subsequent commands. The host would selectively put all but one AT88SA102S’ in the pause state before executing the MAC command on the active chip. After the end of the watchdog interval all the chips will have entered the sleep state and the selection process can be started with a Wake token (which will then be honored by all chips) and selection of a subsequent chip. 5.2 IO Blocks Commands are sent to the chip, and responses received from the chip, within a block that is constructed in the following way: The general IO flow for the MAC command is as follows: 1. 2. 3. 4. 5. 6. 7. System sends Wake token System sends Transmit flag Receive 0x11 value from the AT88SA102S to verify proper wakeup synchronization System sends command flag System sends complete command block System waits tPARSE for the AT88SA102S to check for command formation errors System sends Transmit flag. If command format is OK, the AT88SA102S ignores this flag because the computation engine is busy. If there was an error, the AT88SA102S responds with an error code 8. System waits tEXEC, see Section 5.1.1 9. System sends transmit flag 10. Receive output block from the AT88SA102S, system checks CRC 11. If CRC from the AT88SA102S is incorrect, indicating a transmission error, system resends transmit flag 12. System sends sleep flag to the AT88SA102S All commands other than MAC have a short execution delay. In these cases, the system should omit steps six, seven, and eight and replace this with a wait of duration tPARSE + tEXEC. 5.3 Synchronization Because the communications protocol is half duplex, there is the possibility that the system and AT88SA102S will fall out of synchronization with each other. In order to speed recovery, AT88SA102S implements a timeout that forces the chip to sleep. Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 11 5.3.1 IO Timeout After a leading transition for any data token has been received, the AT88SA102S will expect the remaining bits of the token to be properly received by the chip within the tTIMEOUT interval. Failure to send enough bits or the transmission of an illegal token (a low pulse exceeding tZLO) will cause the chip to enter the sleep state after the tTIMEOUT interval. The same timeout applies during the transmission of the command block. After the transmission of a legal command flag, the IO Timeout circuitry is enabled until the last expected data bit is received. Note: The timeout counter is reset after every legal token, so the total time to transmit the command may exceed the tTIMEOUT interval while the time between bits may not. In order to limit the active current if AT88SA102S is inadvertently awakened, the IO timeout circuitry is also enabled when AT88SA102S receives a wake-up. If the first token does not come within the tTIMEOUT interval, then AT88SA102S will go back to the sleep mode without performing any operations. The IO timeout circuitry is disabled when the chip is busy executing a command. 5.3.2 Synchronization Procedures When the system and the AT88SA102S fall out of synchronization, the system will ultimately end up sending a transmit flag which will not generate a response from AT88SA102S. The system should implement its own timeout which waits for tTIMEOUT during which time AT88SA102S should go to sleep automatically. At this point, the system should send a Wake token and after tWLO + tWHI, a transmit token. The 0x11 status indicates that the resynchronization was successful. It may be possible that the system does not get the 0x11 code from AT88SA102S for one of the following reasons: The system did not wait a full tTIMEOUT delay with the IO signal idle in which case AT88SA102S may have interpreted the Wake token and transmit flag as data bits. Recommended resolution is to wait twice the tTIMEOUT delay and re-issue the Wake token. AT88SA102S went into the sleep mode for some reason while the system was transmitting data. In this case, AT88SA102S will interpret the next data bit as a Wake token, but ignore some of the subsequently transmitted bits during its wake-up delay. If any bytes are transmitted after the wake-up delay, they may be interpreted as a legal flag, though the following bytes would not be interpreted as a legal command due to an incorrect count or the lack of a correct CRC. Recommended resolution is to wait the tTIMEOUT delay and re-issue the Wake token. There is some internal error condition within AT88SA102S which will be automatically reset after a tWATCHDOG interval, see Section 5.4. There is no way to externally reset AT88SA102S – the system should leave the IO pin idle for this interval and issue the Wake token. 1. 2. 3. 5.4 Watchdog Failsafe After the Wake token has been received by AT88SA102S, a watchdog counter is started within the chip. After tWATCHDOG, the chip will enter sleep mode, regardless of whether it is in the middle of execution of a command and/or whether some IO transmission is in progress. There is no way to reset the counter other than to put the chip to sleep and wake it up again. This is implemented as a fail-safe so that no matter what happens on either the system side or inside the various state machines of AT88SA102S including any IO synchronization issue, power consumption will fall to the low sleep level automatically. 5.5 Byte and Bit Ordering AT88SA102S is a little-endian chip: • • • All multi-byte aggregate elements within this spec are treated as arrays of bytes and are processed in the order received Data is transferred to/from the AT88SA102S least significant bit first on the bus In this document, the most significant bit and/or byte appears towards the left hand side of the page Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 12 6. Commands The command packet is broken down in the following way: Byte Name Meaning 0 Opcode The Command code 1 Param1 The first parameter – always present 2-3 Param2 The second parameter – always present 4+ Data Optional remaining input data If a command fails because the CRC within the block is incorrect or there is some other communications error then immediately after tPARSE the system will be able to retrieve an error response block containing a single byte packet. The value of that byte will be all ones. In this situation, the system should re-transmit the command block including the proceeding transmit flag – providing there is sufficient time before the expiration of the watchdog timeout. If the opcode is invalid, one of the parameters is illegal, or the AT88SA102S is in an illegal state for the execution of this command then immediately after tPARSE the system will be able to retrieve an error response block containing a single byte packet. The value of that byte will be 0x0F. In this situation, the condition must be corrected before the (modified) command is sent back to AT88SA102S. If a command is received successfully then after the appropriate execution delay the system will be able to retrieve the output block as described in the individual command descriptions below. In the individual command description tables below, the size column describes the number of bytes in the parameter documented in each particular row. The total size of the block for each of the commands is fixed, though that value is different for each command. If the block size for a particular command is incorrect, the chip will not attempt the command execution and return an error. Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 13 6.1 MAC Computes a SHA-256 digest of a key stored inside the chip, an input challenge and other information on the chip. The output of this command is the digest of this message. If the message includes the serial number of the chip, then the response is said to be diversified. Protocols that utilize diversified responses may be more secure because two AT88SA102S chips with same key will return different responses to an identical challenge based on their unique serial number. Table 6-1. Input Parameters Name Size Notes Opcode MAC 1 0x08 Param1 Mode 1 Controls which fields within the chip are used in the message Param2 KeyID 2 Which internal key is to be used in the message Data Challenge 32 Input portion of message to be digested Table 6-2. Output Parameters Name Size Notes Response 32 SHA-256 digest Regardless of the value of mode, the first 512-bit block of the message that will be hashed with the SHA-256 algorithm will consist of: 256-bits key[KeyID] 256-bits challenge The second block consists of the following information: 8-bits Opcode (always 0x08) 8-bits Mode 16-bits KeyID 64-bits Secret Fuses including BurnFuse and BurnSecure enable (or zeros, see Table 6-3) 24-bits Status Fuses including FuseDisable (or zeros, see Table 6-3) 8-bits Fuse MfrID fuses, (Fuse[88:95]) (never zero’d out) 32-bits Fuse SN, (Fuse[96:127]) (or zeros, see Table 6-3) 16-bits ROM MfrID (never zero’d out) 16-bits ROM SN (or zeros, see Table 6-3) 1-bit ‘1’ pad 255-bit ‘0’ pad 64-bit Total length of message in bits (512+192=704), excluding pad and length Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 14 Mode is encoded as follows: Table 6-3. Mode Encoding Bits Meaning 7 Should be zero 6 If set, include the 48-bit serial number (combination of fuses and ROM values) in the message Otherwise, the corresponding message bits are set to zero 5 If set, and Fuse is burned, include the 64-secret fuses (Fuse through Fuse) in the message Otherwise, the corresponding message bits are set to Zero If Mode is set, then the value of this mode bit is ignored 4 If set, and Fuse is burned, include the 64-secret fuses and 24-status fuses (Fuse through Fuse) in the message Otherwise, the corresponding message bits are set to zero 3-0 Should be zero Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 15 6.2 Read Reads 4-bytes from Fuse or ROM and returns an error if an attempt is made to read any fuse address that is illegal. Table 6-4. Input Parameters Name Size Notes Opcode READ 1 0x02 Param1 Mode 1 Fuse or ROM Param2 Address 2 Which 4-bytes within array. Bits 2-15 should be 0 Data Ignored 0 Table 6-5. Output Parameters Name Size Notes Contents 4 The contents of the specified memory location Table 6-6. Mode Encoding Name Value Notes ROM 0x00 Reads four bytes from the ROM. Bit one of the address parameter must be zero Fuse 0x01 Reads the value of 32-fuses. Bit one of the address parameter must be one. The input address parameter << 5 provides the fuse number corresponding to the LSB of the first returned byte. Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 16 6.3 BurnFuse Burns a single one of the status fuse bits (Fuse – Fuse). No other fuses can be burned with this command – use BurnSecure at personalization time to burn any of the first 88 fuses. If the BurnFuse enable bit (Fuse 1) has been burned to a zero, then attempts to run this command will return an error. The power supply pin must meet the VBURN specification during the entire BurnFuse command in order to burn fuses reliably. If VCC is greater than or equal to 3.7V, then the BurnTime parameter should be set to 0x00 and the internal burn time will be up to 250µs. If VCC is less than 3.7V but greater than VBURN then the BurnTime parameter should be set to 0xFFFF and the internal burn time will be up to 262ms. The chip does not internally check the supply voltage level. There is a very small interval during tEXEC_BURN when the fuse element is actually being burned. During this interval the power supply must not be removed and the watchdog timer must not be allowed to expire; or the fuse may end up in a state where it reads as un-burned but cannot be burned. Table 6-7. Input Parameters Name Size Notes Opcode BURNFUSE 1 0x04 Param1 FuseNum 1 Which bit within fuse array, minimum value is 64, and maximum value is 86 Param2 BurnTime 2 Must be 0x0000 if Vcc >+3.7 V; must be 0xFFFF otherwise Data Ignored 0 Table 6-8. Output Parameters Name Size Notes Success 1 Upon successful execution, a value of zero will be returned by AT88SA102S Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 17 6.4 GenPersonalizationKey Loads a personalization key into internal memory and then uses that key along with an input seed to generate a decryption digest using SHA-256. Neither the key nor the decryption digest can be read from the chip. Upon completion, an internal bit is set indicating that a secure personalization digest has been loaded and is ready for use by BurnSecure. This bit is cleared (and the digest lost) when the watchdog timer expires or the power is cycled. This command will fail if Fuse has been burned. Table 6-9. Input Parameters Name Size Notes Opcode GenPers 1 0x20 Param1 Zero 1 Must be 0x00 Param2 KeyID 2 Identification number of the personalization key to be loaded Data Seed 16 Seed for digest generation. The least significant bit of the last byte is ignored by AT88SA102S Table 6-10. Output Parameters Name Size Notes Success 1 Upon successful execution, a value of 0 will be returned by AT88SA102S The SHA-256 message body used to create the resulting digest internally stored in the chip consists of the following 512-bits: 256-bits 64-bits 127-bits 1-bits 64-bits PersonalizeKey[KeyID] Fixed value of all ones Seed from input stream ‘1’ pad Length of message in bits, fixed at 447 Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 18 6.5 BurnSecure Burns any combination of the first 88-fuse bits. Verification that the proper secret fuse bits have been burned must occur using the MAC command – there is no way to read the values in the first 64-fuses to verify their state. The 24-status fuses can be verified with the Read command. The fuses to be burned are specified by the 88-bit input map parameter. If a bit in the map is set to a ‘1’, then the corresponding fuse is burned. If a bit in the map parameter is set to zero, then the corresponding fuse is left in its current state. The first bit sent to the AT88SA102S corresponds to Fuse and so on up to Fuse. Note: Since a ‘1’ bit in the map parameter results in a ‘0’ data value in the actual fuse array, the value in the map parameter should generally be the inverse of the desired secret or status value. See Section 1.3 for more details. To facilitate secure personalization of AT88SA102S, this map may be encrypted before being sent to the chip. If this mode is desired, then the decrypt parameter should be set to one in the input parameter list. The decryption (transport) key is computed by the GenPersonalizationKey command, which must have been run immediately prior to the execution of BurnSecure. In this case, prior to burning any fuses, the input map parameter is XOR’d with the first 88 bits of that digest from the GenPersonalizationKey command. The GenPersonalizationKey and BurnSecure commands must be run within a single Wake cycle prior to the expiration of the watchdog timer. The power supply pin must meet the VBURN specification during the entire BurnSecure command in order to burn fuses reliably. If VCC is greater than or equal to 3.7 V, then the BurnTime parameter should be set to 0x00 and the internal burn time will be 250 µs. If VCC is less than 3.7 V but greater than VBURN then the BurnTime parameter should be set to 0xFFFF and the internal burn time will be 262 ms per fuse bit burned. The chip does not internally check the supply voltage level. The total BurnSecure execution delay is directly proportional to the total number of fuses being burned. If VCC is less than 3.7V, then the total BurnSecure execution time may exceed the interval remaining before the expiration of the watchdog timer. In this case, the BurnSecure command should be run repeatedly, with each repetition burning only as many fuses as there is time available. The system software is responsible for counting the number of ‘1’ bits in the clear-text version of the map parameter sent to the chip – no error is returned if the fuse burn count is too high. Other than Fuse (see below), the fuses may be burned in any order. Prior to execution of BurnSecure, the AT88SA102S verifies that Fuse is un-burned. If it has been burned, then the BurnSecure command will return an error. Fuse must be burned during the last repetition of BurnSecure as it cannot be individually burned with BurnFuse. There are a series of very small intervals during tEXEC_SECURE when the fuse element is actually being burned. During this interval, the power supply must not be removed and the watchdog timer must not be allowed to expire or the fuse may end up in a state where it reads as un-burned but cannot be burned. Table 6-11. Input Parameters Name Size Notes Opcode BURNSECURE 1 0x10 Param1 Decrypt 1 If 1, decrypt Map data before usage. If 0, the map is transmitted in plain text Param2 BurnTime 2 Must be 0x0000 if VCC >=3.7 V; must be 0xFFFF otherwise Data Map 11 Which fuses to burn, may be encrypted Table 6-12. Output Parameters Name Size Notes Success 1 Upon successful execution, a value of zero will be returned by AT88SA102S. Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 19 6.6 PauseLong Forces the chip into the pause state until the watchdog timer expires, after which it will automatically enter into the sleep state. During execution of this command and while in the pause state the chip will ignore all activity on the IO signal. This command is used to prevent bus conflicts in a system that also includes other AT88SA102S chips or a CryptoAuthentication host chip sharing the same signal wire. Table 6-13. Input Parameters Name Size Notes Opcode PAUSELONG 1 0x01 Param1 Selector 1 Which chip to put into the pause state, 0x00 for all AT88SA102S chips Param2 Zero 2 Must be 0x0000 Data Ignored 0 The Selector parameter provides a mechanism to select which device will pause if there are multiple devices on the bus: • • If the selector parameter is 0x00, then every AT88SA102S chip receiving this command will go into the pause state and no chip will return a success code. If any of the bits of the selector parameter are set, then the chip will read the values of Fuse[84-87] and go into the pause state only if those fuse values match the least significant 4-bits of the selector parameter. If the chip does not go into the pause state, it returns an error code of 0x0F. Otherwise it goes into the pause state and never returns any code. Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 20 7. Pinout Table 7-1. Pin Definitions SOIC/TSSOP SOT-23 Name Description 5 1 Signal IO channel to the system, open drain output. It is expected that an external pullup resistor will be provided to pull this signal up to VCC for proper communications. When the chip is not in use this pin can be pulled to either VCC or GND. 8 2 VCC Power supply, 2.7 – 5.25 V. This pin should be bypassed with a high quality 0.1µF capacitor close to this pin with a short trace to GND Additional applications information at www.atmel.com 4 3 GND Connect to system ground 1,2,3,6,7 -- NC Not connected Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 21 Packaging Information 3TS1 – Shrink SOT 3 GND E1 CL E Signal SDA VCC 1 L1 8. 2 e1 End View Top View b A2 SEATING PLANE e A A1 D Side View Notes: 1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.25mm per end. Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25mm per side. 2. The package top may be smaller than the package bottom. Dimensions D and E1 are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 3. These dimensions apply to the flat section of the lead between 0.08 mm and 0.15mm from the lead tip. This drawing is for general information only. Refer to JEDEC Drawing TO-236, Variation AB for additional information. COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN A A1 A2 D E E1 L1 e1 b 0.89 0.01 0.88 2.80 2.10 1.20 MAX NOM 2.90 1.30 0.54 REF 1.90 BSC 0.30 - 1.12 0.10 1.02 3.04 2.64 1.40 0.50 NOTE 1,2 1,2 3 12/11/09 R Package Drawing Contact: [email protected] TITLE GPC DRAWING NO. REV. 3TS1, 3-lead, 1.30mm Body, Plastic Thin Shrink Small Outline Package (Shrink SOT) TBG 3TS1 B Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 22 8X – TSSOP C 1 Pin 1 indicator this corner E1 E L1 N L Top View End View A b A1 e COMMON DIMENSIONS (Unit of Measure = mm) A2 Side View Notes: MIN NOM MAX A - - 1.20 A1 0.05 - 0.15 A2 0.80 1.00 1.05 D 2.90 3.00 SYMBOL D 1. This drawing is for general information onl y. Refer to JEDEC Drawing MO-153, VariationAA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25mm (0.010in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07mm. 5. Dimension D and E1 to be determined at Datum Plane H. 3.10 E 2, 5 6.40 BSC E1 4.30 b 0.19 e L NOTE 4.40 4.50 3, 5 – 0.30 4 0.65 BSC 0.45 0.60 0.75 L1 1.00 REF C 0.09 - 0.20 6/22/11 TITLE GPC Package Drawing Contact: 8X, 8-lead 4.4mm Body, Plastic Thin [email protected] Shrink Small Outline Package (TSSOP) TNR DRAWING NO. 8X Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 REV. D 23 8S1 – SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 D SIDE VIEW Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. SYMBOL MIN A 1.35 NOM MAX – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e L NOTE 1.27 BSC 0.40 – 1.27 0° – 8° 6/22/11 TITLE Package Drawing Contact: 8S1, 8-lead (0.150” Wide Body), Plastic Gull [email protected] Wing Small Outline (JEDEC SOIC) GPC SWB DRAWING NO. REV. 8S1 G Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 24 9. Ordering Codes Atmel AT88SA102S Ordering Information 10. Atmel Ordering Code Package Type Voltage Range Operating Range AT88SA102S-TSU-T SOT, Tape and Reel 2.7 V–5.25 V Green compliant (exceeds RoHS)/Industrial (−40°C to 85° C) AT88SA102S-TH-T TSSOP, Tape and Reel 2.7 V–5.25 V Green compliant (exceeds RoHS)/Industrial (−40°C to 85° C) AT88SA102S-SH-T SOIC, Tape and Reel 2.7 V–5.25 V Green compliant (exceeds RoHS)/Industrial (−40°C to 85° C) Revision History Doc. Rev. Date Comments 8584G 09/2011 Correct references and sections numbers Section 5.1.3, Sleep Flag, change “ within 0.5V of VCC” to “within 0.3V of VCC” BurnFuse – correct Fuse to Fuse and remove 24 from 24-status BurnSecure – change “can either be burned during the last repetition of BurnSecure or it can be individual…” to “must be burned during the last repetition of BurnSecure as it cannot be individual…” 8584F 08/2010 Update IO Timeout description 8584E 06/2010 Update to Table 3: AC Parameters 8584D 05/2010 Expansion of IO Timeout specification 8584C 04/2010 Added 8ld TSSOP 8584B 02/2010 Updated parameter tables and added 8ld SOIC 8584A 03/2009 Initial document release Atmel AT88SA102S [DATASHEET] 8584G−CRYPTO−9/11 25 Atmel Corporation Atmel Asia Limited Atmel Munich GmbH Atmel Japan 2325 Orchard Parkway Unit 01-5 & 16, 19F Business Campus 9F, Tonetsu Shinkawa Bldg. San Jose, CA 95131 BEA Tower, Millennium City 5 Parkring 4 1-24-8 Shinkawa USA 418 Kwun Tong Road D-85748 Garching b. Munich Chuo-ku, Tokyo 104-0033 Tel: (+1)(408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1)(408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81)(3) 3523-3551 www.atmel.com Tel: (+852) 2245-6100 Fax: (+49) 89-3194621 Fax: (+81)(3) 3523-7581 Fax: (+852) 2722-1369 © 2011 Atmel Corporation. All rights reserved. / Rev.: 8584G−CRYPTO−9/11 Atmel®, logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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