Features • Comprehensive Library of Standard Logic and I/O Cells • ATC20 Core and I/O Cells Designed to Operate with VDD = 1.8V ± 0.15V as Main Target Operating Conditions • IO25 and IO33 Pad Libraries Provide Interfaces to 2.5V and 3V Environments • Oscillators Provide Stable Clock Sources • Basic Analog Input/Output, Power, Ground and Multiplexer Cells Available, High-performance Analog Cells Can Be Developed on Request • Memory Cells Compiled to the Precise Requirements of the Design • Compatible with Atmel’s Extensive Range of Microcontroller, DSP, Standard-interface and Application-specific Cells Cell-based ASIC Description The Atmel ATC20 CBIC family is fabricated on a proprietary 0.21 micron five-layermetal CMOS process intended for use with a supply voltage of 1.8V ± 0.15V. The following table shows the range for which Atmel library cells have been characterized. Summary Table 1. Recommended Operating Conditions Symbol Parameter Conditions Min Typ Max Unit VDD DC Supply Voltage Core and Standard I/Os 1.65 1.8 1.95 V VDD2.5 DC Supply Voltage 2.5V Interface I/Os 2.25 2.5 2.75 V VDD3.3 DC Supply Voltage 3V Interface I/Os 3 3.3 3.6 V VI DC Input Voltage 0 VDD V VO DC Output Voltage 0 VDD V TEMP Operating Free Air Temperature Range -40 +85 °C Industrial ATC20 The Atmel cell libraries and megacell compilers have been designed in order to be compatible with each other. Simulation representations exist for three types of operating conditions. They correspond to three characterization conditions defined as follows: • • • MIN conditions: – TJ = -40°C – VDD (cell) = 1.95V – Process = fast (industrial best case) TYP conditions: – TJ = +25°C – VDD (cell) = 1.8V – Process = typ (industrial typical case) MAX conditions: – TJ = +100°C – VDD (cell) = 1.65V – Process = slow (industrial worst case) Delays to tri-state are defined as delay to turn off (VGS < VT) of the driving devices. Output pad drain current corresponds to the output current of the pad when the output voltage is VOL or VOH. The output resistor of the pad and the voltage drop due to access resistors (in and out of the die) are taken into account. In order to have accurate timing estimates, all characterization has been run on electrical netlists extracted from the layout database. Rev. 1361BS–CBIC–09/02 1 Standard Cell Library SClib Decoding the Cell Name The Atmel Standard Cell Library, SClib, contains a comprehensive set of combinational logic and storage cells. The SClib library includes cells which belong to the following categories: • Buffers and Gates • Multiplexers • Flip-flops • Scan Flip-flops • Latches • Adders and Subtractors The table below shows the naming conventions for the cells in the SClib library. Each cell name begins with either a two-, three-, or four-letter code that defines the type of cell. This indicates the range of standard cells available. Table 2. Cell Codes 2 Code Description Code Description AD Adder INVT Inverting 3-State Buffer AH Half Adder JK JK Flip-Flop AS Adder/Subtractor LA D Latch AN AND Gate MI Inverting Multiplexer AOI AND-OR-Invert Gate MX Multiplexer AON AND-OR-AND-Invert Gates ND NAND Gate AOR AND-OR Gate NR NOR Gate BH Bus Holder OAI OR-AND-Invert Gate BUFB Balanced Buffer OAN OR-AND-OR-Invert Gates BUFF Non-Inverting Buffer OR OR Gate BUFT Non-Inverting 3-State Buffer ORA OR-AND Gate CG Carry Generator SD Multiplexed Scan D Flip-Flop CLK2 Clock Buffer SE Multiplexed Scan Enable D Flip-Flop DE D-Enabled Flip-Flop SRLA Set/Reset Latches with NAND input DF D Flip-Flop SU Subtractor INV0 Inverter XN Exclusive NOR Gate INVB Balanced Inverter XR Exclusive OR Gate ATC20 Summary 1361BS–CBIC–09/02 ATC20 Summary Cell Matrices The following three tables provide a quick reference to the storage elements in the SClib library. Note that all storage elements feature buffered clock inputs and buffered output. Table 3. JK Flip-flops Macro Name JKBRBx Set Clear 1x Drive 2x Drive • • • • Table 4. D Flip-flops Macro Name Clear • Enabled D Input Single Output 1x Drive 2x Drive • • • DFCRBx • • • DFCRQx • • • DFCRNx • • • DFNRBx • • DFNRQx • • • • • • • • DENRQx • • • • DENRBx • • • • • • DFBRBx Set DFPRBx • DEPRQx • • DECRQx • • • Table 5. Scan Flip-flops Macro Name Set Clear 1x Drive 2x Drive • • • • SDCRBx • • • SDCRNx • • • • SDCRQx • • • • SDNRBx • • SDNRNx • • • SDNRQx • • • • • • • • • • • • • • SDBRBx SDPRBx • • SECRQx SENRQx SEPRQx • Single Output 3 1361BS–CBIC–09/02 Input/Output Pad Cell Libraries IO18lib, IO25lib and IO33lib The Atmel Input/Output Cell Library, IO18lib, contains a comprehensive list of input, output, bidirectional and tristate cells. The ATC20 (1.8V) cell library includes two special sets of I/O cells, IO25lib and IO33lib, for interfacing with external 2.5V and 3.3V devices. Voltage Levels The IO18lib library is made up exclusively of low-voltage chip interface circuits powered by a voltage in the range of 1.65V to 1.95V. The library is compatible with the SClib 1.8volt standard cells library. Power and Ground Pads Designers are strongly encouraged to provide three kinds of power pairs for the IO18lib library. These are “AC”, “DC” and core power pairs. AC power is used by the I/O to switch its output from one state to the other. This switching generates noise in the AC power buses on the chip. DC power is used by the I/O to maintain its output in a steady state. The best noise performance is achieved when the DC power buses on the chip are free of noise; designers are encouraged to use separate power pairs for AC and DC power to prevent most of the noise in the AC power buses from reaching the DC power buses. The same power pairs can be used to supply both DC power to the I/Os and power to the core without affecting noise performance. Table 6. VSS Power Pad Combinations Core Switching I/O Quiet I/O Vssi VssAC VssDC Library Cell Name Signal Name pv18i00 VSS pv18a00 VSS • pv18d00 VSS • pv18e00 VSS • pv18b00 VSS • pv18f00 VSS Library Cell Name Signal Name pv18i18 VDD pv18a18 VDD • pv18d18 VDD • pv18e18 VDD • pv18b18 VDD • pv18f18 VDD • • • • • • Table 7. VDD Power Pad Combinations Core Switching I/O Quiet I/O Vddi VddAC VddDC • • • • • 4 • ATC20 Summary 1361BS–CBIC–09/02 ATC20 Summary Cell Matrices Table 8. CMOS Pads CMOS Cell Name Output 3-State I/O Only 3-State Output Only Drive Strength Pad Sites Used PC18B01 • 1x 1 PC18B02 • 2x 1 PC18B03 • 3x 1 PC18B04 • 4x 1 PC18B05 • 5x 1 PC18O01 • 1x 1 PC18O02 • 2x 1 PC18O03 • 3x 1 PC18O04 • 4x 1 PC18O05 • 5x 1 PC18T01 • 1x 1 PC18T02 • 2x 1 PC18T03 • 3x 1 PC18T04 • 4x 1 PC18T05 • 5x 1 3-State Output Only Drive Strength Pad Sites Used Table 9. TTL Pads TTL Cell Name 3-State I/O PT18B01 • 2 mA 1 PT18B02 • 4 mA 1 PT18B03 • 8 mA 1 Output Only PT18O01 • 2 mA 1 PT18O02 • 4 mA 1 PT18O03 • 8 mA 1 PT18T01 • 2 mA 1 PT18T02 • 4 mA 1 PT18T03 • 8 mA 1 Non-Inverting Inverting Pad Sites Used Table 10. CMOS/TTL Input Only Pad CMOS Cell Name Input Levels PC18D01 CMOS PC18D11 CMOS PC18D21 CMOS • PC18D31 CMOS • Note: Schmitt Input Level Shifter • 1 • • 1 1 • 1 All 3-state I/Os, 3-state output only and input pads are also available with pull-up and pull-down device. 5 1361BS–CBIC–09/02 IO25lib and IO33lib Low Slew Rate Cells The IO25lib (IO33lib) cells comprise a series of 1.8V/2.5V (1.8V/3.3V) input/output pads developed for low supply voltage processes in order to interface 1.8V ASICs to 2.5V (3.3V) environments. All IO25lib (IO33lib) cells are slew rate controlled. Advantage has been taken of the 1.8V to 2.5V (3.3V) level shifter (slow by construction) to reduce the slew rate without reducing speed. Table 11. IO25lib/IO33lib Pads 3V Interface Pad Name pc25b0x/pc33b0x 3-State I/O Output Only 3-State Output Only • Drive Strength Pad Sites Used 2 mA, 4 mA, 8 mA, 16 mA 1 • pc25d00/pc33d00 • pc25o0x/pc33o0x • pc25t0x/pc33t0x Note: Input Only 1 2 mA, 4 mA, 8 mA, 16 mA 1 2 mA, 4 mA, 8 mA, 16 mA 1 All 3-state I/Os, 3-state output only and input pads are also available with pull-up and pull-down device. Table 12. IO25lib/IO33lib Power Pads Power Bus Connections Cell Name vssi Pad Sites Used 1 1 • pv25e33/pv33e33 6 mixvdd • pv25i25/pv33i25 pv25ecrn/pv33ecrn vddi • pv25e00/pv33e00 pv25i00/pv33i00 mixvss • 1 • 1 • 2 ATC20 Summary 1361BS–CBIC–09/02 ATC20 Summary Oscillator Cell Library Osc18lib The Atmel Oscillator Library provides stable clock sources. It comprises five oscillators and one power-on-reset. The Atmel two-pad oscillators are designed with the Pierce three-point oscillator structure. For the 32.768 kHz oscillator, the load capacitance must be between 6 pF and 12.5 pF. For high-frequency oscillators, the load capacitance must be between 15 pF and 20 pF. External capacitors must be added in order to obtain the correct load capacitance. Clock output is high at off state (onosc = 0). The oscillators provide a bypass mode (onosc = 0), clock = not (xin). Table 13 gives the available Osc18lib cells and their major characteristics. Table 13. Oscillator and POR Cells Basic Analog Cell Library ANA18lib, ANA25lib, ANA33lib Cell Name Description OSC18f33K Low frequency, optimized for 32.786 kHz crystal OSC18f9M 4 - 9 MHz crystal oscillator OSC18f16M 8 - 16 MHz crystal oscillator OSC18f27M 10 - 27 MHz crystal oscillator OSC33KLP 32.786 Hz uPower crystal oscillator. Low frequency, optimized for 32.786 kHz crystal POR18 Static and dynamic reset with internal hysterisis The Atmel CBIC analog library makes the following parts available: • Multiplexer modules – Multiplexers to minimize cross-talk (for use with high-impedance nodes). – Multiplexers to minimize ON resistance. • Analog input and output cells • Analog power and ground cells A special set of basic analog I/O cells, ANA25lib (ANA33lib), is available for interfacing with external 2.5V (3.3V) devices. General-purpose Analog Cell Library GPlib The General-purpose Analog Cell Library (GPlib) is composed of cells performing various analog functions. Currently available are regulators, power management cells, op amps, comparators, ADCs and DACs. All these cells are on request only. Additional high-performance, complex analog cells can be developed according to specific customer requirements. 7 1361BS–CBIC–09/02 Atmel Compiled Megacell Library The Atmel Compiled Megacell Library enables compilation of megacells for the functions Synchronous RAM, Asynchronous RAM, Asynchronous Dual-port RAM and Synchronous ROM, according to the user’s precise requirements. The Atmel megacells can be instanced as often as required in designs and can be used in parallel with cells from all other Atmel CBIC libraries. All the megacell representations required for schematic entry, simulation, place and route, layout generation, and verification are created automatically. Compiled Synchronous RAM Megacells The Atmel Synchronous RAM compiler has bidirectional or separate I/O ports, and can be configured in multi-bank form, with a maximum of four banks. The range of permitted Synchronous RAM megacell configurations is as follows: Number of bits 128, .. 144K bits Number of words 32, .. 8K Word Size 4, .. 36 bits The following table shows the range of performances for particular Synchronous RAM configurations under typical conditions. Configuration 1K x 8 (8K bits) 2K x 16 (32K bits) 4K x 32 (128K bits) Density (Kbits/mm ) 51 58 62 Frequency (MHz) 237 157 112 Dynamic Power (mW/MHz) 0.17 0.36 0.73 2 Compiled Asynchronous RAM Megacells The Atmel Asynchronous RAM compiler has bidirectional or separate I/O ports, and can be configured in multi-bank form, with a maximum of four banks. The range of permitted Asynchronous RAM megacell configurations is as follows: Number of bits 128, .. 128K bits Number of words 16, .. 4K Word Size 8, .. 36 bits The following table shows the range of performances for particular Asynchronous RAM configurations under typical conditions. Configuration 1K x 8 (8K bits) 2K x 16 (32K bits) 4K x 32 (128K bits) Density (Kbits/mm ) 40 40 50 Frequency (MHz) 270 268 185 Dynamic Power (mW/MHz) 0.24 0.38 0.63 2 8 ATC20 Summary 1361BS–CBIC–09/02 ATC20 Summary Compiled Asynchronous Dual-port RAM Megacells The Atmel Asynchronous Dual-port RAM has bidirectional or separate I/O ports, and can be configured in multi-bank form, with a maximum of four banks. The range of permitted Asynchronous Dual-port RAM Megacell configurations is as follows: Number of bits 128, .. 16K Number of words(1) 64, .. 2K Word Size(1) 2, .. 36 bits Note: 1. Must be the same for both ports. The following table shows the range of performances for particular Asynchronous Dualport RAM configurations under typical conditions. Configuration 128 x 8 (1K bits) 256 x 16 (4K bits) 512 x 32 (16K bits) Density (Kbits/mm ) 22 32 36 Frequency (MHz) 305 274 248 Dynamic Power (mW/MHz) 0.09 0.31 0.41 2 Compiled Synchronous ROM Megacells The Atmel Synchronous ROM is diffusion programmable and is applicable in low power solutions. It can be configured in multi-bank form, with a maximum of four banks. The range of permitted Synchronous ROM Megacell configurations is as follows: Number of bits 256, .. 512K Number of words 64, .. 8K Word Size 4, .. 72 bits The following table shows the range of performances for particular Synchronous ROM configurations under typical conditions. Configuration 2K x 8 (16K bits) 4K x 16 (64K bits) 8K x 32 (256K bits) Density (Kbits/mm ) 400 568 669 Frequency (MHz) 190 170 120 Dynamic Power (mW/MHz) 0.13 0.26 0.54 2 9 1361BS–CBIC–09/02 Document Details Title ATC20 Summary Literature Number 1361S Revision History Version A Publication Date: Mar-00 Version B Publication Date: 06-Sep-02 Page: 7 Adds description of Oscillator Cell Library, Basic Analog Cell Library, General-purpose Analog Cell Library. 10 ATC20 Summary 1361BS–CBIC–09/02 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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