AN74875
Designing with Serial I2C nvSRAM
Author: Shivendra Singh
Associated Project: Yes
Associated Part Family: CY14xxxxI, CY14xxxxJ
Software Version: PSoC ® Creator™ 3.0 or above
Related Application Notes: AN61546, AN43593
AN74875 provides design guidelines and example circuits for inter-integrated circuit (I2C) nvSRAM device. The I2C
nvSRAM is a high-performance nonvolatile serial interface memory that offers zero cycle delay write operation and
infinite SRAM write endurance. The I2C nvSRAM is a slave I2C device and requires an I2C master controller to
access it in a system. An associated library component for PSoC 3 is also provided as an example project.
Contents
Introduction
Introduction ....................................................................... 1
I2C nvSRAM Configurations .............................................. 2
Applicability of I2C-Bus Protocol Features .................... 2
I2C nvSRAM Device Options ........................................ 2
I2C nvSRAM Device Connections ................................ 3
Determining I2C Pull-up Resistor Values ........................... 5
Control Input Pin Configuration .................................... 7
RTC Part Specific Pin Configuration ............................ 8
I2C nvSRAM Operation ..................................................... 9
High-Speed Mode (Hs-mode) Operation .................... 10
Addressing in I2C nvSRAM ......................................... 10
I2C nvSRAM Access ................................................... 12
Summary ......................................................................... 16
Appendix A (Pseudo Code Example) .............................. 17
I2C Write ..................................................................... 17
I2C Read ..................................................................... 18
Worldwide Sales and Design Support ............................. 20
Cypress nvSRAM integrates a SRAM cell and a
nonvolatile memory cell into a single nvSRAM cell. In the
normal mode of operation, all reads and writes happen
directly from and to the SRAM portion of the nvSRAM.
This provides faster write and read access compared to
any existing nonvolatile memory technology such as
EEPROM and flash. In the event of system power loss,
data from the SRAM is transferred to its nonvolatile cell
automatically by using energy stored in a small capacitor
connected to the VCAP pin. During the subsequent poweron cycle, data from the nonvolatile cell is recalled
automatically in the SRAM array and available to the user.
A capacitor connected to the VCAP pin is charged by the
nvSRAM during the normal operation.
The nvSRAM specifies one million endurance cycles for
nonvolatile cells. In nvSRAM, endurance cycle is
consumed only when data transfer happens from the
SRAM cells to nonvolatile cells during the STORE
operation. The nonvolatile store operation in the nvSRAM
is initiated either automatically when the device power
drops below a predefined threshold level (VSWITCH), or on
demand either by writing a specific command in the
command register (0xAA), or through the hardware pin
(
) by toggling it to LOW. The command register in the
nvSRAM is defined in control register space. The control
registers are addressed through a dedicated I2C slave ID.
Detailed description on the nvSRAM addressing has been
provided in Addressing in I2C nvSRAM section described
later in this application note.
The nvSRAM initiates nonvolatile Store only when the
system power failure is detected and new data written in
SRAM is required to be moved safely into nonvolatile
cells. Hence the total non volatile cell endurance count in
nvSRAM equates to the total number of non volatile Store
cycles not the SRAM write cycles.
www.cypress.com
Document No. 001-74875 Rev. *E
1
2
Designing with Serial I C nvSRAM
There are many data logging applications, which require
instant saving of runtime critical information in the event of
power loss. This critical information includes controller run
time states, scratch pad data, parameter settings, and the
other environment variables measured by the controller.
The I2C nvSRAM can ideally fit into such data logging
applications due to its fast nonvolatile write speed. The I2C
master controller can log hundreds of bytes of data in tens
of microseconds in nvSRAM whereas it takes tens of
milliseconds to write the same amount of data in EEPROM
or flash memory. The I2C nvSRAM is offered in industry
standard 8-pin SOIC and 16-pin SOIC packages.
This application note describes about the I2C nvSRAM
configuration, example circuits for different package
options, method of determining suitable pull-up resistor
values for the I2C bus, data byte format for the I2C
communication in nvSRAM, and I2C addressing scheme to
access the Memory, Real Time Clock (RTC), and Control
functions of the nvSRAM. For other details on the I2C
nvSRAM, refer the specific device datasheet.
A PSoC 3 nvRAM I2C library component is attached along
with this application note as an associated project.
I2C nvSRAM Configurations
The I2C nvSRAM supports the highest I2C data transfer
rate up to 3.4 Mbits/s (I2C clock frequency at 3.4 MHz)
along with the support of all the other lower frequency
accesses as defined in I2C-bus standard spec.
Fast-mode Plus (Fm+) - Bit rate up to 1 Mbit/s
High-speed mode (Hs) - Bit rate up to 3.4 Mbit/s.
All the above four bus modes are offered in all device
configurations (see Table 1) and do not require any
special setting in the device.
Applicability of I2C-Bus Protocol Features
Table 1 summarizes all the mandatory and optional
features of standard I2C-slave bus specifications. The I2C
nvSRAM supports all mandatory features of a standard I2C
slave device.
Table 1. Applicability of I2C-bus protocol
2
I C nvSRAM
START condition
I C Spec
Standards
Mandatory
STOP condition
Mandatory
√
Acknowledge
Mandatory
√
7-bit slave address
Mandatory
√
10-bit slave address
Optional
Not Offered
Clock stretching
Optional
Not Required
General call address
Optional
Not Offered
Device ID
Optional
Not Offered
Software Reset
Optional
Not Offered
Feature
2
√
I2C nvSRAM Device Options
Standard-mode (Sm) - Bit rate up to100 Kbit/s
Cypress supports I2C nvSRAM in different configurations
and package options as shown in Table 2.
Fast-mode (Fm) - Bit rate up to 400 Kbit/s
Table 2. I2C nvSRAM Configurations
Status
Operating
Voltage
(Typ)
CY14CXXXJ
1
CY14BXXXJ
NRND
2.5 V
NRND
3V
1
CY14EXXXJ
1
CY14CXXXJ
NRND
5V
NRND
2.5 V
2
CY14BXXXJ
2
CY14EXXXJ
NRND
3V
NRND
5V
2
CY14CXXXJ
3
CY14BXXXJ
NRND
2.5 V
NRND
3V
3
CY14EXXXJ
3
CY14CXXXI
NRND
5V
Contact Cypress
2.5 V
CY14BXXXI
In Production
3V
CY14EXXXI
In Production
5V
nvSRAM
Part Number
Number of
Devices Per
2
I C Bus
Package
WP Pin
VCAP Pin /
AutoStore
(
) Pin /
HW Store
8 SOIC
Yes
No/No
No/No
8 SOIC
Yes
Yes/Yes
No/No
16 SOIC
Yes
Yes/Yes
Yes
Yes
Note 1
4 or 8
Note 1
NO
16 SOIC
Yes
Yes/Yes
Yes
Yes
Note 1
4 or 8
Note 1
YES
A0 Pins
Yes
Note 1
No
4 or 8
Note 1
4
RTC
NO
NO
NRND – Not Recommended for new designs
Note 1 The least significant slave address bit space (A0) is internally used in 1-Mbit nvSRAM devices; therefore it is not available in 1-Mbit
2
density options. The A0 pin is available in all 512-Kbit and lower density options except J2 parts. Without A0 pin, the I C nvSRAM is limited to
2
maximum of four devices per I C bus.
www.cypress.com
Document No. 001-74875 Rev. *E
2
2
Designing with Serial I C nvSRAM
I2C nvSRAM Device Connections
A typical I2C single master-multi slave configuration is
shown in Figure 1. The I2C master device can be any
microcontroller or a programmable device, which should
be capable of generating I2C master protocols, whereas
the slave devices can be any standard I2C slave device. In
Figure 1 example, the I2C nvSRAM is taken as an I2C
slave. Since 512-Kbit and lower density I2C nvSRAMs
support three slave addressing bits in a few package
options, it is possible to connect up to eight devices on the
same I2C bus. A unique slave ID is assigned to each slave
device by configuring slave select address lines (A2, A1,
A0) in eight different combinations. In a package
configuration where A0 is not available, it is possible to
connect only up to four slave devices sharing the same
bus by configuring slave select address pins A2 and A1.
Figure 1. Typical I2C Master Slave Configuration
Vcc
Rp
Rp
SCL
Microcontroller
SDA
Vcc
nvSRAM
A0
Vcc
nvSRAM
SCL
A0
A1
SCL
A0
A1
A2
SDA
nvSRAM
SCL
A1
A2
SDA
#0
A2
#1
SDA
#7
A typical system level configuration of the I2C nvSRAM device is illustrated in Figure 2. For microcontrollers that do not have a
dedicated I2C bus, general purpose I/O ports may be used for SCL and SDA by bit banging.
Figure 2. Typical I2C nvSRAM Connection
VCC
Controller or SOC
Controller
Core
Digital
Blocks
Power and
Clocks
I2C Control (Master)
Analog
Blocks
Rp
General Purpose I/O
Memory
Blocks
Rp
I2C nvSRAM
SCL
SCL
A0 /NC
SDA
SDA
A1
A2
GPIO1
WP
GPIO2
INT
GPIO3
HSB
Controlled
by GPIOs
or
Externally
hardwired
A0 is a NC pin in
1Mbit nvSRAM
devices
These are optional
connections. These pins can
be configured to their default
logic state
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Document No. 001-74875 Rev. *E
3
2
Designing with Serial I C nvSRAM
Sample Circuits
The following figures (Figure 3 to 5) show the detailed schematic connections for 1-Mbit I2C nvSRAMs. The hardware
connections between an I2C master and the nvSRAM slave will remain the same for all lower density (512-Kbit and below)
parts.
Figure 3. 8 Pin SOIC 1-Mbit I2C nvSRAM Interface (No VCAP)
Vcc
All
optional
connections
are
shown as dotted
lines.
0.1 µF
Vcc
Vcc
10
KΩ
10
KΩ
1*
8
VCC
2
7
WP
NC/A0
FROM
MASTER
A1
FROM
MASTER
3
A2
CY14x101J1
8 SOIC
4
VSS
6
5
SCL
SDA
Vcc
Vcc
FROM
MASTER
Rp
FROM
MASTER
Rp
FROM / TO
MASTER
Pull-up resistors on
A2 and A1 will set
the slave addresses
bits A2 and A1 to ‘1’.
If system requires
configuring either of
the address pin as ‘0’
then remove the pullup resistor and leave
the pin floating. It will
be pulled to LOW
internally by a weak
pull-down resistor.
Figure 4. 8 Pin SOIC 1-Mbit I2C nvSRAM Interface (with VCAP)
Vcc
0.1 µF
Vcc
10
KΩ
FROM
MASTER
FROM
MASTER
Vcc
10
KΩ
47 uF +/-10%,
(6.3V)
VCAP
A1
A2
VSS
www.cypress.com
1
2
3
8
CY14x101J2
8 SOIC
4
Document No. 001-74875 Rev. *E
7
6
5
Vcc
VCC
WP
SCL
SDA
Vcc
FROM
MASTER
Rp
FROM
MASTER
Rp
FROM /TO
MASTER
4
2
Designing with Serial I C nvSRAM
Figure 5. 16 Pin SOIC 1-Mbit (RTC) I2C nvSRAM Interface
Vcc
0.1 µF
Vcc
VCC
NC
1
16
VRTCbat
2*
*
15 INT/SQW
XOUT
3*
14
XIN
4
10 KΩ
3V Li
Battery
47 uF +/-10%, (6.3V)
XOUT
XIN
Vcc
10
KΩ
FROM MASTER
WP
5
NC/A0
6
VRTCcap
7
VSS
8
*
CY14x101I
16 SOIC
FROM MASTER
470 mF
(12 days RTC
Backup)
TO MASTER
+
*
Vcc
VCAP
13
A2
12
SDA
11
SCL
10
A1
Vcc
Vcc
10
KΩ
FROM MASTER
Rp
Vcc
9
FROM / TO MASTER
Rp
Vcc
10
KΩ
FROM MASTER
10
KΩ
FROM MASTER
HSB
FROM/ TO MASTER
Y1 = 32.768 KHz (12.5 pF)
Pin marked with ‘*’ are specific to the RTC nv RAM part. These pins become no
connect (NC) pin in non RTC parts.
XIN
XOUT
C1
12 pF
Pin 6 of CY14x101I (Figure 5)and Pin 1 of CY14x101J1 (Figure 3) are NC pins for 1
Mbit density. It is enabled as Slave Address bit 0 (A0) for 512 Kbit and lower density
parts.
C2
68 pF
Connect either a battery on the VRTCbat or a super capacitor on the VRTCcap pin.
Determining I2C Pull-up Resistor
Values
The I2C bus transmits data and clock on SDA and SCL
lines. The SDA and SCL lines are open-drain (also known
as open-collector in the TTL family) output driver, that
means I2C master and slave devices can only drive these
lines to logic LOW or leave them open. The termination
resistor (Rp) pulls the line HIGH to the VCC if no I2C device
on the same bus is pulling it LOW. The open drain driver
configuration is required to support some special I2C
features such as multi-master configuration and clock
stretching by slave. The clock stretching is an optional
feature of I2C standard and not supported in I2C nvSRAM,
therefore the I2C clock signal is an input (only) signal in I2C
nvSRAM.
Together with the total bus capacitance (Cb), the
termination resistor (Rp) affects the timing behavior of the
signals on SDA and SCL. While I2C device pulls down the
line with open drain drivers, the pull-up resistor Rp is
responsible to get the signal back to HIGH level in a
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specified time. The value of pull Rp depends on multiple
electrical parameters such as operating voltage (VCC),
output LOW logic level (VOL) spec of the device; sink
current (IOL) spec, total bus load (Cb) and timing
parameters such as rise time (tR) spec.
The following sections describe the methods of
determining the pull resistor value for I2C bus in a given
system configuration.
Determining Rp (Max)
Consider the input threshold of CMOS logic level as VIH =
0.7 VCC (Min) and VIL = 0.3 VCC (Max) for the purposes of
RC time constant calculation.
Then V(t) = VCC (1 − e−t / RC), where t is the time since
the charging started and RC is the time constant.
V (t1) = 0.3 × VCC = VCC (1 − e−t1 / RC) then:
Equation 1
V (t2) = 0.7 × VCC = VCC (1 − e−t2 / RC); then:
Document No. 001-74875 Rev. *E
Equation 2
5
2
Designing with Serial I C nvSRAM
The total rise time (T) is the time it takes to charge the bus
capacitance voltage level from VIL to VIH:
T = t2 − t1
= 1.2039729 × RC - 0.3566749 × RC
Equation 3
Low power designs should prefer using a value toward the
higher limit of the range in order to limit the current
consumption.
Table 3 provides the list of values of Rp (Min, Max) for a
given bus load condition and operating voltage. Values not
appearing in Table 3 can be obtained from the equations 4
and 5 for calculating Rp (Max) and Rp (Min).
Equation 3 is used to determine the maximum limit for the
pull-up resistor value to connect to the I2C line. Table 3
shows maximum Rp as a function of bus capacitance for
all timing modes. For each mode, the Rp (max) is a
function of the rise time minimum (tR) and the estimated
bus capacitance (Cb):
Shaded region in the Table 3 indicates that Rp (Min)
exceeds the Rp (Max) value for a few bus loads (Cb)
under a given operating voltage condition. Since the
Rp (Min) can never exceed Rp (Max) value, this will put a
limit on the maximum capacitive load (Cb) to be used on
the I2C bus.
Equation 4
The bus capacitance (Cb) is the total capacitance of wire,
connections and pins.
For example: If a 3 V part is configured to operate at
minimum VCC supply (VCC = 2.7 V) then the system must
not exceed the following load (in picofarad) on the SCL
and SDA lines when operating in the following bus modes:
Determining Rp (Min)
Sm = Cb ≤ 550 pF; 0.77 kΩ ≤ Rp ≤ 2.15 kΩ
The operating voltage and the sink current (IOL) limit the
pull-up resistor minimum value, Rp (min). The value of
Rp (Min) as a function of VCC and IOL are calculated using
the Equation 5.
Fm = Cb ≤ 450 pF; 0.77 kΩ ≤ Rp ≤ 0.79 kΩ
Equation 5
The value of Rp must be selected within specified min and
max range.
Fm+ = Cb ≤ 150 pF; 0.77 kΩ ≤ Rp ≤ 0.94 kΩ
Hs
= Cb ≤ 100 pF; 0.77 kΩ ≤ Rp ≤0.94 kΩ
Similarly, the max bus load (Cb) and I2C pull-up resistor
(Rp) value for other operating voltages and operating
frequencies can be obtained from Table 3 and Figure 6.
Equation 6
Table 3. Rp (Min, Max) Values for Different Bus Loads and Operating Voltages
Cb (pf)
10
20
30
40
50
60
70
80
90
100
125
150
200
250
300
350
400
450
500
550
Rp(Min) (kΩ)
Rp(Max) (kΩ)
2.45V
100 KHz 400 KHz 1 MHz 3.4 MHz
0.68
0.68
0.68
0.68
0.68
0.68
0.68
0.68
0.68
0.68
0.68
0.68
0.68
0.68
0.68
0.68
0.68
0.68
0.68
0.68
118.02 35.41 14.16
59.01 17.70 7.08
39.34 11.80 4.72
29.51 8.85 3.54
23.60 7.08 2.83
19.67 5.90 2.36
16.86 5.06 2.02
14.75 4.43 1.77
13.11 3.93 1.57
11.80 3.54 1.42
9.44
2.83 1.13
7.87
2.36 0.94
5.90
1.77 0.71
4.72
1.42 0.57
3.93
1.18 0.47
3.37
1.01 0.40
2.95
0.89 0.35
2.62
0.79 0.31
2.36
0.71 0.28
2.15
0.64 0.26
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9.44
4.72
3.15
2.36
1.89
1.57
1.35
1.18
1.05
0.94
0.76
0.63
0.47
0.38
0.31
0.27
0.24
0.21
0.19
0.17
Cb (pf)
10
20
30
40
50
60
70
80
90
100
125
150
200
250
300
350
400
450
500
550
Rp(Min) (kΩ)
Rp(Max) (kΩ)
2.7V
100 KHz 400 KHz 1 MHz 3.4 MHz
0.77
0.77
0.77
0.77
0.77
0.77
0.77
0.77
0.77
0.77
0.77
0.77
0.77
0.77
0.77
0.77
0.77
0.77
0.77
0.77
118.02 35.41 14.16
59.01 17.70 7.08
39.34 11.80 4.72
29.51 8.85 3.54
23.60 7.08 2.83
19.67 5.90 2.36
16.86 5.06 2.02
14.75 4.43 1.77
13.11 3.93 1.57
11.80 3.54 1.42
9.44
2.83 1.13
7.87
2.36 0.94
5.90
1.77 0.71
4.72
1.42 0.57
3.93
1.18 0.47
3.37
1.01 0.40
2.95
0.89 0.35
2.62
0.79 0.31
2.36
0.71 0.28
2.15
0.64 0.26
9.44
4.72
3.15
2.36
1.89
1.57
1.35
1.18
1.05
0.94
0.76
0.63
0.47
0.38
0.31
0.27
0.24
0.21
0.19
0.17
Document No. 001-74875 Rev. *E
Cb (pf)
10
20
30
40
50
60
70
80
90
100
125
150
200
250
300
350
400
450
500
550
Rp(Min) (kΩ)
Rp(Max) (kΩ)
4.5V
100 KHz 400 KHz 1 MHz 3.4 MHz
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
118.02 35.41 14.16
59.01 17.70 7.08
39.34 11.80 4.72
29.51 8.85 3.54
23.60 7.08 2.83
19.67 5.90 2.36
16.86 5.06 2.02
14.75 4.43 1.77
13.11 3.93 1.57
11.80 3.54 1.42
9.44
2.83 1.13
7.87
2.36 0.94
5.90
1.77 0.71
4.72
1.42 0.57
3.93
1.18 0.47
3.37
1.01 0.40
2.95
0.89 0.35
2.62
0.79 0.31
2.36
0.71 0.28
2.15
0.64 0.26
9.44
4.72
3.15
2.36
1.89
1.57
1.35
1.18
1.05
0.94
0.76
0.63
0.47
0.38
0.31
0.27
0.24
0.21
0.19
0.17
6
2
Designing with Serial I C nvSRAM
Figure 6. Rp (Min, Max) Values for Different Bus Loads and Operating Voltages
3.4 MHz
1 MHz
400 KHz
100 KHz
Operating Voltage (Vcc), V
Bus Load (Cb), pF
Control Input Pin Configuration
2
The I C nvSRAM has many control pins that are input pins
and they should be properly biased to fixed logic state
(HIGH or LOW) for the proper operation of the device. If
an input control pin is left floating without biasing it o
appropriate logic levels (either HIGH or LOW) then it is
possible that the floating pin may settle to some
intermediate metabstable state, which can make device
behavior random. Therefore, all unused input pins that do
not have any internal pull-up or pull-down option should
always be tied to a proper logic level externally by using
pull-up or pull-down resistor. A resistor of value between
1 kΩ -10 kΩ can be used for this purpose.
WP Pin:
The WP pin is an active high pin and protects entire
memory and all registers from write operations. When this
pin is HIGH, all memory and register writes are prohibited
and address counter is not incremented. The I2C nvSRAM
provides an internal pull-down resistor on this pin.
Therefore, this pin can be left floating (no connect) if write
protect functionality is not used. If this pin is connected to
a controller I/O for external control then an external pull-up
resistor is recommended to avoid any undesired triggering
due to noise on this line. A resistor of value between 1 kΩ
-10 kΩ can be used for this purpose.
A2, A1, A0 Pins:
These are slave address pins and are used to configure
the different slave addresses for different slave devices in
multi slave configuration. These pins are internally pulled
to LOW and hence can be left floating (not connected) if
not used. To configure to logic HIGH state, these pins
should either be connected to external pull-up resistor or
these can be directly connected to the VCC power supply.
A resistor of value between 1 kΩ -10 kΩ can be used as a
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pull-up resistor. In a few configurations where system
requires changing the slave address dynamically, these
address pins should be connected to the controller I/Os for
configuring the slave select address pins (A2, A1, A0) on
the fly and access the device.
Pin:
The
pin is a bidirectional pin on the nvSRAM. As an
output, it provides nvSRAM ready or busy status during
normal operation. When device is powering up or a
nonvolatile Store cycle is in progress, the
pin is
pulled to LOW by the device indicating its busy status.
When the
pin is in HIGH state, it indicates that the
device is ready for normal write or read operations. As an
input pin, the
pin is used to initiate hardware STORE
externally by pulling it to LOW by the controller. This pin
can be left floating if not connected to any GPIO. The I2C
nvSRAM provides an internal weak pull-up resistor on the
pin to keep it HIGH during normal operation. If this
pin is connected to a controller I/O for external control then
an external pull-up resistor is recommended to avoid any
undesired triggering due to noise on this line. A resistor of
value between 1 kΩ -10 kΩ can be used for this purpose.
VCAP:
A capacitor connected on the VCAP pin supplies power to
the nvSRAM for transferring data SRAM nonvolatile
elements in case of power loss. During normal operation,
the device draws current from VCC to charge the capacitor
on VCAP. Stored charge on the VCAP is used by the
nvSRAM device to perform a single STORE operation. If
the voltage on the VCC pin drops below VSWITCH, the device
automatically isolates the VCAP pin from VCC and STORE
operation is initiated using stored charge on the VCAP.
Document No. 001-74875 Rev. *E
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Designing with Serial I C nvSRAM
It is a must to connect an appropriate value capacitor on
the VCAP pin for a successful AutoStore operation. The
capacitor value selected should fall within the range
prescribed in the device datasheet. An improper selection
of capacitor may lead to malfunctioning of the device. See
application note, AN43593 - Storage Capacitor Options for
Cypress nvSRAM, for more details on capacitor selection
guidelines for nvSRAM products.
/L set to ‘0’
H/L =0
P/L=0
Pulled HIGH
with External
Pull up
Hi-Z When no
pull up
Interrupt Occurs
RTC Part Specific Pin Configuration
The RTC feature requires following additional pins on the
package. These pins should be configured appropriately
for correct RTC function.
INT Pin: This is an output pin in the RTC parts. The RTC
nvSRAM offers different functionalities such as alarm,
watchdog timer, calibration clock output, and square wave
generator. The INT output is multiplexed to bring out the
status/ output of functionalities, depending upon the RTC
register setting and their priority defined in the nvSRAM.
The INT pin is a configurable driver output. The output
mode of INT pin is configured by setting ‘H/L’ bit in the
Interrupt Status/Control register (0x06) in the I2C slave
device. When the /L bit is set to ‘1’, the INT output is
configured as active HIGH and the drive mode is push
pull. When the /L bit is set to ‘0’, the INT output drive is
configured as active LOW open drain output and thus
requires an external pull-up resistor to drive the output to a
logic HIGH state when not driven by the device. The INT
pin must be pulled to the VCC by using an external pull-up
resistor of value between 1 kΩ – 10 kΩ when using INT in
active low mode ( /L bit is set to ‘0’).
200 ms
H/L =0
P/L=1
VRTCbat and VRTCcap Pins: These pins are used to provide
the backup power supply to the RTC circuitry to keep the
oscillator clock running when the system power supply
(VCC) is down. To backup the RTC oscillation during power
down, either connect VRTCbat to a non-rechargeable or
connect a super capacitor on the VRTCcap pin. If not used,
these pins should be left floating.
Note The VRTCcap pin cannot be shorted to the VSS directly
because this pin is used to charge the super capacitor
connected to it during the normal operation. Hence,
connecting the VRTCcap pin directly to the ground (VSS) may
draw excessive current from the nvSRAM.
For nvSRAM RTC design guidelines and best practices,
see application note, AN61546 - Non Volatile Static
Random Access Memory (nvSRAM) Real Time Clock
(RTC) Design Guidelines and Best Practice.
The INT pin behavior for different H/L and P/L
settings: The H/L bit setting determines the status of INT
pin output as HIGH or LOW when interrupt occurs.
Similarly, the P/L settings determine the pulse or level for
the INT pin. The I2C nvSRAM interrupt pin (INT) behavior
is shown in Figure 7.
Figure 7. INT Pin Behavior (RTC)
/L set to ‘1’
H/L =1
P/L=0
Interrupt Occurs
200 ms
H/L =1
P/L=1
www.cypress.com
Document No. 001-74875 Rev. *E
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Designing with Serial I C nvSRAM
I2C nvSRAM Operation
reads. Each byte has to be followed by an Acknowledge
(A) bit. Data is transferred with the most significant bit
(MSb) first and the least significant bit (LSb) last in each
2
byte transfer. Figure 8 shows the I C nvSRAM data
transfer.
The I2C nvSRAM access is always in byte format and
every byte put on the SDA line must be 8 bits long. The
number of bytes that can be transmitted per transfer is
unrestricted; therefore it supports burst mode writes and
Figure 8. I2C nvSRAM Data Transfer
The I2C nvSRAM data transfers follow the format shown in
communicate on the bus, it can generate a repeated
START condition (Sr) instead and address the slave again
or communicate with the other slave devices without
generating a STOP condition. All standard I2C modes
except the high-speed mode will follow the data format as
described in
Figure 9. After the START condition (S), a slave address
is sent. This address is 7 bits long followed by 8th bit,
which is a data direction bit (R/ ). If bit (R/ ) is set to ‘0’ it
indicates a transmission (WRITE), if this bit (R/ ) is set ‘1’
it indicates a request for data (READ). A data transfer is
always terminated by a STOP condition (P) generated by
the master. However, if a master still wishes to
Figure 9.
Figure 9. I2C Data Byte Format (Sm, Fm, Fm+)
S S
7 Bits
Slave
Address
7 Bits
Slave
Address R/W
A
DATA
A
R/W
A
DATA
ADATA
A/A
DATA P A/A
P
A = Acknowledged
(SDA LOW
during
ACKduring
clock) ACK clock)
A = Acknowledged
(SDA
LOW
= From I2C Master to I2C Slave
= From I2C Master to I2C Slave
A = Not Acknowledged (NACK) (SDA HIGH in ACK clock)
A = Not Acknowledged (NACK) (SDA HIGH in ACK clock)
S/P = START /STOP Condition
= From I2C Slave to I2C Master
S/P = START /STOP Condition
= From I2C Slave to I2C Master
Figure 10. Data Byte Format (Sm, Fm, Fm+) – Write Operation
S
7 Bits Slave Address
0
A
DATA
A
DATA
A
P
Figure 11. Data Byte Format (SM, FM, Fm+) - Read Operation
S
www.cypress.com
7 Bits Slave Address
1
A
DATA
A
Document No. 001-74875 Rev. *E
DATA
A/A
P
9
2
Designing with Serial I C nvSRAM
7 bits slave address followed by 8th bit, which is a data
direction bit (R/ ). If bit (R/ ) is set to ‘0’ it indicates a
In Hs-mode the nvSRAM can transfer data at bit rates up
transmission (WRITE), if this bit (R/ ) is set ‘1’ it indicates
to 3.4 Mbit/s. After the START condition (S) is generated,
a request for data (READ). A data transfer is always
an 8-bit master code (0000 1XXXb) is sent for which
terminated by a STOP condition (P) generated by the
nvSRAM sends the NACK ( ) but put the data interface in
master. However, if a master still wishes to communicate
Hs-mode for all subsequent operations. The device exits
on the bus in Hs-mode, it can generate a repeated START
Hs-mode only after following the STOP (P) condition. After
condition (Sr) and address the slave without generating a
2
putting the slave in Hs-mode, the I C master transmit
STOP condition.
Figure 12. I2C Data Byte Format (Hs)
High-Speed Mode (Hs-mode) Operation
SM/ FM/ Fm+ Mode
S
Hs Mode
Master Code (0000 1XXX)
A/A
Sr
7 Bits Slave Address
R/W
A
SM/ FM/ Fm+ Mode
DATA
A
DATA
A/A
P
A = Acknowledged (SDA LOW during ACK clock)
= From I2C Master to I2C Slave
Hs Mode Continues
A = Not Acknowledged (NACK) (SDA HIGH in ACK clock)
Sr
S/P = START /STOP Condition
= From I2C Slave to I2C Master
7 Bits Slave Address
Sr - Repeated Start
Figure 13. I2C Data Byte Format (Hs) – Write Operation
SM/ FM/ Fm+ Mode
S
Hs Mode
Master Code (0000 1XXX)
A/A
Sr
7 Bits Slave Address
0
A
DATA
A
DATA
A
P
A
DATA
A/A
P
Figure 14. I2C Data Byte Format (Hs) – Read Operation
SM/ FM/ Fm+ Mode
S
Hs Mode
Master Code (0000 1XXX)
A/A
S
7 Bits Slave Address
Addressing in I2C nvSRAM
2
1
A
DATA
operation, it always transmits the most significant bit first
and the least significant bit last.
2
An I C master controller communicates with the I C
nvSRAM slave on byte-by-byte basis and always transmits
the most significant bit in the first clock cycle and the least
significant bit in the 8th clock cycle during a byte
transmission. This holds good for all I2C communication
including command, address, and data bytes. Similarly,
when an I2C nvSRAM transmits the data byte during read
Figure 15 shows an example of address bits being
transmitted over the I2C bus.
The 7 bits long slave address is represented by acronym
“ A [6:0]” to differentiate it from memory address bits,
which use acronym “A [16:0]”. enceforth all the follow on
sections will show slave address bits as SA [x].
Figure 15. Address Bits Transmission in I2C nvSRAM
7 Bits Slave Address
S
4 Bits Slave Device Address
(SA [6:3])
www.cypress.com
SA2
SA1
Address Byte2 (MSB)
SA0 /
A16
0
A
A15
A14
A13
A12
A11
A10
Address Byte1 (LSB)
A9
Document No. 001-74875 Rev. *E
A8
A
A7
A6
A5
A4
A3
A2
A1
A0
A
10
2
Designing with Serial I C nvSRAM
S l a ve D e vi c e Ad d r e s s
The I2C nvSRAM slave supports 7 bits slave addressing
SA [6:0] of which four most significant address bits SA
[6:3] are fixed in the device and not alterable by the user.
The remaining three least significant address bits SA [2:0]
are configurable through external address pins (A2, A1,
A0) provided on the device. The I2C nvSRAM offers three
different functions as data Memory, RTC function, and
2
other Controls in a single device. The I C nvSRAM
assigns three unique slave IDs by fixing upper 4 bits (see
Table 4) of the slave address SA [6:3] to allow an I2C
master to access these functions.
Table 4. Slave Device Address
If any other slave ID on the bus matches with the upper four slave address bit SA [6:3], then the user must configure lower
slave address bits SA [2:0] differently so that it each slave device sharing the same system bus has been assigned an unique
slave ID.
Figure 16. Slave Device Address Select
7 Bits Slave Address
7 Bits Slave Address
S
1
0
1
Slave Device
Address (Memory)
0
SA2
SA1
SA0 /
A16/X
R/W
S
1
1
0
1
SA2
7 Bits Slave Address
SA1
SA0 /
X
Slave Device
Address (RTC)
R/W
S
0
0
1
1
SA2
SA1
SA0 /
X
R/W
Slave Device
Address (Controls)
Table 5. I2C nvSRAM addressing for SRAM Write and Read
Note 2 Unused bits of the most significant address byte (M ) are don’t care bits and nv RAM ignores them. owever, the best practice is to
set the unused address bit locations to ‘0’ in the firmware. This approach makes it easy in upgrading the firmware while moving to a higher
density option in future.
Note 3 In some nvSRAM device configurations only two address pins (A2, A1) are provided either due to unavailability of sufficient pins on the
2
package or A0 address bit is used internally. The I C nvSRAM with 1-Mbit density requires 17 address bits A [16:0] to map its entire memory
location. Therefore, the slave address space SA0 is used to transmit the A16 address bit in these parts and allows only 2 bits SA [2:1] to
configure the slave address externally. In lower density devices (512 Kbit and below) where A0 is not available on the package due to
2
shortage of pins, this bit becomes don’t care (‘X’) internally. The I C slave device with slave address bit A0 as don’t care will acknowledge for
2
two slave addresses (for A0=0 and A0=1) sent by the I C master.
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Document No. 001-74875 Rev. *E
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Designing with Serial I C nvSRAM
I2C nvSRAM Access
All I2C nvSRAM functions including standard (memory
writes and reads) and special (NV Operations, Device ID,
and Serial Number) are accessed through standard I2C
write and read protocols. Figure 17 to Figure 21 shows a
simplified flow diagram explaining I2C nvSRAM write and
read operations. The device datasheet should be referred
for detailed description on each I2C nvSRAM functions and
their implementation details.
Figure 17. Simplified Flow Diagram for I2C nvSRAM Data Memory Write
Device Idle
Start (S) /Repeat Start (Sr)
Slave Address
1010 SA[2:0] (R/W =0)
No
Did Slave
Address Match?
Yes
Send ACK
Receive Addr bytes
Send ACK
Bus status
P or Sr?
No
Are Two Bytes
Addr Rcvd?
No
Yes
Internal address counter is
set to the new address.
Yes
Bus status
P or Sr?
No
Yes
Send NACK
Is it protected
memory?
No
Once address counter reaches to
the last addressable location of
data memory, the auto increment
will roll over to the start address
0x0000 and start overwriting
previously written data
Receive data byte. Auto
increment to next address
Send ACK
Bus status
P or Sr?
No
Yes
Device Idle
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Document No. 001-74875 Rev. *E
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Designing with Serial I C nvSRAM
Figure 18. Simplified Flow Diagram for I2C nvSRAM RTC and Control Registers Write
Device Idle
Device Idle
Start (S) /
Repeated Start (Sr)
Start (S) /
Repeated Start (Sr)
Slave Address
0011 SA[2:0] (R/W =0)
Slave Address
1101 SA[2:0] (R/W =0)
No
Did Slave
Address Match?
No
Did Slave
Address Match?
Yes
Send ACK
Yes
Send ACK
Receive Addr bytes
Receive Addr bytes
Yes
Yes
Send NACK
Is Add Out
of Bound?
Send NACK
Is Add Out
of Bound?
No
Send ACK
No
Send ACK
Bus status
P or Sr?
No
Bus status
P or Sr?
Internal address counter is
set to the new Cntrl Reg Addr.
No
Internal address counter is
set to the new RTC Reg Addr.
Yes
Once the address counter reaches
to the last writable location in
control register, the auto increment
will go to the next addressable
location and stays there. Device will
return a NACK for all Subsequent
bytes sent by master for write.
Bus status
P or Sr?
No
Yes
Bus status
P or Sr?
No
No
Once address counter reaches to
the last addressable location of
RTC Regs, the auto increment will
roll over to the start address 0x00
and start overwriting previously
written data
Receive data byte. Auto
increment to next address
Send ACK
Bus status
P or Sr?
www.cypress.com
No
Is Current address
writable?
Yes
Receive data byte
Receive data byte. Auto
increment to next address
Send ACK
Send
NACK
Bus status
P or Sr?
Yes
Yes
Device Idle
Device Idle
Document No. 001-74875 Rev. *E
No
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2
Designing with Serial I C nvSRAM
Figure 19. Simplified Flow Diagram for I2C nvSRAM Data Memory Current Address Read
Device is Idle
Start (S) /
Repeated Start (Sr)
Slave Address
1010 SA[2:0] (R/W =1)
No
Did Slave
Address Match?
Yes
Send ACK
Yes
Once address counter reaches to
the last addressable location of the
data memory, the auto increment
will roll over to the start address
0x0000 and start reading data
from there onwards.
Bus status
P or Sr?
No
Send Data Byte from Current Addr.
Auto Increment to Next Addr.
No
ACK Rcvd
from Master?
Yes
No
Bus Status
P or Sr?
Yes
Device Idle
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Document No. 001-74875 Rev. *E
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Designing with Serial I C nvSRAM
Figure 20. Simplified Flow Diagram for I2C nvSRAM RTC and Control Register Current Address Read
Device is Idle
Device is Idle
Start (S) /
Repeated Start (Sr)
Start (S) /
Repeated Start (Sr)
Control
Function
RTC
Function
Slave Address
1101 SA[2:0] (R/W =1)
Slave Address
011 SA[2:0] (R/W =1)
Did Slave
Address Match?
Yes
Send ACK
Yes
Send ACK
Yes
Yes
No
Did Slave
Address Match?
No
Bus status
P or Sr?
No
Send Data Byte from Current Addr.
Auto Increment to Next Addr.
Once address counter reaches to
the last addressable location of te
RTC registers, the auto increment
will roll over to the start address
0x00 and start sending data out
from there onwards.
Once the address counter reaches
to the last readable address
location in control register, the
auto increment will go to the start
address 0x00 and start sending
data out from there onwards.
Bus status
P or Sr?
No
Send Data Byte from Current Addr.
Auto Increment to Next Addr.
No
No
No
No
ACK Rcvd
from Master?
ACK Rcvd
from Master?
Yes
Yes
No
No
Bus Status
P or Sr?
Bus Status
P or Sr?
Yes
Yes
Device Idle
Device Idle
The flow charts as shown in Figure 19 and
Figure 20 are for the current location read from data memory, RTC register and control register. The current location is the
address in the address counter at the time of exiting the previous write or read operations. In case if the user needs to read
from a different location then the user must set the address counter with a new address by performing a write cycle as shown
in Figure 21.
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Document No. 001-74875 Rev. *E
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Designing with Serial I C nvSRAM
Figure 21. Simplified Flow Diagram for I2C nvSRAM Data Memory, RTC, and Control Register Random Address Read
Set Current Address for Data
Memory
Set Current Address for RTC
Registers
Set Current Address for Control
Registers
Device Idle
Device Idle
Device Idle
Start (S) /
Repeated Start (Sr)
Start (S) /
Repeated Start (Sr)
Start (S) /
Repeated Start (Sr)
Slave Address
1101 SA[2:0] (R/W =0)
Slave Address
0011 SA[2:0] (R/W =0)
Slave Address
1010 SA[2:0] (R/W =0)
No
No
Did Slave
Address Match?
Did Slave
Address Match?
Yes
Send ACK
Yes
Send ACK
Yes
Send ACK
Receive Addr bytes
Receive Addr bytes
Receive Addr bytes
No
Did Slave
Address Match?
Send ACK
Bus status
P or Sr?
Is Add Out
of Bound?
No
Is Add Out
of Bound?
Send NACK
No
Send ACK
No
Are Two Bytes
Addr Rcvd?
Yes
Yes
Send NACK
No
Internal address counter is
set to the new RTC Reg Addr.
Internal address counter is
set to the new Cntrl Reg Addr.
Initiate a Read by S or Sr
Initiate a Read by S or Sr
Yes
Internal address counter is
set to the new address.
Initiate a Read by S or Sr
Summary
Cypress I2C nvSRAM supports the standard I2C access
protocols similar to any other nonvolatile I2C memory
products. This makes the nvSRAM compatible to all I2C
master controllers and reduces the system development
cycle time. This application note demonstrates how to
configure the I2C nvSRAM in an application with the help
of schematics and timing diagrams.
www.cypress.com
Document No. 001-74875 Rev. *E
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Designing with Serial I C nvSRAM
Appendix A (Pseudo Code Example)
I2C Write
/*Sm, Fm, Fm+ Mode*/
void I2C_Write_nvSRAM(BYTE slave_Addr,BYTE Addr_MSB, BYTE Addr_LSB, BYTE *Data, int
n_Byte)
{
int i=0;
BYTE txBuffer[2];
txBuffer[0]=Addr_MSB; //Copy I2C slave address in local buffer
txBuffer[1]=Addr_LSB;
I2CHW_ClrWrStatus(); //Clear the status register of I2C master
I2CHW_fSendStart(slave_Addr, I2CHW_WRITE); //Returns a non zero if slave device
ACKs
while(!I2CHW_bReadI2CStatus() & I2CHW_WR_COMPLETE); //Wait till all bits are
transmitted
for (i=0;i<n_Byte; i++){
I2CHW_fWrite( Data[i]); //Master transmit data bytes
while (!I2CHW_bReadI2CStatus() & I2CHW_WR_COMPLETE);
}
I2CHW_SendStop (); // Master sends S/Sr to terminate write
}
/*Hs Mode*/
void I2C_Write_HSMODE_nvSRAM(BYTE slave_Addr,BYTE Addr_MSB, BYTE Addr_LSB, BYTE *Data,
int n_Byte)
{
int i=0;
BYTE txBuffer[2];
txBuffer[0]=Addr_MSB;
txBuffer[1]=Addr_LSB; //Copy I2C slave address in local buffer
I2CHW_ClrWrStatus(); //Clear the status register of I2C master
//0x00001xxx is a HS mode address hence. (Read/Write also don’t care).HS mode command
byte can be set anything from 0x08 to 0x0F
I2CHW_fSendStart( 0x04, I2CHW_WRITE); //No ACK from any slave.
while(!I2CHW_bReadI2CStatus() & I2CHW_WR_COMPLETE);//Wait till all bits are
transmitted
I2CHW_fSendRepeatStart(slave_Addr, I2CHW_WRITE); //Send repeat start with slave
ID to access a slave in HS mode.
while(!I2CHW_bReadI2CStatus() & I2CHW_WR_COMPLETE);
for (i=0;i<n_Byte; i++){
I2CHW_fWrite( Data[i]);
while(!I2CHW_bReadI2CStatus() & I2CHW_WR_COMPLETE);
}
I2CHW_SendStop (); //Master sends S/Sr to terminate write
}
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Document No. 001-74875 Rev. *E
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Designing with Serial I C nvSRAM
I2C Read
/*Sm, Fm, Fm+ Mode*/
void I2C_Read_nvSRAM(BYTE slave_Addr, int n_Byte)
{
int i=0;
BYTE dataRD;
I2CHW_ClrWrStatus();//Clear the status register of I2C master
I2CHW_fSendStart( slave_Addr, I2CHW_READ);
while(!I2CHW_bReadI2CStatus() & I2CHW_RD_COMPLETE);
for(i=0;i<n_Byte; i++) {
if(i==(n_Byte-1)) {
dataRD =I2CHW_bRead (I2CHW_NAKslave); //Master sends NACK for the last read to terminate
the Read
while(!I2CHW_bReadI2CStatus() & I2CHW_RD_COMPLETE); //Wait till all bits Rcvd
}
else
{
dataRD =I2CHW_bRead (I2CHW_ACKslave);
while(!I2CHW_bReadI2CStatus() & I2CHW_RD_COMPLETE);
}
}
I2CHW_SendStop (); //Master sends S/Sr to terminate Read
}
/*Hs Mode*/
void I2C_Read_HSMODE_nvSRAM(BYTE slave_Addr, int n_Byte)
{
int i=0;
BYTE dataRD;
I2CHW_ClrWrStatus();//Clear the status register of I2C master
I2CHW_fSendStart( 0x04, I2CHW_READ); //0x0000 1xxx is a HS mode address hence slave addr
can be 0x0X. No ACK from any slave.
while(!I2CHW_bReadI2CStatus() & I2CHW_RD_COMPLETE);//Wait till all bits received
I2CHW_fSendRepeatStart( slave_Addr, I2CHW_READ); //Send repeat start with slave ID to
access a slave in the HS mode.
while(!I2CHW_bReadI2CStatus() & I2CHW_RD_COMPLETE);
for(i=0;i<n_Byte; i++){
if(i==(n_Byte-1)) {
dataRD =I2CHW_bRead (I2CHW_NAKslave);
while(!I2CHW_bReadI2CStatus() & I2CHW_RD_COMPLETE);
}
else {
dataRD =I2CHW_bRead (I2CHW_ACKslave);
while(!I2CHW_bReadI2CStatus() & I2CHW_RD_COMPLETE);
}
}
I2CHW_SendStop //Master sends S/Sr to terminate Read
}
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Document No. 001-74875 Rev. *E
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Designing with Serial I C nvSRAM
Document History
Document Title: Designing with Serial I2C nvSRAM - AN74875
Document Number: 001-74875
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
3471498
ZSK
12/29/2011
New document
*A
3466105
ZSK
01/05/2012
Removed incorrect document
*B
3524014
ZSK
02/13/2012
Reactivated spec
*C
3724929
ZSK
08/27/2012
Attached PSoC 3 based I C nvSRAM component example project
*D
3918328
ZSK
03/01/2013
No update to the App note contents
2
Changed the PSoC 3 component library name from “nv RAM_I2C” to
“nvRAM_I2C”
Added APIs to access the RTC registers in the PSoC 3 example project
Made an enhancement in the PSoC 3 example project to add user select options
for memory density, RTC/non RTC, and nvSRAM /FRAM
*E
4234992
ZSK
01/08/2014
®
Added oftware Version as “P oC Creator™ 3.0 or above”.
Updated Abstract.
2
Updated I C nvSRAM Configurations:
2
Updated I C nvSRAM Device Options:
Updated Table 2.
Updated Determining I2C Pull-up Resistor Values:
Updated Figure 6.
Completing Sunset Review.
Updated in new template.
www.cypress.com
Document No. 001-74875 Rev. *E
19
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Designing with Serial I C nvSRAM
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license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or
safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The
inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies
Cypress against all charges.
This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide
patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a
personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative
works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source
Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT
NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the
right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or
use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a
malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
www.cypress.com
Document No. 001-74875 Rev. *E
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