ATMEL MMDJ-65609EV-40-E

Features
• Operating Voltage: 3.3V
• Access Time: 40 ns
• Very Low Power Consumption
•
•
•
•
•
•
•
•
– Active: 160 mW (Max)
– Standby: 70 µW (Typ)
Wide Temperature Range: -55°C to +125°C
MFP 32 leads 400 Mils Width Package
TTL Compatible Inputs and Outputs
Asynchronous
Designed on 0.35µm Process
No Single Event Latch-up below a LET threshold of 80 MeV/mg/cm2
Tested up to a Total Dose of 200 Krad (Si) according to MIL STD 883 Method 1019
Quality grades: QML Q or V with SMD 5962-02501
Description
The M65609E is a very low power CMOS static RAM organized as 131,072 x 8 bits.
Utilizing an array of six transistors (6T) memory cells, the M65609E combines an
extremely low standby supply current with a fast access time at 40 ns. The high stability of the 6T cell provides excellent protection against soft errors due to noise.
The M65609E is processed according to the methods of the latest revision of the MIL
PRF 38535 and ESCC 9000.
Rad Hard
128K x 8
3.3-volt
Very Low Power
CMOS SRAM
M65609E
It is produced on the same process as the MH1RT sea of gates series.
Rev. 4158I–AERO–07/07
1
M65609E
Block Diagram
Pin Configuration
32 pins Flatpack 400 MILS
Pin Description
Name
Description
A0 - A16
Address Inputs
I/O1 - I/O8
Data Input/Output
CS1
Chip Select 1
CS2
Chip Select 2
WE
Write Enable
OE
Output Enable
VCC
Power
GND
Ground
2
4158I–AERO–07/07
Table 1. Truth Table
Note:
3
CS1
CS2
WE
OE
Inputs/
Outputs
H
X
X
X
Z
Deselect/
Power-down
X
L
X
X
Z
Deselect/
Power-down
L
H
H
L
Data Out
Read
L
H
L
X
Data In
Write
L
H
H
H
Z
Mode
Output
Disable
L = low, H = high, X = H or L, Z = high impedance.
M65609E
4158I–AERO–07/07
M65609E
Electrical Characteristics
Absolute Maximum Ratings
Supply Voltage to GND Potential............................ -0.5V + 5V
*NOTE:
DC Input Voltage............................ GND - 0.3V to VCC + 0.3V
DC Output Voltage High Z State .... GND - 0.3V to VCC + 0.3V
Storage Temperature .................................... -65°C to + 150°C
Output Current Into Outputs (Low) ............................... 20 mA
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
Electro Statics Discharge Voltage................................. > 500V
(MIL STD 883D Method 3015.3)
Military Operating Range
Operating Voltage
Operating Temperature
3.3V + 0.3V
-55°C to + 125°C
Recommended DC Operating Conditions
Parameter
Description
VCC
Supply voltage
Gnd
Ground
Min
Typ
Max
Unit
3
3.3
3.6
V
0.0
0.0
0.0
V
VIL
Input low voltage
GND - 0.3
0.0
0.8
V
VIH
Input high voltage
2.2
–
VCC + 0.3
V
Description
Min
Typ
Max
Unit
Input low voltage
–
–
8
pF
Output high voltage
–
–
8
pF
Capacitance
Parameter
CIN(1)
COUT(1)
Note:
1. Guaranteed but not tested.
4
4158I–AERO–07/07
DC Parameters
DC Test Conditions
Parameter
(1)
IIX
IOZ (1)
1.
2.
3.
Description
Minimum
Typical
Maximum
Unit
Input leakage
current
-1
–
1
µA
Output leakage
current
-1
–
1
µA
VOL
(2)
Output low voltage
-
–
0.4
V
VOH
(3)
Output high voltage
2.4
–
–
V
Gnd < Vin < VCC, Gnd < Vout < VCC Output Disabled.
VCC min. IOL = 4 mA.
VCC min. IOH = -2 mA.
Consumption
1.
2.
3.
5
Symbol
Description
65609E-40
Unit
Value
ICCSB (1)
Standby supply current
1.5
mA
max
ICCSB1 (2)
Standby supply current
1
mA
max
ICCOP (3)
Dynamic operating
current
45
mA
max
CS1 > VIH or CS2 < VIL and CS1 < VIL.
CS1 > VCC - 0.3V or, CS2 < Gnd + 0.3V and CS1 < 0.2V
F = 1/TAVAV, IOUT = 0 mA, W = OE = VIH, Vin = Gnd or VCC, VCC max.
M65609E
4158I–AERO–07/07
M65609E
Write Cycle
Symbol
Note:
Parameter
65609E-40
Unit
Value
tAVAW
Write cycle time
35
ns
min
tAVWL
Address set-up time
0
ns
min
tAVWH
Address valid to end of write
28
ns
min
tDVWH
Data set-up time
18
ns
min
tE1LWH
CS1 low to write end
28
ns
min
tE2HWH
CS2 high to write end
28
ns
min
tWLQZ
Write low to high Z (1)
15
ns
max
tWLWH
Write pulse width
28
ns
min
tWHAX
Address hold from to end of
write
3
ns
min
tWHDX
Data hold time
0
ns
min
tWHQX
Write high to low Z (1)
0
ns
min
1. Parameters guaranteed, not tested, with 5 pF output loading (see Section “AC Test Conditions” Figure 2).
Read Cycle
Symbol
Note:
Parameter
65609E-40
Unit
Value
tAVAV
Read cycle time
40
ns
min
tAVQV
Address access time
40
ns
max
tAVQX
Address valid to low Z
3
ns
min
tE1LQV
Chip-select1 access
time
40
ns
max
tE1LQX
CS1 low to low Z (1)
3
ns
min
tE1HQZ
CS1 high to high Z (1)
15
ns
max
tE2HQV
Chip-select2 access
time
40
ns
max
tE2HQX
CS2 high to low Z (1)
3
ns
min
tE2LQZ
CS2 low to high Z (1)
15
ns
max
tGLQV
Output Enable access
time
12
ns
max
tGLQX
OE low to low Z (1)
0
ns
min
tGHQZ
OE high to high Z (1)
10
ns
max
1. Parameters guaranteed, not tested, with 5 pF output loading (seeSection “AC Test Conditions” Figure 2).
6
4158I–AERO–07/07
AC Parameters
AC Test Conditions
Input Pulse Level:......................................................... GND to 3.0V
Input Rise/Fall Time: .................................................... 5 ns
Input Timing Reference Level: ..................................... 1.5V
Output loading IOL/IOH (see figure 1 and 2)................ +30 pF
AC Test Loads Waveforms
Figure 1
Figure 2
R1 2552
3.3V
3.3V
Figure 3
R1 2552
2824
2824
1340
V
7
M65609E
4158I–AERO–07/07
M65609E
Data Retention Mode
Atmel CMOS RAM’s are designed with battery backup in mind. Data retention voltage
and supply current are guaranteed over temperature. The following rules ensure data
retention:
1. During data retention CS1 must be held high within VCC to VCC - 0.2V or chip
select CS2 must be held down within GND to GND +0.2V.
2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, minimizing power dissipation.
3. During power-up and power-down transitions CS1 and OE must be kept
between VCC + 0.3V and 70% of VCC, or with BS between GND and GND -0.3V.
4. The RAM can begin operation > tR ns after VCC reaches the minimum operation
voltages (3V).
Figure 1. Data Retention Timing
Data Retention Characteristics
Parameter
VCCDR
Description
Min
Typical TA = 25°C
Max
Unit
VCC for data
2.0
–
–
V
retention
TCDR
Chip deselect to
data retention time
0.0
–
–
ns
tR
Operation recovery
time
tAVAV(1)
–
–
ns
ICCDR1(2)
Data retention
current at 2.0V
–
0.010
1.0
mA
Notes:
1. TAVAV = Read Cycle Time
2. CS1 = VCC or CS2 = CS1 = GND, VIN = GND/VCC.
8
4158I–AERO–07/07
Write Cycle 1. WE Controlled.
OE High During Write
Write Cycle 2. WE Controlled.
OE Low
9
M65609E
4158I–AERO–07/07
M65609E
Write Cycle 3. CS1 or CS2
Controlled(1)
Note:
1. The internal write time of the memory is defined by the overlap of CS1 LOW and CS2 HIGH and W LOW. Both signals must
be activated to initiate a write and either signal can terminate a write by going in activated. The data input setup and hold
timing should be referenced to the actived edge of the signal that terminates the write. Data out is high impedance if OE =
VIH.
10
4158I–AERO–07/07
Read Cycle nb 1
Read Cycle nb 2
Read Cycle nb 3
11
M65609E
4158I–AERO–07/07
M65609E
Ordering Information
Part Number
Temperature Range
Speed
Package
Flow
25°C
40 ns
FP32.4
Engineering Samples
5962-0250101QXC
MMDJ-65609EV-40-E
-55 to +125°C
40 ns
FP32.4
QML Q
5962-0250101VXC
-55 to +125°C
40 ns
FP32.4
QML V
5962R0250101VXC
-55 to +125°C
40ns
FP32.4
QML V RHA
SMDJ-65609EV-40SCC
-55 to +125°C
40 ns
FP32.4
ESCC
MM0 -65609EV-40-E(1)
25°C
40 ns
Die
Engineering Samples
MM0 -65609EV-40SV(1)
-55 to +125°C
40 ns
Die
QML V
Note:
1. Contact Atmel for availability.
12
4158I–AERO–07/07
Package Drawing
32-pin Flat Pack (400 Mils)
13
M65609E
4158I–AERO–07/07
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4158H–AERO–05/07
/xM