Features • 80C52 Compatible • • • • • • • • • • • • • • • • • • • • • – 8051 pin and instruction compatible – Four 8-bit I/O ports + 2 I/O I2C Interface pins – Three 16-bit timer/counters – 256 bytes scratch pad RAM – 10 Interrupt sources with 4 priority levels – Dual Data Pointer Variable length MOVX for slow RAM/peripherals ISP (In System Programming) using standard VCC power supply. Boot ROM contains low level FLASH programming routines and a default serial loader High-Speed Architecture – 40 MHz in standard mode – 20 MHz in X2 mode (6 clocks/machine cycle) 32-Kbytes on-chip FLASH program / data Memory – Byte and page (128 bytes) erase and write – 10k write cycles – On-chip 1024 bytes expanded RAM (XRAM) – Software selectable size (0, 256, 512, 768, 1024 bytes) – 256 bytes selected at reset for T87C51RB2/RC2 compatibility Keyboard interrupt interface on port P1 400-Kbits/s Multimaster I 2C Interface SPI Interface (Master / Slave Mode) Sub clock 32kHz crystal oscillator 8-bit clock prescaler Improved X2 mode with independant selection for CPU and each peripheral Programmable Counter Array 5 Channels with: – High Speed Output, – Compare / Capture, – Pulse Width Modulator, – Watchdog Timer Capabilities Asynchronous port reset Full duplex Enhanced UART Dedicated Baud Rate Generator for UART Low EMI (inhibit ALE) Hardware Watchdog Timer (One-time enabled with Reset-Out) Power control modes: – Idle Mode. – Power-down mode. – Power-Off Flag. Power supply: 4.5V to 5.5V or 2.7V to 3.6V Temperature ranges: Commercial (0 to +70°C) and industrial (-40°C to +85°C). Packages: PLC44, VQFP44 8-bit Microcontroller with Flash and I2C Interface T89C51IC2 Summary Description T89C51IC2 is a high performance FLASH version of the 80C51 8-bit microcontrollers. It contains a 32-Kbytes Flash memory block for program and data. The 32-Kbytes FLASH memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin. The T89C51IC2 retains all features of the 80C52 with 256 bytes of internal RAM, a 7source 4-level interrupt controller and three timer/counters. Rev. C – 3-Dec-01 1 In addition, the T89C51IC2 has a 32kHz Subsidiary clock Oscillator, a Programmable Counter Array, an XRAM of 1024 byte, a Hardware Watchdog Timer, a Keyboard Interface, a I2C Interface, a SPI Interface, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a speed improvement mechanism (X2 mode). The fully static design of the T89C51IC2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The T89C51IC2 has 2 software-selectable modes of reduced activity and 8 bit clock prescaler for further reduction in power consumption. In the Idle mode the CPU is frozen while the peripherals and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. The added features of the T89C51IC2 make it more powerful for applications that need pulse width modulation, high speed I/O and counting capabilities such as alarms, motor control, corded phones, smart card readers. Table 1. Memory Size PLCC44 VQFP44 1.4 Flash (bytes) XRAM (bytes) TOTAL RAM (bytes) I/O T89C51IC2 32k 1024 1280 34 (2) (2) XTAL1 XTAL2 (1) EUART + BRG ALE/ PROG RAM 256x8 C51 CORE PSEN F las h 32K x8 or 16K x8 XRAM 1Kx8 Boot ROM 2Kx8 ( 1) (1) PCA SCL SDA T2 T2EX PCA ECI Vss VCC TxD RxD Block Diagram (1) Timer2 I2C IB-bus CPU EA Timer 0 Timer 1 ( 2) INT Ctrl Parallel I/O Ports & Ext. Bus Watch Key Dog B oard SPI SS MOSI SCK MISO PI2 P3 P2 P1 (1) (1) (1) ( 1) P0 INT1 (2) ( 2) T1 (2) (2) INT0 Port 0 Port 1 Port 2 Port 3Port I2 RESET WR ( 2) T0 RD (1): Alternate function of Port 1 (2): Alternate function of Port 3 2 T89C51IC2 Rev. C – 3-Dec-01 T89C51IC2 SFR Mapping The Special Function Registers (SFRs) of the T89C51IC2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, PI2 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • Serial I/O port registers: SADDR, SADEN, SBUF, SCON • PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH, CCAPxL (x: 0 to 4) • Power and clock control registers: PCON • Hardware Watchdog Timer registers: WDTRST, WDTPRG • Interrupt system registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1 • Keyboard Interface registers: KBE, KBF, KBLS • SPI registers: SPCON, SPSTR, SPDAT • I2C Interface registers: SSCON, SSCS, SSDAT, SSADR • BRG (Baud Rate Generator) registers: BRL, BDRCON • Flash register: FCON • Clock Prescaler register: CKRL • 32Khz Sub Clock Oscillator registers: CKSEL, OSSCON • Others: AUXR, AUXR1, CKCON0, CKCON1 3 Rev. C – 3-Dec-01 Table 2. SFR mapping Table below shows all SFRs with their address and their reset value. Bit addressable 0/8 F8h F0h 1/9 2/A 3/B 4/C 5/D 6/E CH CCAP0H CCAP1H CCAPL2H CCAPL3H CCAPL4H 0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX CL CCAP0L CCAP1L CCAPL2L CCAPL3L CCAPL4L 0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX E7h CMOD CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4 00XX X000 X000 0000 X000 0000 X000 0000 X000 0000 X000 0000 D0h PSW 0000 0000 XXXX 0000 C8h T2CON 0000 0000 T2MOD XXXX XX00 B0h A8h A0h 98h 90h 88h 80h DFh FCON (1) D7h RCAP2L 0000 0000 PI2 bit addressable XXXX XX11 B8h EFh ACC 0000 0000 CCON C0h FFh F7h 00X0 0000 D8h 7/F B 0000 0000 E8h E0h Non Bit addressable IPL0 SADEN X000 000 0000 0000 RCAP2H 0000 0000 TL2 0000 0000 TH2 0000 0000 SPCON SPSTA SPDAT 0001 0100 0000 0000 XXXX XXXX CFh C7h BFh P3 IE1 IPL1 IPH1 IPH0 1111 1111 XXXX X000 XXXX X000 XXXX X111 X000 0000 IE0 SADDR CKCON1 0000 0000 0000 0000 XXXX XXX0 P2 AUXR1 WDTRST WDTPRG 1111 1111 XXXX X0X0 XXXX XXXX XXXX X000 SCON SBUF BRL BDRCON KBLS KBE KBF 0000 0000 XXXX XXXX 0000 0000 XXX0 0000 0000 0000 0000 0000 0000 0000 P1 SSCON SSCS SSDAT SSADR CKRL 0000 0000 1111 1000 1111 1111 1111 1110 1111 1111 AUXR XX0X 0000 0000 0000 TCON TMOD TL0 TL1 TH0 TH1 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 P0 1111 1111 SP 0000 0111 DPL 0000 0000 DPH 0000 0000 0/8 1/9 2/A 3/B 4/C AFh A7h 9Fh 1111 1111 0000 0000 B7h CKCON0 CKSEL OSSCON PCON XXXX XXX0 XXXX X001 00X1 0000 5/D 6/E 7/F 97h 8Fh 87h reserved (1) FCON access is reserved for the FLASH API and ISP software. 4 T89C51IC2 Rev. C – 3-Dec-01 T89C51IC2 P0.2/AD2 P0.3/AD3 P0.1/AD1 P0.0/AD0 VCC XTALB2 P1.0/T2/XTALB1 P1.1/T2EX/SS P1.2/ECI P1.3/CEX0 P1.4/CEX1 Pin Configurations 6 5 4 3 2 1 44 43 42 41 40 P1.5/CEX2/MISO 39 38 P0.4/AD4 P1.6/CEX3/SCK 7 8 P1.7/CEx4/MOSI 9 37 P0.6/AD6 RST 10 36 P0.7/AD7 P3.0/RxD 35 34 EA PI2.1/SDA 11 12 P3.1/TxD 13 33 ALE/PROG P3.2/INT0 P3.3/INT1 14 15 32 31 PSEN P3.4/T0 P3.5/T1 16 30 P2.6/A14 17 29 P2.5/A13 PLCC44 P0.5/AD5 PI2.0/SCL P2.7/A15 P0.3/AD3 P0.2/AD2 P2.3/A11 P2.4/A12 P2.2/A10 P0.1/AD1 P0.0/AD0 P2.1/A9 VCC XTALB2 NIC* P2.0/A8 P1.0/T2/XTALB1 VSS P1.1/T2EX/SS XTAL1 P1.2/ECI XTAL2 P1.3/CEX0 P3.7/RD P1.4/CEX1 P3.6/WR 18 19 20 21 22 23 24 25 26 27 28 44 43 42 41 40 39 38 37 36 35 34 P1.5/CEX2/MISO 1 P1.6/CEX3/SCK P1.7/CEX4/MOSI 2 RST P3.0/RxD PI2.1/SDA P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 33 32 31 3 4 P0.4/AD4 P0.5/AD5 P0.6/AD6 30 29 28 27 P0.7/AD7 EA 9 26 25 PSEN P2.7/A15 10 24 P2.6/A14 11 23 P2.5/A13 5 VQFP44 1.4 6 7 8 PI2.0/SCL ALE/PROG P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 NIC* VSS XTAL1 XTAL2 P3.7/RD P3.6/WR 12 13 14 15 16 17 18 19 20 21 22 5 Rev. C – 3-Dec-01 Table 1. Pin Description for 40/44 pin packages Pin Number Type Mnemonic PLCC44 VQFP44 1.4 Name and Function VSS 22 16 I Ground: 0V reference VCC 44 38 I Power Supply: This is the power supply voltage for normal, idle and power-down operation P0.0-P0.7 43-36 37-30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. Port 0 must be polarized to VCC or VSS in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM programming. External pull-ups are required during program verification during which P0 outputs the code bytes. P1.0-P1.7 2-9 40-44 1-3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address byte during memory programming and verification. Alternate functions for T89C51IC2 Port 1 include: 2 40 I/O P1.0: Input / Output I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout I 3 4 41 42 I/O 6 7 43 44 1 P1.1: Input / Output I T2EX: Timer/Counter 2 Reload/Capture/Direction Control I SS: SPI Slave Select I/O I 5 XTALB1 (P1.0): Sub Clock input to the inverting oscillator amplifier P1.2: Input / Output ECI: External Clock for the PCA I/O P1.3: Input / Output I/O CEX0: Capture/Compare External I/O for PCA module 0 I/O P1.4: Input / Output I/O CEX1: Capture/Compare External I/O for PCA module 1 I/O P1.5: Input / Output I/O CEX2: Capture/Compare External I/O for PCA module 2 I/O MISO: SPI Master Input Slave Output line When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in slave mode, MISO outputs data to the master controller. 8 2 I/O P1.6: Input / Output I/O CEX3: Capture/Compare External I/O for PCA module 3 I/O SCK: SPI Serial Clock SCK outputs clock to the slave peripheral 9 6 3 I/O P1.7: Input / Output: T89C51IC2 Rev. C – 3-Dec-01 T89C51IC2 Pin Number Type Mnemonic PLCC44 VQFP44 1.4 Name and Function I/O CEX4: Capture/Compare External I/O for PCA module 4 I/O MOSI: SPI Master Output Slave Input line When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave mode, MOSI receives data from the master controller. XTALA1 21 15 I Crystal A 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTALA2 20 14 O Crystal A 2: Output from the inverting oscillator amplifier XTALB1 2 40 I Crystal B 1: (Sub Clock) Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTALB2 1 39 O Crystal B 2: (Sub Clock) Output from the inverting oscillator amplifier 24-31 18-25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Some Port 2 pins receive the high order address bits during EPROM programming and verification: P2.0-P2.7 P2.0 to P2.5 for 16Kb devices P2.0 to P2.6 for 32Kb devices P3.0-P3.7 PI2.0-PI2.1 11, 13-19 5, 7-13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Port 3 also serves the special features of the 80C51 family, as listed below. 11 5 I RXD (P3.0): Serial input port 13 7 O TXD (P3.1): Serial output port 14 8 I INT0 (P3.2): External interrupt 0 15 9 I INT1 (P3.3): External interrupt 1 16 10 I T0 (P3.4): Timer 0 external input 17 11 I T1 (P3.5): Timer 1 external input 18 12 O WR (P3.6): External data memory write strobe 19 13 O RD (P3.7): External data memory read strobe 34, 12 28, 6 34 28 Port I2: Port I2 is an open drain. It can be used as inputs (must be polarized to Vcc with external resistor to prevent any parasitic current consumption). I/O SCL (PI2.0): I2C Serial Clock SCL output the serial clock to slave peripherals SCL input the serial clock from master 12 6 I/O SDA (PI2.1): I2C Serial Data SDA is the bidirectional I2C data line 7 Rev. C – 3-Dec-01 Pin Number Type Mnemonic PLCC44 VQFP44 1.4 RST 10 4 I/O ALE/PROG 33 27 O (I) PSEN 32 26 O Program Strobe ENable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA 35 29 I External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to FFFFH (RD). If security level 1 is programmed, EA will be internally latched on Reset. 8 Name and Function Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. This pin is an output when the hardware watchdog forces a system reset. Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during Flash programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches. T89C51IC2 Rev. C – 3-Dec-01 T89C51IC2 Ordering Information Table 2. Possible order entries Part Number Flash Memory Size Supply Voltage Temperature Range Max Frequency Package Packing T89C51IC2-SLSCM 32 Kbytes 5V Commercial 20 MHz PLCC44 Stick T89C51IC2-SLSIM 32 Kbytes 5V Industrial 20 MHz PLCC44 Stick T89C51IC2-SLSIL 32 Kbytes 3V Industrial 20 MHz PLCC44 Stick T89C51IC2-RLTIM 32 Kbytes 5V Industrial 20 MHz VQFP44 Tray T89C51IC2-RLTIL 32 Kbytes 3V Commercial 20 MHz VQFP44 Tray Note: Purchase of Atmel I2C components conveys a license under the Philips I2C Patent’s right to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 9 Rev. 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