Features • Six High-side and Six Low-side Drivers • Outputs Freely Configurable as Switch, Half Bridge or H-bridge • Capable to Switch All Kinds of Loads Such as DC Motors, Bulbs, Resistors, Capacitors and Inductors 0.6 A Continuous Current Per Switch Low-side: RDSon < 1.5 Ω Versus Total Temperature Range High-side: RDSon < 2.0 Ω Versus Total Temperature Range Very Low Quiescent Current IS < 20 µA in Standby Mode Outputs Short-circuit Protected Overtemperature Prewarning and Protection Under- and Overvoltage Protection Various Diagnosis Functions Such as Shorted Output, Open Load, Overtemperature and Power Supply Fail • Serial Data Interface • Daisy Chaining Possible • SO28 Power Package • • • • • • • • Description Dual Hex DMOS Output Driver with Serial Input Control U6815BM The U6815BM is a fully protected driver interface designed in 0.8-µm BCDMOS technology. It is used to control up to 12 different loads by a microcontroller in automotive and industrial applications. Each of the 6 high-side and 6 low-side drivers is capable to drive currents up to 600 mA. The drivers are freely configurable and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors can be combined. The IC design especially supports the applications of H-bridges to drive DC motors. Protection is guaranteed in terms of short-circuit conditions, overtemperature, underand overvoltage. Various diagnostic functions and a very low quiescent current in standby mode enable a wide range of applications. Automotive qualification referring to conducted interferences, EMC protection and 2-kV ESD protection gives added value and enhanced quality for the strict automotive requirements. Rev. 4545B–BCD–12/02 1 Figure 1. Block Diagram HS3 HS2 HS1 15 15 Fault Detect 3 3 12 Fault Detect Fault Detect HS5 HS4 13 13 Fault Detect HS6 2 2 28 Fault Detect 28 5 Fault Detect 10 DI CS INH VS 26 VS 25 S I 24 17 S C T O L D H S 6 L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 S R R P S F I N H S C D H S 6 L S 6 protection 7 VS 8 Control Input Register Output Register 6 GND OV - Osc CLK VS UV - protection logic 9 GND GND GND Thermal H S 5 H S 4 L S 5 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 1 T P protection 20 GND P - ON - 18 Reset DO 21 GND Vcc 22 Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect 23 GND GND Vcc 19 16 14 LS1 4 11 LS2 LS3 1 LS4 Vcc 27 LS5 LS6 Pin Configuration Figure 2. Pinning SO28 HS6 LS6 DI CLK CS 28 27 26 25 24 GND GND GND GND VCC 23 22 DO INH LS1 HS1 21 20 19 18 17 16 15 8 9 10 11 12 13 14 VS LS3 HS3 HS2 LS2 U6815BM Lead frame 2 1 2 LS5 HS5 3 4 HS4 LS4 5 VS 6 7 GND GND GND GND U6815BM 4545B–BCD–12/02 U6815BM Pin Description Pin Symbol Function 1 LS5 Low-side driver output 5, power-MOS open drain with internal reverse diode, overvoltage protection by active zenering, short-circuit protection, diagnosis for short and open load 2 HS5 High-side driver output 5, power-MOS open drain with internal reverse diode, overvoltage protection by active zenering, short-circuit protection, diagnosis for short and open load 3 HS4 High-side driver output 4 (see Pin 2) 4 LS4 Low-side driver output 4 (see Pin 1) 5 VS Power supply output stages HS4, HS5, HS6, internal supply; external connection to Pin 10 necessary 6, 7, 8, 9 GND 10 VS Ground, reference potential, internal connection to Pin 20 - 23, cooling tab Power supply output stages HS1, HS2 and HS3 11 LS3 Low-side driver output 3 (see Pin 1) 12 HS3 High-side driver output 3 (see Pin 2) 13 HS2 High-side driver output 2 (see Pin 2) 14 LS2 Low-side driver output 2 (see Pin 1) 15 HS1 High-side driver output 1 (see Pin 2) 16 LS1 Low-side driver output 1 (see Pin 1) 17 INH Inhibit input, 5-V logic input with internal pull down, low = standby, high = normal operating 18 DO Serial data output, 5-V CMOS logic level tristate output for output (status) register data, sends 16-bit status information to the microcontroller (LSB is transferred first). Output will remain tristated unless device is selected by CS = low, therefore, several ICs can operate on one data output line only. 19 VCC Logic supply voltage (5 V) 20, 21, 22, 23 GND Ground (see Pins 6 - 9) 24 CS Chip select input, 5-V CMOS logic level input with internal pull up, low = serial communication is enabled, high = disabled 25 CLK Serial clock input, 5-V CMOS logic level input with internal pull down, controls serial data input interface and internal shift register (fmax = 2 MHz) 26 DI Serial data input, 5-V CMOS logic level input with internal pull down, receives serial data from the control device, DI expects a 16-bit control word with LSB being transferred first 27 LS6 Low-side driver output 6 (see Pin 1) 28 HS6 High-side driver output 6 (see Pin 2) 3 4545B–BCD–12/02 Functional Description Serial Interface Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the rising edge of the CS signal. When CS is high, Pin DO is in tristate condition. This output is enabled on the falling edge of CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is transferred first. Figure 3. Data Transfer CS DI SRR LS1 HS1 LS2 HS2 LS3 LS4 HS3 HS4 LS5 HS5 LS6 HS6 OLD 0 1 2 3 4 5 6 7 8 9 10 11 12 13 TP SLS1 SHS1 SLS2 SHS2 SLS3 SHS3 SLS4 SHS4 SLS5 SHS5 SLS6 SHS6 SCD SCT SI 14 15 CLK DO INH PSF Input Data Protocol 4 Bit Input Register 0 SRR Function Status register reset (high = reset; the bits PSF, SCD and overtemperature shutdown in the output data register are set to low) 1 LS1 Controls output LS1 (high = switch output LS1 on) 2 HS1 Controls output HS1 (high = switch output HS1 on) 3 LS2 See LS1 4 HS2 See HS1 5 LS3 See LS1 6 HS3 See HS1 7 LS4 See LS1 8 HS4 See HS1 9 LS5 See LS1 10 HS5 See HS1 11 LS6 See LS1 12 HS6 See HS1 13 OLD Open load detection (low = on) 14 SCT Programmable time delay for short circuit and overvoltage shutdown (short circuit shutdown delay high/low = 100 ms/12.5 ms, overvoltage shutdown delay high/low = 15 ms/3.5 ms 15 SI Software inhibit; low = standby, high = normal operation (data transfer is not affected by standby function because the digital part is still powered) U6815BM 4545B–BCD–12/02 U6815BM After power-on reset, the input register has the following status: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (SI) (SCT) (OLD) (HS6) (LS6) (HS5) (LS5) (HS4) (LS4) (HS3) (LS3) (HS2) (LS2) (HS1) (LS1) (SRR) H H H L L L L L L L L L L L L L Output Data Protocol Bit Output (Status) Register Function 0 TP 1 Status LS1 Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) 2 Status HS1 Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected if the corresponding output is switched off) 3 Status LS2 Description see LS1 4 Status HS2 Description see HS1 5 Status LS3 Description see LS1 6 Status HS3 Description see HS1 7 Status LS4 Description see LS1 8 Status HS4 Description see HS1 9 Status LS5 Description see LS1 10 Status HS5 Description see HS1 11 Status LS6 Description see LS1 12 Status HS6 Temperature prewarning: high = warning (overtemperature shut down) (1) Description see HS1 13 SCD Short circuit detected: set high, when at least one output is switched off by a short circuit condition 14 INH Inhibit: this bit is controlled by software (bit SI in input register) and hardware inhibit (Pin 17). High = standby, low = normal operation 15 PSF Power supply fail: over- or undervoltage at Pin VS detected Note: 1. Bit 0 to 15 = high: overtemperature shutdown Power Supply Fail In case of over-/undervoltage at Pin VS, an internal timer is started. When the overvoltage delay time (tdOV) programmed by the SCT Bit, or the undervoltage delay time (tdUV) is reached, the power supply fail bit (PSF) in the output register is set and all outputs are disabled. When normal voltage is present again, the outputs are enabled immediately. The PSF bit remains high until it is reset by the SRR bit in the input register. Open-load Detection If the open-load detection bit (OLD) is set to low, a pull-up current for each high-side switch and a pull-down current for each low-side switch is turned on (open-load detection current IHS1-6, ILS1-6). If VVS-VHS1-6 or VLS1-6 is lower than the open-load detection threshold (open-load condition) the corresponding bit of the output in the output register is set to high. Switching on an output stage with OLD bit set to low disables the openload function for this output. 5 4545B–BCD–12/02 Overtemperature Protection If the junction temperature exceeds the thermal prewarning threshold, TjPW set, the temperature prewarning bit (TP) in the output register is set. When temperature falls below the thermal prewarning threshold TjPW reset, the bit TP is reset. The TP bit can be read without transferring a complete 16-bit data word: with CS = high to low, the state of TP appears at Pin DO. After the microcontroller has read this information, CS is set high and the data transfer is interrupted without affecting the state of input and output registers. If the junction temperature exceeds the thermal shutdown threshold Tj switch off, the outputs are disabled and all bits in the output register are set high. The outputs can be enabled again when the temperature falls below the thermal shutdown threshold, Tj switch on, and when a high has been written to the SRR bit in the input register. Thermal prewarning and shutdown threshold have hysteresis. Short-circuit Protection The output currents are limited by a current regulator. Current limitation takes place when the over-current limitation and shutdown threshold (I HS1-6, ILS1-6 ) are reached. Simultaneously, an internal timer is started. The shorted output is disabled when during a permanent short the delay time (tdSd) programmed by the Short-Circuit Timer (SCT) bit is reached. Additionally, the Short-Circuit Detection (SCD) bit is set. If the temperature prewarning bit TP in the output register is set during a short, the shorted output is disabled immediately and SCD bit is set. By writing a high to the SRR bit in the input register, the SCD bit is reset and the disabled outputs are enabled. Inhibit There are two ways to inhibit the U6815BM: 1. Set bit SI in the input register to zero 2. Switch Pin 17 (INH) to 0 V In both cases, all output stages are turned off but the serial interface stays active. The output stages can be activated again by bit SI = 1 or by Pin 17 (INH) switched back to 5 V. 6 U6815BM 4545B–BCD–12/02 U6815BM Absolute Maximum Ratings All values refer to GND pins Parameters Pins Symbol Value Unit Supply voltage 5, 10 VVS - 0.3 to +40 V Supply voltage, t < 0.5 s; IS > - 2 A 5, 10 VVS -1 V |VS_Pin5 - VS_Pin10| DVVS 150 mV Supply current 5, 10 IVS 1.4 A Supply current, t < 200 ms 5, 10 IVS 2.6 A 19 VVCC -0.3 to +7 V V Supply voltage difference Logic supply voltage 17 VINH -0.3 to +17 24 to 26 VDI, VCLK, VCS -0.3 to VVCC + 0.3 V 18 VDO -0.3 to VVCC + 0.3 V 17, 24 to 26 IINH, IDI, ICLK, ICS -10 to +10 mA mA Input voltage Logic input voltage Logic output voltage Input current Output current 18 IDO -10 to +10 Output current 1 to 4, 11 to 16 ILS1 to ILS6 mA 27, 28 IHS1 to IHS6 Internally limited (see output specification) 2, 3, 12, 13, 15, 28 towards 5, 10 IHS1 to IHS6 17 A Junction temperature range Tj -40 to +150 °C Storage temperature range Tstg -55 to +150 °C Symbol Value Unit Junction - pin, measured to GND, Pins 6 to 9 and 20 to 23 RthJP 25 K/W Junction ambient RthJA 65 K/W Reverse conducting current (tpulse = 150 µs) mA Thermal Resistance All values refer to GND pins Parameters Operating Range All values refer to GND pins Parameters Supply voltage Logic supply voltage Logic input voltage Serial interface clock frequency Junction temperature Notes: Pins 5, 10 Symbol VVS Min. VUV 19 VVCC 4.5 17, 24 to 26 VINH, VDI, VCLK, VCS -0.3 25 fCLK Tj Typ. (1) -40 Max. 40 5 (2) Unit V 5.5 V VVCC V 2 MHz +150 °C 1. Threshold for undervoltage detection 2. Output disabled for VVS > VOV (threshold for overvoltage detection) 7 4545B–BCD–12/02 Noise and Surge Immunity Parameters Test Conditions Conducted interferences ISO 7637-1 Interference suppression VDE 0879 Part 2 ESD (human body model) MIL-STD-883D Method 3015.7 ESD (machine model) EOS/ESD - S 5.2 Note: Value level 4 (1) level 5 2 kV 150 V 1. Test pulse 5: VSmax = 40 V Electrical Characteristics 7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit Current Consumption Quiescent current (VS) VVS < 16 V, INH or bit SI = low Pins 5, 10 IVS 40 µA Quiescent current (VCC) 4.5 V < VVCC < 5.5 V, INH or bit SI = low, Pin 19 IVCC 20 µA Supply current (VS) normal operating VVS < 16 V, Pins 5, 10 all output stages off IVS 1.2 mA all output stages on, no load IVS 10 mA 4.5 V < VVCC < 5.5 V, normal operating, Pin 19 IVCC 150 µA 45 kHz Supply current (VCC) 0.8 Internal Oscillator Frequency Frequency (time-base for delay timers) fOSC 19 Over- and Undervoltage Detection, Power-on Reset Power-on reset threshold Pin 19 VVCC 3.4 3.9 4.4 V Power-on reset delay time After switching on VVCC tdPor 30 95 160 µs Undervoltage detection threshold Pins 5, 10 VUV 5.5 7.0 V Pins 5, 10 DVUV Undervoltage detection hysteresis Undervoltage detection delay 0.4 V tdUV 7 21 ms 18 22.5 V 21 ms 5.25 ms Overvoltage detection threshold Pins 5, 10 VOV Overvoltage detection hysteresis Pins 5, 10 DVOV 1 V Overvoltage detection delay Input register, Bit 14 (SCT) = high tdOV 7 Overvoltage detection delay Input register, Bit 14 (SCT) = low tdOV 1.75 TjPWset 125 145 165 °C TjPWreset 105 125 145 °C Thermal Prewarning and Shutdown Thermal prewarning, set Thermal prewarning, reset Thermal prewarning hysteresis DTjPW 20 K Thermal shutdown, off Tj switch off 150 170 190 °C Thermal shutdown, on Tj switch on 130 150 170 °C Thermal shutdown hysteresis Notes: 8 DTj switch off 20 K 1. Only valid for version U6815BM-N. 2. Delay time between rising edge of CS after data transmission and switch-on output stages to 90% of final level. U6815BM 4545B–BCD–12/02 U6815BM Electrical Characteristics (Continued) 7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. Parameters Test Conditions/Pins Symbol Min. Typ. Ratio thermal shutdown, off/thermal prewarning, set Tj switch off/ TjPW set 1.05 1.17 Ratio thermal shutdown, on/thermal prewarning, reset Tj switch on/ TjPW reset 1.05 1.2 Max. Unit Output Specification (LS1 - LS6, HS1 - HS6), 7.5 V < VVS < VOV On resistance, low On resistance, high IOut = 600 mA, Pins 1, 4, 11, 14, 16 and 27 RDS On L 1.5 W IOut = -600 mA, Pins 2, 3, 12, 13, 15 and 28 RDS On H 2.0 W 60 V 10 µA 15 mJ ILS1–6 = 50 mA, Pins 1, 4, 11, 14, 16, 27 VLS1–6 VLS1–6 = 40 V, all output stages off, Pins 1, 4, 11, 14, 16 and 27 ILS1–6 VHS1–6 = 0 V, all output stages off, Pins 2, 3, 12, 13, 15 and 28 IHS1–6 Inductive shutdown energy (1) Pins 1-4, 11-16, 27 and 28 Woutx Output voltage edge steepness Pins 1-4, 11-16, 27 and 28 dVLS1–6/dt dVHS1–6/dt 50 200 400 mV/µ s Overcurrent limitation and shutdown threshold Pins 1, 4, 11, 14, 16 and 27 ILS1–6 650 950 1250 mA Pins 2, 3, 12, 13,15 and 28 IHS1–6 -1250 -950 -650 mA Overcurrent shutdown delay time Input register, Bit 14 (SCT) = high tdSd 70 100 140 ms Input register, Bit 14 (SCT) = low tdSd 8.75 17.5 ms Input register, Bit 13 (OLD) = low, output off, Pins 1, 4, 11, 14, 16, 27 ILS1–6 60 200 µA Input register, Bit 13 (OLD) = low, output off, Pins 2, 3, 12, 13, 15, 28 IHS1–6 -150 -30 µA ILS1–6/ IHS1–6 1.2 Input register, Bit 13 (OLD) = low, output off, Pins 1, 4, 11, 14, 16, 27 VLS1–6 0.6 4 V Input register, Bit 13 (OLD) = low, output off, Pins 2, 3, 12, 13, 15, 28 VVS– VHS1–6 0.6 4 V Output clamping voltage Output leakage current Open load detection current Open load detection current ratio Open load detection threshold Output switch on delay (2) 40 -10 µA RLoad = 1 kW tdon 0.5 ms RLoad = 1 kW tdoff 1 ms Inhibit Input Input voltage low level threshold Pin 17 Input voltage high level threshold Pin 17 Hysteresis of input voltage Pin 17 DVI Pull-down current VINH = VVCC, Pin 17 IPD VIL 0.3 ´ VVCC V 0.7´ VVCC V 100 700 mV 10 80 µA VIH Serial Interface - Logic Inputs (DI, CLK, CS) Notes: 1. Only valid for version U6815BM-N. 2. Delay time between rising edge of CS after data transmission and switch-on output stages to 90% of final level. 9 4545B–BCD–12/02 Electrical Characteristics (Continued) 7.5 V < VVS < 40 V; 4.5 V < VVCC < 5.5 V; INH = High; -40°C < Tj < 150°C; unless otherwise specified, all values refer to GND pins. Parameters Test Conditions/Pins Symbol Min. Input voltage low level threshold Pins 24–26 VIL 0.3 ´ VVCC Input voltage high level threshold Pins 24–26 Hysteresis of input voltage Pins 24–26 DVI Pull-down current, Pins DI and CLK VDI, VCLK = VVCC, Pins 25, 26 Pull-up current Pin CS VCS= 0 V, Pin 24 Output voltage low level IOL = 3 mA, Pin 18 VDOL Output voltage high level IOL = -2 mA, Pin 18 VDOH VVCC-1 V Leakage current (tristate) VCS = VVCC, 0 V < VDO < VVCC, Pin 18 IDO -10 Typ. Max. Unit V 0.7 ´ VVCC V 50 500 mV IPDSI 2 50 µA IPUSI -50 -2 µA 0.5 V 10 mA VIH Serial Interface - Logic Output (DO) Notes: V 1. Only valid for version U6815BM-N. 2. Delay time between rising edge of CS after data transmission and switch-on output stages to 90% of final level. Serial Interface – Timing Timing Chart No. (1) Symbol CDO = 100 pF 1 DO disable after CS rising edge CDO = 100 pF DO fall time Parameters Test Conditions DO enable after CS falling edge Max. Unit tENDO 200 ns 2 tDISDO 200 ns CDO = 100 pF - tDOf 100 ns DO rise time CDO = 100 pF - tDOr 100 ns DO valid time CDO = 100 pF 10 tDOVal 200 ns 4 tCSSethl 225 ns CS setup time VDO < 0.2 ´ VVCC 8 tCSSetlh 225 ns CS high time Input register, Bit 14 (SCT) = high 9 tCSh 140 ns Input register, Bit 14 (SCT) = low 9 tCSh 17.5 ns CLK high time 5 tCLKh 225 ns CLK low time 6 tCLKl 225 ns CS setup time Min. Typ. CLK period time - tCLKp 500 ns CLK setup time 7 tCLKSethl 225 ns CLK setup time 3 tCLKSetlh 225 ns DI setup time 11 tDIset 40 ns DI hold time 12 tDIHold 40 ns Note: 10 1. see Figure 4 U6815BM 4545B–BCD–12/02 U6815BM Figure 4. Serial Interface Timing Diagram with Chart Numbers 1 2 CS DO 9 CS 4 7 CLK 5 3 6 8 DI 11 CLK 10 12 DO Inputs DI, CLK, CS: High level = 0.7 ´ VCC, Low level = 0.3 ´ VCC Output DO: High level = 0.8 ´ VCC, Low level = 0.2 ´ VCC For chart numbers, see Table Serial Interface - Timing, page 10. 11 4545B–BCD–12/02 Figure 5. Application Circuit Vcc U5021M WATCHDOG Enable HS2 HS1 HS5 HS4 HS3 13 12 3 HS6 2 28 Vs Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect 5 VS Fault Detect 10 DI CLK µC CS 26 25 S I 24 17 INH DO Osc S O C L T D H S H S L S L S 6 6 5 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 S L S 1 R R Control logic Input Register Output Register P S F I N H S C D H S 6 L S 6 H S 5 L S 5 H S 4 L S 4 H S 3 L S 3 H S 2 L S 2 H S 1 L S 6 VS UV protection 8 Thermal protection T P 1 VS OV protection P - ON Reset 18 Vcc Fault Detect Fault Detect Fault Detect Fault Detect Fault Detect 7 9 VS BYT41D + Reset Trigger 15 GND GND GND GND 20GND 21GND 22GND 23GND Fault Detect Vcc 19 Vcc Vcc Vcc LS1 14 LS2 11 4 LS4 LS3 Vs Application Notes 1 LS5 27 + 16 VBATT 13V Vcc 5V LS6 Vs It is strongly recommended to connect the blocking capacitors at VCC and VS as close as possible to the power supply and GND pins. Recommended value for capacitors at VS: Electrolythic capacitor C > 22 µF in parallel with a ceramic capacitor C = 100 nF. Value for electrolytic capacitor depends on external loads, conducted interferences and reverse conducting current IHSx (see table Absolute Maximum Ratings). Recommended value for capacitors at VCC: Electrolythic capacitor C > 10 µF in parallel with a ceramic capacitor C = 100 nF. To reduce thermal resistance, it is recommended to place cooling areas on the PCB as close as possible to the GND pins. 12 U6815BM 4545B–BCD–12/02 U6815BM Ordering Information Extended Type Number Package Remarks U6815BM-NFL SO28 Tubed U6815BM-NFLG3 SO28 Taped and reeled Package Information Package SO28 Dimensions in mm 9.15 8.65 18.05 17.80 7.5 7.3 2.35 1.27 28 0.25 0.25 0.10 0.4 10.50 10.20 16.51 15 technical drawings according to DIN specifications 1 14 13 4545B–BCD–12/02 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. Atmel ® is the registered trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper. 4545B–BCD–12/02 xM