Features • Four Short-circuit-protected High-side Drivers with a Maximum Current Capability of 50 mA Each • Four Short-circuit-protected Low-side Drivers with a Maximum Current Capability of • • • • • • • • • 50 mA Each ON Resistance High Side Ron < 10 Ω Versus Total Temperature Range ON Resistance Low Side Ron < 7 Ω Versus Total Temperature Range Short-circuit Detection of Each Driver Stage Disabling of Driver Stages in the Case of Short-circuit and Overtemperature Detection Independent Control of Each Driver Stage via an 8-bit Shift Register Status Output Reports Short-circuit Condition Status Output Reports when All Loads Are Switched Off Timing of Status Output Reset Signalizes Failure Mode Temperature Protection in Conjunction with Short-circuit Detection Description The U6820BM is a driver interface in BCDMOS technology with 8 independent driver stages having a maximum current capability of 50 mA each. Its partitioning into 4 high-side and 4 low-side driver stages allows an easy connection of either 4 halfbridges or 2 H-bridges on the pc board. The U6820BM communicates with a microcontroller via an 8-bit serial interface. Integrated protection against short circuit and overtemperature give added value. EMI protection and 2-kV ESD protection together with automotive qualification referring to conducted interference (ISO/TR 7637/1) make this IC ideal for both automotive and industrial applications. Dual Quad BCDMOS Driver IC U6820BM Figure 1. Block Diagram V HS4 CC 16 6 Current limiter V STATUS CS CLK DI HS3 HS2 HS1 9 8 1 Current limiter Current limiter Current limiter 3 VS CC 14 11 H S 4 H S 3 H S 2 H S 1 L S 4 L S 3 L S 2 L S 1 12 V 13 Thermal protection V Power-on reset V CC Control logic CC Input Register CC 5 Current limiter 4 GND CC Current limiter 15 LS4 Current limiter 10 LS3 GND S Current limiter 7 2 LS2 LS1 Rev. 4527A–BCD–03/02 1 Pin Configuration Figure 2. Pinning SO16 HS1 1 16 HS4 LS1 2 15 LS4 VS 3 14 STATUS GNDCC 4 13 DI GNDS 5 12 CLK VCC 6 11 CS LS2 7 10 LS3 HS2 8 9 HS3 Pin Description 2 Pin Symbol Function 1 HS1 Output high side 1 2 LS1 Output low side 1 3 VS Supply voltage 6 V to 18 V 4 GNDCC Digital ground 5 GNDS Power ground 6 VCC Supply voltage 5 V (external) 7 LS2 Output low side 2 8 HS2 Output high side 2 9 HS3 Output high side 3 10 LS3 Output low side 3 11 CS Set supply status (chip select) 12 CLK Clock line for 8-bit control shift register 13 DI Data line for 8-bit control shift register 14 STATUS Status output (H = fault, diagnostic “H” if all driver stages are switched off) 15 LS4 Output low side 4 16 HS4 Output high side 4 U6820BM 4527A–BCD–03/02 U6820BM Description of the Control Interface to the Microcontroller The serial-parallel interface basically includes an 8-bit shift register (SR), an 8-bit command register (CR) and a 4-bit counter. The data input takes place with commands at Pins DI (data input), CS (chip select) and CLK (clock). With a falling edge at CLK, the information at DI is transferred into the SR. The first information written into the SR is the least significant bit (LSB). The Pin STATUS is used for diagnostic purposes and reports any fault condition to the microcontroller. The input CS in accordance with the CR controls the serial interface. A high level at CS disables the SR. With a falling edge at CS, the SR is enabled. The CR control allows only the first 8 bits to be transferred into the SR, and further clocks at CLK are ineffective. If a rising edge occurs at CS after 8 clocks precisely, the information from the SR is transferred into the CR. If the number of clock cycles during the low phase of CS was less or more than eight transitions, no transfer will take place. A new command switches the output stages on or off immediately. Each output stage is controlled by one specific bit of the CR. Low level means “supply off” or inactive, and high level means “supply on” or active. If all 8 bits are at a low level, the output stages will be set into standby mode. If one of the output stages detects a short circuit and additionally overtemperature condition, the corresponding control bit in the CR is set to low. This reset has priority over an external command to CR, thus, this does not affect the 1st control bit. The priority protects the IC against overtemperature by activating the temperature shut down immediately. The STATUS Output The STATUS output is at low level during normal operation. If one or more output stages detect short circuit or if overtemperature is indicated, the STATUS output changes to high level (OR-connection). For diagnostic purposes (self test of the status output), the status output can also be brought into high level during standby mode. Timing of the Status Output Reset Signalizes the Failure Mode The use of different reset conditions at the STATUS output simplifies the failure analysis during normal operation, and is also beneficial during testing. The storage content can be used for STATUS output. It is indicated and latched immediately with the rising edge of CS at STATUS output if less than 8 clocks were received during the low phase of CS. The reset is initiated by the falling edge of the 8th clock (bit 7) of the next data input. Also, the appearance of more than 8 clocks is latched and indicated at STATUS by the rising edge of the 9th clock. The reset is initiated by the falling edge of the 2nd clock (bit 1) of the next data input. The detection of overtemperature is latched internally. It is reset by the falling edge of the 4th clock (bit 3) of a data transfer if overtemperature is no longer present. Power-on Reset After switching on the supply voltage, all data latches are reset and the outputs are switched off. The typical power-on reset threshold is VCC = 3.7 V. The outputs are activated after the first data transfer. 3 4527A–BCD–03/02 Short-circuit Protection The current of the output stages is limited by an active feedback control. Short circuit at one output stage sets the diagnostic Pin 14 (STATUS) to high. In case of both conditions, short circuit at one of the outputs and temperature detection, the affected output is switched off selectively. It will be activated again after the first new data transfer. Inductance Protection Clamping diodes and FETs are integrated to protect the IC against too high or too low voltages at the outputs. They prevent the IC from latch up and parasitic currents which may exceed power dissipation. Temperature Protection The IC is protected by an overtemperature detection. As soon as the junction temperature Tj = 155°C typically is exceeded, the diagnostic Pin 14 (STATUS) is set “high”. General overtemperature detection along with short-circuit condition at a specific output result in temperature shut down at that specific output. After temperature shut down, the data input register has to be set again with a hysteresis of typically ∆ T = 15 K (Tj = 140°C). ESD Protection All output stages are protected against electrostatic discharge up to 5 kV (HBM) with external components (see Figure 5), all other pins are protected up to 2 kV (HBM). Table 1. Timing of the STATUS Output Shift Register Command Register Low-side Switch High-side Switch Status Condition LS1 LS2 LS3 LS4 HS1 HS2 HS3 HS4 Set Reset New CS 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 All out = OK off off off off off off off off H 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 All on = OK on on on on on on on on L 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 E.g. one on = OK off off off off off off off on L 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 Short at LS3 off on on on on on on on H No short 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 Temp & short at HS4 on on on off on on on on H New CS4 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 VVCC < 3.7 V = P-ON off off off off off off off off H P-ON, CS 1 1 1 0 0 0 1 1 x x x x x x x x CS with less 8 CLK x x x x x x x x H New CS 8 0 0 0 1 1 1 0 0 x x x x x x x x CS with more 8 CLK x x x x x x x x H New CS 2 4 U6820BM 4527A–BCD–03/02 U6820BM Figure 3. Data Transfer Timing Diagram t CSCLK t t CLKP CLKH tr CLK tf 90 % LSB t CLKCS 90 % 50% MSB 10% t CLKL 50% DI t DICLK t DIH/L t CS CS 50% t CLKCSH Table 2. AC Characteristics for Testing Specification Conditions Minimum Maximum Unit tr (rise) 10% to 90% VCC on CLK, DI and CS 10 ns tf (fall) 10% to 90% VCC on CLK, DI and CS 10 ns tCLKP 1/2 VCC 250 ns tCLKH 1/2 VCC 100 ns tCLKL 1/2 VCC 100 ns tCLKCS 1/2 VCC 150 ns tCSCLK 1/2 VCC 100 ns tDICLK 1/2 VCC 80 ns tDIH/L 1/2 VCC 100 ns tCLKCSH 1/2 VCC 100 ns tCS 1/2 VCC 250 ns 5 4527A–BCD–03/02 Figure 4. Block Diagram of the Control Interface Serial-Parallel Interface DFF 1 CS 2 CL 11 DFF D EN 4 8 R DFF D Q D Q CL R Q Counter R Q0 CL NQ Q1 Q2 R NQ CL NQ Q3 h if 8 8CLK DFF h if 4 h if 2 CLK D POR Q R norm=0 CL NQ CLK EN 12 CL H4 H3 H2 H1 L4 L3 L2 Q2 Q1 L1 Shift register SR LSB DIN 13 Q7 DI Q6 DIN Load CR Q5 DIN DIN Q3 DIN DIN DIN Q0 DIN DIN NR NQ NR NQ Command register BR CL NR NQ Q4 NR NQ NR NQ NR NQ NR NQ NR NQ DFF D Q CL P-ON-Reset R NQ Th-protection 14 All norm = 0 6 norm = 0 STD_BY LS1_ON ISC_LS1 LS2_ON ISC_LS2 LS3_ON ISC_LS3 LS4_ON ISC_LS4 HS1_ON ISC_HS1 HS2_ON ISC_HS2 HS3_ON ISC_HS3 HS4_ON ISC_HS4 STATUS norm = 0 U6820BM 4527A–BCD–03/02 U6820BM Absolute Maximum Ratings Parameters Pin Symbol Minimum Maximum Unit Supply voltage 3 VVS -0.3 +40 V Logic supply voltage 6 VVCC -0.3 +7 V 11, 12 13 CS, CLK, DI -0.3 VVCC + 0.5 V 14 STATUS -0.3 VVCC + 0.3 V Logic input voltage Logic output voltage 3 IVS 0.2 mA 6 IVCC 5 mA 1-2, 8-11, 15-16 I 1H-4H and I 1L-4L 30 65 mA Junction temperature range Tj -40 +150 °C Storage temperature range Tstg -55 +150 °C Input current Output current (internally limitted) Thermal Resistance Parameters Symbol Value Unit Junction ambient RthJA 110 K/W Junction case RthJC 26 K/W Operating Range Parameters Pin Symbol Value Unit Supply voltage 3 VVS 6 to 18 V Logic supply voltage 6 VVCC 4.5 to 5.5 V Logic input voltage low 11, 12, 13 CS, CLK, DI -0.2 to (0.2 x VVCC) V Logic input voltage high 11, 12, 13 CS, CLK, DI (0.7 x VVCC) to (VVCC + 0.3) V 14 STATUS 0.5 to (VVCC - 1) V fCLK 5 MHz Tj -40 to +150 °C Logic output voltage (1 mA load) Clock frequency Junction temperature range 7 4527A–BCD–03/02 Electrical Characteristics 7 V < VVS < 40 V; 4.5 V < VVCC > 5.5 V; -40°C < Tj < 150°C; unless otherwise specified No. 1 Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Current Consumption 1.1 Supply current VS No external load 3 IVS 0.2 mA A 1.2 Supply current VCC No external load 6 IVCC 5 mA A 1.3 Power-on reset threshold 6 VCC POR 3.4 3.7 4.0 V A 1.4 Power-on reset delay time 6 Td POR 60 95 130 µs D t j PW set 140 155 165 °C A t j PW reset 130 135 155 °C A K A 2 Thermal Shutdown 2.1 Thermal shutdown set 2.2 Thermal shutdown reset 2.3 Thermal hysteresis 3 After switching on VCC Dt 20 Output Specifications (1L - 4L, 1H - 4H) 3.1 On-resistance low Iout = 26 mA, Tj = 125°C 2, 7, 10, 15 RDSONLOW 3 4 7 Ω A 3.2 On-resistance high Iout = 26 mA, Tj = 125°C 1, 8, 9, 16 RDSONHIGH 4 6.25 10 Ω A 3.3 Output leakage current lowside VLSIDE 1-4 = 17.5 V 2, 7, 10, 15 ILOWSIDE 5 µA A 3.4 Output leakage current highside VHSIDE 1-4 = 0.5 V 1, 8, 9, 16 IHIGHSIDE -5 µA A 3.5 Output leakage steepness 1-2, 7-10, 15-16 dVOUT/ dt 50 200 400 mV/µs D 3.6 Over current limitation highside 1, 8, 9, 16 IHIGHSIDE 27 45 95 mA A 3.7 Over current limitation lowside 2, 7, 10, 15 ILOWSIDE 27 45 80 mA A 0.2× VVCC V A V A mV A 4 Serial Interface – Inputs: CS, CLK and DATA 4.1 Input voltage low level threshold 11-13 4.2 Input voltage high level threshold 11-13 4.3 Hysteresis of input voltage 11-13 4.4 Pull-down current 5 (internal pull-up resistor: 30 kΩ to 140 kΩ) VILOW VIHIGH 0.7× VVCC ∆Vi 300 11-13 Ii 300 µA A 0.5 V A VVCC V A Serial Interface – Output: STATUS 5.1 Output voltage low level I = 1 mA VOLOW 5.2 Output voltage high level I = 1 mA VOHIGH VVCC-1 *) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 8 U6820BM 4527A–BCD–03/02 U6820BM Figure 5. Application Circuit Typical application with 4 Hall-ICs for rotational speed detection + VCC 5V 100nF 33µF RR LR RF LF R* 4.7nF R* 4.7nF R* 4.7nF VBATT R* 4.7nF 12 V VCC HS4 16 6 U6820BM &XUUHQW OLPLWHU HS3 HS2 HS1 9 8 1 &XUUHQW OLPLWHU &XUUHQW OLPLWHU &XUUHQW OLPLWHU 3 VCC STATUS µC VS + 14 CS 11 CLK 12 DI 13 H S 4 H S 3 H S 2 H S 1 L S 4 L S 3 L S 2 L S 1 Thermal protection VCC Power-on reset VCC 100nF 47µF Control logic VCC Input register 5 15 GNDCC 10 LS4 LS3 &XUUHQW OLPLWHU 7 2 LS2 LS1 4.7nF 100 4.7nF 100 4.7nF &XUUHQW OLPLWHU 4.7nF 100 4 &XUUHQW OLPLWHU 100 &XUUHQW OLPLWHU GNDS 27k Sensor control 27k 27k 27k R * = ca. 4 Ohm (I Lim for inv. supply) Note: It is strongly recommended to connect the blocking capacitors at VS and VCC as close as possible to the power supply and GND pins. Recommended value for VS is less than 100 µF electrolytic in parallel with 100 nF ceramic. Value for electrolytic capacitor depends on external loads, noise and surge immunity efforts. Recommended value for VCC is 33 µF electrolytic in parallel with 100 nF ceramic. The 4-Ω resistors connected to the Pins HS1 - HS4 support the protection in case of a short circuit of these pins to VBatt. 9 4527A–BCD–03/02 Ordering Information Extended Type Number Package U6820BM-FP Remarks SO16 Package Information 5.2 4.8 Package SO16 10.0 9.85 Dimensions in mm 3.7 1.4 0.25 0.10 0.4 1.27 6.15 5.85 8.89 16 0.2 3.8 9 technical drawings according to DIN specifications 1 10 13036 8 U6820BM 4527A–BCD–03/02 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. 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