Features • • • • • • • Digital Self-supervising Watchdog with Hysteresis One 150-mA Output Driver for Relay One High-side Driver for N-channel Power FET Positive and Negative Enable Output Positive and Negative Reset Output Over/Under-voltage Detection Relay and Power FET Outputs Protected Against Standard Transients and 55-V Load Dump Description The function of microcontrollers in safety-critical applications (e.g., anti-lock systems) needs to be monitored permanently. Usually, this task is accomplished by an independent watchdog timer. The monolithic IC U6813B, designed in bipolar technology and qualified according to the needs of the automotive industry, includes such a watchdog timer and provides additional features for added value. With the help of integrated driver stages, it is easy to control safety-related functions of a relay and of an N-channel power MOSFET in high-side applications. In case of a microcontroller malfunction or supply-voltage anomalies, the U6813B provides positive and negative reset and enable output signals. This flexibility guarantees a broad range of applications. The U6813B is based on of Atmel’s fail-safe ICs U6808B and U6809B. Fail-safe IC with High-side and Relay Driver U6813B Figure 1. Block Diagram VCC Bandgap reference 2.44 V Power-on reset Reset debounce Reset delay fosc fosc 3.3 V 16 3 P-RES 4 N-RES 1 RELO 6 N-EN 5 P-EN 3.3-V under- and overvoltage detect. VCC 14 Current limitation VCC 5-V under- and overvoltage detect. Internal oscillator RELI 13 19k fosc 19k RCoscillator supervisor FETI 12 Watchdog WDI 11 19k 15 SGND 2 GND VCC RC oscillator FET output 10 8 WDC 9 FETO 7 VS CAPI Rev. 4543A–AUTO–05/02 1 Pin Configuration Figure 2. Pinning SO16 RELO GND P-RES N-RES P-EN N-EN VS CAPI 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 3.3V SGND VCC RELI FETI WDI WDC FETO Pin Description Pin Symbol Description Function Type 1 RELO Open-collector output driver Fail-safe relay driver Driver on: L 2 GND Supply General ground 3 P-RES Digital output Positive reset signal Reset: H 4 N-RES Digital output Negative reset signal Reset: L 5 P-EN Digital output Positive enable signal Enable: H 6 N-EN Digital output Negative enable signal Enable: L 7 VS Battery supply Voltage for charge pump 8 CAPI Analog input Input bootstrap capacitor 9 FETO Power FET output High voltage for N-channel FET 10 WDC Analog input External RC for watchdog timer 11 WDI Digital input Watchdog trigger signal Pulse sequence 12 FETI Digital input Activation of power FET FET on: H 13 RELI Digital input Activation of relay driver Driver on: H 14 VCC Supply 5-V supply 15 SGND Supply Sense ground, reference for VCC and 3.3 V 16 3.3V Analog input 3.3-V supply Fail-safe Functions 2 A fail-safe IC has to maintain its monitoring function even if there is a fault condition at one of the pins (e.g., short circuit), ensuring that a microcontroller system does not reach a “critical status”. A critical status means, for example, if the system is not able to switch off the relay or disable the power MOSFET, or if the system is not able to provide a signal to the microcontroller via ENABLE- and RESET-outputs in the case of a fault condition. The U6813B is designed to handle those fault conditions according to Table 1 for a maximum of system safety. U6813B 4543A–AUTO–05/02 U6813B Table 1. Truth Table RELI FETI RELO FETO N-RES P-RES P-EN (2) N-EN (3) ok H x on x H L H L ok L (1) x off x H L H L ok x H x on H L H L x off H L H L VCC 3.3V WDI ok ok ok ok ok ok ok ok ok x ok ok wrong x x off off H L L H x wrong x x x off off L H L H x x x x off off L H L H wrong Notes: L (1) 1. default state at open input 2. P-EN disable: low 3. N-EN disable: high Watchdog Description Figure 3. Watchdog Block Diagram Binary counter WDC Dual MUX WDI Slope detector Up/down counter RS-FF WD-OK RESET OSCERR The microcontroller is monitored by a digital window watchdog which accepts an incomming trigger signal of a constant frequency for correct operation. The frequency of the trigger signal can be varied in a broad range as the watchdog’s time window is determined by external R/C components. The following description refers to the watchdog timing diagram with tolerances (see Figure 4). WDI Input (Pin 11) The microcontroller has to provide a trigger signal with the frequency fWDI which is fed to the WDI input. A positive edge of fWDI detected by a slope detector resets the binary counter and clocks the up/down counter.The latter one counts only from 0 to 3 or reverse. Each correct trigger increments the up/down counter by 1, each wrong trigger decrements it by 1. As soon as the counter reaches status 3, the RS flip-flop is set; see Figure 5 (Watchdog state diagram). A missing incoming trigger signal is detected after 250 clocks of the internal watchdog frequency fRC (see WD_OK output) and resets the up/down counter directly. WDC Input (Pin 10) It is to be equiped by external R/C components. By means of an external R/C circuitry, the IC generates a time base (frequency fWDC) independent from the microcontroller. The watchdog’s time window refers to a frequency of fWDC = 100 ´ fWDI. 3 4543A–AUTO–05/02 OSCERR Input A smart watchdog has to ensure that internal problems with its own time base are detected and do not lead to an undesired status of the complete system. If the RC oscillator stops oscillating, a signal is fed to the OSCERR input after a timeout delay. It resets the up/down counter and disables the WD-OK output. Without this reset function, the watchdog would freeze its current status when fRC stops. RESET Input During power-on and under/overvoltage detection, a reset signal is fed to this pin. It resets the watchdog timer and sets the initial state. WD-OK Output After the up/down counter has reached to status 3 (see Figure 5, Watchdog State Diagram), the RS flip-flop is set and the WD-OK output becomes logic “1”. As WD-OK is directly connected to the enable pins, the open-collector output P-EN provides also logic “1” while a logic “0” is available at N-EN output. If on the other hand the up/down counter is decremented to “0”, the RS flip-flop is reset, the WD-OK output and the P-EN output are logic “0” and N-EN output is logic “1”. The WD-OK output also controls a dual MUX stage which shifts the time window by one clock after a successful trigger, thus forming a hysteresis to provide stable conditions for the evaluation of the trigger signal “good or false”. The WD-OK signal is also reset in case the watchdog counter is not reset after 250 clocks (missing trigger signal). Figure 4. Watchdog Timing Diagram with Tolerances Time/s 79/ fWDC 80/ fWDC 169/ fWDC 170/ fWDC 250/ fWDC 251/ fWDC Watchdog Window update rate is good Update rate is too fast Update rate is either too fast or good Update rate is either too slow or good Update rate is too slow Update rate is either too slow or pulse has dropped out Pulse has dropped out Figure 5. Watchdog State Diagram good Initial status 2/NF 1/NF bad bad bad good good bad O/F 3/NF bad good bad 1/F 2/F good good Explanation 4 In each block, the first character represents the state of the counter. The second notation indicates the fault status of the counter. A fault status is indicated by an “F” and a no-fault status is indicated by an “NF”. When the watchdog is powered up initially, the counter starts at the 0/F block (initial state). “Good” indicates that a pulse has been received whose width resides within the timing window. “Bad” indicates that a pulse has been received whose width is either too short or too long. U6813B 4543A–AUTO–05/02 U6813B Watchdog Window Calculation Example with recommended values Cosc = 6.8 nF (should be preferably 10%, NPO) Rosc = 36 kW (can be 5%, Rosc < 200 kW due to leakage current and humidity) RC oscillator tWDC (s) = 10-3 [Cosc (nF) [(0.00078 Rosc (kW)) + 0.0005]] fWDC (Hz) = 1 / (tWDC) Watchdog WDI fWDI (Hz) = 0.01 fWDC tWDC = 200 µs ® fWDC = 5 kHz fWDI = 50 Hz ® tWDI = 20 ms WDI pulse width for fault detection after 3 pulses: Upper watchdog window Minimum: 169/ fWDC = 33.8 ms -> fWDC/ 169 = 29.55 Hz Maximum: 170/ fWDC = 34 ms -> fWDC/ 170 = 29.4 Hz Lower watchdog window Minimum: 79/ fWDC = 15.8 ms -> fWDC / 79 = 63.3 Hz Maximum: 80/ fWDC = 16 ms -> fWDC / 80 = 62.5 Hz WDI dropouts for immediate fault detection: Minimum: Maximum: 250/ fWDC = 50.0 ms 251/ fWDC = 50.2 ms Remarks to reset relay The duration of the over- or undervoltage pulses determines the enable- and reset outputs. A pulse duration shorter than the debounce time has no effect on the outputs. A pulse longer than the debounce time results in the first reset delay. If a pulse appears during this delay, a second delay time is triggered. Therefore, the total reset delay time can be longer than specified in the data sheet. 5 4543A–AUTO–05/02 Absolute Maximum Ratings Parameters Symbol Value Unit VS - 0.2 to +26 V Ptot Ptot 250 150 mW mW Tj 150 °C Ambient temperature range Tamb -40 to +125 °C Storage temperature range Tstg -55 to +155 °C Symbol Value Unit RthJA 110 K/W Supply voltage range Power dissipation VS = 5 V; Tamb = -40°C VS = 5 V; Tamb = 125°C Junction temperature Thermal Resistance Parameters Junction ambient Electrical Characteristics VCC = 5 V, Tamb = -40 to +125°C; reference pin is GND or SGND (over- and under-voltage detection); fintern = 200 kHz +50%/-45%, fWDC = 5 kHz ±10%; fWDI = 50 Hz, bootstrap capacitor CBoot = 47 nF at Pin CAPI No. 1 Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Supply 1.1 Operation-voltage range 14 VCC 4.5 5.5 V D 1.2 Operation-voltage range of RESET outputs 14 VCC 1.1 18.0 V A 1.3 Current consumption 15 10 mA mA 2 V = 5.25 V, Relay on Tamb = -40°C Tamb = +125°C A 14 ICC ICC Digital Input WDI 2.1 Detection low 11 VWDI -0.2 0.3 ´ VCC V D 2.2 Detection high 11 VWDI 0.7 ´ VCC VCC + 0.2 V V D 2.3 Internal pull-down resistor 11 RINT11 10 40 kW A 2.4 Input current low Input voltage = 0 V 11 IWDI -5 5 µA A 2.5 Input current high Input voltage = 5 V 11 IWDI 100 550 µA A 3 Digital Input RELI 3.1 Detection low 13 VRELI -0.2 0.3 ´ VCC V D 3.2 Detection high 13 VRELI 0.7 ´ VCC VCC + 0.2 V V D 3.3 Internal pull-down resistor 13 RINT13 10 40 kW A 3.4 Input current low 13 IRELI -5 5 µA A Input voltage = 0 V *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. If VS > 26 V the current has to be limited at 5 mA by an external resistor. 6 U6813B 4543A–AUTO–05/02 U6813B Electrical Characteristics (Continued) VCC = 5 V, Tamb = -40 to +125°C; reference pin is GND or SGND (over- and under-voltage detection); fintern = 200 kHz +50%/-45%, fWDC = 5 kHz ±10%; fWDI = 50 Hz, bootstrap capacitor CBoot = 47 nF at Pin CAPI No. Parameters Test Conditions Pin Symbol Min. 3.5 Input current high Input voltage = 5 V 13 IRELI 4 Digital Input FETI Typ. Max. Unit Type* 100 550 µA A 4.1 Detection low 12 VFETI -0.2 0.3 ´ VCC V A 4.2 Detection high 12 VFETI 0.7 ´ VCC VCC + 0.2 V V A 4.3 Internal pull-down resistor 12 RINT12 10 40 kW A 4.4 Input current low Input voltage = 0 V 12 IFETI -5 5 µA A Input current high Input voltage = 5 V 12 IFETI 100 550 µA A 0.5 V A 0.5 µA A 500 µs A ms A V A 4.5 5 Digital Output N-RES (Open Collector) 5.1 Saturation voltage low Ireset £ 2.5 mA 4 VSAT4 5.2 Leakage current at 5 V, high state 4 ILEAK4 5.3 Reset debounce time (switch to low) Over- or undervoltage 4 tDEB4 5.4 Reset delay (switch back to high) Over- or undervoltage 4 tDEL4 6 120 50 Digital Output P-RES (Internal Pull-down Resistor) 6.1 Saturation voltage high Ireset £ 0.3 mA 3 VSAT3 6.2 Leakage current at 0 V, low state 3 ILEAK3 VCC0.5 V VCC 0.5 µA A 100 kW A 500 µs A ms A VCC V A 0.5 µA A 100 kW A 500 µs A ms A 6.3 Internal pull-down resistor at 5 V 3 RINT3 25 6.4 Reset debounce time (switch to low) Over- or undervoltage 3 tDEB3 120 6.5 Reset delay (switch back to high) Over- or undervoltage 3 tDEL3 7 320 320 50 Digital Output N-EN (with Open Collector and Internal Pull-down Resistor) 7.1 Saturation voltage high I £ 1 mA 6 VSAT6 7.2 Leakage current at 0 V, low state 6 ILEAK6 7.3 Internal pull-down resistor at 5 V 6 RINT6 25 7.4 Enable debounce time (switch to low) Over- or undervoltage 6 tDEB6 120 7.5 Enable delay (switch back to high) Over- or undervoltage 6 tDEL6 VCC0.5V 320 85 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. If VS > 26 V the current has to be limited at 5 mA by an external resistor. 7 4543A–AUTO–05/02 Electrical Characteristics (Continued) VCC = 5 V, Tamb = -40 to +125°C; reference pin is GND or SGND (over- and under-voltage detection); fintern = 200 kHz +50%/-45%, fWDC = 5 kHz ±10%; fWDI = 50 Hz, bootstrap capacitor CBoot = 47 nF at Pin CAPI No. 8 Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Digital Output P-EN (Internal Pull-up Resistor) 8.1 Saturation voltage high I £ 3 mA 5 VSAT5 0.5 V A 8.2 Leakage current at 5 V, high state 5 ILEAK5 0.5 mA A 8.3 Internal pull-up resistor at 0 V 5 RINT5 12.5 50 kW A 8.4 Enable debounce time (switch to high) Over- or undervoltage 5 tDEB5 120 500 ms A 8.5 Enable delay (switch back to low) Over- or undervoltage 5 tDEL5 ms A 9 Relay Driver (RELO) I £ 150 mA 1 VSAT1 0.1 0.5 V A 320 85 9.1 Saturation voltage 9.2 Current limitation 1 ILIM 150 300 mA A 9.3 Internal clamping voltage 1 VCL 26 30 V A 9.4 Turn-off energy 1 mJ C 9.5 Leakage current mA mA A 10 Power-FET Output FETO (Maximum Load Capacitor at FET Gate 470 pF, Charge-pump Frequency 110 to 300 kHz) 10.1 Output voltage 10.2 Operation range VBatt = 16 V VBatt = 26 V at 25°C VS = 9 V to 15 V 1 30 20 200 ILEAK1 ILEAK1 9 VOUT9 VS + 10 V 7 VS 9 20 V A 24 V A 30 V A 10.3 Overvoltage shutdown 7 VS 20 10.4 Internal clamping voltage 9 VCL 26 10.5 On/off frequency 10.6 Maximum current FETO 9 f 9 IFETO 10 200 11 Battery Supply 11.1 Internal clamping voltage 7 VCL 26 11.2 Clamping current capability (1) 7 IVS 5 11.3 Leakage current at FETI = low 7 ILEAVS 12 VS + 15 V V A Hz A mA A V A mA A 100 mA A 30 Reset and VCC Control 12.1 Lower reset level Reference SGND 14 VCC 4.5 4.75 V A 12.2 Upper reset level Reference SGND 14 VCC 5.25 5.5 V A 12.3 Hysteresis 14 VHYST14 25 100 mV A 12.4 Reset debounce time 14 tDEB 120 320 500 ms A 12.5 Reset delay 14 tDEL 20 50 80 ms A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. If VS > 26 V the current has to be limited at 5 mA by an external resistor. 8 U6813B 4543A–AUTO–05/02 U6813B Electrical Characteristics (Continued) VCC = 5 V, Tamb = -40 to +125°C; reference pin is GND or SGND (over- and under-voltage detection); fintern = 200 kHz +50%/-45%, fWDC = 5 kHz ±10%; fWDI = 50 Hz, bootstrap capacitor CBoot = 47 nF at Pin CAPI No. Parameters Test Conditions 13 Reset and 3.3 V Control Pin Symbol Min. Typ. Max. Unit Type* 13.1 Lower reset level Reference SGND 16 V3.3V 2.97 3.13 V A 13.2 Upper reset level Reference SGND 16 V3.3V 3.47 3.63 V A 13.3 Hysteresis 16 VHYST16 15 70 mV A 13.4 Reset debounce time 16 tDEB16 120 320 500 ms A 13.5 Reset delay 16 tDEL16 20 50 13.6 Current 16 I3.3V 10 fWDC 4.5 tPOR 14 RC Oscillator WDC 14.1 Oscillator frequency 15 Watchdog Timing ROSC = 36 kW COSC = 6.8 nF 80 ms A 0.5 mA C 5.5 kHz A 34.3 103.1 ms A tRCerror 81.9 246 ms A 5 15.1 Power-on-reset prolongation time 15.2 Detection time for RC-oscillator fault 15.3 Time interval for over/under-voltage detection tD,OUV 0.16 0.64 ms A 15.4 Reaction time of reset output at over/under voltage tR,OUV 0.187 0.72 ms A 15.5 Nominal frequency for WDI fRC = 100 fWDI fWDI 10 65 Hz D 15.6 Nominal frequency for WDC fWDI = 1/100 fWDC fWDC 1 6.5 kHz D 15.7 Minimum pulse duration for a guaranteed WDI input-pulse detection fWDC = 5 kHz tP,WDI 364 µs A 15.8 Frequency range for a correct WDI signal fWDC = 5 kHz fWDI 32.35 Hz D 15.9 Number of incorrect WDI trigger counts for locking the outputs nlock 3 A 15.10 Number of correct WDI trigger counts for releasing the outputs nrelease 3 A 15.11 Detection time for a stucked WDI signal VCR = constant VWDI = constant fWDC = 5 kHz tWDIerror 49 56.25 51 ms A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. If VS > 26 V the current has to be limited at 5 mA by an external resistor. 9 4543A–AUTO–05/02 Electrical Characteristics (Continued) VCC = 5 V, Tamb = -40 to +125°C; reference pin is GND or SGND (over- and under-voltage detection); fintern = 200 kHz +50%/-45%, fWDC = 5 kHz ±10%; fWDI = 50 Hz, bootstrap capacitor CBoot = 47 nF at Pin CAPI No. Parameters Test Conditions 16 Watchdog Timing Relative to fWDC 16.1 Minimum pulse duration for a guaranteed WDI input-pulse detection 16.2 Frequency range for a correct WDI signal 16.3 Hysteresis range at the WDI ok margins 16.4 Detection time for a stucked WDI signal (WDI dropout) Pin Symbol Min. Typ. Max. 2 80 170 1 VWDI = constant 250 251 Unit Type* cycles A cycles D cycle A cycles A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. If VS > 26 V the current has to be limited at 5 mA by an external resistor. Table 2. Protection Versus Transient Voltages According to ISO TR 7637-1 Level 4 (Except Pulse 5) Note: 10 Pulse Voltage Source Resistance (1) Rise Time Duration Amount 1 - 110 V 10 W 100 V/s 2 ms 15.000 2 + 110 V 10 W 100 V/s 0.05 ms 15.000 3a - 160 V 50 W 30 V/ns 0.1 µs 1h 3b + 150 V 50 W 20 V/ns 0.1 µs 1h 5 55 V 2W 10 V/ms 250 ms 20 1. In the case of the relay driver, the coil resistance of Rmin = 150 W has to be added to the source resistance. U6813B 4543A–AUTO–05/02 U6813B Timing Diagrams Figure 6. Watchdog in Too-fast Condition Normal operation WDI too fast Normal operation 5V WDI 0V V Batt RELO 0V V Batt FETO 0V 5V P-EN 0V 5V N-EN 0V Don't care 14195 Figure 7. Watchdog in Too-slow Condition Normal operation WDI too slow Normal operation 5V WDI 0V V Batt RELO 0V V Batt FETO 0V 5V P-EN 0V 5V N-EN 0V Don't care 14196 11 4543A–AUTO–05/02 Figure 8. Overvoltage Condition Overvoltage condition > 120 µs 5V < 120 µs >5.5 V >5.5 V V CC 0V V Batt RELO 0V V Batt FETO 0V 5V P-EN 0V 5V N-EN 0V 5V N-RES 0V 5V P-RES 0V Reset debounce time 3 good WDI pulses Don't care 1st Reset delay 2nd Reset delay Figure 9. Undervoltage Condition Undervoltage condition > 120 µs 5V V CC <4.5 V <120 µs <4.5 V 0V V Batt RELO 0V V Batt FETO 0V 5V P-EN 0V 5V N-EN 0V 5V N-RES 0V 5V P-RES 0V Reset debounce time 3 good WDI pulses Don't care 1st Reset delay 2nd Reset delay 12 U6813B 4543A–AUTO–05/02 U6813B Figure 10. Application Circuit From mC FET in Relay in Watchdog in VBatt Sense ground 3.3 V 1k 36k VCC 2.7M 47n 16 15 3.3V SGND 14 13 12 VCC RELI FETI 11 WDI 10 9 WDC FETO 6.8n U6813B RELO 1 GND 2 P-RES N-RES P-EN N-EN VS 3 4 5 6 7 CAPI 8 47n To mC 1k VBatt 100n 13 4543A–AUTO–05/02 Ordering Information Extended Type Number Package U6813B-MFPG3 SO16 Remarks Taped and reeled Package Information Package SO16 Dimensions in mm 5.2 4.8 10.0 9.85 3.7 1.4 0.25 0.10 0.4 1.27 6.15 5.85 8.89 16 0.2 3.8 9 technical drawings according to DIN specifications 1 14 8 U6813B 4543A–AUTO–05/02 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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