5 4 3 2 1 3.3V J1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 1 2 3 4 5 6 XRES P1_0 P1_1 P1_2 P1_3 P1_4 P1_5 SWDIO SWDCK SWV VBUSB2 D1 3.3V CDBU0520 0603 U5 C19 10uF 0603 D3 3 D14 GREEN LED 7 CDBU0520 OUT 2 SENSE SHUTDOWN FED_BK LP2951CMM-3.3 1 0603 IN 1 C23 10uF C18 5 ERROR PSoC3 chip - CY8C3866LTI-030 0.1uF Or Alternate PSoC5LP chip - CY8C5868LTI-LP039 6 VTAP P2_4 P2_3 P2_2 P2_1 P2_0 P0_7 P0_6 P0_5 P0_4 P0[3] (GPIO, OpAmp0-/Extref0) P0[2] (GPIO, OpAmp0+) P0[1] (GPIO, OpAmp0out) P0[0] (GPIO, OpAmp2out) P12[3] (SIO) P12[2] (SIO) Vssd3 Vdda Vssa Vcca P15[3] (GPIO, kHz XTAL: Xi) P15[2] (GPIO, kHz XTAL: Xo) P12[1] (SIO, I2C1: SDA) P12[0] (SIO, 12C1: SCL) P3[7] (GPIO, OpAmp3out) P3[6] (GPIO, OpAmp1out) Vddio3 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 P0_3 P0_2 P0_1 P0_0 P12_3 P12_2 C 3.3V P12_1 P12_0 C2 1uF 3.3V B D+RES D-RES CDBU0520 3.3V GND VBEXT 2 8 4 D2 B (GPIO) P2[6] (GPIO) P2[7] (I2C0: SCL, SIO) P12[4] I2C0: SDA, SIO) P12[5] Vssb Ind Vboost Vbat Vssd1 XRES (TMS, SWDIO, GPIO) P1[0] (TCK, SWDCK, GPIO) P1[1] (configurable XRES, GPIO) P1[2] (TDO, SWV, GPIO) P1[3] (TDI, GPIO) P1[4] (nTRST, GPIO) P1[5] Vddio1 69 HDR 6x1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 P2_6 P2_7 P12_4 P12_5 HDR 14x1 VBUSB1 P2[5] (GPIO) Vddio2 P2[4] (GPIO) P2[3] (GPIO) P2[2] (GPIO) P2[1] (GPIO) P2[0] (GPIO) P15[5] (GPOI) P15[4] (GPIO) Vddd1 Vssd4 Vccd1 P0[7] (GPIO, IDAC2) P0[6] (GPIO, IDAC0) P0[5] (GPIO, OpAmp P0[4] (GPIO, OpAmp Vddio0 1 2 3 4 5 6 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 C J4 1 2 3 4 5 6 P3_5 P3_4 P3_3 P3_2 P3_1 P3_0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (GPIO) P1[6] (GPIO) P1[7] (SIO) P12[6] (SIO) P12[7] (USBIO, D+, SWDIO) P15[6] (USBIO, D-, SWDCK) P15[7] Vddd0 Vssd2 Vccd0 (MHz XTAL: Xo, GPIO) P15[0] (MHz XTAL: Xi, GPIO) P15[1] (IDAC1, GPIO) P3[0] (IDAC3, GPIO) P3[1] (OpAmp3-/Extref1, GPIO) P3[2] (OpAmp3+, GPIO) P3[3] (OpAmp1-, GPIO) P3[4] (OpAmp1+, GPIO) P3[5] J2 thrm_pad U1 HDR 14x1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C1 .1uF 3.3V 3.3V HDR 6x1 VBEXT P0_6 P0_4 P0_2 P0_0 P2_6 P2_4 P2_2 P2_0 XRES P1_6 P1_4 P1_2 P1_0 D VCCD_0/1 P2_5 P1_7 P1_5 P1_3 P1_1 J3 P12_4 P12_5 P12_3 P12_2 P12_1 P12_0 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 P1_6 P1_7 P0_7 P0_5 P0_3 P0_1 P2_7 P2_5 P2_3 P2_1 C5 1uF 4 6 7 8 9 A VCC J5 REMOVE R2 FOR USB COMPLIANCE. 1 VBUSB1 3.3V C3 0.1uF 3.3V C4 0.1uF NC USBDUSBD+ MP MP1 MP2 MP3 2 3 1 DD+ 5 C7 0.1uF C8 0.1uF C9 0.1uF 2 22 ohm 0402 5% Note: Schematic Rev 5.1.1 is valid for PCB Rev 5.1.0 R3 VBUSB2 C6 0.1uF R4 GND 2 1 VCCD_0/1 FED_BK R2 1k 0402 5% 1 USB_SM_MINI A Ansync, Inc. (c) Copyright 2012 2 3.3V Title VBUSB2 5 PSOC3PIM1/PSOC5PIM1 22 ohm 0402 5% 3.3V 4 3 2 Size B Document Number <Doc> Date: Sunday, April 21, 2013 Rev 5.1.1 Sheet 1 1 of 2 5 4 3 2 1 D 2 D 3.3V 3.3V 9 8 3.3V 13 54 10K 44 29 30 31 R28 2.2K 0402 0402 3.3V 3.3V DMINUS DPLUS 3.3V 0402 R24 1 2 R29 2.2K PB0/FD0 PB1/FD1 PB2/FD2 PB3/FD3 PB4/FD4 PB5/FD5 PB6/FD6 PB7/FD7 IFCLK CLKOUT WAKEUP# CTL0/FLAGA CTL1/FLAGB CTL2/FLAGC PD0/FD8 PD1/FD9 PD2/FD10 PD3/FD11 PD4/FD12 PD5/FD13 PD6/FD14 PD7/FD15 RDY0/SLRD RDY1/SLWR U4 AGND1 AGND2 24LC01B SOT-23-5 SCL SDA 12 41 6 10 B CP 15 16 57 1 2 3 GND3 GND4 GND5 GND6 WP SCL VSS SDA 26 28 53 56 VCC 5 GND1 GND2 SOT-23 4 4 XTALOUT PA0/nINT0 PA1/nINT1 PA2/SLOE PA3/WU2 PA4/FIFOADR0 PA5/FIFOADR1 PA6/PKTEND PA7/FLAGD RESET# 33 34 35 36 37 38 39 40 C 18 19 20 21 22 23 24 25 XRES 45 46 47 48 49 50 51 52 SWV SWDIO RESERVED 2 3 AVCC1 AVCC2 SWDCK B 14 1 NC USBDUSBD+ MP MP1 MP2 MP3 42 5 C 3 7 0.1 uFd GND 4 USB_SM_MINI 6 7 8 9 VCC J6 5 17 27 43 55 C20 0402 1 Y1 24 MHz XTALIN 0.1 uFd VCC3 VCC4 VCC5 VCC6 VBUSB2 U3 C22 0402 VCC1 VCC2 0603 C21 2.2 uFd 6.3V 0402 11 32 3 R21 100K 1% CY7C68013A-56LFXC 3.3V A C12 C13 C14 C15 C16 C17 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF A Ansync, Inc. (c) Copyright 2012 VBUSB2 3.3V Title PSOC3PIM1/PSOC5PIM1 3.3V VBUSB2 5 4 3 2 Size B Document Number <Doc> Date: Sunday, April 21, 2013 Rev 5.1.1 Sheet 1 2 of 2