TJA1080A FlexRay transceiver Rev. 5 — 24 February 2011 Product data sheet 1. General description The TJA1080A is a FlexRay transceiver that is fully compliant with the FlexRay electrical physical layer specification V2.1 Rev. A (see Ref. 1). In addition, it incorporates features and parameters included in V3.0.1 (see Ref. 2 and Section 14). It is primarily intended for communication systems from 1 Mbit/s to 10 Mbit/s, and provides an advanced interface between the protocol controller and the physical bus in a FlexRay network. The TJA1080A can be configured to be used as an active star transceiver or as a node transceiver. The TJA1080A provides differential transmit capability to the network and differential receive capability to the FlexRay controller. It offers excellent EMC performance as well as high ESD protection. The TJA1080A actively monitors the system performance using dedicated error and status information (readable by any microcontroller), as well as internal voltage and temperature monitoring. The TJA1080A supports the mode control as used in NXP Semiconductors TJA1054 (see Ref. 3) and TJA1041 (see Ref. 4) CAN transceivers. The TJA1080A is the next step up from the TJA1080 FlexRay transceiver (Ref. 5). Being fully pin compatible and offering the same excellent ESD protection, the TJA1080A also features: • • • • Improved power-on reset concept Improved ElectroMagnetic Emission (EME) Support of 60 ns minimum bit time Improved bus error detection functionality This makes the TJA1080A an excellent choice in any kind of FlexRay node. See Section 14 for a detailed overview of differences between the TJA1080 and the TJA1080A. 2. Features and benefits 2.1 Optimized for time triggered communication systems Compliant with FlexRay electrical physical layer specification V2.1 Rev. A (see Ref. 1) Automotive product qualification in accordance with AEC-Q100 Data transfer up to 10 Mbit/s Support of 60 ns minimum bit time TJA1080A NXP Semiconductors FlexRay transceiver Very low EME to support unshielded cable Differential receiver with high common-mode range for ElectroMagnetic Immunity (EMI) Auto I/O level adaptation to host controller supply voltage VIO Can be used in 14 V and 42 V powered systems Instant shut-down interface (via BGE pin) Independent power supply ramp-up for VBAT, VCC and VIO Transceiver can be used for linear passive bus topologies as well as active star topologies 2.2 Low power management Low power management including two inhibit switches Very low current in Sleep and Standby modes Local and remote wake-up Supports remote wake-up via dedicated data frames Wake-up source recognition Automatic power-down (in Star-sleep mode) in star configuration 2.3 Diagnosis (detection and signalling) Overtemperature detection Short-circuit on bus lines VBAT power-on flag (first battery connection and cold start) Pin TXEN and pin BGE clamping Undervoltage detection on pins VBAT, VCC and VIO Wake source indication 2.4 Protection Bus pins protected against 8 kV HBM ESD pulses Bus pins protected against transients in automotive environment (according to ISO 7637 class C) Bus pins short-circuit proof to battery voltage (14 V and 42 V) and ground Fail-silent behavior in case of an undervoltage on pins VBAT, VCC or VIO Passive behavior of bus lines in the event that transceiver is not powered 2.5 Functional classes according to FlexRay electrical physical layer specification (see Ref. 1) TJA1080A Product data sheet Bus driver voltage regulator control Bus driver - bus guardian control interface Bus driver logic level adaptation Active star - communication controller interface Active star - bus guardian interface Active star voltage regulator control All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 2 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 3. Ordering information Table 1. Ordering information Type number TJA1080ATS/2/T TJA1080A Product data sheet Package Name Description Version SSOP20 plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 3 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 4. Block diagram VIO VCC 4 VBUF 19 VBAT 20 14 1 2 TJA1080A TRXD0 INH1 11 18 SIGNAL ROUTER TRXD1 INH2 TRANSMITTER 17 BP BM 10 VIO TXD TXEN BGE STBN EN RXD ERRN RXEN 5 6 INPUT VOLTAGE ADAPTATION 8 9 3 7 13 12 OUTPUT VOLTAGE ADAPTATION VBAT WAKE BUS FAILURE DETECTION 15 RXDINT STATE MACHINE RXDINT NORMAL RECEIVER OVERTEMPERATURE DETECTION WAKE-UP DETECTION OSCILLATOR LOWPOWER RECEIVER UNDERVOLTAGE DETECTION 16 015aaa051 GND Fig 1. Block diagram TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 4 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 5. Pinning information 5.1 Pinning INH2 1 20 VBUF INH1 2 19 VCC EN 3 18 BP VIO 4 TXD 5 TXEN 6 15 WAKE RXD 7 14 VBAT BGE 8 13 ERRN STBN 9 12 RXEN 17 BM TJA1080A 16 GND TRXD1 10 11 TRXD0 015aaa052 Fig 2. Pin configuration 5.2 Pin description Table 2. TJA1080A Product data sheet Pin description Symbol Pin Type Description INH2 1 O inhibit 2 output for switching external voltage regulator INH1 2 O inhibit 1 output for switching external voltage regulator EN 3 I enable input; when HIGH enabled; internal pull-down VIO 4 P supply voltage for VIO voltage level adaptation TXD 5 I transmit data input; internal pull-down TXEN 6 I transmitter enable input; when HIGH transmitter disabled; internal pull-up RXD 7 O receive data output BGE 8 I bus guardian enable input; when LOW transmitter disabled; internal pull-down STBN 9 I standby input; low-power mode when LOW; internal pull-down TRXD1 10 I/O data bus line 1 for inner star connection TRXD0 11 I/O data bus line 0 for inner star connection RXEN 12 O receive data enable output; when LOW bus activity detected ERRN 13 O error diagnoses output; when LOW error detected VBAT 14 P battery supply voltage WAKE 15 I local wake-up input; internal pull-up or pull-down (depends on voltage at pin WAKE) GND 16 P ground BM 17 I/O bus line minus BP 18 I/O bus line plus VCC 19 P supply voltage (+5 V) VBUF 20 P buffer supply voltage All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 5 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 6. Functional description The block diagram of the total transceiver is illustrated in Figure 1. 6.1 Operating configurations 6.1.1 Node configuration In node configuration the transceiver operates as a stand-alone transceiver. The transceiver can be configured as node by connecting pins TRXD0 and TRXD1 to ground during a power-on situation (PWON flag is set). The configuration will be latched when the PWON flag is reset, see Section 6.7.4. The following operating modes are available: • • • • • Normal (normal power mode) Receive-only (normal power mode) Standby (low power mode) Go-to-sleep (low power mode) Sleep (low power mode) 6.1.2 Star configuration In star configuration the transceiver operates as a branch of a FlexRay active star. The transceiver can be configured as star by connecting pin TRXD0 or TRXD1 to VBUF during a PWON situation (PWON flag is set). The configuration will be latched when the PWON flag is reset, see Section 6.7.4 “Power-on flag”. It is possible to redirect data from one branch to other branches via the inner bus. It is also possible to send data to all branches via pin TXD, if pins TXEN and BGE have the correct polarity. The following operating modes are available: • • • • • • Star-idle (normal power mode) Star-transmit (normal power mode) Star-receive (normal power mode) Star-sleep (low power mode) Star-standby (low power mode) Star-locked (normal power mode) In the star configuration all modes are autonomously controlled by the transceiver, except in the case of a wake-up. TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 6 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 6.1.3 Bus activity and idle detection The following mechanisms for activity and idle detection are valid for node and star configurations in normal power modes: • If the absolute differential voltage on the bus lines is higher than |Vi(dif)det(act)| for tdet(act)(bus), then activity is detected on the bus lines and pin RXEN is switched to LOW which results in pin RXD being released: – If, after bus activity detection, the differential voltage on the bus lines is higher than VIH(dif), pin RXD will go HIGH – If, after bus activity detection, the differential voltage on the bus lines is lower than VIL(dif), pin RXD will go LOW • If the absolute differential voltage on the bus lines is lower than |Vi(dif)det(act)| for tdet(idle)(bus), then idle is detected on the bus lines and pin RXEN is switched to HIGH. This results in pin RXD being blocked (pin RXD is switched to HIGH or stays HIGH) Additionally, in star configuration, activity and idle can be detected (see Figure 6 for state transitions due to activity/idle detection in star configuration): • If pin TXEN is LOW for longer than tdet(act)(TXEN), activity is detected on pin TXEN • If pin TXEN is HIGH for longer than tdet(idle)(TXEN), idle is detected on pin TXEN • If pin TRXD0 or TRXD1 is LOW for longer than tdet(act)(TRXD), activity is detected on pins TRXD0 and TRXD1 • If pin TRXD0 and TRXD1 is HIGH for longer than tdet(idle)(TRXD), idle is detected on pins TRXD0 and TRXD1 6.2 Operating modes in node configuration The TJA1080A provides two control pins STBN and EN in order to select one of the modes of operation in node configuration. See Table 3 for a detailed description of the pin signalling in node configuration, and Figure 3 for the timing diagram. All modes are directly controlled via pins EN and STBN unless an undervoltage situation is present. If VIO and (VBUF or VBAT) are within their operating range, pin ERRN indicates the status of the error flag. Table 3. Pin signalling in node configuration Mode STBN EN ERRN[1] LOW RXEN HIGH RXD LOW HIGH LOW HIGH HIGH error flag error flag reset LOW set bus activity bus idle bus DATA_0 bus enabled DATA_1 disabled or idle wake flag wake set[2] flag reset wake flag set[2] wake flag reset Normal HIGH Receive-only HIGH Go-to-sleep LOW Standby LOW HIGH error flag error flag [2] reset LOW set Sleep LOW X [1] Pin ERRN provides a serial interface for retrieving diagnostic information. [2] Valid if VIO and (VBUF or VBAT) are present. [3] If wake flag is not set. TJA1080A Product data sheet Transmitter INH1 INH2 All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 HIGH HIGH float[3] float float © NXP B.V. 2011. All rights reserved. 7 of 49 TJA1080A NXP Semiconductors FlexRay transceiver TXD BGE TXEN BP BM RXEN RXD 001aae439 Fig 3. Timing diagram in Normal mode node configuration normal receive only standby receive only normal 0.7VIO STBN 0.3VIO tdet(EN) td(STBN-INH2) tdet(EN) td(STBN-RXD) EN ERRN 0.7VIO 0.3VIO S2 001aag894 Fig 4. Timing diagram of control pins EN and STBN The state diagram in node configuration is illustrated in Figure 5. TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 8 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 1 RECEIVE ONLY NORMAL STBN = HIGH EN = LOW STBN = HIGH EN = HIGH 4 3, 30 15, 25, 42, 43 8, 17, 39 5 6, 33 31, 32 10, 20 11, 21 2 14, 24, 40, 41 7, 16, 38 28, 29 12, 22 19 STANDBY(1) GO-TO-SLEEP STBN = LOW EN = LOW STBN = LOW EN = HIGH 23 9, 18 36, 37 13, 34, 35 26, 44 27, 45 SLEEP STBN = LOW EN = X 001aae438 (1) At the first battery connection the transceiver will enter the Standby mode. Fig 5. State diagram in node configuration The state transitions are represented with numbers, which correspond with the numbers in column 3 of Table 4 to Table 7. TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 9 of 49 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors TJA1080A Product data sheet Table 4. State transitions forced by EN and STBN (node configuration) → indicates the action that initiates a transaction; →1 and →2 are the consequences of a transaction. Transition from mode Direction to mode Normal Rev. 5 — 24 February 2011 All information provided in this document is subject to legal disclaimers. Go-to-sleep Sleep Pin Flag Note STBN EN UVVIO UVVBAT UVVCC PWON Wake Receive-only 1 H →L cleared cleared cleared cleared cleared Go-to-sleep 2 →L H cleared cleared cleared cleared cleared Standby 3 →L →L cleared cleared cleared cleared cleared 4 H →H cleared cleared cleared X X Go-to-sleep 5 →L →H cleared cleared cleared X X Standby 6 →L L cleared cleared cleared X X Normal 7 →H →H cleared cleared 2 → cleared X 1 → cleared [2][3] Receive-only 8 →H L cleared cleared 2 → cleared X 1 → set [2][3] Go-to-sleep 9 L →H cleared cleared X X X Normal 10 →H H cleared cleared cleared X 1 → cleared [2][4] Receive-only 11 →H →L cleared cleared cleared X 1 → set [2][4] Standby 12 L →L cleared cleared X X X [4] Sleep 13 L H cleared cleared X X cleared [5] Normal 14 →H H 2 → cleared 2 → cleared 2 → cleared X 1 → cleared [2][3] Receive-only 15 →H L 2 → cleared 2 → cleared 2 → cleared X 1 → set [2][3] Receive-only Normal Standby Transition number [1] STBN must be set to LOW at least tdet(EN) after the falling edge on EN. [2] Positive edge on pin STBN sets the wake flag. In the case of a transition to Normal mode the wake flag is immediately cleared. [3] Setting the wake flag clears the UVVIO, UVVBAT and UVVCC flags. [4] Hold time of go-to-sleep is less than th(gotosleep). [5] Hold time of go-to-sleep becomes greater than th(gotosleep). [1] TJA1080A FlexRay transceiver 10 of 49 © NXP B.V. 2011. All rights reserved. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors TJA1080A Product data sheet Table 5. State transitions forced by a wake-up (node configuration) → indicates the action that initiates a transaction; →1 and →2 are the consequences of a transaction. Transition from mode Direction to mode Transition number Pin STBN EN UVVIO UVVBAT UVVCC PWON Wake Standby Normal 16 H H cleared cleared 1 → cleared X → set [1] Receive-only 17 H L cleared cleared 1 → cleared X → set [1] Go-to-sleep 18 L H cleared cleared 1 → cleared X → set [1] Standby 19 L L cleared cleared 1 → cleared X → set [1] Normal 20 H H cleared cleared 1 → cleared X → set [1] Receive-only 21 H L cleared cleared 1 → cleared X → set [1] Standby 22 L L cleared cleared 1 → cleared X → set [1] Go-to-sleep 23 L H cleared cleared 1 → cleared X → set [1] Go-to-sleep Rev. 5 — 24 February 2011 All information provided in this document is subject to legal disclaimers. Sleep Flag Note Normal 24 H H 1 → cleared 1 → cleared 1 → cleared X → set [1][2] Receive-only 25 H L 1 → cleared 1 → cleared 1 → cleared X → set [1][2] Standby 26 L L 1 → cleared 1 → cleared 1 → cleared X → set [1] Go-to-sleep 27 L H 1 → cleared 1 → cleared 1 → cleared X → set [1][2] [1] Setting the wake flag clears the UVVIO, UVVBAT and UVVCC flag. [2] Transition via Standby mode. TJA1080A FlexRay transceiver 11 of 49 © NXP B.V. 2011. All rights reserved. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors TJA1080A Product data sheet Table 6. State transitions forced by an undervoltage condition (node configuration) → indicates the action that initiates a transaction; →1 and →2 are the consequences of a transaction. Transition from mode Direction to mode Transition number Flag UVVIO UVVBAT UVVCC PWON Wake Normal Sleep 28 → set cleared cleared cleared cleared [1] Sleep 29 cleared → set cleared cleared cleared [1] Standby 30 cleared cleared → set cleared cleared [1] Sleep 31 → set cleared cleared X 1 → cleared [1] Sleep 32 cleared → set cleared X 1 → cleared [1] Standby 33 cleared cleared → set X 1 → cleared [1] Sleep 34 → set cleared cleared X 1 → cleared [1] Sleep 35 cleared → set cleared X 1 → cleared [1] Sleep 36 → set cleared X X 1 → cleared [1][2] Sleep 37 cleared → set X X 1 → cleared [1][3] Receive-only Go-to-sleep Rev. 5 — 24 February 2011 All information provided in this document is subject to legal disclaimers. Standby [1] UVVIO, UVVBAT or UVVCC detected clears the wake flag. [2] UVVIO overrules UVVCC. [3] UVVBAT overrules UVVCC. Note TJA1080A FlexRay transceiver 12 of 49 © NXP B.V. 2011. All rights reserved. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors TJA1080A Product data sheet Table 7. State transitions forced by an undervoltage recovery (node configuration) → indicates the action that initiates a transaction; →1 and →2 are the consequences of a transaction. Transition from mode Direction to mode Transition number Pin STBN EN UVVIO UVVBAT UVVCC PWON Wake Standby Normal 38 H H cleared cleared → cleared X X [1] Receive-only 39 H L cleared cleared → cleared X X [1] Normal 40 H H cleared → cleared cleared X 1 → cleared Normal 41 H H → cleared cleared cleared X X Sleep Flag Note [2][3] [4] Rev. 5 — 24 February 2011 All information provided in this document is subject to legal disclaimers. Receive-only 42 H L cleared → cleared cleared X 1 → set Receive-only 43 H L → cleared cleared cleared X X Standby 44 L L cleared → cleared cleared X 1 → set Sleep 45 L X → cleared cleared cleared X cleared [4] [2][3] [4] [2][3] Go-to-sleep 46 L H cleared → cleared cleared X 1 → set [2][3] Sleep 47 L X → cleared cleared cleared X cleared [4] [1] Recovery of UVVCC flag. [2] Recovery of UVVBAT flag. [3] Clearing the UVVBAT flag sets the wake flag. In the case of a transition to Normal mode the wake flag is immediately cleared. [4] Recovery of UVVIO flag. TJA1080A FlexRay transceiver 13 of 49 © NXP B.V. 2011. All rights reserved. TJA1080A NXP Semiconductors FlexRay transceiver 6.2.1 Normal mode In Normal mode the transceiver is able to transmit and receive data via the bus lines BP and BM. The output of the normal receiver is directly connected to pin RXD. The transmitter behavior in Normal mode of operation, with no time-out present on pins TXEN and BGE and the temperature flag not set, is given in Table 8. In this mode pins INH1 and INH2 are set HIGH. Table 8. Transmitter function table BGE TXEN TXD Transmitter L X X transmitter is disabled X H X transmitter is disabled H L H transmitter is enabled; the bus lines are actively driven; BP is driven HIGH and BM is driven LOW H L L transmitter is enabled; the bus lines are actively driven; BP is driven LOW and BM is driven HIGH 6.2.2 Receive-only mode In Receive-only mode the transceiver can only receive data. The transmitter is disabled, regardless of the voltages on pins BGE and TXEN. In this mode pins INH1 and INH2 are set HIGH. 6.2.3 Standby mode In Standby mode the transceiver has entered a low power mode which means very low current consumption. In the Standby mode the device is not able to transmit or receive data and the low power receiver is activated to monitor for bus wake-up patterns. Standby mode can be entered if the correct polarity is applied to pins EN and STBN (see Figure 5 and Table 4) or an undervoltage is present on pin VCC; see Figure 5. In this mode, pin INH1 is set HIGH. If the wake flag is set, pin INH2 is set to HIGH and pins RXEN and RXD are set to LOW, otherwise pin INH2 is floating and pins RXEN and RXD are set to HIGH; see Section 6.5. 6.2.4 Go-to-sleep mode In this mode the transceiver behaves as in Standby mode. If this mode is selected for a longer time than the go-to-sleep hold time parameter (minimum hold time) and the wake flag has been previously cleared, the transceiver will enter Sleep mode, regardless of the voltage on pin EN. TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 14 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 6.2.5 Sleep mode In Sleep mode the transceiver has entered a low power mode. The only difference with Standby mode is that pin INH1 is also set floating. Sleep mode is also entered if the UVVIO or UVVBAT flag is set. In case of an undervoltage on pin VCC or VBAT while VIO is present, the wake flag is set by a positive edge on pin STBN. The undervoltage flags will be reset by setting the wake flag, and therefore the transceiver will enter the mode indicated on pins EN and STBN if VIO is present. A detailed description of the wake-up mechanism is given in Section 6.5. 6.3 Operating modes in star configuration In star configuration mode control via pins EN and STBN is not possible. The transceiver autonomously controls the operating modes except in the case of wake-up. The timing diagram of a transceiver configured in star configuration is illustrated in Figure 7. The state diagram in star configuration is illustrated in Figure 6. A detailed description of the pin signalling in star configuration is given in Table 9. If VIO and (VBUF or VBAT) are within their operating range, pin ERRN will indicate the error flag. Table 9. Pin signalling in star configuration Mode TRXD0 / TRXD1 ERRN[1] Star-transmit output[2] input[3] error flag error flag bus set reset activity Star-receive output Star-idle input Star-locked input Star-standby input Star-sleep input [1] LOW RXEN HIGH LOW RXD HIGH LOW HIGH bus idle bus DATA_0 bus DATA_1 or idle error flag error flag wake flag wake flag wake flag wake flag reset set[4] reset set[4] reset set[4] Transmitter INH1 INH2 enabled HIGH HIGH float float disabled Pin ERRN provides a serial interface for retrieving diagnostic information. [2] TRXD lines switched as output if TXEN activity is the initiator for Star-transmit mode. [3] TRXD lines are switched as input if TRXD activity is the initiator for Star-transmit mode. [4] Valid if VIO and (VBUF or VBAT) are present. Pin BGE must be HIGH in order to enable the transmitter via pin TXEN. If pin BGE is LOW, it is not possible to activate the transmitter via pin TXEN. If pin TXEN is not used (no controller connected to the transceiver), it has to be connected to pin GND in order to prevent TXEN activity detection. In all normal modes pin RXD is connected to the output of the normal mode receiver and therefore represents the data on the bus lines. TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 15 of 49 TJA1080A NXP Semiconductors FlexRay transceiver STAR LOCKED INH1 = HIGH INH2 = HIGH TXEN activity detected for longer than tto(tx-locked) bus activity detected for longer than tto(rx-locked) idle detected on the bus lines and TXEN for longer than tto(locked-idle) STAR TRANSMIT idle detected on TRXD0, TRXD1, TXEN and the bus lines idle detected on TRXD0, TRXD1, TXEN and the bus lines STAR IDLE INH1 = HIGH INH2 = HIGH INH1 = HIGH INH2 = HIGH INH1 = HIGH INH2 = HIGH TRXD0, TRXD1, TXEN activity detected wake flag 1 time in star locked longer than tto(locked-sleep) STAR RECEIVE bus activity detected wake flag 1 or UVVCC signal 0 no acivity on TRXD0, TRXD1, TXEN and the bus lines for longer than tto(idle-sleep) STAR SLEEP STAR STANDBY(1) INH1 = floating INH2 = floating INH1 = HIGH INH2 = HIGH from any mode if UVVCC flag is set regardless PWON flag from star idle, star transmit or star receive if wake flag set and under voltage present on VCC for longer than t > tto(uv)(VCC) 001aae441 (1) At the first battery connection the transceiver will enter the Star-standby mode. Fig 6. State diagram in star configuration TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 16 of 49 TJA1080A NXP Semiconductors FlexRay transceiver star transmit star idle star receive star idle star transmit star idle TRXD0 TRXD1 TXEN TXD TRXDOUT BP BM RXEN RXD 001aae440 TRXDOUT is a virtual signal that indicates the state of the TRXD lines. TRXDOUT HIGH means TRXD lines switched as output. TRXDOUT LOW means TRXD lines switched as input. Fig 7. Timing diagram in star configuration 6.3.1 Star-idle mode This mode is entered if one of the following events occurs: • From Star-receive mode and Star-transmit mode if idle is detected on the bus lines, on pin TXEN and on pins TRXD0 and TRXD1. • If the transceiver is in Star-locked mode and idle is detected on the bus lines and pin TXEN for longer than tto(locked-idle). • If the transceiver is in Star-standby mode and the wake flag is set or no undervoltage is present. • If the transceiver is in Star-sleep mode and the wake flag is set, the transceiver enters Star-idle mode in order to obtain a stable starting point (no glitches on the bus lines etc.). In Star-idle mode the transceiver monitors pins TXEN, TRXD0 and TRXD1 and the bus lines for activity. In this mode the transmitter is disabled. TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 17 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 6.3.2 Star-transmit mode This mode is entered if one of the following events occur: • If the transceiver is in Star-idle mode and activity is detected on pin TXEN. • If the transceiver is in Star-idle mode and activity is detected on pins TRXD0 and TRXD1. In Star-transmit mode the transmitter is enabled and the transceiver can transmit data on the bus lines and on the TRXD lines. It transmits the data received on pins TXD or TRXD0 and TRXD1, depending on where activity is detected: • If activity is detected on the TRXD lines, the transceiver transmits data from pins TRXD0 and TRXD1 to the bus. • If activity is detected on the TXEN, the transceiver transmits data from pin TXD to the bus and to the TRXD lines. 6.3.3 Star-receive mode This mode is entered if the transceiver is in Star-idle mode and activity has been detected on the bus lines. In Star-receive mode the transceiver transmits data received on the bus via the TRXD0 and TRXD1 lines to other transceivers connected to the TRXD lines. The transmitter is always disabled. RXD, which represents the data on the bus lines, is output at TRXD0 and TRXD1. 6.3.4 Star-standby mode This mode is entered if one of the following events occur: • From Star-idle, Star-transmit or Star-receive modes if the wake flag is set and an undervoltage on pin VCC is present for longer than tto(uv)(VCC). • If the PWON flag is set. In Star-standby mode the transceiver has entered a low power mode. In this mode the current consumption is as low as possible to prevent discharging the capacitor at pin VBUF. If pins VIO and VBUF are within their operating range, pins RXD and RXEN will indicate the wake flag. TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 18 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 6.3.5 Star-sleep mode This mode is entered if one of the following events occur: • From any mode if an undervoltage on pin VCC is present for longer than tdet(uv)(VCC). • If the transceiver is in Star-idle mode and no activity is detected on the bus lines and pins TXEN, TRXD0 and TRXD1 for longer than tto(idle-sleep). • If Star-locked mode is active for longer than tto(locked-sleep). In Star-sleep mode the transceiver has entered a low power mode. In this mode the current consumption is as low as possible to prevent the car battery from discharging. The inhibit switches are switched off. In this mode the wake flag wakes the transceiver. A detailed description of the wake-up mechanism is given in Section 6.5. If pins VIO and VBUF are within their operating range, pins RXD and RXEN will indicate the wake flag. 6.3.6 Star-locked mode This mode is entered if one of the following events occur: • If the transceiver is in Star-transmit mode and activity on pin TXEN is detected for longer than tto(tx-locked). • If the transceiver is in Star-receive mode and activity is detected on the bus lines for longer than tto(rx-locked). This mode is a fail-silent mode and in this mode the transmitter is disabled. 6.4 Start-up The TJA1080A initialization is independent of the way the voltage supplies VBAT, VCC and VIO ramp up. A dedicated power-up sequence is not necessary. 6.4.1 Node configuration Node configuration can be selected by applying a voltage lower than 0.3VBUF to pins TRXD0 and TRXD1 during power-on. Node configuration is latched by resetting the PWON flag while the voltage on pins TRXD0 and TRXD1 is lower than 0.3VBUF; see Section 6.7.4 for (re)setting the PWON flag. 6.4.2 Star configuration Star configuration can be selected by applying a voltage higher than 0.7VBUF to pins TRXD0 or TRXD1 during power-on. Star configuration is latched by resetting the PWON flag while one of the voltages on pins TRXD0 or TRXD1 is higher than 0.7VBUF. See Section 6.7.4 for (re)setting the PWON flag. In this case the transceiver goes from Star-standby mode to Star-idle mode. TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 19 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 6.5 Wake-up mechanism 6.5.1 Node configuration In Sleep mode (pins INH1 and INH2 are switched off), the transceiver will enter Standby mode or Go-to-sleep mode (depending on the value at pin EN), if the wake flag is set. Consequently, pins INH1 and INH2 are switched on. If no undervoltage is present on pins VIO and VBAT, the transceiver switches immediately to the mode indicated on pins EN and STBN. In Standby, Go-to-sleep and Sleep modes pins RXD and RXEN are driven LOW if the wake flag is set. 6.5.2 Star configuration In Star-sleep mode (pins INH1 and INH2 are switched off), the transceiver will enter Star-idle mode (pins INH1 and INH2 are switched on) if the wake flag is set. After entering Star-idle mode the transceiver monitors for activity to choose the appropriate mode transition (see Figure 6). 6.5.3 Remote wake-up 6.5.3.1 Bus wake-up via wake-up pattern Bus wake-up is detected if two consecutive DATA_0 of at least tdet(wake)DATA_0 separated by an idle or DATA_1 of at least tdet(wake)idle, followed by an idle or DATA_1 of at least tdet(wake)idle are present on the bus lines within tdet(wake)tot. tdet(wake)tot 0V Vdif −425 mV tdet(wake)Data_0 tdet(wake)idle tdet(wake)Data_0 tdet(wake)idle 001aae442 Fig 8. 6.5.3.2 Bus wake-up timing Bus wake-up via dedicated FlexRay data frame The reception of a dedicated data frame, emulating a valid wake-up pattern, as shown in Figure 9, sets the wake-up flag of the TJA1080A. Due to the Byte Start Sequence (BSS), preceding each byte, the DATA_0 and DATA_1 phases for the wake-up symbol are interrupted every 1 μs. For 10 Mbit/s the maximum interruption time is 130 ns. Such interruptions do not prevent the transceiver from recognizing the wake-up pattern in the payload of a data frame. The wake-up flag will not be set upon reception of an invalid wake-up pattern. TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 20 of 49 TJA1080A NXP Semiconductors FlexRay transceiver Vdif 130 ns wake-up 870 ns 870 ns +1500 0V −1500 770 870 870 ns ns ns 130 130 ns ns 5 μs 5 μs 5 μs 5 μs 015aaa043 Each interruption is 130 ns. The transition time from DATA_0 to DATA_1 and from DATA_1 to DATA_0 is about 20 ns. The TJA1080A wake-up flag will be set with the following pattern: FFh, FFh, FFh, FFh, FFh, 00h, 00h, 00h, 00h, 00h, FFh, FFh, FFh, FFh, FFh, 00h, 00h, 00h, 00h, 00h, FFh, FFh, FFh, FFh, FFh, 00h, 00h, 00h, 00h, 00h, FFh, FFh, FFh, FFh, FFh, FFh Fig 9. Minimum bus pattern for bus wake-up 6.5.4 Local wake-up via pin WAKE If the voltage on pin WAKE is lower than Vth(det)(WAKE) for longer than twake(WAKE) (falling edge on pin WAKE) a local wake-up event on pin WAKE is detected. At the same time, the biasing of this pin is switched to pull-down. If the voltage on pin WAKE is higher than Vth(det)(WAKE) for longer than twake(WAKE), the biasing of this pin is switched to pull-up, and no local wake-up will be detected. pull-up twake(WAKE) pull-down pull-up twake(WAKE) VBAT WAKE 0V RXD and RXEN INH1 and INH2 VBAT 0V 001aae443 Sleep mode: VIO and (VBAT or VCC) still provided. Fig 10. Local wake-up timing via pin WAKE TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 21 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 6.6 Fail silent behavior In order to be fail silent, undervoltage detection and a reset mechanism for the digital state machine is implemented. If an undervoltage is detected on pins VCC, VIO and/or VBAT, the transceiver will enter a low power mode. This ensures a passive and defined behavior of the transmitter and receiver in case of an undervoltage detection. In the region between the minimum operating voltage and the undervoltage detection threshold, the principle function of the transmitter and receiver is maintained. However, in this region parameters (e.g. thresholds and delays of the transmitter and receiver) may deviate from the range specified for the operating range. The digital state machine is supplied by VCC, VIO or VBAT, depending on which voltage is available. Therefore, the digital state machine will be properly supplied as long as the voltage on pin VCC or pin VIO remains above 4.75 V or the voltage on pin VBAT remains above 6.5 V. If the voltage on all pins VCC, VIO and VBAT breaks down, a reset signal will be given to the digital state machine as soon as the internal supply voltage for the digital state machine is not sufficient for proper operation of the state machine. This ensures a passive and defined behavior of the digital state machine in case of an overall supply voltage breakdown. 6.6.1 VBAT undervoltage • Node configuration: If the UVVBAT flag is set the transceiver will enter Sleep mode (pins INH1 and INH2 are switched off) regardless of the voltage present on pins EN and STBN. If the undervoltage recovers the wake flag will be set and the transceiver will enter the mode determined by the voltages on pins EN and STBN. • Star configuration: The TJA1080A in star configuration is able to transmit and receive data as long as VCC and VIO are within their operating ranges, regardless of the undervoltage on VBAT. 6.6.2 VCC undervoltage • Node configuration: If the UVVCC flag is set the transceiver will enter the Standby mode (pin INH2 is switched off) regardless of the voltage present on pins EN and STBN. If the undervoltage recovers or the wake flag is set mode switching via pins EN and STBN is possible. • Star configuration: If the UVVCC flag is set the transceiver will enter the Star-sleep mode. 6.6.3 VIO undervoltage • Node configuration: If the voltage on pin VIO is lower than Vuvd(VIO) (even if the UVVIO flag is reset) pins EN, STBN, TXD and BGE are set LOW (internally) and pin TXEN is set HIGH (internally). If the UVVIO flag is set the transceiver will enter Sleep mode (pins INH1 and INH2 are switched off). If the undervoltage recovers or the wake flag is set, mode switching via pins EN and STBN is possible. TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 22 of 49 TJA1080A NXP Semiconductors FlexRay transceiver • Star configuration: If an undervoltage is present on pin VIO (even if the UVVIO flag is reset) pins EN, STBN, TXD and BGE are set LOW (internally) and pin TXEN is set HIGH (internally). If the UVVIO flag is set, pin INH1 is switched off. If an undervoltage is present on pin VIO and VCC is within the operating range, the TJA1080A will forward the received data on TRXD or bus lines to all other branches. 6.7 Flags 6.7.1 Local wake-up source flag The local wake-up source flag can only be set in a low power mode. When a wake-up event on pin WAKE is detected (see Section 6.5.4) it sets the local wake-up source flag. The local wake-up source flag is reset by entering a low power mode. 6.7.2 Remote wake-up source flag The remote wake-up source flag can only be set in a low power mode if pin VBAT is within its operating range. When a remote wake-up event is detected on the bus lines (see Section 6.5.3) it sets the remote wake-up source flag. The remote wake-up source flag is reset by entering a low power mode. 6.7.3 Wake flag The wake flag is set if one of the following events occurs: • • • • The local or remote wake-up source flag is set (edge sensitive) A positive edge is detected on pin STBN if VIO is present Recovery of the UVVBAT flag (only in node configuration) By recognizing activity on pins TRXD0 and TRXD1 (only in star configuration) In node configuration the wake flag is reset by entering Normal mode, a low power mode or setting one of the undervoltage flags. In star configuration the wake flag is reset by entering a low power mode or by recovery of the UVVCC signal (without trec(uv)(VCC)). 6.7.4 Power-on flag The PWON flag is set if the internal supply voltage for the digital part becomes higher than the lowest value it needs to operate. In node configuration, entering Normal mode resets the PWON flag. In star configuration the PWON flag is reset when the UVVCC signal goes LOW (no undervoltage detected). 6.7.5 Node configuration flag Configuration flag set means node configuration. 6.7.6 Temperature medium flag The temperature medium flag is set if the junction temperature exceeds Tj(warn)(medium) in a normal power mode while pin VBAT is within its operating range. The temperature medium flag is reset when the junction temperature drops below Tj(warn)(medium) in a normal power mode with pin VBAT within its operating range or after a read of the status register in a low power mode while pin VBAT is within its operating range. No action will be taken if this flag is set. TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 23 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 6.7.7 Temperature high flag The temperature high flag is set if the junction temperature exceeds Tj(dis)(high) in a normal power mode while pin VBAT is within its operating range. In node configuration the temperature high flag is reset if a negative edge is applied to pin TXEN while the junction temperature is lower than Tj(dis)(high) in a normal power mode with pin VBAT within its operating range. In star configuration, the temperature high flag is reset by any activity detection (edge) while the junction temperature is lower than Tj(dis)(high) in a normal power mode while pin VBAT is within its operating range. If the temperature high flag is set the transmitter is disabled and pins TRXD0 and TRXD1 are switched off. 6.7.8 TXEN_BGE clamped flag The TXEN_BGE clamped flag is set if pin TXEN is LOW and pin BGE is HIGH for longer than tdetCL(TXEN_BGE). The TXEN_BGE clamped flag is reset if pin TXEN is HIGH or pin BGE is LOW. If the TXEN_BGE flag is set, the transmitter is disabled. 6.7.9 Bus error flag The bus error flag is set if pin TXEN is LOW and pin BGE is HIGH and the data received from the bus lines (pins BP and BM) is different to that received on pin TXD. Additionally in star configuration the bus error flag is also set if the data received on the bus lines is different to that received on pins TRXD0 and TRXD1. The transmission of any valid communication element, including a wake-up pattern, does not lead to bus error indication. The error flag is reset if the data on the bus lines (pins BP and BM) is the same as on pin TXD or if the transmitter is disabled. No action will be taken if the bus error flag is set. 6.7.10 UVVBAT flag The UVVBAT flag is set if the voltage on pin VBAT is lower than Vuvd(VBAT). The UVVBAT flag is reset if the voltage is higher than Vuvd(VBAT) or by setting the wake flag; see Section 6.6.1. 6.7.11 UVVCC flag The UVVCC flag is set if the voltage on pin VCC is lower than Vuvd(VCC) for longer than tdet(uv)(VCC). The flag is reset if the voltage on pin VCC is higher than Vuvd(VCC) for longer than trec(uv)(VCC) or the wake flag is set; see Section 6.6.2. 6.7.12 UVVIO flag The UVVIO flag is set if the voltage on pin VIO is lower than Vuvd(VIO) for longer than tdet(uv)(VIO). The flag is reset if the voltage on pin VIO is higher than Vuvd(VIO) or the wake flag is set; see Section 6.6.3. 6.7.13 Error flag The error flag is set if one of the status bits S4 to S12 is set. The error flag is reset if none of the S4 to S12 status bits are set; see Table 10. TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 24 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 6.8 TRXD collision A TRXD collision is detected when both TRXD lines are LOW for more than the TRXD collision detection time (tdet(col)(TRXD)) in star configuration. 6.9 Status register The status register can be read out on pin ERRN by using pin EN as clock; the status bits are given in Table 10. The timing diagram is illustrated in Figure 11. The status register is accessible if: • UVVIO flag is not set and the voltage on pin VIO is between 4.75 V and 5.25 V • UVVCC flag is not set and the voltage on pin VIO is between 2.2 V and 4.75 V After reading the status register, if no edge is detected on pin EN for longer than tdet(EN), the status bits (S4 to S12) will be cleared if the corresponding flag has been reset. Pin ERRN is LOW if the corresponding status bit is set. Table 10. Status bits Bit number Status bit Description S0 local wake-up source flag is redirected to this bit LOCAL WAKEUP S1 REMOTE WAKEUP remote wake-up source flag is redirected to this bit S2 NODE CONFIG node configuration flag is redirected to this bit S3 PWON status bit set means PWON flag has been set previously S4 BUS ERROR status bit set means bus error flag has been set previously S5 TEMP HIGH status bit set means temperature high flag has been set previously S6 TEMP MEDIUM status bit set means temperature medium flag has been set previously S7 TXEN_BGE CLAMPED status bit set means TXEN_BGE clamped flag has been set previously S8 UVVBAT status bit set means UVVBAT flag has been set previously S9 UVVCC status bit set means UVVCC flag has been set previously S10 UVVIO status bit set means UVVIO flag has been set previously S11 STAR LOCKED status bit is set if Star-locked mode has been entered previously S12 TRXD COLLISION status bit is set if a TRXD collision has been detected previously TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 25 of 49 TJA1080A NXP Semiconductors FlexRay transceiver receive only normal 0.7VIO STBN tdet(EN) 0.7VIO EN TEN td(EN-ERRN) 0.7VIO ERRN 0.3VIO S0 S1 S2 001aag896 Fig 11. Timing diagram for status bits TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 26 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 7. Limiting values Table 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND. Symbol Parameter Conditions Min Max Unit VBAT battery supply voltage no time limit −0.3 +60 V operating range 6.5 60 V VCC supply voltage no time limit −0.3 +5.5 V operating range 4.75 5.25 V no time limit −0.3 +5.5 V operating range 4.75 5.25 V no time limit −0.3 +5.5 V operating range 2.2 5.25 V −0.3 VBAT + 0.3 V −1 - mA −0.3 VBAT + 0.3 V −1 - mA −0.3 VBAT + 0.3 V VBUF supply voltage on pin VBUF VIO supply voltage on pin VIO VINH1 voltage on pin INH1 IO(INH1) output current on pin INH1 VINH2 voltage on pin INH2 IO(INH2) output current on pin INH2 VWAKE voltage on pin WAKE no time limit no time limit Io(WAKE) output current on pin WAKE pin GND not connected −15 - mA VBGE voltage on pin BGE no time limit −0.3 +5.5 V VTXEN voltage on pin TXEN no time limit −0.3 +5.5 V VTXD voltage on pin TXD no time limit −0.3 +5.5 V VERRN voltage on pin ERRN no time limit −0.3 VIO + 0.3 V VRXD voltage on pin RXD no time limit −0.3 VIO + 0.3 V VRXEN voltage on pin RXEN no time limit −0.3 VIO + 0.3 V VEN voltage on pin EN no time limit −0.3 +5.5 V VSTBN voltage on pin STBN no time limit −0.3 +5.5 V VTRXD0 voltage on pin TRXD0 no time limit −0.3 +5.5 V VTRXD1 voltage on pin TRXD1 no time limit −0.3 +5.5 V VBP voltage on pin BP no time limit −60 +60 V VBM voltage on pin BM no time limit Vtrt transient voltage on pins BM and BP −60 +60 V [1] −100 - V [2] - 75 V [3] −150 - V [4] - 100 V −55 +150 °C virtual junction temperature [5] −40 +150 °C electrostatic discharge voltage HBM on pins BP and BM to ground [6] −8.0 +8.0 kV HBM at any other pin [6] −4.0 +4.0 kV MM on all pins [7] −200 +200 V CDM on all pins [8] −1000 +1000 V storage temperature Tstg Tvj VESD [1] According to ISO7637, test pulse 1, class C; verified by an external test house. [2] According to ISO7637, test pulse 2a, class C; verified by an external test house. TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 27 of 49 TJA1080A NXP Semiconductors FlexRay transceiver [3] According to ISO7637, test pulse 3a, class C; verified by an external test house. [4] According to ISO7637, test pulse 3b, class C; verified by an external test house. [5] In accordance with IEC 60747-1. An alternative definition of virtual junction temperature Tvj is: Tvj = Tamb + P × Rth(j-a), where Rth(j-a) is a fixed value to be used for the calculation of Tvj. The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb). [6] HBM: C = 100 pF; R = 1.5 kΩ. [7] MM: C = 200 pF; L = 0.75 μH; R = 10 Ω. [8] CDM: R = 1 Ω. 8. Thermal characteristics Table 12. Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient in free air 126 K/W 9. Static characteristics Table 13. Static characteristics All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = −40 °C to +150 °C; Rbus = 45 Ω; RTRXD = 200 Ω unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit battery supply current low power modes in node configuration; no load on pins INH1 and INH2 - - 55 μA Star-sleep mode - - 55 μA Star-standby mode; no load on pins INH1 and INH2 - - 150 μA normal power modes - - 1 mA 2.75 - 4.5 V low power modes −1 0 +10 μA Normal mode; VBGE = 0 V; VTXEN = VIO; Receive-only mode; Star-idle mode - - 15 mA - - 35 mA Normal mode; VBGE = VIO; VTXEN = 0 V; Rbus = ∞ Ω - - 15 mA Star-transmit mode - - 62 mA Star-receive mode - - 42 mA (VBAT ≥ 5.5 V AND VIO ≥ 4.75 V) OR VBAT ≥ 6.5 V 2.75 3.7 4.5 V Pin VBAT IBAT Vuvd(VBAT) undervoltage detection voltage on pin VBAT Pin VCC ICC supply current Normal mode; VBGE = VIO; VTXEN = 0 V; VBUF open Vuvd(VCC) TJA1080A Product data sheet undervoltage detection voltage on pin VCC [1] All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 28 of 49 TJA1080A NXP Semiconductors FlexRay transceiver Table 13. Static characteristics …continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = −40 °C to +150 °C; Rbus = 45 Ω; RTRXD = 200 Ω unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit supply current on pin VIO low power modes −1 +1 +10 μA Normal and Receive-only modes; VTXD = VIO - - 1000 μA Pin VIO IIO Vuvd(VIO) undervoltage detection voltage on pin VIO 1 1.5 2 V Vuvr(VIO) undervoltage recovery voltage on pin VIO 1 1.6 2.2 V Vuvhys(VIO) undervoltage hysteresis VBAT > 5.5 V voltage on pin VIO 25 - 200 mV supply current on pin VBUF −1 0 +10 μA −40 −20 +1 μA −1 0 +15 μA - - 35 mA Star-transmit mode - - 62 mA Star-receive mode - - 42 mA Normal mode; VBGE = 0 V; VTXEN = VIO; Receive-only mode; Star-idle mode - - 15 mA Pin VBUF IBUF low power modes in node configuration low power modes in star configuration VBUF = 0 V; VCC = 0 V VBUF = 5.25 V Normal mode; VBGE = VIO; VTXEN = 0 V; VBUF = VCC [1] VBUF(on) on-state voltage on pin VBUF VCC switch is switched on; Normal mode; VBGE = VIO; VTXEN = 0 V; VCC > maximum value of Vuvd(VCC) VCC − 0.25 - VCC V VBUF(off) off-state voltage on pin VBUF VCC switch is switched off; low power modes in star configuration; VCC < minimum value of Vuvd(VCC) 4.5 - 5.25 V Pin EN VIH(EN) HIGH-level input voltage on pin EN 0.7VIO - 5.5 V VIL(EN) LOW-level input voltage on pin EN −0.3 - 0.3VIO V IIH(EN) HIGH-level input current VEN = 0.7VIO on pin EN 3 - 11 μA IIL(EN) LOW-level input current VEN = 0 V on pin EN −1 0 +1 μA TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 29 of 49 TJA1080A NXP Semiconductors FlexRay transceiver Table 13. Static characteristics …continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = −40 °C to +150 °C; Rbus = 45 Ω; RTRXD = 200 Ω unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit Pin STBN VIH(STBN) HIGH-level input voltage on pin STBN 0.7VIO - 5.5 V VIL(STBN) LOW-level input voltage on pin STBN −0.3 - 0.3VIO V IIH(STBN) HIGH-level input current VSTBN = 0.7VIO on pin STBN 3 - 11 μA IIL(STBN) LOW-level input current VSTBN = 0 V on pin STBN −1 0 +1 μA VIH(TXEN) HIGH-level input voltage on pin TXEN 0.7VIO - 5.5 V VIL(TXEN) LOW-level input voltage on pin TXEN −0.3 - 0.3VIO V IIH(TXEN) HIGH-level input current VTXEN = VIO on pin TXEN −1 0 +1 μA IIL(TXEN) LOW-level input current VTXEN = 0.3VIO on pin TXEN −15 - −3 μA IL(TXEN) leakage current on pin TXEN −1 0 +1 μA Pin TXEN VTXEN = 5.25 V; VIO = 0 V Pin BGE VIH(BGE) HIGH-level input voltage on pin BGE 0.7VIO - 5.5 V VIL(BGE) LOW-level input voltage on pin BGE −0.3 - 0.3VIO V IIH(BGE) HIGH-level input current VBGE = 0.7VIO on pin BGE 3 - 11 μA IIL(BGE) LOW-level input current VBGE = 0 V on pin BGE −1 0 +1 μA VIH(TXD) HIGH-level input voltage normal power modes on pin TXD 0.7VIO - VIO + 0.3 V VIL(TXD) LOW-level input voltage normal power modes on pin TXD −0.3 - 0.3VIO V IIH(TXD) HIGH-level input current VTXD = VIO on pin TXD 70 230 650 μA IIL(TXD) LOW-level input current normal power modes; on pin TXD VTXD = 0 V −5 0 +5 μA −1 0 +1 μA −1 0 +1 μA - 5 10 pF Pin TXD low power modes ILI(TXD) input leakage current on VTXD = 5.25 V; VIO = 0 V pin TXD Ci(TXD) input capacitance on pin not tested; with respect to all TXD other pins at ground; VTXD = 100 mV; f = 5 MHz TJA1080A Product data sheet [2] All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 30 of 49 TJA1080A NXP Semiconductors FlexRay transceiver Table 13. Static characteristics …continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = −40 °C to +150 °C; Rbus = 45 Ω; RTRXD = 200 Ω unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit IOH(RXD) HIGH-level output current on pin RXD VRXD = VIO − 0.4 V; VIO = VCC −20 - −2 mA IOL(RXD) LOW-level output current on pin RXD VRXD = 0.4 V 2 - 20 mA HIGH-level output current on pin ERRN node configuration; VERRN = VIO − 0.4 V; VIO = VCC −1500 −600 −100 μA star configuration; VERRN = VIO − 0.4 V; VIO = VCC −1 0 +1 μA LOW-level output current on pin ERRN VERRN = 0.4 V 300 700 1500 μA IOH(RXEN) HIGH-level output current on pin RXEN VRXEN = VIO − 0.4 V; VIO = VCC −4 −1.7 −0.5 mA IOL(RXEN) LOW-level output current on pin RXEN VRXEN = 0.4 V 1 3.2 8 mA Pin RXD Pin ERRN IOH(ERRN) IOL(ERRN) Pin RXEN Pins TRXD0 and TRXD1 VIH(TRXD0) HIGH-level input voltage Star-idle and Star-transmit on pin TRXD0 modes 0.7VBUF - VBUF + 0.3 V VIL(TRXD0) LOW-level input voltage Star-idle and Star-transmit on pin TRXD0 modes −0.3 - 0.3VBUF V VOL(TRXD0) LOW-level output voltage on pin TRXD0 −0.3 - +0.8 V VIH(TRXD1) HIGH-level input voltage Star-idle and Star-transmit on pin TRXD1 modes 0.7VBUF - VBUF + 0.3 V VIL(TRXD1) LOW-level input voltage Star-idle and Star-transmit on pin TRXD1 modes −0.3 - 0.3VBUF V VOL(TRXD1) LOW-level output voltage on pin TRXD1 Rpu = 200 Ω −0.3 - +0.8 V idle output voltage on pin BP Normal, Receive-only, Star-idle, Star-transmit and Star-receive modes; VTXEN = VIO 0.4VBUF 0.5VBUF 0.6VBUF V Standby, Go-to-sleep, Sleep, Star-standby and Star-sleep modes −0.1 0 +0.1 V Normal, Receive-only, Star-idle, Star-transmit and Star-receive modes; VTXEN = VIO 0.4VBUF 0.5VBUF 0.6VBUF V Standby, Go-to-sleep, Sleep, Star-standby and Star-sleep modes −0.1 0 +0.1 V Rpu = 200 Ω Pins BP and BM Vo(idle)(BP) Vo(idle)(BM) TJA1080A Product data sheet idle output voltage on pin BM All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 31 of 49 TJA1080A NXP Semiconductors FlexRay transceiver Table 13. Static characteristics …continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = −40 °C to +150 °C; Rbus = 45 Ω; RTRXD = 200 Ω unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit Io(idle)BP idle output current on pin BP −60 V ≤ VBP ≤ +60 V; with respect to GND and VBAT −7.5 - +7.5 mA Io(idle)BM idle output current on pin BM −60 V ≤ VBM ≤ +60 V; with respect to GND and VBAT −7.5 - +7.5 mA Vo(idle)(dif) differential idle output voltage −25 0 +25 mV VOH(dif) differential HIGH-level output voltage 40 Ω ≤ Rbus ≤ 55 Ω; VCC = VBUF = 5 V; Cbus = 100 pF 600 850 1500 mV VOL(dif) differential LOW-level output voltage 40 Ω ≤ Rbus ≤ 55 Ω; VCC = VBUF = 5 V; Cbus = 100 pF −1500 −850 −600 mV VIH(dif) differential HIGH-level input voltage normal power modes; −10 V ≤ VBP ≤ +15 V; −10 V ≤ VBM ≤ +15 V 150 210 300 mV VIL(dif) differential LOW-level input voltage normal power modes; −10 V ≤ VBP ≤ +15 V; −10 V ≤ VBM ≤ +15 V −300 −210 −150 mV low power modes; −10 V ≤ VBP ≤ +15 V; −10 V ≤ VBM ≤ +15 V −400 −210 −125 mV |ΔVi(dif)(H-L)| differential input volt. normal power modes diff. betw. HIGH- and (VBP + VBM) / 2 = 2.5 V LOW-levels (abs. value) - - 10 % |Vi(dif)det(act)| activity detection normal power modes differential input voltage (absolute value) 150 210 300 mV |IO(sc)| short-circuit output on pin BP; 0 V ≤ VBP ≤ 60 V current (absolute value) on pin BM; 0 V ≤ V ≤ 60 V BM - - 35 mA - - 35 mA on pins BP and BM; VBP = VBM; 0 V ≤ VBP ≤ 60 V; 0 V ≤ VBM ≤ 60 V - - 35 mA Ri(BP) input resistance on pin BP idle level; Rbus = ∞ Ω 10 18.5 40 kΩ Ri(BM) input resistance on pin BM idle level; Rbus = ∞ Ω 10 18.5 40 kΩ Ri(dif)(BP-BM) differential input resistance between pin BP and pin BM idle level; Rbus = ∞ Ω 20 37 80 kΩ ILI(BP) input leakage current on VBP = 5 V; pin BP VBAT = VCC = VIO = 0 V −10 0 +10 μA ILI(BM) input leakage current on VBM = 5 V; pin BM VBAT = VCC = VIO = 0 V −10 0 +10 μA Vcm(bus)(DATA_0) DATA_0 bus common-mode voltage 0.4VBUF 0.5VBUF 0.6VBUF V TJA1080A Product data sheet Rbus = 45 Ω All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 32 of 49 TJA1080A NXP Semiconductors FlexRay transceiver Table 13. Static characteristics …continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = −40 °C to +150 °C; Rbus = 45 Ω; RTRXD = 200 Ω unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit Vcm(bus)(DATA_1) DATA_1 bus common-mode voltage Rbus = 45 Ω 0.4VBUF 0.5VBUF 0.6VBUF V ΔVcm(bus) bus common-mode voltage difference Rbus = 45 Ω −25 0 +25 mV Ci(BP) input capacitance on pin not tested; with respect to all BP other pins at ground; VBP = 100 mV; f = 5 MHz [2] - 8 15 pF Ci(BM) input capacitance on pin not tested; with respect to all BM other pins at ground; VBM = 100 mV; f = 5 MHz [2] - 8 15 pF Ci(dif)(BP-BM) differential input capacitance between pin BP and pin BM not tested; with respect to all other pins at ground; V(BM-BP) = 100 mV; f = 5 MHz [2] - 2 5 pF VOH(INH1) HIGH-level output voltage on pin INH1 IINH1 = −0.2 mA VBAT − 0.8 VBAT − 0.3 VBAT − 0.1 V IL(INH1) leakage current on pin INH1 Sleep mode −5 0 +5 μA IOL(INH1) LOW-level output current on pin INH1 VINH1 = 0 V −15 −5 −1 mA VOH(INH2) HIGH-level output voltage on pin INH2 IINH2 = −0.2 mA VBAT − 0.8 VBAT − 0.3 VBAT − 0.1 V IL(INH2) leakage current on pin INH2 Sleep mode −5 0 +5 μA IOL(INH2) LOW-level output current on pin INH2 VINH2 = 0 V −15 −5 −1 mA Vth(det)(WAKE) detection threshold voltage on pin WAKE low power mode 2.5 - 4.5 V IIL(WAKE) LOW-level input current VWAKE = 2.4 V for on pin WAKE t > twake(WAKE) 3 - 11 μA IIH(WAKE) HIGH-level input current VWAKE = 4.6 V for on pin WAKE t > twake(WAKE) −11 - −3 μA Pin INH1 Pin INH2 Pin WAKE Temperature protection Tj(warn)(medium) medium warning junction temperature VBAT > 5.5 V 155 165 175 °C Tj(dis)(high) high disable junction temperature VBAT > 5.5 V 180 190 200 °C TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 33 of 49 TJA1080A NXP Semiconductors FlexRay transceiver Table 13. Static characteristics …continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = −40 °C to +150 °C; Rbus = 45 Ω; RTRXD = 200 Ω unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit Power-on reset Vth(det)POR power-on reset detection threshold voltage 3.0 - 3.4 V Vth(rec)POR power-on reset recovery threshold voltage 3.1 - 3.5 V Vhys(POR) power-on reset hysteresis voltage 100 - 200 mV [1] Current flows from VCC to VBUF. This means that the maximum sum current ICC + IBUF is 35 mA. [2] These values are based on measurements taken on several samples (less than 10 pieces). These measurements have taken place in the laboratory and have been done at Tamb = 25 °C and Tamb = 125 °C. No characterization has been done for these parameters. No industrial test will be performed on production products. 10. Dynamic characteristics Table 14. Dynamic characteristics All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = −40 °C to +150 °C; Rbus = 45 Ω; RTRXD = 200 Ω unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit - - 50 ns - - 50 ns - - 4 ns DATA_0 - - 50 ns DATA_1 - - 50 ns - - 5 ns DATA_0 - - 50 ns DATA_1 - - 50 ns - - 5 ns DATA_0 - - 50 ns DATA_1 - - 50 ns Pins BP and BM td(TXD-bus) delay time from TXD to bus Normal or Star-transmit mode [1] DATA_0 DATA_1 Δtd(TXD-bus) delay time difference from TXD to bus Normal or Star-transmit mode; between DATA_0 and DATA_1 [1] td(TRXD-bus) delay time from TRXD to bus Star-transmit mode [2] Δtd(TRXD-bus) delay time difference from TRXD Star-transmit mode; between to bus DATA_0 and DATA_1 td(bus-RXD) delay time from bus to RXD Normal or Star-transmit mode; CRXD = 15 pF; see Figure 13 Δtd(bus-RXD) delay time difference from bus to Normal or Star-transmit mode; RXD CRXD = 15 pF; between DATA_0 and DATA_1; see Figure 13 td(bus-TRXD) delay time from bus to TRXD TJA1080A Product data sheet [2][3] Star-receive mode; see Figure 13 All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 34 of 49 TJA1080A NXP Semiconductors FlexRay transceiver Table 14. Dynamic characteristics …continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = −40 °C to +150 °C; Rbus = 45 Ω; RTRXD = 200 Ω unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit - - 5 ns Δtd(bus-TRXD) delay time difference from bus to Star-receive mode; between TRXD DATA_0 and DATA_1; see Figure 13 td(TXEN-busidle) delay time from TXEN to bus idle Normal mode - 46 100 ns td(TXEN-busact) delay time from TXEN to bus active Normal mode - 39 75 ns td(BGE-busidle) delay time from BGE to bus idle Normal mode - 47 100 ns td(BGE-busact) delay time from BGE to bus active Normal mode - 40 75 ns td(bus)(idle-act) bus delay time from idle to active Normal mode - 7 30 ns td(bus)(act-idle) bus delay time from active to idle Normal mode - 7 30 ns tr(dif)(bus) bus differential rise time 10 % to 90 % Rbus = 45 Ω; Cbus = 100 pF 5 17 25 ns tf(dif)(bus) bus differential fall time 90 % to 10 % Rbus = 45 Ω Cbus = 100 pF 5 17 25 ns [3] WAKE symbol detection tdet(wake)DATA_0 DATA_0 wake-up detection time tdet(wake)idle idle wake-up detection time tdet(wake)tot total wake-up detection time Standby, Sleep, Star-standby or Star-sleep modes 10 V ≤ VBP ≤ +15 V 10 V ≤ VBM ≤ +15 V 1 - 4 μs 1 - 4 μs 50 - 115 μs Undervoltage tdet(uv)(VCC) undervoltage detection time on pin VCC 100 - 670 ms trec(uv)(VCC) undervoltage recovery time on pin VCC 1 - 5.2 ms tdet(uv)(VIO) undervoltage detection time on pin VIO 100 - 670 ms tto(uv)(VCC) undervoltage time-out time on pin VCC for entering Standby mode 432 - 900 μs tdet(uv)(VBAT) undervoltage detection time on pin VBAT - - 1 ms star configuration; wake flag is set Activity detection tdet(act)(TXEN) activity detection time on pin TXEN star configuration 100 - 200 ns tdet(act)(TRXD) activity detection time on pin TRXD star configuration 100 - 200 ns tdet(act)(bus) activity detection time on bus pins Vdif: 0 mV → 400 mV 100 - 250 ns tdet(idle)(TXEN) idle detection time on pin TXEN star configuration 100 - 200 ns tdet(idle)(TRXD) idle detection time on pin TRXD star configuration 50 - 100 ns tdet(idle)(bus) idle detection time on bus pins Vdif: 400 mV → 0 mV 100 - 250 ns TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 35 of 49 TJA1080A NXP Semiconductors FlexRay transceiver Table 14. Dynamic characteristics …continued All parameters are guaranteed for VBAT = 6.5 V to 60 V; VCC = 4.75 V to 5.25 V; VBUF = 4.75 V to 5.25 V; VIO = 2.2 V to 5.25 V; Tvj = −40 °C to +150 °C; Rbus = 45 Ω; RTRXD = 200 Ω unless otherwise specified. All voltages are defined with respect to ground; positive currents flow into the IC. Symbol Parameter Conditions Min Typ Max Unit Star modes tto(idle-sleep) idle to sleep time-out time 640 - 2660 ms tto(tx-locked) transmit to locked time-out time 2600 - 10400 μs tto(rx-locked) receive to locked time-out time 2600 - 10400 μs tto(locked-sleep) locked to sleep time-out time 64 - 333 ms tto(locked-idle) locked to idle time-out time 1.4 - 5.1 μs Node modes td(STBN-RXD) STBN to RXD delay time STBN HIGH to RXD HIGH; wake flag set - - 2 μs td(STBN-INH2) STBN to INH2 delay time STBN LOW to INH2 floating; Normal mode - - 12 μs th(gotosleep) go-to-sleep hold time 20 35 50 μs Status register tdet(EN) detection time on pin EN for mode control 20 - 80 μs TEN time period on pin EN for reading status bits 4 - 20 μs td(EN-ERRN) delay time from EN to ERRN for reading status bits - - 2 μs wake-up time on pin WAKE low power mode; falling edge on pin WAKE; 6.5 V ≤ VBAT ≤ 27 V 5 28 100 μs low power mode; falling edge on pin WAKE; 27 V < VBAT ≤ 60 V 25 75 175 μs 2600 - 10400 μs 20 - - ns WAKE twake(WAKE) Miscellaneous tdetCL(TXEN_BGE) TXEN_BGE clamp detection time tdet(col)(TRXD) TRXD collision detection time TRXD0 and TRXD1 [1] Rise and fall time (10 % to 90 %) of tr(TXD) and tf(TXD) = 5 ns ± 1ns. [2] Rise and fall time (10 % to 90 %) of tr(TRXD) and tf(TRXD) = 5 ns ± 1ns. [3] The worst case asymmetry from one branch to another is the sum of the delay difference from TRXD0 and TRXD1 to DATA_0 and DATA_1 plus the delay difference from DATA_0 and DATA_1 to TRXD0 and TRXD1. TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 36 of 49 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx td(TXEN-busact) NXP Semiconductors TJA1080A Product data sheet td(TXD-bus) td(TXD-bus) td(BGE-busact) td(TXEN-busidle) td(BGE-busidle) 0.7VIO TXD 0.3VIO 0.7VIO TXEN 0.3VIO 0.7VIO BGE 0.3VIO Rev. 5 — 24 February 2011 All information provided in this document is subject to legal disclaimers. BP and BM 90 % +300 mV 0V −300 mV −150 mV −300 mV −150 mV −300 mV 10 % 0.7VIO RXEN 0.3VIO 0.7VIO RXD 0.3VIO td(bus-RXD) td(bus-RXD) td(bus-RXD) + td(bus-RXD) + tdet(idle)(bus) tdet(act)(bus) td(bus-RXD) + td(bus-RXD) + tdet(idle)(bus) tdet(act)(bus) tr(dif)(bus) tf(dif)(bus) 015aaa143 Fig 12. Detailed timing diagram in node configuration TJA1080A FlexRay transceiver 37 of 49 © NXP B.V. 2011. All rights reserved. TJA1080A NXP Semiconductors FlexRay transceiver Vdif (mV) 22.5 ns 22.5 ns 400 300 37.5 ns −300 −400 60 ns td(bus-RXD) RXD Vdif (mV) td(bus-RXD) 22.5 ns 22.5 ns 400 300 37.5 ns −300 −400 60 ns td(bus-RXD) RXD td(bus-RXD) 015aaa044 Vdif is the receiver test signal. Fig 13. Receiver test signal TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 38 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 11. Test information +12 V +5 V 100 nF 10 μF 4 VIO 19 VCC 22 μF 14 20 VBAT VBUF BP 18 Rbus TJA1080A BM RXD Cbus 17 7 15 pF 015aaa053 Fig 14. Test circuit for dynamic characteristics ISO 7637 G 12 V or 42 V +5 V 100 nF 10 μF 4 VIO 19 VCC 10 μF 14 20 VBAT VBUF BP 1 nF 18 ISO 7637 TJA1080A Rbus BM Cbus G 17 1 nF 015aaa054 The waveforms of the applied transients are in accordance with ISO 7637, test pulses 1, 2, 3a and 3b. Test conditions: Normal mode: bus idle Normal mode: bus active; TXD at 5 MHz and TXEN at 1 kHz Fig 15. Test circuit for automotive transients TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 39 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 12. Package outline SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm D SOT339-1 E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 7.4 7.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.9 0.5 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 16. Package outline SOT339-1 (SSOP20) TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 40 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 41 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 17) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 15 and 16 Table 15. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 16. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 17. TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 42 of 49 TJA1080A NXP Semiconductors FlexRay transceiver temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 17. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 43 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 14. Appendix 14.1 EPL 3.0.1 requirements implemented in the TJA1080A Table 17. EPL 3.0.1 requirements implemented EPL 3.0.1 parameter Description - wake-up via dedicated data frames RDCLoad transmitter output voltage defined for DC bus load of 40 Ω to 55 Ω/100 pF dBDTx10, dBDTx01 transmitter delay: ≤ 75 ns uData0_LP receiver thresholds for detecting DATA_0 in low-power modes: −400 mV (min) / −100 mV (max) dBDRxai idle reaction time: 50 ns to 275 ns dBDActivityDetection activity detection time 100 ns to 250 ns dBDRxia activity reaction time: 100 ns to 325 ns uData1 − |uData0| receiver threshold mismatch: ≤ 30 mV dBDRx10, dBDRx01 receiver delay: ≤ 75 ns dBusRx0BD, dBusRx1BD minimum bit time: 70 ns C_StarTxD, C_BDTxD maximum input capacitance on pin TXD: 10 pF - BD_Off mode defined short-circuit currents: iBPBMShortMax,iBMBPShortMax BP shorted to BM: < 60 mA; no time limit iBPGNDShortMax,iBMGNDShortMax BP/BM shorted to ground: < 60 mA; no time limit iBP-5ShortMax,iBM-5ShortMax BP/BM shorted to −5 V: < 60 mA; no time limit iBPBAT48ShortMax,iBMBAT27ShortMax BP/BM shorted to 27 V: < 60 mA; no time limit iBPBAT48ShortMax,iBMBAT27ShortMax BP/BM shorted to 48 V: < 72 mA; no time limit iBPBAT60ShortMax,iBMBAT60ShortMax BP/BM shorted to 60 V: < 90 mA; for 400 ms (max) dBDRVCC VCC undervoltage recovery time: 10 ms (max) uINH1Not_Sleep voltage drop from VBAT to INH: ≤ 1 V @ 200 μA and VBAT ≥ 5.5 V iINH1Leak leakage current, when INH is floating: ≤ 10 μA - qualification according to AEC-Q100 temperature classes uESDExt 6 kV ESD (min) on pins BP and BM according to HBM (100 pF/1500 Ω) uESDInt 2 kV ESD (min) on all other pins according to HBM (100 pF/1500 Ω) TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 44 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 15. Abbreviations Table 18. Abbreviations Abbreviation Description BSS Byte Start Sequence CAN Controller Area Network CDM Charged Device Model EMC ElectroMagnetic Compatibility EME ElectroMagnetic Emission EMI ElectroMagnetic Immunity ESD ElectroStatic Discharge FES Frame End Sequence HBM Human Body Model MM Machine Model PWON Power-on TSS Transmission Start Sequence 16. References TJA1080A Product data sheet [1] EPL — FlexRay Communications System Electrical Physical Layer Specification Version 2.1 Rev. A, FlexRay Consortium, Dec. 2005 [2] EPL — FlexRay Communications System Electrical Physical Layer Specification Version 3.0.1, FlexRay Consortium [3] PS54 — Product specification: TJA1054; Fault-tolerant CAN transceiver, www.nxp.com [4] PS41 — Product specification: TJA1041; High speed CAN transceiver, www.nxp.com [5] DS80 — Product data sheet: TJA1080; FlexRay transceiver, www.nxp.com All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 45 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 17. Revision history Table 19. Revision history Document ID Release date Data sheet status Change notice Supersedes TJA1080A v.5 20110224 Product data sheet - TJA1080A v.4 Modifications: • • • • • • • • • • Added FlexRay logo Product name changed to TJA1080A Section 1, Section 2, Section 14, Section 16: text revised Table 1: type number changed Table 11, Table 13, Table 14: parameter values/conditions/description/table notes revised Table 17: parameter description revised - uESDExt Figure 1, Figure 2, Figure 9, Figure 12, Figure 14, Figure 15: amended Section 14 removed; replaced with Section 14 “Appendix” Ref. 2: added Section 18 “Legal information”: updated TJA1080A v.4 20090219 Product data sheet - TJA1080A v.3 TJA1080A v.3 20090115 Preliminary data sheet - TJA1080A v.2 TJA1080A v.2 20080826 Preliminary data sheet - TJA1080A v.1 TJA1080A v.1 20071029 Objective data sheet - - TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 46 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be TJA1080A Product data sheet suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 47 of 49 TJA1080A NXP Semiconductors FlexRay transceiver Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 18.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18.4 Licenses NXP ICs with FlexRay functionality This NXP product contains functionality that is compliant with the FlexRay specifications. These specifications and the material contained in them, as released by the FlexRay Consortium, are for the purpose of information only. The FlexRay Consortium and the companies that have contributed to the specifications shall not be liable for any use of the specifications. The material contained in these specifications is protected by copyright and other types of Intellectual Property Rights. The commercial exploitation of the material contained in the specifications requires a license to such Intellectual Property Rights. These specifications may be utilized or reproduced without any modification, in any form or by any means, for informational purposes only. For any other purpose, no part of the specifications may be utilized or reproduced, in any form or by any means, without permission in writing from the publisher. The FlexRay specifications have been developed for automotive applications only. They have neither been developed nor tested for non-automotive applications. The word FlexRay and the FlexRay logo are registered trademarks. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] TJA1080A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 24 February 2011 © NXP B.V. 2011. All rights reserved. 48 of 49 TJA1080A NXP Semiconductors FlexRay transceiver 20. Contents 1 2 2.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Optimized for time triggered communication systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Low power management . . . . . . . . . . . . . . . . . 2 2.3 Diagnosis (detection and signalling) . . . . . . . . . 2 2.4 Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.5 Functional classes according to FlexRay electrical physical layer specification (see Ref. 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 6 6.1 Operating configurations . . . . . . . . . . . . . . . . . 6 6.1.1 Node configuration . . . . . . . . . . . . . . . . . . . . . . 6 6.1.2 Star configuration . . . . . . . . . . . . . . . . . . . . . . . 6 6.1.3 Bus activity and idle detection . . . . . . . . . . . . . 7 6.2 Operating modes in node configuration . . . . . . 7 6.2.1 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2.2 Receive-only mode . . . . . . . . . . . . . . . . . . . . . 14 6.2.3 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2.4 Go-to-sleep mode . . . . . . . . . . . . . . . . . . . . . . 14 6.2.5 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 Operating modes in star configuration . . . . . . 15 6.3.1 Star-idle mode. . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3.2 Star-transmit mode . . . . . . . . . . . . . . . . . . . . . 18 6.3.3 Star-receive mode. . . . . . . . . . . . . . . . . . . . . . 18 6.3.4 Star-standby mode . . . . . . . . . . . . . . . . . . . . . 18 6.3.5 Star-sleep mode . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.6 Star-locked mode . . . . . . . . . . . . . . . . . . . . . . 19 6.4 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4.1 Node configuration . . . . . . . . . . . . . . . . . . . . . 19 6.4.2 Star configuration . . . . . . . . . . . . . . . . . . . . . . 19 6.5 Wake-up mechanism . . . . . . . . . . . . . . . . . . . 20 6.5.1 Node configuration . . . . . . . . . . . . . . . . . . . . . 20 6.5.2 Star configuration . . . . . . . . . . . . . . . . . . . . . . 20 6.5.3 Remote wake-up . . . . . . . . . . . . . . . . . . . . . . 20 6.5.3.1 Bus wake-up via wake-up pattern. . . . . . . . . . 20 6.5.3.2 Bus wake-up via dedicated FlexRay data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.5.4 Local wake-up via pin WAKE . . . . . . . . . . . . . 21 6.6 Fail silent behavior . . . . . . . . . . . . . . . . . . . . . 22 6.6.1 VBAT undervoltage . . . . . . . . . . . . . . . . . . . . . 22 6.6.2 VCC undervoltage . . . . . . . . . . . . . . . . . . . . . . 22 6.6.3 6.7 6.7.1 6.7.2 6.7.3 6.7.4 6.7.5 6.7.6 6.7.7 6.7.8 6.7.9 6.7.10 6.7.11 6.7.12 6.7.13 6.8 6.9 7 8 9 10 11 12 13 13.1 13.2 13.3 13.4 14 14.1 15 16 17 18 18.1 18.2 18.3 18.4 18.5 19 20 VIO undervoltage . . . . . . . . . . . . . . . . . . . . . . Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Local wake-up source flag . . . . . . . . . . . . . . . Remote wake-up source flag . . . . . . . . . . . . . Wake flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-on flag. . . . . . . . . . . . . . . . . . . . . . . . . Node configuration flag . . . . . . . . . . . . . . . . . Temperature medium flag . . . . . . . . . . . . . . . Temperature high flag . . . . . . . . . . . . . . . . . . TXEN_BGE clamped flag . . . . . . . . . . . . . . . Bus error flag . . . . . . . . . . . . . . . . . . . . . . . . . UVVBAT flag . . . . . . . . . . . . . . . . . . . . . . . . . . UVVCC flag . . . . . . . . . . . . . . . . . . . . . . . . . . . UVVIO flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . Error flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRXD collision . . . . . . . . . . . . . . . . . . . . . . . . Status register . . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics. . . . . . . . . . . . . . . . . Test information . . . . . . . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EPL 3.0.1 requirements implemented in the TJA1080A . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 23 23 23 23 23 23 23 24 24 24 24 24 24 24 25 25 27 28 28 34 39 40 41 41 41 41 42 44 44 45 45 46 47 47 47 47 48 48 48 49 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 24 February 2011 Document identifier: TJA1080A