ATMEL AT93C86-10SI-2.7

Features
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
• User Selectable Internal Organization
– 16K: 2048 x 8 or 1024 x 16
3-wire Serial Interface
Sequential Read Operation
Schmitt Trigger, Filtered Inputs for Noise Suppression
2 MHz Clock Rate (5V) Compatibility
Self-timed Write Cycle (10 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Automotive Grade, Extended Temperature and Lead-Free Devices Available
• 8-lead PDIP, 8-lead JEDEC SOIC, and 8-lead TSSOP Packages
•
•
•
•
•
•
3-wire Serial
EEPROM
16K (2048 x 8 or 1024 x 16)
Description
The AT93C86 provides 16384 bits of serial electrically erasable programmable read
only memory (EEPROM) organized as 1024 words of 16 bits each when the ORG Pin
is connected to V CC and 2048 words of 8 bits each when it is tied to ground. The
device is optimized for use in many industrial and commercial applications where low
power and low voltage operations are essential. The AT93C86 is available in space
saving 8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP packages.
AT93C86
The AT93C86 is enabled through the Chip Select pin (CS), and accessed via a 3-wire
serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK).
Pin Configurations
Pin Name
Function
CS
Chip Select
SK
Serial Data Clock
DI
Serial Data Input
DO
Serial Data Output
GND
Ground
VCC
Power Supply
ORG
Internal Organization
DC
Don’t Connect
8-lead PDIP
1
2
3
4
CS
SK
DI
DO
VCC
DC
ORG
GND
8
7
6
5
8-lead SOIC
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
DC
ORG
GND
8-lead TSSOP
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
DC
ORG
GND
Rev. 1237E–SEEPR–01/03
1
Upon receiving a READ instruction at DI, the address is decoded and the data is clocked out serially on the data output pin
DO. The WRITE cycle is completely self-timed and no separate ERASE cycle is required before WRITE. The WRITE cycle
is only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is brought “high” following the initiation of
a WRITE cycle, the DO pin outputs the READY/BUSY status of the part. The AT93C86 is available in a 2.7V to 5.5V
version.
Absolute Maximum Ratings*
*NOTICE:
Operating Temperature.................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
DC Output Current........................................................ 5.0 mA
Block Diagram
Vcc
GND
MEMORY ARRAY
ORG
2048 x 8
OR
1024 x 16
ADDRESS
DECODER
DATA
REGISTER
OUTPUT
BUFFER
DI
Note:
2
CS
MODE
DECODE
LOGIC
SK
CLOCK
GENERATOR
DO
1. When the ORG pin is connected to Vcc, the x 16 organization is selected. When it is connected to ground, the x 8 organization is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the
internal 1 Meg ohm pullup, then the x 16 organization is selected. This feature is not available on the 1.8V devices.
AT93C86
1237E–SEEPR–01/03
AT93C86
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Symbol
Test Conditions
COUT
CIN
Note:
Max
Units
Conditions
Output Capacitance (DO)
5
pF
VOUT = 0V
Input Capacitance (CS, SK, DI)
5
pF
VIN = 0V
1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +2.7V to +5.5V,
TAE = -40°C to +125°C, VCC = +2.7V to +5.5V (unless otherwise noted).
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Supply Voltage
ICC
Supply Current
ISB1
Standby Current
ISB2
IIL
Test Condition
Min
Typ
Max
Unit
2.7
5.5
V
4.5
5.5
V
READ at 1.0 MHz
0.5
2.0
mA
WRITE at 1.0 MHz
0.5
2.0
mA
VCC = 2.7V
CS = 0V
6.0
10.0
µA
Standby Current
VCC = 5.0V
CS = 0V
17
30
µA
Input Leakage
VIN = 0V to VCC
0.1
1.0
µA
Output Leakage
VIN = 0V to VCC
0.1
1.0
µA
VIL1
VIH1(1)
Input Low Voltage
Input High Voltage
4.5V ≤ VCC ≤ 5.5V
-0.6
VCC x 0.7
VCC x 0.3
VCC + 1
V
VIL2 (1)
VIH2(1)
Input Low Voltage
Input High Voltage
VCC ≤ 2.7V
-0.6
VCC x 0.7
VCC x 0.3
VCC + 1
V
VOL1
VOH1
Output Low Voltage
Output High Voltage
4.5V ≤ VCC ≤ 5.5V
0.4
V
VOL2
VOH2
Output Low Voltage
Output High Voltage
VCC ≤ 2.7V
IOL
(1)
Note:
VCC = 5.0V
IOL = 2.1 mA
IOH = -0.4 mA
2.4
IOL = 0.15 mA
IOH = -100 µA
V
0.2
VCC - 0.2
V
V
1. VIL min and VIH max are reference only and are not tested.
3
1237E–SEEPR–01/03
AC Characteristics
Applicable over recommended operating range from TAI = -40°C to + 85°C, TAE = -40°C to + 125°C,VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Test Condition
fSK
SK Clock
Frequency
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
0
0
tSKH
SK High Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
ns
tSKL
SK Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
ns
tCS
Minimum CS
Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
ns
tCSS
CS Setup Time
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
50
50
ns
tDIS
DI Setup Time
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
100
ns
tCSH
CS Hold Time
Relative to SK
0
ns
tDIH
DI Hold Time
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
100
ns
tPD1
Output Delay to ‘1’
AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
ns
tPD0
Output Delay to ‘0’
AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
ns
tSV
CS to Status Valid
AC Test
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
ns
tDF
CS to DO in High
Impedance
AC Test
CS = VIL
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
100
ns
10
ms
tWP
Write Cycle Time
Endurance
Note:
4
(1)
Min
4.5V ≤ VCC ≤ 5.5V
5.0V, 25°C, Page Mode
Typ
4
1M
Max
Units
2
1
MHz
ms
Write Cycles
1. This parameter is characterized and is not 100% tested.
AT93C86
1237E–SEEPR–01/03
AT93C86
Instruction Set for the AT93C86
Address
Instruction
Data
SB
Op Code
x8
x 16
READ
1
10
A10 - A0
A9 - A0
Reads data stored in memory,
at specified address.
EWEN
1
00
11XXXXXXXX
11XXXXXXXX
Write enable must precede all
programming modes.
ERASE
1
11
A10 - A0
A9 - A0
WRITE
1
01
A10 - A0
A9 - A0
ERAL
1
00
10XXXXXXXX
10XXXXXXXX
WRAL
1
00
01XXXXXXXX
01XXXXXXXX
EWDS
1
00
00XXXXXXXX
00XXXXXXXX
Functional
Description
x8
x 16
Comments
Erases memory location An - A0.
D7 - D0
D15 - D0
Writes memory location An - A0.
Erases all memory locations.
Valid only at VCC = 4.5V to 5.5V.
D7 - D0
D15 - D0
Writes all memory locations.
Valid when VCC = 4.5V to 5.5V and
Disable Register cleared.
Disables all programming instructions.
The AT93C86 is accessed via a simple and versatile 3-wire serial communication interface. Device operation is controlled by seven instructions issued by the host processor.
A valid instruction starts with a rising edge of CS and consists of a Start Bit (logic
“1”) followed by the appropriate Op Code and the desired memory Address location.
READ (READ): The Read (READ) instruction contains the Address code for the memory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output string.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable
(EWEN) instruction must be executed first before any programming instructions can be
carried out. Please note that once in the Erase/Write Enable state, programming
remains enabled until an Erase/Write Disable (EWDS) instruction is executed or VCC
power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
ERASE instruction and address are decoded. The DO pin outputs the READY/BUSY
status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS).
A logic “1” at pin DO indicates that the selected memory location has been erased, and
the part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be
written into the specified memory location. The self-timed programming cycle, tWP, starts
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
READY/BUSY status of the part if CS is brought high after being kept low for a minimum
of 250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic
“1” indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions. A
READY/BUSY status cannot be obtained if the CS is brought high after the end of
the self-timed programming cycle, tWP.
5
1237E–SEEPR–01/03
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic “1” state and is primarily used for testing purposes. The DO pin
outputs the READY/BUSY status of the part if CS is brought high after being kept low for
a minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin outputs the READY/BUSY
status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS).
The WRAL instruction is valid only at VCC = 5.0V ± 10%.
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the READ instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
6
AT93C86
1237E–SEEPR–01/03
AT93C86
Timing Diagrams
Synchronous Data Timing
Note:
1. This is the minimum SK period.
Organization Key for Timing Diagrams
AT93C86 (16K)
I/O
x8
x 16
AN
A10
A9
DN
D7
D15
7
1237E–SEEPR–01/03
READ Timing
tCS
High Impedance
EWEN Timing
tCS
CS
SK
DI
1
0
0
1
1
...
EWDS Timing
tCS
CS
SK
DI
8
1
0
0
0
0
...
AT93C86
1237E–SEEPR–01/03
AT93C86
WRITE Timing
tCS
CS
SK
DI
DO
1
0
1
AN
...
A0
DN
...
D0
HIGH IMPEDANCE
BUSY
READY
tWP
WRAL Timing(1)
tCS
CS
SK
DI
DO
1
0
0
0
1
...
DN
...
D0
BUSY
HIGH IMPEDANCE
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
9
1237E–SEEPR–01/03
ERASE Timing
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
1
1
1
AN AN-1 AN-2
...
A0
tDF
tSV
HIGH IMPEDANCE
DO
HIGH IMPEDANCE
BUSY
READY
tWP
ERAL Timing(1)
tCS
CS
CHECK
STATUS
STANDBY
tSV
tDF
SK
DI
DO
1
0
0
1
0
BUSY
HIGH IMPEDANCE
HIGH IMPEDANCE
READY
tWP
Note:
10
1. Valid only at VCC = 4.5V to 5.5V.
AT93C86
1237E–SEEPR–01/03
AT93C86
AT93C86 Ordering Information
Ordering Code
Package
AT93C86-10PI-2.7
AT93C86-10SI-2.7
AT93C86-10TI-2.7
8P3
8S1
8A2
Industrial
(-40°C to 85°C)
AT93C86-10SJ-2.7
8S1
Lead-Free/Industrial Temperature
(-40°C to 85°C)
AT93C86-10SE-2.7
8S1
High Grade/Extended Temperature
(-40°C to 125°C)
Note:
Operation Range
For 2.7V devices used in a 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
-2.7
Low Voltage (2.7V to 5.5V)
11
1237E–SEEPR–01/03
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
D1
A2 A
MIN
NOM
A2
0.115
0.130
0.195
b
0.014
0.018
0.022
5
b2
0.045
0.060
0.070
6
b3
0.030
0.039
0.045
6
c
0.008
0.010
0.014
D
0.355
0.365
0.400
D1
0.005
E
0.300
0.310
0.325
4
E1
0.240
0.250
0.280
3
SYMBOL
A
b2
b3
b
4 PLCS
Side View
L
Notes:
0.210
0.100 BSC
eA
0.300 BSC
0.115
NOTE
2
3
3
e
L
MAX
0.130
4
0.150
2
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
R
12
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO.
REV.
8P3
B
AT93C86
1237E–SEEPR–01/03
AT93C86
8S1 – JEDEC SOIC
3
2
1
H
N
Top View
e
B
A
D
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
A2
C
L
SYMBOL
MIN
NOM
MAX
A
–
–
1.75
B
–
–
0.51
C
–
–
0.25
D
–
–
5.00
E
–
–
4.00
e
E
End View
NOTE
1.27 BSC
H
–
–
6.20
L
–
–
1.27
Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.
10/10/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
REV.
8S1
A
13
1237E–SEEPR–01/03
8A2 – TSSOP
3
2 1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
b
D
MIN
NOM
MAX
NOTE
2.90
3.00
3.10
2, 5
3, 5
E
e
D
A2
6.40 BSC
E1
4.30
4.40
4.50
A
–
–
1.20
A2
0.80
1.00
1.05
b
0.19
–
0.30
e
Side View
L
0.65 BSC
0.45
L1
Notes:
0.60
0.75
1.00 REF
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
5/30/02
R
14
4
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
DRAWING NO.
8A2
REV.
B
AT93C86
1237E–SEEPR–01/03
Atmel Headquarters
Atmel Operations
Corporate Headquarters
Memory
2325 Orchard Parkway
San Jose, CA 95131
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© Atmel Corporation 2003.
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which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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Printed on recycled paper.
1237E–SEEPR–01/03
xM