PCF85162 Universal LCD driver for low multiplex rates Rev. 3 — 16 June 2011 Product data sheet 1. General description The PCF85162 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 32 segments. It can be easily cascaded for larger LCD applications. The PCF85162 is compatible with most microcontrollers and communicates via the two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing, and by display memory switching (static and duplex drive modes). 2. Features and benefits 1. Single chip LCD controller and driver Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing Selectable display bias configuration: static, 1⁄2, or 1⁄3 Internal LCD bias generation with voltage-follower buffers 32 segment drives: Up to sixteen 7-segment numeric characters Up to eight 14-segment alphanumeric characters Any graphics of up to 128 elements 32 4-bit RAM for display data storage Display memory bank switching in static and duplex drive modes Versatile blinking modes Independent supplies possible for LCD and logic voltages Wide power supply range: from 1.8 V to 5.5 V Wide logic LCD supply range: From 2.5 V for low-threshold LCDs Up to 6.5 V for guest-host LCDs and high-threshold twisted nematic LCDs Low power consumption 400 kHz I2C-bus interface No external components required Manufactured in silicon gate CMOS process The definition of the abbreviations and acronyms used in this data sheet can be found in Section 17. PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 3. Ordering information Table 1. Ordering information Type number PCF85162T/1 Package Name Description Version TSSOP48 plastic thin shrink small outline package; 48 leads; SOT362-1 body width 6.1 mm 4. Marking Table 2. Marking codes Type number Marking code PCF85162T/1 PCF85162T 5. Block diagram S0 to S31 BP0 BP2 BP1 BP3 32 VLCD BACKPLANE OUTPUTS DISPLAY SEGMENT OUTPUTS DISPLAY REGISTER LCD VOLTAGE SELECTOR VSS CLK OUTPUT BANK SELECT AND BLINK CONTROL DISPLAY CONTROLLER LCD BIAS GENERATOR PCF85162 SYNC CLOCK SELECT AND TIMING BLINKER TIMEBASE OSC OSCILLATOR POWER-ON RESET COMMAND DECODER DISPLAY RAM 40 × 4-BIT WRITE DATA CONTROL DATA POINTER AND AUTO INCREMENT VDD SCL INPUT FILTERS SDA I2C-BUS CONTROLLER SUBADDRESS COUNTER SA0 A0 A1 A2 013aaa064 Fig 1. Block diagram of PCF85162 PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 2 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 6. Pinning information 6.1 Pinning S23 1 48 S22 S24 2 47 S21 S25 3 46 S20 S26 4 45 S19 S27 5 44 S18 S28 6 43 S17 S29 7 42 S16 S30 8 41 S15 S31 9 40 S14 SDA 10 39 S13 SCL 11 38 S12 SYNC 12 CLK 13 37 S11 PCF85162T 36 S10 VDD 14 35 S9 OSC 15 34 S8 A0 16 33 S7 A1 17 32 S6 A2 18 31 S5 SA0 19 30 S4 VSS 20 29 S3 VLCD 21 28 S2 BP0 22 27 S1 BP2 23 26 S0 BP1 24 25 BP3 013aaa065 Top view. For mechanical details, see Figure 26. Fig 2. PCF85162 Product data sheet Pinning diagram for TSSOP48 (PCF85162T) All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 3 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 6.2 Pin description Table 3. PCF85162 Product data sheet Pin description Symbol Pin Type Description SDA 10 input/output I2C-bus serial data line SCL 11 input I2C-bus serial clock SYNC 12 input/output cascade synchronization CLK 13 input/output clock line VDD 14 supply supply voltage OSC 15 input internal oscillator enable A0 to A2 16 to 18 input subaddress inputs SA0 19 input I2C-bus address input VSS 20 supply ground supply voltage VLCD 21 supply LCD supply voltage BP0 to BP3 22 to 25 output LCD backplane outputs S0 to S22, S23 to S31 26 to 48, 1 to 9 output LCD segment outputs All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 4 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 7. Functional description The PCF85162 is a versatile peripheral device designed to interface between any microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 3). It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 32 segments. dot matrix 7-segment with dot 14-segment with dot and accent 013aaa312 Fig 3. Example of displays suitable for PCF85162 The possible display configurations of the PCF85162 depend on the number of active backplane outputs required. A selection of display configurations is shown in Table 4. All of these configurations can be implemented in the typical system shown in Figure 4. Table 4. Selection of possible display configurations Number of Backplanes Icons Digits/Characters 7-segment[1] PCF85162 Product data sheet 14-segment[2] Dot matrix/ Elements 4 128 16 8 128 dots (4 32) 3 96 12 6 96 dots (3 32) 2 64 8 4 64 dots (2 32) 1 32 4 2 32 dots (1 32) [1] 7 segment display has 8 elements including the decimal point. [2] 14 segment display has 16 elements including decimal point and accent dot. All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 5 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates VDD R≤ tr 2Cb VDD VLCD 14 21 32 segment drives SDA 10 HOST MICROPROCESSOR/ MICROCONTROLLER SCL OSC LCD PANEL PCF85162 11 4 backplanes (up to 128 elements) 15 16 17 A0 A1 18 A2 19 20 SA0 VSS 013aaa066 VSS The resistance of the power lines must be kept to a minimum. Fig 4. Typical system configuration The host microcontroller maintains the 2-line I2C-bus communication channel with the PCF85162. The internal oscillator is enabled by connecting pin OSC to pin VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are to the power supplies (VDD, VSS, and VLCD) and the LCD panel chosen for the application. 7.1 Power-On Reset (POR) At power-on the PCF85162 resets to the following starting conditions: • • • • • • • All backplane and segment outputs are set to VLCD The selected drive mode is: 1:4 multiplex with 1⁄3 bias Blinking is switched off Input and output bank selectors are reset The I2C-bus interface is initialized The data pointer and the subaddress counter are cleared (set to logic 0) Display is disabled Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow the reset action to complete. 7.2 LCD bias generator Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of three impedances connected in series between VLCD and VSS. The center impedance is bypassed by switch if the 1⁄2 bias voltage level for the 1:2 multiplex drive mode configuration is selected. The LCD voltage can be temperature compensated externally, using the supply to pin VLCD. 7.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting discrimination ratios (D) are given in Table 5. PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 6 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates Discrimination is a term which is defined as the ratio of the on and off RMS voltage across a segment. It can be thought of as a measurement of contrast. Table 5. Biasing characteristics LCD drive mode Number of: LCD bias Backplanes Levels configuration V off RMS ------------------------V LCD V on RMS -----------------------V LCD static V on RMS D = -----------------------V off RMS 1 2 static 0 1 1:2 multiplex 2 3 1⁄ 2 0.354 0.791 2.236 1:2 multiplex 2 4 1⁄ 3 0.333 0.745 2.236 4 1⁄ 3 0.333 0.638 1.915 4 1⁄ 3 0.333 0.577 1.732 1:3 multiplex 3 1:4 multiplex 4 A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode a suitable choice is VLCD > 3Vth(off). Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and hence the contrast ratios are smaller. 1 Bias is calculated by ------------- , where the values for a are 1+a a = 1 for 1⁄2 bias a = 2 for 1⁄3 bias The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1: V on RMS = V LCD a 2 + 2a + n -----------------------------2 n 1 + a (1) where the values for n are n = 1 for static drive mode n = 2 for 1:2 multiplex drive mode n = 3 for 1:3 multiplex drive mode n = 4 for 1:4 multiplex drive mode The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2: V off RMS = V LCD a 2 – 2a + n -----------------------------2 n 1 + a (2) Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3: V on RMS D = ----------------------- = V off RMS PCF85162 Product data sheet 2 a + 2a + n --------------------------2 a – 2a + n All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 (3) © NXP B.V. 2011. All rights reserved. 7 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with 1⁄ 2 bias is 1⁄ 2 21 bias is ---------- = 1.528 . 3 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD as follows: • 1:3 multiplex (1⁄2 bias): V LCD = 6 V off RMS = 2.449V off RMS 4 3 - = 2.309V off RMS • 1:4 multiplex (1⁄2 bias): V LCD = --------------------3 These compare with V LCD = 3V off RMS when 1⁄3 bias is used. It should be noted that VLCD is sometimes referred as the LCD operating voltage. 7.3.1 Electro-optical performance Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of the pixel. For any given liquid, there are two threshold values defined. One point is at 10 % relative transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see Figure 5. For a good contrast performance, the following rules should be followed: V on RMS V th on (4) V off RMS V th off (5) Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection of a, n (see Equation 1 to Equation 3) and the VLCD voltage. Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module manufacturer. It is important to match the module properties to those of the driver in order to achieve optimum performance. PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 8 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 100 % Relative Transmission 90 % 10 % Vth(off) OFF SEGMENT Vth(on) GREY SEGMENT VRMS [V] ON SEGMENT 013aaa494 Fig 5. PCF85162 Product data sheet Electro-optical characteristic: relative transmission curve of the liquid All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 9 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BPn) and segment (Sn) drive waveforms for this mode are shown in Figure 6. Tfr LCD segments VLCD BP0 VSS state 1 (on) VLCD state 2 (off) Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD state 1 0V −VLCD VLCD state 2 0V −VLCD (b) Resultant waveforms at LCD segment. 013aaa207 Vstate1(t) = VSn(t) VBP0(t). Von(RMS) = VLCD. Vstate2(t) = V(Sn + 1)(t) VBP0(t). Voff(RMS) = 0 V. Fig 6. PCF85162 Product data sheet Static drive mode waveforms All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 10 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF85162 allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 7 and Figure 8. Tfr VLCD BP0 LCD segments VLCD/2 VSS state 1 VLCD BP1 state 2 VLCD/2 VSS VLCD Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD VLCD/2 state 1 0V −VLCD/2 −VLCD VLCD VLCD/2 state 2 0V −VLCD/2 −VLCD (b) Resultant waveforms at LCD segment. 013aaa208 Vstate1(t) = VSn(t) VBP0(t). Von(RMS) = 0.791VLCD. Vstate2(t) = VSn(t) VBP1(t). Voff(RMS) = 0.354VLCD. Fig 7. PCF85162 Product data sheet Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 11 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates Tfr BP0 BP1 Sn Sn+1 VLCD 2VLCD/3 LCD segments VLCD/3 VSS state 1 VLCD 2VLCD/3 state 2 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 state 1 0V −VLCD/3 −2VLCD/3 −VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V −VLCD/3 −2VLCD/3 −VLCD (b) Resultant waveforms at LCD segment. 013aaa209 Vstate1(t) = VSn(t) VBP0(t). Von(RMS) = 0.745VLCD. Vstate2(t) = VSn(t) VBP1(t). Voff(RMS) = 0.333VLCD. Fig 8. PCF85162 Product data sheet Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 12 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as shown in Figure 9. Tfr BP0 BP1 BP2 Sn Sn+1 Sn+2 VLCD 2VLCD/3 LCD segments VLCD/3 VSS state 1 VLCD 2VLCD/3 state 2 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 state 1 0V −VLCD/3 −2VLCD/3 −VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V −VLCD/3 −2VLCD/3 −VLCD (b) Resultant waveforms at LCD segment. 013aaa210 Vstate1(t) = VSn(t) VBP0(t). Von(RMS) = 0.638VLCD. Vstate2(t) = VSn(t) VBP1(t). Voff(RMS) = 0.333VLCD. Fig 9. PCF85162 Product data sheet Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 13 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.4 1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as shown in Figure 10. Tfr BP0 VLCD 2VLCD/3 VLCD/3 VSS BP1 VLCD 2VLCD/3 VLCD/3 VSS BP2 VLCD 2VLCD/3 VLCD/3 VSS BP3 VLCD 2VLCD/3 VLCD/3 VSS Sn VLCD 2VLCD/3 VLCD/3 VSS Sn+1 VLCD 2VLCD/3 VLCD/3 VSS Sn+2 VLCD 2VLCD/3 VLCD/3 VSS Sn+3 VLCD 2VLCD/3 VLCD/3 VSS state 1 VLCD 2VLCD/3 VLCD/3 0V −VLCD/3 −2VLCD/3 −VLCD state 2 VLCD 2VLCD/3 VLCD/3 0V −VLCD/3 −2VLCD/3 −VLCD LCD segments state 1 state 2 (a) Waveforms at driver. (b) Resultant waveforms at LCD segment. 013aaa211 Vstate1(t) = VSn(t) VBP0(t). Von(RMS) = 0.577VLCD. Vstate2(t) = VSn(t) VBP1(t). Voff(RMS) = 0.333VLCD. Fig 10. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 14 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 7.5 Oscillator 7.5.1 Internal clock The internal logic of the PCF85162 and its LCD drive signals are timed either by its internal oscillator or by an external clock. The internal oscillator is enabled by connecting pin OSC to pin VSS. If the internal oscillator is used, the output from pin CLK can be used as the clock signal for several PCF85162 in the system that are connected in cascade. 7.5.2 External clock Pin CLK is enabled as an external clock input by connecting pin OSC to VDD. The LCD frame signal frequency is determined by the clock frequency (fclk). Remark: A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal. 7.6 Timing The PCF85162 timing controls the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the correct timing relationship between each PCF85162 in the system is maintained by the synchronization signal at pin SYNC. The timing also generates the LCD frame signal whose frequency is derived from the clock frequency. The frame signal frequency is a fixed division of the clock frequency from either the internal or an external f clk clock: f fr = ------24 7.7 Display register The display register holds the display data while the corresponding multiplex signals are generated. 7.8 Segment outputs The LCD drive section includes 32 segment outputs S0 to S31 which should be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the display register. When less than 32 segment outputs are required, the unused segment outputs should be left open-circuit. 7.9 Backplane outputs The LCD drive section includes four backplane outputs BP0 to BP3 which must be connected directly to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane outputs are required, the unused outputs can be left open-circuit. • In the 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. • In the 1:2 multiplex drive mode, BP0 and BP2, respectively, BP1 and BP3 carry the same signals and may also be paired to increase the drive capabilities. PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 15 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates • In the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 7.10 Display RAM The display RAM is a static 32 4-bit RAM which stores LCD data. There is a one-to-one correspondence between • the bits in the RAM bitmap and the LCD elements • the RAM columns and the segment outputs • the RAM rows and the backplane outputs. A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element; similarly, a logic 0 indicates the off-state. The display RAM bit map Figure 11 shows the rows 0 to 3 which correspond with the backplane outputs BP0 to BP3, and the columns 0 to 31 which correspond with the segment outputs S0 to S31. In multiplexed LCD applications the segment data of the first, second, third, and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2, and BP3 respectively. columns display RAM addresses/segment outputs (S) 0 rows 1 2 3 4 27 28 29 30 31 0 display RAM rows/ 1 backplane outputs (BP) 2 3 001aac265 The display RAM bit map shows the direct relationship between the display RAM addresses and the segment outputs and between the bits in a RAM word and the backplane outputs. Fig 11. Display RAM bit map When display data is transmitted to the PCF85162, the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and depending on the current multiplex drive mode the bits are stored singularly, in pairs, triples or quadruples. To illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in Figure 12; the RAM filling organization depicted applies equally to other LCD types. PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 16 of 46 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LCD segments Sn+2 Sn+3 static display RAM filling order b f Sn+1 BP0 rows display RAM 0 rows/backplane 1 outputs (BP) 2 3 g e Sn+6 Sn Sn+7 c DP d n n+1 n+2 n+3 n+4 n+5 n+6 n+7 c x x x b x x x a x x x f x x x g x x x e x x x d x x x DP x x x Sn a b f g multiplex Sn+2 BP1 e Sn+3 c Sn+1 1:3 Sn+2 DP d a b Sn multiplex BP1 c b f BP0 g multiplex 17 of 46 © NXP B.V. 2011. All rights reserved. Sn+1 BP1 c d g e d DP n n+1 n+2 n+3 a b x x f g x x e c x x d DP x x MSB a b LSB f g e c d DP n rows display RAM 0 b rows/backplane 1 DP outputs (BP) 2 c 3 x n+1 n+2 a d g x f e x x MSB LSB b DP c a d g f e DP BP2 n rows display RAM 0 a rows/backplane 1 c BP3 outputs (BP) 2 b 3 DP n+1 f e g d MSB a c b DP f LSB e g d 001aaj646 x = data bit unchanged. Fig 12. Relationship between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I2C-bus PCF85162 e f columns display RAM address/segment outputs (s) byte1 byte2 byte3 byte4 byte5 a Sn 1:4 BP2 DP d c b a columns display RAM address/segment outputs (s) byte1 byte2 byte3 g e rows display RAM 0 rows/backplane 1 outputs (BP) 2 3 BP0 f LSB Universal LCD driver for low multiplex rates Rev. 3 — 16 June 2011 All information provided in this document is subject to legal disclaimers. Sn+1 MSB columns display RAM address/segment outputs (s) byte1 byte2 BP0 1:2 transmitted display byte columns display RAM address/segment outputs (s) byte1 a Sn+4 Sn+5 LCD backplanes NXP Semiconductors PCF85162 Product data sheet drive mode PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates The following applies to Figure 12: • In static drive mode the eight transmitted data bits are placed in row 0 as one byte. • In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into row 0 and 1 as two successive 4-bit RAM words. • In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is not recommended to use this bit in a display because of the difficult addressing. This last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overwriting adjacent data because always full bytes are transmitted (see Section 7.10.3). • In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples into row 0, 1, 2, and 3 as two successive 4-bit RAM words. 7.10.1 Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load-data-pointer command (see Table 12). Following this command, an arriving data byte is stored at the display RAM address indicated by the data pointer. The filling order is shown in Figure 12. After each byte is stored, the content of the data pointer is automatically incremented by a value dependent on the selected LCD drive mode: • • • • In static drive mode by eight In 1:2 multiplex drive mode by four In 1:3 multiplex drive mode by three In 1:4 multiplex drive mode by two If an I2C-bus data access is terminated early then the state of the data pointer is unknown. The data pointer should be re-written prior to further RAM accesses. 7.10.2 Subaddress counter The storage of display data is determined by the contents of the subaddress counter. Storage is allowed only when the content of the subaddress counter matches with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined by the device-select command (see Table 13). If the content of the subaddress counter and the hardware subaddress do not match then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. In cascaded applications each PCF85162 in the cascade must be addressed separately. Initially, the first PCF85162 is selected by sending the device-select command matching the first device's hardware subaddress. Then the data pointer is set to the preferred display RAM address by sending the load-data-pointer command. PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 18 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates Once the display RAM of the first PCF85162 has been written, the second PCF85162 is selected by sending the device-select command again. This time however the command matches the second device's hardware subaddress. Next the load-data-pointer command is sent to select the preferred display RAM address of the second PCF85162. This last step is very important because during writing data to the first PCF85162, the data pointer of the second PCF85162 is incremented. In addition, the hardware subaddress should not be changed whilst the device is being accessed on the I2C-bus interface. 7.10.3 RAM writing in 1:3 multiplex drive mode In 1:3 multiplex drive mode, the RAM is written as shown in Table 6 (see Figure 12 as well). Table 6. Standard RAM filling in 1:3 multiplex drive mode Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display. Display RAM bits (rows)/ backplane outputs (BPn) Display RAM addresses (columns)/segment outputs (Sn) 0 1 2 3 4 5 6 7 8 9 : 0 a7 a4 a1 b7 b4 b1 c7 c4 c1 d7 : 1 a6 a3 a0 b6 b3 b0 c6 c3 c0 d6 : 2 a5 a2 - b5 b2 - c5 c2 - d5 : 3 - - - - - - - - - - : If the bit at position BP2/S2 would be written by a second byte transmitted, then the mapping of the segment bits would change as illustrated in Table 7. Table 7. Entire RAM filling by rewriting in 1:3 multiplex drive mode Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display. Display RAM bits (rows)/ backplane outputs (BPn) Display RAM addresses (columns)/segment outputs (Sn) 0 1 2 0 a7 a4 a1/b7 b4 b1/c7 c4 c1/d7 d4 d1/e7 e4 : 1 a6 a3 a0/b6 b3 b0/c6 c3 c0/d6 d3 d0/e6 e3 : 2 a5 a2 b5 b2 c5 c2 d5 d2 e5 e2 : 3 - - - - - - - - - - : 3 4 5 6 7 8 9 : In the case described in Table 7 the RAM has to be written entirely and BP2/S2, BP2/S5, BP2/S8 etc. have to be connected to elements on the display. This can be achieved by a combination of writing and rewriting the RAM like follows: • In the first write to the RAM, bits a7 to a0 are written. • In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7 and b6. • In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and c6. Depending on the method of writing to the RAM (standard or entire filling by rewriting), some elements remain unused or can be used, but it has to be considered in the module layout process as well as in the driver software design. PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 19 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 7.10.4 Output bank selector The output bank selector (see Table 14) selects one of the four rows per display RAM address for transfer to the display register. The actual row selected depends on the particular LCD drive mode in operation and on the instant in the multiplex sequence. • In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by the contents of row 1, 2, and then 3 • In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially • In 1:2 multiplex mode, rows 0 and 1 are selected • In static mode, row 0 is selected The PCF85162 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank-select command may request the contents of row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. 7.10.5 Input bank selector The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see Table 14). The input bank selector functions independently to the output bank selector. 7.11 Blinking The display blinking capabilities of the PCF85162 are very versatile. The whole display can blink at a frequencies selected by the blink-select command (see Table 15). The blink frequencies are fractions of the clock frequency. The ratio between the clock and blink frequencies depends on the blink mode selected (see Table 8). An additional feature is for an arbitrary selection of LCD elements to blink. This applies to the static and 1:2 multiplex drive modes and can be implemented without any communication overheads. By means of the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blink frequency. This mode can also be specified by the blink-select command. In the 1:3 and 1:4 multiplex modes, where no alternative RAM bank is available, groups of LCD elements can blink by selectively changing the display RAM data at fixed time intervals. PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 20 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates Blink frequencies[1] Table 8. Blink mode Blink frequency equation off - 1 f clk f blink = ---------768 2 f clk f blink = ------------1536 3 f clk f blink = ------------3072 [1] The blink frequency is proportional to the clock frequency (fclk). For the range of the clock frequency see Table 19. The entire display can blink at a frequency other than the nominal blink frequency. This can be effectively performed by resetting and setting the display enable bit E at the required rate using the mode-set command (see Table 11). 7.12 Command decoder The command decoder identifies command bytes that arrive on the I2C-bus. The commands available to the PCF85162 are defined in Table 9. Table 9. Definition of PCF85162 commands Bit position labeled as - is not used. Command Operation code Bit 7 6 5 4 3 2 1 Reference mode-set C 1 0 - E B M[1:0] load-data-pointer C 0 0 P[4:0] 0 Table 11 Table 12 device-select C 1 1 0 0 A[2:0] bank-select C 1 1 1 1 0 I Table 13 blink-select C 1 1 1 0 AB BF[1:0] O Table 14 Table 15 All available commands carry a continuation bit C in their most significant bit position as shown in Figure 18. When this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command. If this bit is reset, it indicates that the command byte is the last in the transfer. Further bytes will be regarded as display data (see Table 10). PCF85162 Product data sheet Table 10. C bit description Bit Symbol 7 C Value Description continue bit 0 last control byte in the transfer; next byte will be regarded as display data 1 control bytes continue; next byte will be a command too All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 21 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates Table 11. Mode-set command bit description Bit Symbol Value Description 7 C 0, 1 see Table 10 6 to 5 - 10 fixed value 4 - - unused 3 E display status disabled (blank)[1] 0 1 2 1 to 0 Product data sheet 0 1⁄ 3 bias 1 1⁄ 2 bias M[1:0] LCD drive mode selection 01 static; BP0 10 1:2 multiplex; BP0, BP1 11 1:3 multiplex; BP0, BP1, BP2 00 1:4 multiplex; BP0, BP1, BP2, BP3 [1] The possibility to disable the display allows implementation of blinking under external control. [2] Not applicable for static drive mode. Table 12. PCF85162 enabled LCD bias configuration[2] B Load-data-pointer command bit description Bit Symbol Value Description 7 C 0, 1 see Table 10 6 to 5 - 00 fixed value 4 to 0 P[4:0] 00000 to 11111 5 bit binary value, 0 to 31; transferred to the data pointer to define one of 32 display RAM addresses Table 13. Device-select command bit description Bit Symbol Value Description 7 C 0, 1 see Table 10 6 to 3 - 1100 fixed value 2 to 0 A[2:0] 000 to 111 3 bit binary value, 0 to 7; transferred to the subaddress counter to define one of eight hardware subaddresses All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 22 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates Table 14. Bank-select command bit description Bit Symbol Value Description Static 7 C 0, 1 see Table 10 6 to 2 - 11110 fixed value 1 I input bank selection; storage of arriving display data 0 1 0 [1] 1:2 multiplex[1] O RAM bit 0 RAM bits 0 and 1 RAM bit 2 RAM bits 2 and 3 output bank selection; retrieval of LCD display data 0 RAM bit 0 RAM bits 0 and 1 1 RAM bit 2 RAM bits 2 and 3 The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes. Table 15. Blink-select command bit description Bit Symbol Value Description 7 C 0, 1 see Table 10 6 to 3 - 1110 fixed value 2 AB 1 to 0 blink mode selection 0 normal blinking[1] 1 alternate RAM bank blinking[2] BF[1:0] blink frequency selection 00 off 01 1 10 2 11 3 [1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected. [2] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes. 7.13 Display controller The display controller executes the commands identified by the command decoder. It contains the device’s status registers and coordinates their effects. The display controller is also responsible for loading display data into the display RAM in the correct filling order. PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 23 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 8. Characteristics of the I2C-bus The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta Line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 8.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 13). SDA SCL data line stable; data valid change of data allowed mba607 Fig 13. Bit transfer 8.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 14). SDA SDA SCL SCL S P START condition STOP condition mbc622 Fig 14. Definition of START and STOP conditions 8.3 System configuration A device generating a message is a transmitter; a device receiving a message is the receiver. The device that controls the message is the master, and the devices which are controlled by the master are the slaves (see Figure 15). PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 24 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates MASTER TRANSMITTER/ RECEIVER SLAVE TRANSMITTER/ RECEIVER SLAVE RECEIVER MASTER TRANSMITTER/ RECEIVER MASTER TRANSMITTER SDA SCL mga807 Fig 15. System configuration 8.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • A slave receiver, which is addressed, must generate an acknowledge after the reception of each byte. • A master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. • The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). • A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is illustrated in Figure 16. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 8 9 S START condition clock pulse for acknowledgement mbc602 Fig 16. Acknowledgement of the I2C-bus PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 25 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 8.5 I2C-bus controller The PCF85162 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF85162 are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data and on the hardware subaddress. In single device applications, the hardware subaddress inputs A0, A1, and A2 are normally tied to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1, and A2 are tied to VSS or VDD using a binary coding scheme, so that no two devices with a common I2C-bus slave address have the same hardware subaddress. 8.6 Input filters To enhance noise immunity in electrical adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 8.7 I2C-bus protocol Two I2C-bus slave addresses (0111 000 and 0111 001) are used to address the PCF85162. The entire I2C-bus slave address byte is shown in Table 16. Table 16. I2C slave address byte Slave address Bit 7 6 5 4 3 2 1 MSB 0 0 LSB 1 1 1 0 0 SA0 R/W The PCF85162 is a write-only device and will not respond to a read access, therefore bit 0 should always be logic 0. Bit 1 of the slave address byte, that a PCF85162 will respond to, is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1). Having two reserved slave addresses allows the following on the same I2C-bus: • Up to 16 PCF85162 for very large LCD applications • The use of two types of LCD multiplex drive modes The I2C-bus protocol is shown in Figure 17. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of two possible PCF85162 slave addresses available. All PCF85162 whose SA0 inputs correspond to bit 0 of the slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is ignored by all PCF85162 whose SA0 inputs are set to the alternative level. PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 26 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates acknowledge by A0, A1 and A2 selected PCF85162 only acknowledge by all addressed PCF85162 R/W slave address S S 0 1 1 1 0 0 A 0 A C 0 COMMAND A n ≥ 1 byte(s) 1 byte DISPLAY DATA A P n ≥ 0 byte(s) update data pointers and if necessary, subaddress counter 013aaa235 Fig 17. I2C-bus protocol After an acknowledgement, one or more command bytes follow, that define the status of each addressed PCF85162. The last command byte sent is identified by resetting its most significant bit, continuation bit C, (see Figure 18). The command bytes are also acknowledged by all addressed PCF85162s on the bus. MSB C LSB REST OF OPCODE msa833 Fig 18. Format of command byte After the last command byte, one or more display data bytes may follow. Display data bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated and the data directed to the intended PCF85162 device. An acknowledgement, after each byte is asserted, only by the PCF85162s that are addressed via address lines A0, A1, and A2. After the last display byte, the I2C-bus master asserts a STOP condition (P). Alternately a START may be asserted to restart an I2C-bus access. PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 27 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 9. Internal circuitry VDD VDD VSS VSS SA0 VDD CLK SCL VSS VDD VSS OSC VSS VDD SDA SYNC VSS VSS VDD A0, A1, A2 VSS VLCD BP0, BP1, BP2, BP3 VSS VLCD VLCD S0 to S31 VSS VSS 001aac269 Fig 19. Device protection circuits PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 28 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 10. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. Table 17. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Max Unit supply voltage 0.5 +6.5 V VLCD LCD supply voltage 0.5 +7.5 V VI input voltage on each of the pins CLK, SDA, SCL, SYNC, SA0, OSC, A0 to A2 0.5 +6.5 V VO output voltage on each of the pins S0 to S31, BP0 to BP3 0.5 +7.5 V II input current 10 +10 mA IO output current 10 +10 mA IDD supply current 50 +50 mA IDD(LCD) LCD supply current 50 +50 mA ISS ground supply current 50 +50 mA Ptot total power dissipation - 400 mW Po output power - 100 mW VESD electrostatic discharge voltage HBM [1] - 2000 V MM [2] - 300 V CDM [3] - 1000 V latch-up current [4] - 200 mA Tstg storage temperature [5] 65 +150 C Tamb ambient temperature 40 +85 C [1] Product data sheet Min VDD Ilu PCF85162 Conditions operating device Pass level; Human Body Model (HBM), according to Ref. 6 “JESD22-A114”. [2] Pass level; Machine Model (MM), according to Ref. 7 “JESD22-A115”. [3] Pass level; Charged-Device Model (CDM), according to Ref. 8 “JESD22-C101”. [4] Pass level; latch-up testing according to Ref. 9 “JESD78” at maximum ambient temperature (Tamb(max)). [5] According to the NXP store and transport requirements (see Ref. 11 “NX3-00092”) the devices have to be stored at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %. For long term storage products deviant conditions are described in that document. All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 29 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 11. Static characteristics Table 18. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VDD supply voltage 1.8 - 5.5 V VLCD LCD supply voltage [1] 2.5 - 6.5 V supply current fclk(ext) = 1536 Hz [2][3] - - 20 A fclk(ext) = 1536 Hz [2][4] - - 60 A 1.0 1.3 1.6 V VSS - 0.3VDD V 0.7VDD - VDD V on pins CLK and SYNC 1 - - mA on pin SDA 3 - - mA IDD IDD(LCD) LCD supply current Logic[5] VP(POR) power-on reset supply voltage VIL LOW-level input voltage on pins CLK, SYNC, OSC, A0 to A2, SA0, SCL, SDA VIH HIGH-level input voltage on pins CLK, SYNC, OSC, A0 to A2, SA0, SCL, SDA IOL LOW-level output current output sink current; VOL = 0.4 V; VDD = 5 V [6] IOH(CLK) HIGH-level output current on pin CLK output source current; VOH = 4.6 V; VDD = 5 V 1 - - mA IL leakage current VI = VDD or VSS; on pins CLK, SCL, SDA, A0 to A2, and SA0 1 - +1 A IL(OSC) leakage current on pin OSC VI = VDD 1 - +1 A - - 7 pF 100 - +100 mV on pins BP0 to BP3 - 1.5 - k on pins S0 to S31 - 6.0 - k [7] input capacitance CI LCD outputs VO output voltage variation on pins BP0 to BP3 and S0 to S31 RO output resistance VLCD = 5 V [8] [1] VLCD > 3 V for 1⁄3 bias. [2] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive. [3] For typical values, see Figure 20. [4] For typical values, see Figure 21. [5] The I2C-bus interface of PCF85162 is 5 V tolerant. [6] I2C pins SCL and SDA have no diode to VDD and when tested may therefore be driven to the VI limiting values given in Table 17 (see also Figure 19). [7] Periodically sampled, not 100 % tested. [8] Outputs measured one at a time. PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 30 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 001aal523 5 IDD (μA) 4 3 2 1 0 2 3 4 5 6 VDD (V) Tamb = 30 C; 1:4 multiplex drive mode; VLCD = 6.5 V; fclk(ext) = 1.536 kHz; all RAM written with logic 1; no display connected; I2C-bus inactive. Fig 20. Typical IDD with respect to VDD 001aal524 20 IDD(LCD) (μA) 16 12 8 4 0 3 5 7 9 VLCD (V) Tamb = 30 C; 1:4 multiplex drive mode; fclk(ext) = 1.536 kHz; all RAM written with logic 1; no display connected. Fig 21. Typical IDD(LCD) with respect to VLCD PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 31 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 12. Dynamic characteristics Table 19. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 1440 1970 2640 Hz 960 - 2640 Hz internal clock 60 82 110 Hz external clock 40 - 110 Hz Clock fclk(int) internal clock frequency fclk(ext) external clock frequency ffr frame frequency [1] tclk(H) HIGH-level clock time 60 - - s tclk(L) LOW-level clock time 60 - - s - 30 - ns 1 - - s - - 30 s Synchronization tPD(SYNC_N) SYNC propagation delay tSYNC_NL SYNC LOW time tPD(drv) driver propagation delay VLCD = 5 V [2] I2C-bus[3] Pin SCL fSCL SCL clock frequency - - 400 kHz tLOW LOW period of the SCL clock 1.3 - - s tHIGH HIGH period of the SCL clock 0.6 - - s tSU;DAT data set-up time 100 - - ns tHD;DAT data hold time 0 - - ns Pin SDA Pins SCL and SDA tBUF bus free time between a STOP and START condition 1.3 - - s tSU;STO set-up time for STOP condition 0.6 - - s tHD;STA hold time (repeated) START condition 0.6 - - s tSU;STA set-up time for a repeated START condition 0.6 - - s tr rise time of both SDA and SCL signals fSCL = 400 kHz - - 0.3 s fSCL < 125 kHz - - 1.0 s - - 0.3 s tf fall time of both SDA and SCL signals Cb capacitive load for each bus line tw(spike) spike pulse width on the I2C-bus - - 400 pF - - 50 ns [1] Typical output duty factor: 50 % measured at the CLK output pin. [2] Not tested in production. [3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 32 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 1 / fclk tclk(H) tclk(L) 0.7 VDD CLK 0.3 VDD 0.7 VDD SYNC 0.3 VDD tPD(SYNC_N) tSYNC_NL 10 % 80 % BPn, Sn 10 % tPD(drv) 013aaa298 Fig 22. Driver timing waveforms SDA tBUF tLOW tf SCL tHD;STA tr tHD;DAT tHIGH tSU;DAT SDA tSU;STA tSU;STO mga728 Fig 23. I2C-bus timing waveforms PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 33 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 13. Application information 13.1 Cascaded operation Large display configurations of up to 16 PCF85162 can be recognized on the same I2C-bus by using the 3-bit hardware subaddress (A0, A1, and A2) and the programmable I2C-bus slave address (SA0). Table 20. Addressing cascaded PCF85162 Cluster Bit SA0 Pin A2 Pin A1 Pin A0 Device 1 0 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 2 1 1 1 1 7 0 0 0 8 0 0 1 9 0 1 0 10 0 1 1 11 1 0 0 12 1 0 1 13 1 1 0 14 1 1 1 15 When cascaded PCF85162 are synchronized, they can share the backplane signals from one of the devices in the cascade. Such an arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other PCF85162 of the cascade contribute additional segment outputs, but their backplane outputs are left open-circuit (see Figure 24). PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 34 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates VDD VLCD SDA 32 segment drives SCL LCD PANEL SYNC PCF85162 CLK (up to 2048 elements) (2) OSC BP0 to BP3 (open-circuit) A0 A1 A2 SA0 VSS VLCD VDD R≤ HOST MICROPROCESSOR/ MICROCONTROLLER tr 2CB V DD V LCD 32 segment drives SDA SCL SYNC PCF85162 CLK (1) 4 backplanes BP0 to BP3 OSC 013aaa067 A0 VSS A1 A2 SA0 VSS (1) Is master (OSC connected to VSS). (2) Is slave (OSC connected to VDD). Fig 24. Cascaded PCF85162 configuration The SYNC line is provided to maintain the correct synchronization between all cascaded PCF85162. Synchronization is guaranteed after a power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments or by defining a multiplex drive mode when PCF85162 with different SA0 levels are cascaded). SYNC is organized as an input/output pin. The output selection is realized as an open-drain driver with an internal pull-up resistor. A PCF85162 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. If synchronization in the cascade is lost, it is restored by the first PCF85162 to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal for the various drive modes of the PCF85162 are shown in Figure 25. The contact resistance between the SYNC on each cascaded device must be controlled. If the resistance is too high, the device is not able to synchronize properly; this is particularly applicable to chip-on-glass applications. The maximum SYNC contact resistance allowed for the number of devices in cascade is given in Table 21. PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 35 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates Table 21. SYNC contact resistance Number of devices Maximum contact resistance 2 6 k 3 to 5 2.2 k 6 to 10 1.2 k 10 to 16 700 The PCF85162 can always be cascaded with other devices of the same type or conditionally with other devices of the same family. This allows optimal drive selection for a given number of pixels to display. Figure 22 and Figure 25 show the timing of the synchronization signals. Tfr = 1 ffr BP0 SYNC (a) static drive mode. BP0 (1/2 bias) BP0 (1/3 bias) SYNC (b) 1:2 multiplex drive mode. BP0 (1/3 bias) SYNC (c) 1:3 multiplex drive mode. BP0 (1/3 bias) SYNC (d) 1:4 multiplex drive mode. mgl755 Fig 25. Synchronization of the cascade for the various PCF85162 drive modes In a cascaded configuration only one PCF85162 master must be used as clock source. All other PCF85162 in the cascade must be configured as slave such that they receive the clock from the master. PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 36 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates If an external clock source is used, all PCF85162 in the cascade must be configured such as to receive the clock from that external source (pin OSC connected to VDD). Thereby it must be ensured that the clock tree is designed such that on all PCF85162 the clock propagation delay from the clock source to all PCF85162 in the cascade is as equal as possible since otherwise synchronization artefacts may occur. In mixed cascading configurations, care has to be taken that the specifications of the individual cascaded devices are met at all times. PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 37 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 14. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 E D A X c HE y v M A Z 48 25 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 24 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.0 0.5 8.3 7.9 1 0.8 0.4 0.50 0.35 0.25 0.08 0.1 0.8 0.4 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 26. Package outline SOT362-1 (TSSOP48) PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 38 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 15. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • PCF85162 Product data sheet Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 39 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 16.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 16.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 27) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 22 and 23 Table 22. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 < 2.5 235 220 2.5 220 220 Table 23. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 27. PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 40 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 27. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 17. Abbreviations Table 24. PCF85162 Product data sheet Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor CDM Charged-Device Model DC Direct Current HBM Human Body Model I2C Inter-Integrated Circuit IC Integrated Circuit LCD Liquid Crystal Display MM Machine Model MSL Moisture Sensitivity Level PCB Printed-Circuit Board RAM Random Access Memory RC Resistance and Capacitance RMS Root Mean Square SCL Serial CLock line SDA Serial Data Line SMD Surface-Mount Device All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 41 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 18. References [1] AN10365 — Surface mount reflow soldering description [2] AN10853 — ESD and EMC sensitivity of IC [3] IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices [4] IEC 61340-5 — Protection of electronic devices from electrostatic phenomena [5] IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices [6] JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) [7] JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) [8] JESD22-C101 — Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components [9] JESD78 — IC Latch-Up Test [10] JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [11] NX3-00092 — NXP store and transport requirements [12] SNV-FA-01-02 — Marking Formats Integrated Circuits [13] UM10204 — I2C-bus specification and user manual PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 42 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 19. Revision history Table 25. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF85162 v.3 20110616 Product data sheet - PCF85162_2 Modifications: • Added Section 7.10.3 PCF85162_2 20100507 Product data sheet - PCF85162_1 PCF85162_1 20100107 Product data sheet - - PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 43 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 20.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 20.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 44 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 20.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 21. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] PCF85162 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 16 June 2011 © NXP B.V. 2011. All rights reserved. 45 of 46 PCF85162 NXP Semiconductors Universal LCD driver for low multiplex rates 22. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.3.1 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.5 7.5.1 7.5.2 7.6 7.7 7.8 7.9 7.10 7.10.1 7.10.2 7.10.3 7.10.4 7.10.5 7.11 7.12 7.13 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9 10 11 12 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 6 LCD bias generator . . . . . . . . . . . . . . . . . . . . . 6 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 6 Electro-optical performance . . . . . . . . . . . . . . . 8 LCD drive mode waveforms . . . . . . . . . . . . . . 10 Static drive mode . . . . . . . . . . . . . . . . . . . . . . 10 1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 11 1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 13 1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 14 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 15 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 15 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Display register . . . . . . . . . . . . . . . . . . . . . . . . 15 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 15 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 15 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Subaddress counter . . . . . . . . . . . . . . . . . . . . 18 RAM writing in 1:3 multiplex drive mode. . . . . 19 Output bank selector . . . . . . . . . . . . . . . . . . . 20 Input bank selector . . . . . . . . . . . . . . . . . . . . . 20 Blinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Command decoder . . . . . . . . . . . . . . . . . . . . . 21 Display controller . . . . . . . . . . . . . . . . . . . . . . 23 Characteristics of the I2C-bus . . . . . . . . . . . . 24 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 START and STOP conditions . . . . . . . . . . . . . 24 System configuration . . . . . . . . . . . . . . . . . . . 24 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 25 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 26 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 26 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 28 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 29 Static characteristics. . . . . . . . . . . . . . . . . . . . 30 Dynamic characteristics . . . . . . . . . . . . . . . . . 32 13 13.1 14 15 16 16.1 16.2 16.3 16.4 17 18 19 20 20.1 20.2 20.3 20.4 21 22 Application information . . . . . . . . . . . . . . . . . Cascaded operation. . . . . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 34 38 39 39 39 39 40 40 41 42 43 44 44 44 44 45 45 46 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 16 June 2011 Document identifier: PCF85162