ADC to Filter – Dual Channel 16-Bit Streaming using DMA – PSoC® 3 / PSoC 5 EP58353 Associated Part Families CY8C38xx/CY8C55xx ® Software: PSoC Creator™ Related Hardware: CY8CKIT-001 Author: Anu MD Project Objective This project demonstrates dual channel 16-bit streaming from ADC to filter using DMA. Overview This example project demonstrates how to stream 16-bit data from ADC to filter using DMA. It also demonstrates how to enable dual channel filtering and stream in data through both the channels simultaneously. The Project implements two simultaneous channels of the filter, one implementing a low pass and other a band stop filter. 8 bit Filter LPF channel Signal In ADC VDAC Low pass Filter out 16 bit 8 bit Filter BSF channel VDAC Band Stop Filter out Component List Instance Name Component Name Component Category Comments ADC_DelSig ADC_DelSig Analog ADC Filter Filter Filters – – VDAC8_LPF Voltage DAC Analog DAC – VDAC8_BSF Voltage DAC Analog DAC – DMA_ADC2Filter DMA System – DMA_LPF2VDAC DMA System – Pin_SigInput Analog Pin Ports and Pins – Pin_LPF_Out Analog Pin Ports and Pins – Pin_BSF_Out Analog Pin Ports and Pins – January 24, 2011 Document No. 001-58353 Rev. *C 1 [+] Feedback EP58353 Top Design The following figure shows the components and their routing. The following figure shows the Pin Placement (as in the .cydwr file). Component Configuration ADC This is configured as single ended 0 V to 2.048 V, 16-bit, 48 ksps ADC. January 24, 2011 Document No. 001-58353 Rev. *C 2 [+] Feedback EP58353 Filter Both the channels of the filter are enabled and configured as shown in the following figure. Channel A Configured as a LPF with 1 kHz cut off frequency. Channel B Click Channel B tab, Channel B is configured as a BSF with 3 kHz center frequency. January 24, 2011 Document No. 001-58353 Rev. *C 3 [+] Feedback EP58353 VDAC8 The VDACs, VDAC8_LPF, and VDAC8_BSF take the following configuration. Note that the ADC is configured for an input range of 0 V to 2.048 V, whereas the DAC is configured in the range of 0 to 1.024 V. Therefore, there is corresponding scaling in the output of the DAC. DMA The three DMA components on this project should have their configuration completed using the DMA wizard. The DMA wizard generates the code that has to be placed in the user code area for configuring the DMA channel. For more information on DMA Wizard, refer to Using DMA on PSoC 3 / PSoC 5 – AN52705. Following are the steps for setting up one of the DMA channels. Step 1: Selecting DMA Channel Select the DMA wizard under the Tools menu. This opens a window for channel selection. January 24, 2011 Document No. 001-58353 Rev. *C 4 [+] Feedback EP58353 Select the DMA_ADC2Filter channel that requires configuration. Step 2: DMA Initialization Here, the source for the first channel is set as the ADC and destination is the staging registers of the filter. . The transformation here is two bytes per burst and every burst is triggered by a request. Two transaction descriptors (TD) are assigned, one each for each of the filter channels in the filter component. Step 3: TD Configuration January 24, 2011 Document No. 001-58353 Rev. *C 5 [+] Feedback EP58353 In this case, the TDs are configured to transfer two bytes. The source is set as the ADC sample register. The first TD is configured to a destination stage A (first filter channel input) register of the filter with source and destination increment option enabled. The Auto next is enabled so as to automatically activate the next TD. The second TD is configured similar to the first but the destination is to stage B (second filter channel input) register of the filter. After the input stage DMA channel is configured we configure the output stage DMAs from the filter outputs to the VDACs. The first one is the DMA_LPF2VDAC where the Filter is set as source and VDAC8_LPF as the destination with single byte transfers. January 24, 2011 Document No. 001-58353 Rev. *C 6 [+] Feedback EP58353 The source is set as the Filter_HOLDAM_PTR and the destination is the VDAC8_LPF_Data_PTR. This acts as the DMA, transferring the data from the low pass filter channel (Channel A) of the filter to the corresponding VDAC. The next DMA_BSF2VDAC is configured similarly with single-byte bursts. The only difference is, the source is Filter_HOLDBM_PTR and the destination is VDAC8_BSF_Data_PTR. Design Wide Resources The project uses the default configuration of design wide resources. Refer to Filter_8bitStreaming.cydwr file. Operation This project demonstrates how to stream in 16-bit ADC data through filter. The default coherency setting of Filter component has to be modified for proper streaming of data using DMA. Filter Coherency The DFB staging register (DFB is the block that implements the Filter component) coherency key byte should be set to the byte that is written last. The DFB Filter component sets the default coherency key as the High byte. It should be changed to middle byte as DMA reads or writes low byte followed by high byte in the staging register. Refer to DFB[0..0]_COHER register to learn more about filter coherency settings (Refer to the TRM register book for details) /*Filter Coherency set to mid byte */ Filter_COHER_REG = 0x55; The data is transferred from the middle byte of the 24-bit output holding register. This is to avoid the sign bit present in the MSB. It is for the same reason the Coherency bits are set for a middle coherency. DMA moves data through the signal chain. The DMA channel ‘DMA_ADC2Filter’ transfers 16-bit data from the ADC to the Filter. The filter in this example implements two simultaneous filters whose data inputs are provided at the staging registers A and B. Hence the DMA TDs, ADC2Filter_TD1 and ADC2Filter_TD2, are each configured to transfer data to Stage register A and Stage register B respectively. The DMA channels, DMA_LPF2VDAC and DMA_BSF2VDAC are each configured to transfer data from each of the respective channel output holding registers of the Filter out to the respective VDACs. Since the output is going to the VDAC, the data transfer is just 8-bits wide. Since the reconstruction of the analog waveform is achieved using the VDAC which is single ended the whole signal chain follows an offset binary structure. The offset in the signal is maintained as long as the filter implementation in the example does not attenuate the DC content in the waveform. For this reason, this example is not able to successfully reproduce the filter output in case of implementing a High pass or Band pass filter, since in those cases the offset is nullified. One way to reconstruct a high pass or Band pass filtered signal is by deliberately adding an offset in the signal before feeding it to the VDAC. January 24, 2011 Document No. 001-58353 Rev. *C 7 [+] Feedback EP58353 Hardware Connections This project can be tested on the CY8CKIT-001 development board. The following connections are done on the board to make the project work. Connect Signal Generator output to Pin P0_0. Make sure that output amplitude is varying between 0 V to 2 V. Do not feed negative voltage to ADC input. Check the filtered output on Pin P3[4] and P3[5] by connecting the oscilloscope For rest of the basic settings of the DVK, refer to the CY8CKIT-001 PSoC Development Kit Board Guide supplied with the kit. Output Use device selector (Project Device Selector) window in PSoC Creator to select the appropriate device and Device Revision. If you are using PSoC3 device (example CY8C3866AXI-040) with production revision, then use the following selection. Similarly, select appropriate device number to work with PSoC5 Device family (example CY8C5588AXI-060) Note For engineering samples, device revision is marked on the package as part of the device number. Production silicon will not have ES marking. January 24, 2011 Document No. 001-58353 Rev. *C 8 [+] Feedback EP58353 Build the Project and Program the chip The input is provided as a sine waveform form a function generator at pin 3[0]. The input amplitude need to be under 2 V with an offset of 1 V. Vary the signal frequency from 0 to 10 kHz. Observe low pass filter (LPF) response (1 kHz cutoff frequency) at pin P3[4] Observe band stop filter (BSF) response (3 kHz notch frequency) at P3[5]. Observe the dip in signal amplitude when the input signal frequency is closer to 3 kHz. Suggested Application Notes/Example Projects Using DMA on PSoC 3 / PSoC 5 – AN52705. January 24, 2011 Document No. 001-58353 Rev. *C 9 [+] Feedback EP58353 Document History ® Document Title: ADC to Filter – Dual Channel 16-Bit Streaming using DMA - PSoC 3 / PSoC 5 Document Number: 001-58353 Revision ECN Orig. of Change Submission Date ** *A 2828375 2941722 ANMD ANMD 12/16/2009 06/03/2010 *B *C 3012567 3137300 ANMD ANMD 08/25/2010 01/24/2011 Description of Change New Spec. Updated to PSoC Creator Beta 4.1 and made the projects PSoC 5 compatible Technical Updates Added Document History Page in the document. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. January 24, 2011 Document No. 001-58353 Rev. *C 10 [+] Feedback