ATMEL AT28HC256E

Features
• Fast Read Access Time - 70 ns
• Automatic Page Write Operation
•
•
•
•
•
•
•
•
•
– Internal Address and Data Latches for 64 Bytes
– Internal Control Timer
Fast Write Cycle Times
– Page Write Cycle Time: 3 ms or 10 ms Maximum
– 1 to 64-Byte Page Write Operation
Low Power Dissipation
– 80 mA Active Current
– 3 mA Standby Current
Hardware and Software Data Protection
DATA Polling for End of Write Detection
High Reliability CMOS Technology
– Endurance: 104 or 105 Cycles
– Data Retention: 10 Years
Single 5V ± 10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-Wide Pinout
Full Military, Commercial, and Industrial Temperature Ranges
256 (32K x 8)
High Speed
Parallel
EEPROMs
AT28HC256
Description
The AT28HC256 is a high-performance Electrically Erasable and Programmable
Read Only Memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the AT28HC256
(continued)
Pin Configurations
TSOP
Top View
Pin Name
Function
A0 - A14
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
NC
No Connect
DC
Don’t Connect
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
14
15
16
17
18
19
20
5
6
7
8
9
10
11
12
13
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
I/O1
I/O2
GND
DC
I/O3
I/O4
I/O5
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CERDIP, PDIP, FLATPACK
Top View
A7
A12
A14
DC
VCC
WE
A13
LCC, PLCC
Top View
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
PGA
Top View
Rev. 0007G–10/98
Note: PLCC package pins 1 and
17 are DON’T CONNECT.
1
offers access times to 70 ns with power dissipation of just
440 mW. When the AT28HC256 is deselected, the standby
current is less than 5 mA.
The AT28HC256 is accessed like a Static RAM for the read
or write cycle without the need for external components.
The device contains a 64-byte page register to allow writing
of up to 64 bytes simultaneously. During a write cycle, the
address and 1 to 64 bytes of data are internally latched,
freeing the addresses and data bus for other operations.
Following the initiation of a write cycle, the device will automatically write the latched data using an internal control
timer. The end of a write cycle can be detected by DATA
polling of I/O 7 . Once the end of a write cycle has been
detected a new access for a read or write can begin.
Atmel’s 28HC256 has additional features to ensure high
quality and manufacturability. The device utilizes internal
error correction for extended endurance and improved data
retention characteristics. An optional software data protection mechanism is available to guard against inadvertent
writes. The device also includes an extra 64 bytes of
EEPROM for device identification or tracking.
Block Diagram
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
2
AT28HC256
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
AT28HC256
Device Operation
READ: The AT28HC256 is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE or OE is high. This dualline control gives designers flexibility in preventing bus contention in their system.
BYTE WRITE: A low pulse on the WE or CE input with CE
or WE low (respectively) and OE high initiates a write cycle.
The address is latched on the falling edge of CE or WE,
whichever occurs last. The data is latched by the first rising
edge of CE or WE. Once a byte write has been started it
will automatically time itself to completion. Once a programming operation has been initiated and for the duration
of tWC, a read operation will effectively be a polling operation.
PAGE WRITE: The page write operation of the
AT28HC256 allows 1 to 64 bytes of data to be written into
the device during a single internal programming period. A
page write operation is initiated in the same manner as a
byte write; the first byte written can then be followed by 1 to
63 additional bytes. Each successive byte must be written
within 150 µs (tBLC) of the previous byte. If the tBLC limit is
exceeded the AT28C256 will cease accepting data and
commence the internal programming operation. All bytes
during a page write operation must reside on the same
page as defined by the state of the A6 - A14 inputs. That is,
for each WE high to low transition during the page write
operation, A6 - A14 must be the same.
The A0 to A5 inputs are used to specify which bytes within
the page are to be written. The bytes may be loaded in any
order and may be altered within the same load period. Only
bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not
occur.
DATA POLLING: The AT28HC256 features DATA Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be presented
on I/O 7. Once the write cycle has been completed, true
data is valid on all outputs, and the next write cycle may
begin. DATA Polling may begin at anytime during the write
cycle.
TOGGLE BIT: In addition to DATA Polling the AT28HC256
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O 6 toggling
between one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Testing the
toggle bit may begin at any time during the write cycle.
DATA PROTECTION: If precautions are not taken, inadvertent writes to any 5-volt-only nonvolatile memory may
occur during transition of the host system power supply.
Atmel has incorporated both hardware and software features that will protect the memory against inadvertent
writes.
HARDWARE PROTECTION: Hardware features protect
against inadvertent writes to the AT28HC256 in the following ways: (a) VCC sense—if VCC is below 3.8V (typical) the
write function is inhibited; (b) V CC power-on delay—once
VCC has reached 3.8V the device will automatically time out
5 ms typical) before allowing a write; (c) write inhibit—holding any one of OE low, CE high or WE high inhibits write
cycles; and (d) noise filter—pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION: A software controlled
data protection feature has been implemented on the
AT28HC256. When enabled, the software data protection
(SDP), will prevent inadvertent writes. The SDP feature
may be enabled or disabled by the user; the AT28HC256 is
shipped from Atmel with SDP disabled.
SDP is enabled by the host system issuing a series of three
write commands; three specific bytes of data are written to
three specific addresses (refer to Software Data Protection
Algorithm). After writing the 3-byte command sequence
and after t WC the entire AT28HC256 will be protected
against inadvertent write operations. It should be noted,
that once protected the host may still perform a byte or
page write to the AT28HC256. This is done by preceding
the data to be written by the same 3-byte command
sequence.
Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable
SDP and SDP will protect the AT28HC256 during power-up
and power-down conditions. All command sequences must
conform to the page write timing specifications. It should
also be noted that the data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with
data in either a byte or page write operation.
After setting SDP, any attempt to write to the device without
the three byte command sequence will start the internal
write timers. No data will be written to the device; however,
for the duration of tWC, read operations will effectively be
polling operations.
DEVICE IDENTIFICATION: An extra 64 bytes of EEPROM
memory are available to the user for device identification.
By raising A9 to 12V ± 0.5V and using address locations
7FC0H to 7FFFH the additional bytes may be written to or
read from in the same manner as the regular memory
array.
OPTIONAL CHIP ERASE MODE: The entire device can
be erased using a 6-byte software code. Please see Software Chip Erase application note for details.
3
DC and AC Operating Range
Com.
Operating
Temperature (Case)
Ind.
AT28HC256-70
AT28HC256-90
AT28HC256-12
0°C - 70°C
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
-55°C - 125°C
-55°C - 125°C
5V ± 10%
5V ± 10%
Mil.
5V ± 10%
VCC Power Supply
Operating Modes
Mode
CE
OE
WE
I/O
Read
VIL
VIL
VIH
DOUT
VIL
VIH
VIL
DIN
VIH
X(1)
X
High Z
Write Inhibit
X
X
VIH
Write Inhibit
X
VIL
X
Output Disable
X
VIH
X
High Z
Chip Erase
VIL
VH(3)
VIL
High Z
Write
(2)
Standby/Write Inhibit
Notes:
1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC + 1V
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
AT28HC256-90, -12
3
mA
ISB1
VCC Standby Current TTL
CE = 2.0V to VCC + 1V
AT28HC256-70
60
mA
ISB2
VCC Standby Current CMOS
CE = -3.0V to VCC + 1V
AT28HC256-90, -12
300
µA
ICC
VCC Active Current
f = 5 MHz; IOUT = 0 mA
80
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 6.0 mA
VOH
Output High Voltage
IOH = -4 mA
4
Min
2.0
AT28HC256
V
0.45
2.4
V
V
AT28HC256
AC Read Characteristics
AT28HC256-70
Symbol
Parameter
Min
Max
AT28C256-90
Min
Max
AT28HC256-12
Min
Max
Units
Address to Output Delay
70
90
120
ns
(1)
CE to Output Delay
70
90
120
ns
(2)
OE to Output Delay
0
35
0
40
0
50
ns
tDF(3)(4)
CE or OE to Output Float
0
35
0
40
0
50
ns
tOH
Output Hold from OE, CE or Address,
whichever occurred first
0
tACC
tCE
tOE
0
0
ns
AC Read Waveforms(1)(2)(3)(4)
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
COUT
Note:
Typ
Max
Units
Conditions
4
6
pF
VIN = 0V
8
12
pF
VOUT = 0V
1. This parameter is characterized and is not 100% tested.
5
AC Write Characteristics
Symbol
Parameter
tAS, tOES
Address, OE Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tCS
Chip Select Set-up Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
100
ns
tDS
Data Set-up Time
50
ns
tDH, tOEH
Data, OE Hold Time
0
ns
tDV
Note:
Time to Data Valid
1. NR = No Restriction.
AC Write Waveforms
WE Controlled
CE Controlled
6
AT28HC256
Min
(1)
NR
Max
Units
AT28HC256
Page Mode Write Characteristics
Symbol
Parameter
Min
Typ
Max
Units
tWC
Write Cycle Time
AT28HC256
5
10
ms
AT28HC256F
2
3.0
ms
tAS
Address Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tDS
Data Set-up Time
50
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
100
ns
tBLC
Byte Load Cycle Time
tWPH
Write Pulse Width High
150
50
µs
ns
Page Mode Write Waveforms(1)(2)
Notes:
1.
A6 through A14 must specify the same page address during each high to low transition of WE (or CE).
2.
OE must be high only when WE and CE are both low.
Chip Erase Waveforms
tS = tH = 5 µsec (min.)
tW = 10 msec (min.)
VH = 12.0V ± 0.5V
7
Software Data Protection
Enable Algorithm(1)
Software Data Protection
Disable Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
LOAD DATA 80
TO
ADDRESS 5555
WRITES ENABLED(2)
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD DATA AA
TO
ADDRESS 5555
LOAD LAST BYTE
TO
LAST ADDRESS
LOAD DATA 55
TO
ADDRESS 2AAA
ENTER DATA
PROTECT STATE
Notes for software program code:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Write Protect state will be activated at end of
write even if no other data is loaded.
3. Write Protect state will be deactivated at end of
write period even if no other data is loaded.
4. 1 to 64 bytes of data are loaded.
LOAD DATA 20
TO
ADDRESS 5555
EXIT DATA
PROTECT STATE(3)
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
Software Protected Write Cycle Waveforms(1)(2)
Notes:
1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the software
code has been entered.
2. OE must be high only when WE and CE are both low.
8
AT28HC256
AT28HC256
Data Polling Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
Min
Max
OE to Output Delay
tWR
Write Recovery Time
Units
0
ns
0
ns
(2)
tOE
Notes:
Typ
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
tOE
OE to Output Delay(2)
tOEHP
OE High Pulse
tWR
Write Recovery Time
Notes:
Min
Typ
Max
Units
ns
150
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Toggle Bit Waveforms
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit.
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
9
10
AT28HC256
AT28HC256
Ordering Information(1)
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
70
80
60
AT28HC256(E,F)-70JC
AT28HC256(E,F)-70PC
32J
28P6
Commercial
(0°C to 70°C)
0.3
AT28HC256(E,F)-70JI
AT28HC256(E,F)-70PI
32J
28P6
Industrial
(-40°C to 85°C)
0.3
AT28HC256(E,F)-90JC
AT28HC256(E,F)-90PC
32J
28P6
Commercial
(0°C to 70°C)
AT28HC256(E,F)-90JI
AT28HC256(E,F)-90PI
32J
28P6
Industrial
(-40°C to 85°C)
90
120
80
Operation Range
80
0.3
AT28HC256(E,F)-90DM/883
AT28HC256(E,F)-90FM/883
AT28HC256(E,F)-90LM/883
AT28HC256(E,F)-90UM/883
28D6
28F
32L
28U
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
80
0.3
AT28HC256(E,F)-12JC
AT28HC256(E,F)-12PC
AT28HC256(E,F)-12SC
AT28HC256(E,F)-12TC
32J
28P6
28S
28T
Commercial
(0°C to 70°C)
80
0.3
AT28HC256(E,F)-12JI
AT28HC256(E,F)-12PI
AT28HC256(E,F)-12SI
AT28HC256(E,F)-12TI
32J
28P6
28S
28T
Industrial
(-40°C to 85°C)
80
0.3
AT28HC256(E,F)-12DM/883
AT28HC256(E,F)-12FM/883
AT28HC256(E,F)-12LM/883
AT28HC256(E,F)-12UM/883
28D6
28F
32L
28U
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
Package Type
28D6
28-Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline Package (Cerdip)
28F
28-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack)
32J
32-Lead, Plastic J-Leaded Chip Carrier (PLCC)
32L
32-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)
28P6
28-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
28S
28-Lead, 0.300" Wide Plastic Gull Wing Small Outline (SOIC)
28T
28-Lead, Plastic Thin Small Outline Package (TSOP)
28U
28-Pin, Ceramic Pin Grid Array (PGA)
W
Die
Options
Blank
Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
E
High Endurance Option: Endurance = 100K Write Cycles
F
Fast Write Option: Write Time = 3 ms
11
Ordering Information(1) (Continued)
ICC (mA)
tACC
(ns)
Active
Standby
90
80
120
Note:
Ordering Code
Package
0.3
5962-88634 03 UX
5962-88634 03 XX
5962-88634 03 YX
5962-88634 03 ZX
28U
28D6
32L
28F
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
80
0.3
5962-88634 04 UX
5962-88634 04 XX
5962-88634 04 YX
5962-88634 04 ZX
28U
28D6
32L
28F
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
80
0.3
5962-88634 01 UX
5962-88634 01 XX
5962-88634 01 YX
5962-88634 01 ZX
28U
28D6
32L
28F
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
80
0.3
5962-88634 02 UX
5962-88634 02 XX
5962-88634 02 YX
5962-88634 02 ZX
28U
28D6
32L
28F
Military/883C
Class B, Fully Compliant
(-55°C to 125°C)
1. See Valid Part Numbers table on next page.
Package Type
28D6
28-Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline Package (Cerdip)
28F
28-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack)
32J
32-Lead, Plastic J-Leaded Chip Carrier (PLCC)
32L
32-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)
28P6
28-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
28S
28-Lead, 0.300" Wide Plastic Gull Wing Small Outline (SOIC)
28T
28-Lead, Plastic Thin Small Outline Package (TSOP)
28U
28-Pin, Ceramic Pin Grid Array (PGA)
W
Die
Options
Blank
Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
E
High Endurance Option: Endurance = 100K Write Cycles
F
Fast Write Option: Write Time = 3 ms
12
AT28HC256
Operation Range
AT28HC256
Ordering Information Note
Previous data sheets included the low power suffixes L, LE and LF on the At28HC256 for 120 ns and 90 ns speeds.
The low power parameters are now standard; therefore, the L, LE and LF suffixes are no longer required.
Valid Part Numbers
The following table lists standard Atmel products that can be ordered:
Device Numbers
Speed
Package and Temperature Combinations
AT28HC256
70
JC, JI, PC, PI
AT28HC256
90
JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883
AT28HC256E
90
JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883
AT28HC256F
90
JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883
AT28HC256
12
JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883
AT28HC256E
12
JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883
AT28HC256F
12
JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883
Die Products
Reference Section: Parallel EEPROM Die Products
13
Packaging Information
28D6, 28-Lead, 0.600" Wide, Non-Windowed,
Ceramic Dual Inline Package (Cerdip)
Dimensions in Inches and (Millimeters)
28F, 28-Lead, Non-Windowed, Ceramic BottomBrazed Flat Package (Flatpack)
Dimensions in Inches and (Millimeters)
MIL-STD-1835 D-10 CONFIG A
MIL-STD-1835 F-12 CONFIG B
1.49(37.9)
1.44(36.6)
PIN
1
.370(9.40)
.250(6.35)
PIN #1 ID
.019(.483)
.015(.381)
.610(15.5)
.510(13.0)
.098(2.49)
MAX
1.300(33.02) REF
.050(1.27) BSC
.728(18.5)
.712(18.1)
.045(1.14) MAX
.005(.127)
MIN
.225(5.72)
MAX
SEATING
PLANE
.200(5.08)
.125(3.18)
.060(1.52)
.015(.381)
.023(.584)
.014(.356)
.065(1.65)
.045(1.14)
.110(2.79)
.090(2.29)
.620(15.7)
.590(15.0)
.006(.152)
.004(.102)
.119(3.02)
.087(2.21)
.077(1.96)
.043(1.09)
0 REF
15
.015(.381)
.008(.203)
.416(10.6)
.384(9.75)
.286(7.26)
.274(6.96)
.045(1.14)
.026(.660)
.700(17.8) MAX
32J, 32-Lead, Plastic J-Leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
32L, 32-Pad, Non-Windowed, Ceramic Leadless
Chip Carrier (LCC)
Dimensions in Inches and (Millimeters)*
MIL-STD-1835 C-12
.045(1.14) X 45°
PIN NO. 1
IDENTIFY
.025(.635) X 30° - 45°
.012(.305)
.008(.203)
.553(14.0)
.547(13.9)
.595(15.1)
.585(14.9)
.032(.813)
.026(.660)
.050(1.27) TYP
.530(13.5)
.490(12.4)
.021(.533)
.013(.330)
.300(7.62) REF
.430(10.9)
.390(9.90)
AT CONTACT
POINTS
.030(.762)
.015(3.81)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
.022(.559) X 45° MAX (3X)
.453(11.5)
.447(11.4)
.495(12.6)
.485(12.3)
*Controlling dimension: millimeters
14
AT28HC256
AT28HC256
Packaging Information
28P6, 28-Lead, 0.600" Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)
28S, 28-Lead, 0.300" Wide, Plastic Gull Wing Small
Outline (SOIC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-011 AB
1.47(37.3)
1.44(36.6)
PIN
1
.566(14.4)
.530(13.5)
.090(2.29)
MAX
1.300(33.02) REF
.220(5.59)
MAX
.005(.127)
MIN
SEATING
PLANE
.065(1.65)
.015(.381)
.022(.559)
.014(.356)
.161(4.09)
.125(3.18)
.110(2.79)
.090(2.29)
.012(.305)
.008(.203)
.065(1.65)
.041(1.04)
.630(16.0)
.590(15.0)
0 REF
15
.690(17.5)
.610(15.5)
28T, 28-Lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches)*
28U, 28-Pin, Ceramic Pin Grid Array (PGA)
Dimensions in Inches and (Millimeters)
INDEX
MARK
AREA
11.9 (0.469)
11.7 (0.461)
13.7 (0.539)
13.1 (0.516)
0.27 (0.011)
0.18 (0.007)
0.55 (0.022)
BSC
7.15 (0.281)
REF
8.10 (0.319)
7.90 (0.311)
1.25 (0.049)
1.05 (0.041)
0.20 (0.008)
0.10 (0.004)
0
5 REF
0.20 (0.008)
0.15 (0.006)
0.70 (0.028)
0.30 (0.012)
*Controlling dimension: millimeters
15
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© Atmel Corporation 1998.
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