Features • • • • • • • • • Supply Voltage Range 3V to 4.6V (Unregulated) Auxiliary Voltage Regulator On-chip Low Current Consumption Few Low Cost External Components No Mechanical Tuning Required Non-blindslot and Blindslot Operation Unlimited Multislot Operation with Advanced Closed-loop Modulation Supports Multiple Reference Clocks (10.368 MHz/13.824 MHz/20.736 MHz) TX Preamplifier with 0 dBm Output Power at 1.9 GHz and Ramp-signal Generator for SiGe Power Amplifier 1. Description The T2801 is an RF IC for low-power DECT applications. The QFN48 packaged IC is a complete transceiver including image rejection mixer, IF amplifier, FM demodulator, baseband filter, RSSI, TX preamplifier, power-ramping generator for power amplifiers, integrated synthesizer, fully integrated VCO, TX filter and modulation compensation circuit for advanced closed-loop modulation concept. No mechanical tuning is necessary in production. Figure 1-1. DECT Single-chip Transceiver T2801 Block Diagram DEMOD MIXER IF_IN OUT IF_TANK IF AMP 1 IR MIXER CF TANK IF AMP 2 BB_OUT RF_IN DEMOD BB FILTER RAMP_OUT RAMP_SET D/A RAMP GEN DEMOD DAC RSSI RSSI GF VCO TX / RX SWITCH TX_DATA PC PD MCC 3-WIRE BUS CLOCK DATA ENABLE RC CTRL LOGIC RX_ON TX_ON PU_RX/TX PU_PLL f TX_OUT :n TX DRIVER PU_VCO VCO REG AUX REG CP VREG_VCO VS_VCO VREG VS_REG VTUNE GND_VCO PU_REG REG_CTRL f :n CP LD REF_CLK I_CPSW Rev. 4567B–DECT–03/06 Table 1-1. Functional Block Description Name Description AUX REG Auxiliary voltage regulator BBF Baseband filter CP Charge pump DAC D/A converter for demodulator tuning DEMOD Demodulator GF Gaussian filter for transmit data IF AMP1 1st intermediate frequency amplifier IF AMP2 2nd intermediate frequency amplifier IR MIXER Image rejection mixer MCC Modulation compensation circuit PC Programmable counter PD Phase detector RAMP GEN Ramp-signal generator RC Reference counter RSSI Received signal-strength indicator TX DRIVER Buffer amplifier for TX_OUT TX/RX SWITCH Switches VCO signal to IR mixer resp. TX driver VCO Voltage-controlled oscillator VCO REG Voltage regulator for VCO 2 T2801 4567B–DECT–03/06 T2801 2. Pin Configuration I_CPSW TX_DATA PU_PULL PU_RX/TX PU_VCO GND_PLL VS_MIXER MIXER_OUT2 MIXER_OUT1 TX_ON RX_ON RAMP_SET Pinning QFN48 48 47 46 45 44 43 42 41 40 39 38 37 CLOCK 1 36 RAMP_OUT DATA 2 35 IF_IN2 ENABLE 3 34 IF_IN1 REF_CLK 4 33 VS_IF LD 5 32 TX_OUT PU_REG 6 31 GND3 VS_PLL 7 30 RF_IN2 VREG 8 29 RF_IN1 REG_CTRL 9 28 GND2 VS_REG 10 27 IF_TANK2 GND_CP 11 26 IF_TANK1 VS_CP 12 25 RSSI 13 14 15 16 17 18 19 20 21 22 23 24 VS_VCO VREG_VCO GND_VCO VTUNE GND1 DEMOD_TANK1 DEMOD_TANK2 DAC_DEC REG_DEC BB_CF BB_OUT T2801 CP Figure 2-1. 3 4567B–DECT–03/06 Table 2-1. Pin Pin Description Symbol Function Configuration VS_PLL 7 1 2 3 CLOCK DATA ENABLE 3-wire-bus: Clock input 3-wire-bus: Data input 3-wire-bus: Enable input CLOCK DATA ENABLE 1,2,3 5k 5k GND_PLL 43 VS_PLL 7 4 REF_CLK 10k 10k Reference-frequency input REF_CLK 4 GND_PLL 43 LD 5 100 5 LD Lock-detect output GND_PLL 43 PU_REG 6 6 PU_REG 25k Power-up input for auxiliary voltage regulator 25k GND_PLL 43 4 T2801 4567B–DECT–03/06 T2801 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration VS_PLL 7 VS_REG 10 VS_CP 12 GND1 18 GND2 28 VS_VCO 14 7 VS_PLL GND3 31 PLL supply voltage VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 VS_REG 10 VS_PLL 7 REG_CTRL 9 VREG 8 8 9 10 VREG REG_CTRL VS_REG Auxiliary voltage-regulator output Auxiliary voltage-regulator control output Auxiliary voltage-regulator supply voltage GND_PLL 43 VS_CP 12 VS_PLL 7 11 12 13 GND_CP VS_CP CP Charge-pump ground Charge-pump supply voltage Charge-pump output CP 13 GND_PLL 43 GND_CP 11 5 4567B–DECT–03/06 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration VS_VCO 14 VS_PLL 7 14 15 16 VS_VCO VREG_VCO GND_VCO VREG_VCO 15 VCO voltage-regulator supply voltage VCO voltage-regulator control output VCO ground GND_PLL 43 GND_VCO 16 VREG_VCO 15 VS_PLL 7 17 VTUNE VCO tuning voltage input VTUNE 17 GND_PLL 43 GND_VCO 16 VS_PLL 7 VS_REG 10 VS_CP 12 VS_VCO 14 18 GND1 Ground VS_IF 33 GND1 18 GND2 28 GND3 31 GND_VCO 16 GND_CP 11 VS_MIXER 42 6 GND_PLL 43 T2801 4567B–DECT–03/06 T2801 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration VS_MIXER 42 VS_IF 33 10k 19 20 DEMOD_TANK1 DEMOD_TANK2 Demodulator tank circuit Demodulator tank circuit 10k DEMOD TANK1 19 DEMOD TANK2 20 GND2 28 GND1 18 VREG_VCO 15 VS_PLL 7 21 DAC_DEC Decoupling pin for VCO_DAC 10k DAC_DEC 21 GND_PLL 43 GND_VCO 16 400 VREG_VCO 15 VS_IF 33 22 REG_DEC Decoupling pin for VCO_REG 2k REG_DEC 22 GND2 28 42k GND_VCO 16 7 4567B–DECT–03/06 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration VS_IF 33 23 BB_CF Baseband filter corner-frequency control input BB_CF 23 GND2 28 GND1 18 VS_IF 33 24 BB_OUT Baseband filter output BB_OUT 24 GND2 28 GND1 18 VS_IF 33 25 RSSI Received signal-strength indicator output RSSI 25 13k GND2 28 VS_IF 33 26 27 IF_TANK1 IF_TANK2 IF tank circuit IF tank circuit RSSI 25 13k GND2 28 8 T2801 4567B–DECT–03/06 T2801 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration VS_PLL 7 VS_REG 10 VS_CP 12 VS_VCO 14 28 GND2 Ground VS_IF 33 GND1 18 GND2 28 GND3 31 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 VS_MIXER 42 29 30 RF_IN1 RF_IN2 RF input of image reject mixer RF input of image reject mixer RF_IN1 29 RF_IN2 30 GND2 28 VS_PLL 7 VS_REG 10 VS_CP 12 VS_VCO 14 31 GND3 Ground VS_IF 33 GND1 18 GND2 28 GND3 31 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 9 4567B–DECT–03/06 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration TX_OUT 32 32 TX_OUT TX driver amplifier output for PA GND3 31 VS_PLL 7 VS_REG 10 VS_CP 12 GND1 18 GND2 28 VS_VCO 14 33 VS_IF GND3 31 IF amplifier supply voltage VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 VS_IF 33 34 35 IF_IN1 IF_IN2 IF input of IF amplifier IF input of IF amplifier IF_IN1 34 IF_IN2 35 4.3k GND2 28 VS_MIXER 42 VS_IF 33 36 RAMP_OUT Ramp-generator output for PA power ramping RAMP_OUT 36 GND2 28 10 T2801 4567B–DECT–03/06 T2801 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration VS_MIXER 42 VS_IF 33 37 RAMP_SET RAMP SET 37 Slew-rate setting of ramping signal 1k 100 GND2 25 VS_IF 33 38 39 RX_ON TX_ON RX control input TX control input RX_ON TX_ON 38, 39 5k 5k GND2 28 GND1 18 VS_MIXER 42 VS_IF 33 40 41 MIXER_OUT1 MIXER_OUT2 Mixer output to SAW filter Mixer output to SAW filter MIXER_ OUT1 40 270 270 MIXER_ OUT2 41 GND2 28 11 4567B–DECT–03/06 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration VS_PLL 7 VS_REG 10 VS_CP 12 GND1 18 GND2 28 VS_VCO 14 42 43 VS_MIXER GND_PLL GND3 31 Mixer supply voltage PLL ground VS_IF 33 GND_VCO 16 GND_CP 11 VS_MIXER 42 GND_PLL 43 VS_VCO 14 44 PU_VCO VCO power-up input PU_VCO 44 5k 5k GND_PLL 7 GND_VCO 16 PU_RX/TX 45 45 PU_RX/TX 25k 25k RX/TX power-up input GND_PLL 7 GND1 18 12 T2801 4567B–DECT–03/06 T2801 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration PU_RX/TX 45 46 PU_PLL 25k 25k PLL power-up input GND_PLL 7 GND1 18 VS_PLL 7 47 TX_DATA TX data input of Gaussian filter and modulation-compensation circuit TX_DATA 47 5k 5k GND_PLL 43 VS_PLL 7 48 I_CPSW Charge pump switch input controls charge pump current I_CPSW 48 5k GND_PLL 43 13 4567B–DECT–03/06 3. Functional Description 3.1 Receiver The RF signal at RF_IN is fed to an image rejection mixer IR_MIXER with its differential outputs MIXER_OUT1 and MIXER_OUT2 driving an IF-SAW filter at 110.592 MHz or 112.32 MHz. The IF amplifiers IF_AMP1 and IF_AMP2 with an external IF_TANK and an integrated RSSI function feed the signal to the demodulator DEMOD working at f = fIF/2 ([55 MHz) and finally to an integrated baseband filter BB. For demodulator tuning in production, an integrated 5-bit Digital-to-Analog (D/A) converter is provided to control the on-chip varicap diode. 3.2 Transmitter The transmit data at TX_DATA is filtered by an integrated Gaussian Filter (GF) and fed to the fully integrated VCO operating at twice the output frequency. After modulation, the signal is frequency-divided by 2 and fed via a TX/RX SWITCH to the TX_DRIVER. This bus-controlled driver amplifier supplies typical +3 dBm output power at TX_OUT. An integrated ramp-signal generator, RAMP_GEN, provides a ramp signal at RAMP_OUT for the external power amplifier. The slope of the ramp signal is controlled by a capacitor at the RAMP_SET pin. 3.3 Synthesizer The IR_MIXER, the TX_DRIVER and the programmable counter PC are driven by the fully integrated VCO (including on-chip inductors and varactors). An 3-bit digital-to-analog converter is used to pretune the frequency. The output signal is frequency-divided to supply the desired frequency to the TX_DRIVER, 0/90 degree phase shifter for the IR_MIXER and to be used by the PC for the phase detector PD (fPD = 3.456 MHz). Unlimited multislot operation is possible by using the integrated advanced closed-loop modulation concept based on the modulation compensation circuit MCC. 3.4 Power Supply An integrated bandgap-stabilized voltage regulator for use with an external low-cost PNP transistor is implemented. Multiple power-down and current saving modes are provided. 14 T2801 4567B–DECT–03/06 T2801 Figure 3-1. PLL Principle RF_IN Programable counter PC "- Main counter MC "- Swallow counter SC fVCO = fPD x (SMC x 32 + SSC) fVCO ext. loop filter PA driver Phase frequency detector PD fPD = 3.456 MHz Charge pump Divider by 2 VCO Mixer VCO DAC GF_DATA Controlled phase shifting Reference counter RC REF_CLK SMC 10.368MHz 13.824MHz 20.736MHz 3 4 6 Modulation compensation MCC Gaussian filter GF 6.912 MHz 1.152 Mbit/s PLL reference Frequency REF_CLK TX_DATA Baseband controller 15 4567B–DECT–03/06 Table 3-1 shows the LO frequencies for RX and TX for the DECT band plus additional channels for the extended DECT band. Intermediate frequencies of 110.592 MHz and 112.32 MHz are supported. Table 3-1. LO Frequencies Mode fIF/MHz Channel fANT/MHz fVCO/MHz SMC SSC TX C9 1881.792 1881.792 34 1 TX C8 1883.520 1883.520 34 2 TX ... ... ... ... ... TX C1 1895.616 1895.616 34 9 TX C0 1897.344 1897.344 34 10 TX C10 1899.072 1899.072 34 11 TX C11 1900.800 1900.800 34 12 TX ... ... ... ... ... TX C29 1931.904 1931.904 34 30 TX C30 1933.632 1933.632 34 31 RX 110.592 C9 1881.792 1771.200 32 1 RX 110.592 C8 1883.520 1772.928 32 2 RX 110.592 ... ... ... ... ... RX 110.592 C1 1895.616 1785.024 32 9 RX 110.592 C0 1897.344 1786.752 32 10 RX 110.592 C10 1899.072 1788.480 32 11 RX 110.592 C11 1900.800 1790.208 32 12 RX 110.592 ... ... ... ... ... RX 110.592 C29 1931.904 1821.312 32 30 RX 110.592 C30 1933.632 1823.040 32 31 RX 112.320 C9 1881.792 1769.472 32 0 RX 112.320 C8 1883.520 1771.200 32 1 RX 112.320 ... ... ... ... ... RX 112.320 C1 1895.616 1783.296 32 8 RX 112.320 C0 1897.344 1785.024 32 9 RX 112.320 C10 1899.072 1786.752 32 10 RX 112.320 C11 1900.800 1788.480 32 11 RX 112.320 ... ... ... ... ... RX 112.320 C29 1931.904 1819.584 32 29 RX 112.320 C30 1933.632 1821.312 32 30 Formula: TX: fANT = fVCO = 1.728 MHz x (32 x SMC + SSC) RX: fANT = 1.728 MHz x (32 x SMC + SSC) + fIF 16 T2801 4567B–DECT–03/06 T2801 4. Control Signals Table 4-1. Control Signals – Functions Signal Function I_CPSW Controls the charge pump current PU_REG Activates AUX voltage regulator supplying the complete transceiver PU_VCO Activates VCO voltage regulator which supplies only the VCO PU_RX/TX Activates RX/TX blocks PU_PLL Activates PLL circuits: PC, PD, CP, RC RX_ON Activates RX circuits: BBF, DEMOD, IF AMP, IR MIXER TX_ON Activates TX circuits: TX–DRIVER, RAMP GEN. Starts RAMP SIGNAL at RAMP OUT Data Word 1, Bit D10 Activates GF in TX mode Data Word 1, Bit D9 Activates MCC in TX mode Table 4-2. Control Signals – Modes Mode TX Mode RX Mode RSSI Only PU_REG 1 1 1 PU_VCO 1 1 1 PU_RX/TX 1 1 1 PU_PLL 1 1 1 RX_ON 0 1 1 TX_ON 1 0 1 BB filter OFF ON OFF Demodulator OFF ON OFF IF amplifiers and RSSI OFF ON ON IR mixer OFF ON ON RX switch OFF ON ON TX switch ON OFF OFF TX driver ON OFF OFF Ramp generator ON OFF OFF Programmable counter ON ON ON Voltage-controlled oscillator ON ON ON Gaussian filter ON OFF OFF Phase detector/charge pump ON ON ON Modulation compensation circuit ON OFF OFF Reference counter ON ON ON Typical current consumption/mA at VS = 3.2 V 54 85 80 17 4567B–DECT–03/06 5. Serial Programming Bus The transceiver is programmed by the 3-wire bus (CLOCK, DATA and ENABLE). After setting enable signal to low condition, on the rising edge of the clock signal, the data is transferred bit by bit into the shift register, starting with the MSB-bit. After enable returning to high condition, the programmed information is loaded into the addressed latches, according to the addressbit condition (last bit). Additional leading bits are ignored and there is no check made on how many pulses arrived during enable-low condition. During enable low condition, the bus current is increased to speed up the bus logic. The programming of the transceiver is separated into two data words. Data word 1 controls mainly the channel information together with settings, which are closely related with the channel. Data word 2 holds setup information, which is adjusted during production. 5.1 Data Word 1 MSB LSB Data Bits Add. bit D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 RC 5.2 SC MC D12 D11 D10 D9 VCOs 1 1 D8 D7 D6 D5 D4 D3 D2 D1 D0 A0 GF MCC GFCS CPCS GF 1 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 Data Word 2 DEMODDAC 18 VCODAC MCCS TEST A0 0 T2801 4567B–DECT–03/06 T2801 6. Data Word 1 Programs 6.1 PLL Settings Table 6-1. With the Reference Counter Bits D21-D22 RC (Referene Counter) D22 D21 SRC REF_CLK (MHz) 0 0 3 10.638 0 1 4 13.824 1 0 6 20.736 Table 6-2. With the Main Counter Bits D14-D15 MC (Main Counter) Table 6-3. D15 D14 SRC 0 0 32 0 1 33 1 0 34 1 1 35 With the Swallow Counter Bits D16-D20 SC (Swallow Counter) D20 D19 D18 D17 D16 SSC 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 1 1 1 0 1 29 1 1 1 1 0 30 1 1 1 1 1 31 ... 6.2 ... VCO Select (RX/TX VCO) Table 6-4. Note: With bit D13 D13 VCOS (VCO Select) 0 RX-VCO 1 TX-VCO Used to switch between RX/TX VCO 19 4567B–DECT–03/06 6.3 Gaussian Filter On/Off Table 6-5. Note: 6.4 With bit D10 D10 GF (Gaussian Filter) 0 OFF 1 ON GF is used only in TX mode Modulation Compensation Circuit On/Off Table 6-6. Note: 6.5 With bit D9 D9 MCC (Modulation Compensation Circuit) 0 OFF 1 ON MCC is used only in TX mode GFCS Adjustment Table 6-7. With bit D6 - D8 GFCS(Gaussian Filter Settings) Note: 20 D8 D7 D6 GFCS (%) 0 0 0 60 0 0 1 70 0 1 0 80 0 1 1 90 1 0 0 100 1 0 1 110 1 1 0 120 1 1 1 130 Only in TXmode effective for setting the frequency deviation of the modulation T2801 4567B–DECT–03/06 T2801 6.6 VCO_DAC Adjustment Table 6-8. With bit D3 - D5 Pretune DAYC Voltage Note: 6.7 D5 D4 D3 fVCO/% 0 0 0 -5 0 0 1 ... 0 1 0 ... 0 1 1 ... 1 0 0 ... 1 0 1 ... 1 1 0 ... 1 1 1 5 Used to pretune the VCO frequency in case of production tolerances of the device. Tuning voltage in locked condition should be around 1.8V at room temperature. This gives margin for ambient temperature changes CPCS Adjustment Table 6-9. With bit D0 - D2 CPCS (Charge-pump Current Settings) Note: D2 D1 D0 CPCS 0 0 0 –4 0 0 1 –3 0 1 0 –2 0 1 1 –1 1 0 0 0 1 0 1 1 1 1 0 2 1 1 1 3 Used to adjust the charge pump current. This can be used to compensate the change of the tuning sensitivity over frequency and device tolerances 21 4567B–DECT–03/06 7. Data Word 2 Programs 7.1 DEMODDAC Adjustment Table 7-1. With bits E6 - E10 Demod DAC Voltage E10 E9 E8 E7 E6 fIFcenter (%) 0 0 0 0 0 –5 0 0 0 0 1 ... 0 0 0 1 0 ... 1 1 1 0 1 ... 1 1 1 1 0 ... 1 1 1 1 1 5 ... Note: 7.2 Only in RX mode effective. Used to tune the demodulator center frequency and allows to compensate tolerances of extenal components and the T2801 MCCS Adjustment Table 7-2. With bits E3 - E5 MCCS (Modulation Compensation Settings) Note: 22 E5 E4 E3 MCCS (%) 0 0 0 60 0 0 1 70 0 1 0 80 0 1 1 90 1 0 0 100 1 0 1 110 1 1 0 120 1 1 1 130 Only in TX mode effective. Adjusts the modulation compensation circuit for closed loop modulation. This adjustment is done with a test sequence of a long stream of ,1' - ,0'. The correct setting is achieved, if the modulation is not affected by the PLL T2801 4567B–DECT–03/06 T2801 7.3 TEST Mode Settings Table 7-3. D11 E2 E1 E0 Signal at Lock Detect Output CP Mode 1 0 0 0 Lock detect Active 0 0 1 0 0 1 RC out/2 Active 1 0 PC out/2 Active X 0 1 1 MCCTEST: RC out diviced by 512 Active 1 1 0 0 Lock detect High imp. 0 1 0 1 RC out/2 High imp. 1 1 1 0 PC out/2 High imp. X 1 1 1 GFTEST: RC out High imp. Note: Figure 7-1. With bit E0 - E2 and D11 In normal operation Lock detect output is used. All other settings are for test only 3-wire Bus Protocol Timing Diagram DATA CLOCK ENABLE TC TPER TL Table 7-4. TS TEC TT TH 3-wire Bus Protocol Description Symbol Minimum Value Unit Clock period TPER 125 ns Set time data to clock TS 60 ns Hold time data to clock TH 60 ns Clock pulse width TC 60 ns Set time enable to clock TL 200 ns Hold time enable to data TEC 0 ns TT 250 ns Time between two protocols Figure 7-2. TX DATA Timing RefCLK TX_DATA TS Table 7-5. TH TX DATA Timing Values Parameters Symbol Value Remarks Set-up time TX DATA TS 10 ns Hold time TX DATA TH 10 ns TS and TH must be considered for both (falling and rising) edges of RefCLK when using REF_CLK = 10.368 MHz. 23 4567B–DECT–03/06 8. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages refer to GND Parameters Symbol Min. Max. Unit Supply voltage regulator, Pin 10 VS_REG 3.2 4.7 V Supply voltage, pins 7, 12, 14, 33 and 42 VS 3.0 4.7 V Logic input voltage, pins 1, 2, 3, 38, 39, 44, 45, 46, 47 and 48 VIN –0.3 VS V 150 °C –40 +150 °C Junction temperature Tjmax Storage temperature TStg 9. Thermal Resistance Parameters Junction ambient Symbol Value Unit RthJA TBD K/W 10. Operating Range Parameters Symbol Min. Typ. Max. Unit Supply voltage regulator, Pins 10 VS_REG 3.2 3.6 4.6 V VS 3.0 3.0 4.6 V Tamb –25 +85 °C Supply voltage, pins 7, 12, 14, 33 and 42 Ambient temperature 24 T2801 4567B–DECT–03/06 T2801 11. Electrical Characteristics Test conditions (unless otherwise specified): VS_REG = 3.2V, Tamb = 25°C Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit IR Mixer, Pins 29, 30, 40 and 41 Ω Input impedance Pins 29 and 30 Zin 50 Input matching Pins 29 and 30 VSWRin < 2:1 Image rejection ratio Pins 40 and 41 IRR 20 dB DSB noise figure Pins 40 and 41 NFDSB = NFSSB 10 dB Conversion gain Rload = 200Ω Gconv 11 dB Input interception point Pins 40 and 41 IIP3 –10 dBm Pins 34 and 35 Zin IF Amplifier, Pins 26, 27, 34 and 35 Input impedance 200 400 Ω Lower cut-off frequency fl3dB 90 Upper cut-off frequency fu3dB 130 MHz Gp 85 dB BW3dB 10 MHz NF 9 dB Power gain Bandwidth of external tank circuit Pins 26 and 27 Noise figure MHz RSSI, Pins 25, 34 and 35 RSSI sensitivity At IF_IN1, IF_IN2 Pins 34 and 35 Pmin 20 dBµV RSSI compression At IF_IN1, IF_IN2 Pins 34 and 35 Pmax 100 dBµV DR 80 dB RSSI dynamic range RSSI resolution Slope of the RSSI has to be steady Acc ±2 dB RSSI rise time Pin = 30 to 100 dBµV, pin 25 tr 1 µs RSSI fall time Pin = 100 to 30 dBµV, pin 25 tf 1 µs Quiescent output voltage At Pin < 20 dBµV at IF_IN1, IF_IN2, pin 25 Iout 0.45 µA Maximum output voltage At Pin = 100 dBµV at IF_IN1, IF_IN2, pin 25 Iout 2.25 µA CCRR 10 dB FM Demodulator, BB-Filter Pins 19, 20, 23 and 24 Co-channel rejection ratio At Pin = –75 dBm at IR-mixer input Sensitivity Quality factor of external tank circuit approximately 20, fres = FIF/2, Pin 24 S 0.5 V/MHz Amplitude of recovered signal Nominal deviation of signal ± 288 kHz, Pin 24 A 450 mVss Corner frequency Pin 23: C = 68 pF fc Output voltage DC range Pin 24 VoutDC 680 1 kHz Vs – 1 V DAC for FM Demodulator (Internally Connected) DEMOD_DAC range (see bus protocol E6 ... E10) ∆fIFcenter ±5 % 25 4567B–DECT–03/06 11. Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS_REG = 3.2V, Tamb = 25°C Parameters Test Conditions/Pins Symbol Min. fvco fvco Typ. Max. Unit 1769 1824 MHz 1881 1934 MHz VCO RX-VCO frequency range TX-VCO frequency range VCOS = ‘0’ Bit D13 VCOS = ‘1’ Bit D13 Tuning gain 40 Gtune Frequency control voltage range Pin 17 VCO_DAC range (see bus protocol D3 ... D5) Vtune 0.4 MHz/V 2.8 ∆fvco,DAC ±5 Scaling factor prescaler SPSC 32/33 Scaling factor main counter SMC 32/33/34/35 Scaling factor swallow counter SSC V % PLL External reference input frequency AC coupled sinewave, pin 4 fREF_CLK External reference input voltage AC coupled sinewave, pin 4 VREF_CLK Scaling factor reference counter 0 31 10.368 13.824 20.736 50 MHz MHz MHz 250 SRC 3/4/6/8 mVRMS Charge Pump, Pin 13 Output current VCP = VVS_CP / 2, I_CPSW = ‘1’, pin 48 ICP_nom ±6.5 mA Output current VCP = VVS_CP / 2, I_CPSW = ‘0’, pin 48 ICP_nom ±1.2 mA Current scaling ICP = ICP_nom + CPCS × ICP_step (see bus protocol D0 ... D2) ICP_step 0.2 mA IL ±100 pA fTXFCLK 13.824 MHz GFFM_nom ±350 kHz Leakage current Gaussian Transmit Filter (Gaussian Shape B × T = 0.5) Tx data filter clock 12 taps in filter Frequency deviation Frequency deviation scaling GFFM = GFFM_nom × GFCS (see bus protocol D6 ... D8) GFCS 60 130 % Modulation Compensation Circuit Oversampling OVS Digital sum variation Current scaling factor 6 DSV (see bus protocol E3 ... E5) MCCS 85 60 130 % VCO Switch and TX Driver, Pin 32 Power gain At Pin = –40 dBm Gp 30 dB Output impedance Pin 32 Zout 100 Ω Maximum output power Pin 32 Pmax 3 dBm Gain compression At TX_RF_OUT, Pin 32 P1dB 1 dBm Output interception point Pin 32 OIP3 10 dBm 26 0 T2801 4567B–DECT–03/06 T2801 11. Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS_REG = 3.2V, Tamb = 25°C Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit Ramp Generator, Pins 36 and 37 Minimum output voltage According to RAMP_SET input Vmin 0.7 V Vmax 2.2 V Maximum output voltage According to RAMP_SET input Rise time Cramp = 270 pF at pin 37 tr 5 µs Fall time Cramp = 270 pF at pin 37 tf 5 µs Lock Detect and Test Mode Output Pin 5 Lock detect output, test mode output Locked = ‘1’, unlocked = ‘0’ Test modes (see bus protocol E0 ... E2) Leakage current VOH = 4.6V Saturation voltage IOL = 0.5 mA LD IL 5 µA VSL 0.4 V 3.1 V Auxiliary Regulator, Pins 8, 9 and 10 Output voltage VSREG = 3V, pin 8 VREG Supply voltage rejection VPin10 = VDC + 0.1Vpp fPin10 = 0.1 to 10 kHz CPin8 = 100 nF SVR 2.9 3.0 TBD dB VCO Regulator; Pins 14, 15 and 12 Output voltage VSVCO = 3V, pin 15 VREG_VCO 2.6 2.7 2.8 V 6.912 MHz 3-wire Bus Clock fClock Logic Input Levels (CLOCK, DATA, ENABLE, RX_ON, TX_ON, PU_VCO, TX_DATA, I_CPSW), Pins 1, 2, 3, 38, 39, 44, 47 and 48 High input level = ‘1’ ViH Low input level = ‘0’ ViL High input current = ‘1’ IiH Low input current = ‘0’ IiL 1.5 V 0.5 V -5 5 µA -5 5 µA Standby Control, Pins 6, 45 and 46 Power up PU_REG = ‘1‘ PU_RX/TX = ‘1‘ PU_PLL = ‘1‘ High input level Standby PU_REG = ‘0‘ PU_RX/TX = ‘0‘ PU_PLL = ‘0‘ Low input level Pin 6 Pin 45 Pin 46 VPU_REG VPU_RX/TX VPU_PLL Pin 6 Pin 45 Pin 46 VPU_REG,OFF VPU_RX/TX,OF F VPU_PLL,OFF Power up PU_REG = ‘1‘ PU_RX/TX = ‘1‘ VPU = 3V, pin 6 VPU = 5.5V, pin 45 PU_PLL = ‘1‘ High input current VPU = 3V, pin 46 VPU = 5.5V IPU_PLL Standby PU_xxxx = ‘0’ Low input current VPU = 0V, pin 6, VPU = 0.5V, pins 45, 46 IPU,OFF IPU_REG IPU_RX/TX 2.0 V 0.7 V 20 60 30 80 40 100 µA µA 100 200 125 300 150 400 µA µA 0.1 1 µA µA 27 4567B–DECT–03/06 11. Electrical Characteristics (Continued) Test conditions (unless otherwise specified): VS_REG = 3.2V, Tamb = 25°C Parameters Test Conditions/Pins Symbol Min. Typ. Max. Unit Settling Time VS = 0 → active operation Switched from VS = 0 to VS = 3V tsoa < 10 µs Settling Time Standby → active operation Switched from PU = ‘0’ to PU = ‘1’ tssa < 10 µs Settling Time Aactive operation → standby Switched from PU = ‘1’ to standby tsas <2 µs Power Supply Pins 7, 10, 12, 14, 33 and 42 Total supply current RX IS 85 mA Total supply current RSSI only IS 82 mA Total supply current TX IS 54 mA Total supply current TX (MCC, GF active) IS 58 mA Standby current PU_RX/TX = GND IS Supply current CP VVS_CP = 3V, PLL in lock condition, pin 13 ICP 28 10 1 µA µA T2801 4567B–DECT–03/06 T2801 12. T2801 Aplication Circuit RAMP_OUT TX_OUT RF_IN 33 pF 180 nH 100 nH 33 pF 18 pF 15 pF R SSI 25 IF _ T A N K 1 2 6 G N D 2 28 R F _ IN 1 2 9 G N D 3 31 R F _ IN 2 3 0 BB_OUT 24 37 RAMP_SET BB_CF 23 38 RX_ON 39 TX_ON REG_DEC 22 40 MIXER_OUT1 DAC_DEC 21 T2801 41 MIXER_OUT2 11 G N D _C P VS_VCO 14 10 VS_R EG 8 VR EG 9 R EG _C TR L 48 I_CPSW 6 PU _R EG 47 TX_DATA I_CPSW tbd 22 nF GND_VCO 16 7 VS_PLL TX_DATA tbd VREG_VCO 15 5 LD 46 PU_PLL 3 EN ABLE 45 PU_RX/TX PU_PLL GND1 18 4 R EF _C LO C K PU_RX/TX 100 pF VTUNE 17 1 C LO C K 43 GND_PLL 44 PU_VCO 2.2 nF DEMOD_TANK1 19 2 D ATA PU_VCO BB_OUT 68 pF DEMOD_TANK2 20 42 VS_MIXER 12 VS_C P TX_ON IF _ T A N K 2 2 7 560 pF V S _ IF 3 3 15 pF T X_O U T 32 R AM P_O U T 36 IF _ IN 2 3 5 270 nH RX_ON RSSI 68 pF IF _ IN 1 3 4 SAW Filter TFS 112B 180 W 150 nF CP 13 56 pF 470 nF CLOCK DATA ENABLE 220 pF REF_CLK LD PU_REG 4.7 nF VCC BC808 or similar tantal tantal 29 4567B–DECT–03/06 13. Ordering Information Extended Type Number Package T2801-PLQ Remarks QFN48 Taped and reeled 14. Package Information Package: QFN 48 - 7 x 7 Exposed pad 5.1 x 5.1 (acc. JEDEC OUTLINE No. MO-220) Dimensions in mm 7 0.85+0.15 0.42×45˚ 5.5 0.65+0.15 5.1±0.15 37 48 36 1 25 12 6.75 0.5 1 48 +0.04 0.01-0.01 technical drawings according to DIN specifications 0.23-0.05 +0.07 12 10:1 24 13 +0.05 0.4-0.10 Drawing-No.: 6.543-5068.01-4 Issue: 3; 24.01.03 30 T2801 4567B–DECT–03/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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