Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • • • – 54 Powerful Instructions – Most Single Clock Cycle Execution – 16 x 8 General Purpose Working Registers – Fully Static Operation – Up to 12 MIPS Throughput at 12 MHz Non-volatile Program and Data Memories – 2K Bytes of In-System Programmable Flash Program Memory – 128 Bytes Internal SRAM – Flash Write/Erase Cycles: 10,000 – Data Retention: 20 Years at 85oC / 100 Years at 25oC Peripheral Features – One 8-bit Timer/Counter with Two PWM Channels – One 16-bit Timer/Counter with Two PWM Channels – 10-bit Analog to Digital Converter • 8 Single-Ended Channels – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Master/Slave SPI Serial Interface – Slave TWI Serial Interface Special Microcontroller Features – In-System Programmable – External and Internal Interrupt Sources – Low Power Idle, ADC Noise Reduction, Stand-by and Power-down Modes – Enhanced Power-on Reset Circuit – Internal Calibrated Oscillator I/O and Packages – 14-pin SOIC/TSSOP: 12 Programmable I/O Lines – 15-pad UFBGA: 12 Programmable I/O Lines – 20-pad QFN/MLF: 12 Programmable I/O Lines Operating Voltage: – 1.8 – 5.5V Programming Voltage: – 5V Speed Grade – 0 – 4 MHz @ 1.8 – 5.5V – 0 – 8 MHz @ 2.7 – 5.5V – 0 – 12 MHz @ 4.5 – 5.5V Industrial Temperature Range Low Power Consumption – Active Mode: • 200 µA at 1 MHz and 1.8V – Idle Mode: • 25 µA at 1 MHz and 1.8V – Power-down Mode: • < 0.1 µA at 1.8V 8-bit Microcontroller with 2K Bytes In-System Programmable Flash ATtiny20 Preliminary Summary Rev. 8235AS–AVR–03/10 1. Pin Configurations Figure 1-1. Pinout of ATtiny20 SOIC/TSSOP VCC (PCINT8/TPICLK/T0/CLKI) PB0 (PCINT9/TPIDATA/MOSI/SDA/OC1A) PB1 (PCINT11/RESET) PB3 (PCINT10/INT0/MISO/OC1B/OC0A/CKOUT) PB2 (PCINT7/SCL/SCK/T1/ICP1/OC0B/ADC7) PA7 (PCINT6/SS/ADC6) PA6 1 2 3 4 5 6 7 14 13 12 11 10 9 8 GND PA0 (ADC0/PCINT0) PA1 (ADC1/AIN0/PCINT1) PA2 (ADC2/AIN1/PCINT2) PA3 (ADC3/PCINT3) PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5) NOTE Bottom pad should be soldered to ground. DNC: Do Not Connect Table 1-1. A 1.1.1 6 7 8 9 10 15 14 13 12 11 PA7 (ADC7/OC0B/ICP1/T1/SCL/SCK/PCINT7) PB2 (CKOUT/OC0A/OC1B/MISO/INT0/PCINT10) PB3 (RESET/PCINT11) PB1 (OC1A/SDA/MOSI/TPIDATA/PCINT9) PB0 (CLKI/T0/TPICLK/PCINT8) UFBGA - Pinout ATtiny20. 1 1.1 1 2 3 4 5 Pin 16: PA6 (ADC6/SS/PCINT6) Pin 17: PA5 (ADC5/PCINT5) DNC DNC GND VCC DNC (PCINT4/ADC4) PA4 (PCINT3/ADC3) PA3 (PCINT2/AIN1/ADC2) PA2 (PCINT1/AIN0/ADC1) PA1 (PCINT0/ADC0) PA0 20 19 18 17 16 DNC DNC DNC PA5 PA6 VQFN 2 3 4 PA5 PA6 PB2 B PA4 PA7 PB1 PB3 C PA3 PA2 PA1 PB0 D PA0 GND GND VCC Pin Description VCC Supply voltage. 1.1.2 GND Ground. 2 ATtiny20 8235AS–AVR–03/10 ATtiny20 1.1.3 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 21-4 on page 176. Shorter pulses are not guaranteed to generate a reset. The reset pin can also be used as a (weak) I/O pin. 1.1.4 Port A (PA7:PA0) Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A has alternate functions as analog inputs for the ADC, analog comparator and pin change interrupt as described in “Alternate Port Functions” on page 49. 1.1.5 Port B (PB3:PB0) Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. The port also serves the functions of various special features of the ATtiny20, as listed on page 39. 3 8235AS–AVR–03/10 2. Overview ATtiny20 is a low-power CMOS 8-bit microcontroller based on the compact AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny20 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2-1. Block Diagram VCC RESET PROGRAMMING LOGIC PROGRAM COUNTER INTERNAL OSCILLATOR CALIBRATED OSCILLATOR PROGRAM FLASH STACK POINTER WATCHDOG TIMER TIMING AND CONTROL INSTRUCTION REGISTER SRAM RESET FLAG REGISTER INSTRUCTION DECODER INTERRUPT UNIT MCU STATUS REGISTER CONTROL LINES GENERAL PURPOSE REGISTERS TIMER/ COUNTER0 X Y Z ISP INTERFACE TIMER/ COUNTER1 ALU SPI ANALOG COMPARATOR STATUS REGISTER TWI ADC 8-BIT DATA BUS DIRECTION REG. PORT A DATA REGISTER PORT A DRIVERS PORT A PA7:0 DIRECTION REG. PORT B DATA REGISTER PORT B DRIVERS PORT B GND PB3:0 The AVR core combines a rich instruction set with 16 general purpose working registers and system registers. All registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. 4 ATtiny20 8235AS–AVR–03/10 ATtiny20 The resulting architecture is compact and code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny20 provides the following features: 2K byte of In-System Programmable Flash, 128 bytes of SRAM, twelve general purpose I/O lines, 16 general purpose working registers, an 8-bit Timer/Counter with two PWM channels, a 16-bit Timer/Counter with two PWM channels, Internal and External Interrupts, an eight-channel, 10-bit ADC, a programmable Watchdog Timer with internal oscillator, a slave two-wire interface, a master/slave serial peripheral interface, an internal calibrated oscillator, and four software selectable power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and interrupt system to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules except the ADC. In Power-down mode registers keep their contents and all chip functions are disabled until the next interrupt or hardware reset. In Standby mode, the oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined with low power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The onchip, in-system programmable Flash allows program memory to be re-programmed in-system by a conventional, non-volatile memory programmer. The ATtiny20 AVR is supported by a suite of program and system development tools, including macro assemblers and evaluation kits. 5 8235AS–AVR–03/10 3. General Information 3.1 Resources A comprehensive set of drivers, application notes, data sheets and descriptions on development tools are available for download at http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. 3.3 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 3.4 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device has been characterized. 6 ATtiny20 8235AS–AVR–03/10 ATtiny20 4. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x3F SREG I T H S V N Z C Page 14 0x3E SPH Stack Pointer High Byte Page 13 0x3D SPL Stack Pointer Low Byte Page 13 0x3C CCP 0x3B RSTFLR – – – CPU Change Protection Byte 0x3A MCUCR ICSC01 ICSC00 – 0x39 OSCCAL 0x38 Reserved – – – – 0x37 CLKMSR – – – – 0x36 CLKPSR – – – – 0x35 PRR – – – PRTWI PRSPI – Page 13 – WDRF BORF EXTRF PORF Page 37 BODS SM2 SM1 SM0 SE Pages 28, 41 – – – – – CLKMS1 CLKMS0 CLKPS3 CLKPS2 CLKPS1 CLKPS0 Page 22 PRTIM1 PRTIM0 PRADC Page 29 Oscillator Calibration Byte Page 23 – QTouch Control and Status Register Page 22 0x34 QTCSR 0x33 NVMCMD – Page 152 0x32 NVMCSR NVMBSY – – – – – – – 0x31 WDTCSR WDIF WDIE WDP3 – WDE WDP2 WDP1 WDP0 Page 35 0x30 SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 Page 136 SPIF WCOL – – – – SSPS SPI2X Page 138 TWPME TWSME NVM Command Page 171 Page 172 0x2F SPSR 0x2E SPDR 0x2D TWSCRA TWSHE – TWDIE TWASIE TWEN TWSIE 0x2C TWSCRB – – – – – TWAA 0x2B TWSSRA TWDIF TWASIF TWCH TWRA TWC TWBE 0x2A TWSA TWI Slave Address Register 0x29 TWSAM TWI Slave Address Mask Register Page 151 0x28 TWSD TWI Slave Data Register Page 151 0x27 GTCCR TSM – – – – – – PSR Page 108 0x26 TIMSK ICE1 – OCIE1B OCIE1A TOIE1 OCIE0B OCIE0A TOIE0 Pages 76, 104 Pages 76, 105 SPI Data Register Page 138 TWCMD[1.0] TWDIR Page 147 Page 148 TWAS Page 149 Page 150 0x25 TIFR ICF1 – OCF1B OCF1A TOV1 OCF0B OCF0A TOV0 0x24 TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 Page 99 0x23 TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 Page 101 0x22 TCCR1C FOC1A FOC1B – – – – – – 0x21 TCNT1H Timer/Counter1 – Counter Register High Byte Page 102 Page 103 0x20 TCNT1L Timer/Counter1 – Counter Register Low Byte Page 103 0x1F OCR1AH Timer/Counter1 – Compare Register A High Byte Page 103 Page 103 0x1E OCR1AL Timer/Counter1 – Compare Register A Low Byte 0x1D OCR1BH Timer/Counter1 – Compare Register B High Byte Page 103 0x1C OCR1BL Timer/Counter1 – Compare Register B Low Byte Page 103 0x1B ICR1H Timer/Counter1 - Input Capture Register High Byte Page 104 0x1A ICR1L Timer/Counter1 - Input Capture Register Low Byte Page 104 0x19 TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 Page 71 0x18 TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Page 74 0x17 TCNT0 Timer/Counter0 – Counter Register Page 75 0x16 OCR0A Timer/Counter0 – Compare Register A Page 75 0x15 OCR0B 0x14 ACSRA Timer/Counter0 – Compare Register B ACD ACBG ACO ACI ACIE Page 76 ACIC ACIS1 ACIS0 Page 110 Page 111 0x13 ACSRB HSEL HLEV ACLP – ACCE ACME ACIRS1 ACIRS0 0x12 ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 Page 127 0x11 ADCSRB VDEN VDPD – – ADLAR ADTS2 ADTS1 ADTS0 Page 128 0x10 ADMUX – REFS REFEN ADC0EN MUX3 MUX2 MUX1 MUX0 0x0F ADCH ADC Conversion Result – High Byte Page 125 Page 126 0x0E ADCL 0x0D DIDR0 ADC7D ADC6D ADC5D ADC Conversion Result – Low Byte ADC4D ADC3D ADC2D ADC1D Page 126 0x0C GIMSK – – PCIE1 PCIE0 – – 0x0B GIFR – – PCIF1 PCIF0 – – 0x0A PCMSK1 – – – – PCINT11 0x09 PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 0x08 PORTCR – – – – 0x07 PUEB – – – – PUEB3 PUEB2 0x06 PORTB – – – – PORTB3 PORTB2 0x05 DDRB – – – – DDRB3 DDRB2 DDRB1 ADC0D Page 129 – INT0 Page 41 – INTF0 Page 42 PCINT10 PCINT9 PCINT8 Page 43 PCINT3 PCINT2 PCINT1 PCINT0 Page 43 – – BBMB BBMA Page 58 PUEB1 PUEB0 Page 58 PORTB1 PORTB0 Page 59 DDRB0 Page 59 0x04 PINB – – – – PINB3 PINB2 PINB1 PINB0 Page 59 0x03 PUEA PUEA7 PUEA6 PUEA5 PUEA4 PUEA3 PUEA2 PUEA1 PUEA0 Page 58 0x02 PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 Page 58 0x01 DDRA DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 Page 58 0x00 PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 Page 58 7 8235AS–AVR–03/10 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 8 ATtiny20 8235AS–AVR–03/10 ATtiny20 5. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add without Carry Rd ← Rd + Rr Z,C,N,V,S,H ADC Rd, Rr Add with Carry Rd ← Rd + Rr + C Z,C,N,V,S,H 1 SUB Rd, Rr Subtract without Carry Rd ← Rd - Rr Z,C,N,V,S,H 1 1 SUBI Rd, K Subtract Immediate Rd ← Rd - K Z,C,N,V,S,H 1 SBC Rd, Rr Subtract with Carry Rd ← Rd - Rr - C Z,C,N,V,S,H 1 SBCI Rd, K Subtract Immediate with Carry Rd ← Rd - K - C Z,C,N,V,S,H 1 AND Rd, Rr Logical AND Rd ← Rd • Rr Z,N,V,S 1 ANDI Rd, K Logical AND with Immediate Rd ← Rd • K Z,N,V,S 1 OR Rd, Rr Logical OR Rd ← Rd v Rr Z,N,V,S 1 ORI Rd, K Logical OR with Immediate Rd ← Rd v K Z,N,V,S 1 EOR Rd, Rr Exclusive OR Rd ← Rd ⊕ Rr Z,N,V,S 1 1 COM Rd One’s Complement Rd ← $FF − Rd Z,C,N,V,S NEG Rd Two’s Complement Rd ← $00 − Rd Z,C,N,V,S,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V,S 1 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FFh - K) Z,N,V,S INC Rd Increment Rd ← Rd + 1 Z,N,V,S 1 DEC Rd Decrement Rd ← Rd − 1 Z,N,V,S 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V,S 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V,S 1 SER Rd Set Register Rd ← $FF None 1 Relative Jump PC ← PC + k + 1 None 2 Indirect Jump to (Z) PC(15:0) ← Z, PC(21:16) ← 0 None 2 BRANCH INSTRUCTIONS RJMP k IJMP Relative Subroutine Call PC ← PC + k + 1 None 3/4 ICALL Indirect Call to (Z) PC(15:0) ← Z, PC(21:16) ← 0 None 3/4 RET Subroutine Return PC ← STACK None 4/5 RETI Interrupt Return PC ← STACK I if (Rd = Rr) PC ← PC + 2 or 3 None RCALL k 4/5 CPSE Rd,Rr Compare, Skip if Equal 1/2/3 CP Rd,Rr Compare Rd − Rr Z, C,N,V,S,H 1 CPC Rd,Rr Compare with Carry Rd − Rr − C Z, C,N,V,S,H 1 CPI Rd,K Compare with Immediate Rd − K Z, C,N,V,S,H SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3 SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b)=0) PC ← PC + 2 or 3 None 1/2/3 SBIS A, b Skip if Bit in I/O Register is Set if (I/O(A,b)=1) PC ← PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V,H LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V,H 1 ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 1 9 8235AS–AVR–03/10 Mnemonics Operands Description Operation Flags #Clocks BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 SBI A, b Set Bit in I/O Register I/O(A, b) ← 1 None 1 1 CBI A, b Clear Bit in I/O Register I/O(A, b) ← 0 None BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← T None 1 1 SEC Set Carry C←1 C CLC Clear Carry C←0 C 1 SEN Set Negative Flag N←1 N 1 CLN Clear Negative Flag N←0 N 1 SEZ Set Zero Flag Z←1 Z 1 CLZ Clear Zero Flag Z←0 Z 1 SEI Global Interrupt Enable I←1 I 1 CLI Global Interrupt Disable I←0 I 1 1 SES Set Signed Test Flag S←1 S CLS Clear Signed Test Flag S←0 S 1 SEV Set Two’s Complement Overflow. V←1 V 1 CLV Clear Two’s Complement Overflow V←0 V 1 SET Set T in SREG T←1 T 1 CLT Clear T in SREG T←0 T 1 SEH CLH Set Half Carry Flag in SREG Clear Half Carry Flag in SREG H←1 H←0 H H 1 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Copy Register Rd ← Rr None 1 LDI Rd, K Load Immediate Rd ← K None 1 1/2 LD Rd, X Load Indirect Rd ← (X) None LD Rd, X+ Load Indirect and Post-Increment Rd ← (X), X ← X + 1 None 2 LD Rd, - X Load Indirect and Pre-Decrement X ← X - 1, Rd ← (X) None 2/3 1/2 LD Rd, Y Load Indirect Rd ← (Y) None LD Rd, Y+ Load Indirect and Post-Increment Rd ← (Y), Y ← Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Decrement Y ← Y - 1, Rd ← (Y) None 2/3 1/2 LD Rd, Z Load Indirect Rd ← (Z) None LD Rd, Z+ Load Indirect and Post-Increment Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Decrement Z ← Z - 1, Rd ← (Z) None 2/3 LDS Rd, k Store Direct from SRAM Rd ← (k) None 1 ST X, Rr Store Indirect (X) ← Rr None 1 ST X+, Rr Store Indirect and Post-Increment (X) ← Rr, X ← X + 1 None 1 ST - X, Rr Store Indirect and Pre-Decrement X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store Indirect (Y) ← Rr None 1 ST Y+, Rr Store Indirect and Post-Increment (Y) ← Rr, Y ← Y + 1 None 1 ST - Y, Rr Store Indirect and Pre-Decrement Y ← Y - 1, (Y) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 1 ST Z+, Rr Store Indirect and Post-Increment. (Z) ← Rr, Z ← Z + 1 None 1 ST -Z, Rr Store Indirect and Pre-Decrement Z ← Z - 1, (Z) ← Rr None 2 STS k, Rr Store Direct to SRAM (k) ← Rr None 1 IN Rd, A In from I/O Location Rd ← I/O (A) None 1 OUT A, Rr Out to I/O Location I/O (A) ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 MCU CONTROL INSTRUCTIONS BREAK Break (see specific descr. for Break) NOP No Operation SLEEP WDR Sleep Watchdog Reset 10 (see specific descr. for Sleep) (see specific descr. for WDR) None 1 None 1 None None 1 1 ATtiny20 8235AS–AVR–03/10 ATtiny20 6. Ordering Information 6.1 ATtiny20 Speed (MHz) 12 Notes: Power Supply Ordering Code(1) Package(2) 1.8 - 5.5V ATtiny20-SSU ATtiny20-SSUR ATtiny20-XU ATtiny20-XUR ATtiny20-CCU ATtiny20-CCUR ATtiny20-MMH(3) ATtiny20-MMHR(3) 14S1 14S1 14X 14X 15CC1 15CC1 20M2 20M2 Operational Range Industrial (-40°C to 85°C)(4) 1. Code indicators: – H: NiPdAu lead finish – U: matte tin – R: tape & reel 2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). 3. Topside marking for ATtiny20: – 1st Line: T20 – 2nd Line: xx – 3rd Line: xxx 4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. Package Type 14S1 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 14X 14-lead, 4.4 mm Body, Thin Shrink Small Outline Package (TSSOP) 15CC1 15-ball (4 x 4 Array), 0.65 mm Pitch, 3.0 x 3.0 x 0.6 mm, Ultra Thin, Fine-Pitch Ball Grid Array Package (UFBGA) 20M2 20-pad, 3 x 3 x 0.85 mm Body, Very Thin Quad Flat No Lead Package (VQFN) 11 8235AS–AVR–03/10 7. Packaging Information 7.1 14S1 1 E H E N L Top View End View e COMMON DIMENSIONS (Unit of Measure = mm/inches) b SYMBOL A1 A D Side View NOM MAX – 1.75/0.0688 NOTE 1.35/0.0532 A1 0.1/.0040 – 0.25/0.0098 b 0.33/0.0130 – 0.5/0.0200 5 D 8.55/0.3367 – 8.74/0.3444 2 E 3.8/0.1497 – 3.99/0.1574 3 H 5.8/0.2284 – 6.19/0.2440 L 0.41/0.0160 – 1.27/0.0500 e Notes: MIN A 4 1.27/0.050 BSC 1. This drawing is for general information only; refer to JEDEC Drawing MS-012, Variation AB for additional information. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusion and gate burrs shall not exceed 0.15 mm (0.006") per side. 3. Dimension E does not include inter-lead Flash or protrusion. Inter-lead flash and protrusions shall not exceed 0.25 mm (0.010") per side. 4. L is the length of the terminal for soldering to a substrate. 5. The lead width B, as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024") per side. 2/5/02 TITLE R 12 2325 Orchard Parkway San Jose, CA 95131 DRAWING NO. 14S1, 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 14S1 REV. A ATtiny20 8235AS–AVR–03/10 ATtiny20 7.2 14X Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. JEDEC Standard MO-153 AB-1. INDEX MARK PIN 1 4.50 (0.177) 6.50 (0.256) 4.30 (0.169) 6.25 (0.246) 5.10 (0.201) 4.90 (0.193) 0.65 (.0256) BSC 0.30 (0.012) 0.19 (0.007) 1.20 (0.047) MAX 0.15 (0.006) 0.05 (0.002) SEATING PLANE 0.20 (0.008) 0.09 (0.004) 0º~ 8º 0.75 (0.030) 0.45 (0.018) 05/16/01 R y 2325 Orchard Parkway San Jose, CA 95131 TITLE 14X (Formerly "14T"), 14-lead (4.4 mm Body) Thin Shrink Small Outline Package (TSSOP) DRAWING NO.. REV.. 14X B 13 8235AS–AVR–03/10 7.3 15CC1 1 2 3 4 0.08 A Pin#1 ID B SIDE VIEW D C b1 D A1 A E A2 TOP VIEW E1 15-Øb e D COMMON DIMENSIONS (Unit of Measure = mm) C D1 MIN NOM MAX A – – 0.6 A1 0.05 0.010 0.015 SYMBOL B A A2 1 2 3 4 A1 Ball Corner BOTTOM VIEW 0.43 REF b 0.25 b1 0.25 D 2.90 D1 E Note1: Dimention “b” is measured at the maximum ball dia. in a plane parallel NOTE 0.30 0.35 1 – – 2 3.00 3.10 1.95 BSC 2.90 E1 e to the seating plane. Note2: Dimention “b1” is the solderable surface defined by the opening of the solder resist layer. TITLE Package Drawing Contact: 15CC1, 15-ball (4 x 4 Array), 3.0 x 3.0 x 0.6mm [email protected] package, ball pitch 0.65mm, 3.00 3.10 1.95 BSC 0.65 BSC 27/07/09 GPC CBC DRAWING NO. REV. 15CC1 B Ultra thin, Fine-Pitch Ball Grid Array Package (UFBGA) 14 ATtiny20 8235AS–AVR–03/10 ATtiny20 7.4 20M2 D C y Pin 1 ID E SIDE VIEW TOP VIEW A1 A D2 16 17 18 19 20 COMMON DIMENSIONS (Unit of Measure = mm) C0.18 (8X) 15 Pin #1 Chamfer (C 0.3) 14 2 e E2 13 3 12 4 11 5 MIN NOM MAX A 0.75 0.80 0.85 A1 0.00 0.02 0.05 b 0.17 0.22 0.27 SYMBOL 1 C b 10 9 8 7 6 K L BOTTOM VIEW 0.3 Ref (4x) NOTE 0.152 D 2.90 3.00 3.10 D2 1.40 1.55 1.70 E 2.90 3.00 3.10 E2 1.40 1.55 1.70 e – 0.45 – L 0.35 0.40 0.45 K 0.20 – – y 0.00 – 0.08 10/24/08 Package Drawing Contact: [email protected] GPC TITLE 20M2, 20-pad, 3 x 3 x 0.85 mm Body, Lead Pitch 0.45 mm, ZFC 1.55 x 1.55 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) DRAWING NO. REV. 20M2 B 15 8235AS–AVR–03/10 8. Errata The revision letters in this section refer to the revision of the corresponding ATtiny20 device. 8.1 Rev. A • Lock bits re-programming 1. Lock bits re-programming Attempt to re-program Lock bits to present, or lower protection level (tampering attempt), causes erroneously one, random line of Flash program memory to get erased. The Lock bits will not get changed, as they should not. Problem Fix / Workaround Do not attempt to re-program Lock bits to present, or lower protection level. 16 ATtiny20 8235AS–AVR–03/10 ATtiny20 9. Datasheet Revision History 9.1 Rev. 8235A – 03/10 1. Initial revision 17 8235AS–AVR–03/10 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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